Reference clock frequency multiplier circuit and chip

Abstract

The invention relates to the technical field of analog integrated circuits, and discloses a reference clock frequency multiplier circuit and a chip, and the reference clock frequency multiplier circuit comprises a phase discriminator, a charge pump, a loop filter, a voltage-controlled delay unit, a multiphase injection locked ring oscillator and an edge combiner. And the voltage-controlled delay unit, the phase discriminator, the charge pump and the loop filter form a multi-phase clock generator. The multi-phase injection clock signal is generated by adopting the voltage-controlled delay unit, and the multi-phase injection locking ring oscillator is further adopted as an input clock source of the edge combiner, so that the phase error of the multi-phase injection clock signal generated by the voltage-controlled delay unit is suppressed; therefore, a frequency multiplication clock signal with an accurate duty ratio and low noise is obtained.

Description

Technical Field

[0001] The present invention relates to the technical field of analog integrated circuits, and in particular to a reference clock frequency multiplication circuit and chip. Background Art

[0002] The traditional clock frequency multiplication circuit is usually based on the phase locked loop (PLL) structure, whose basic components include phase frequency detector (PFD), charge pump (CP), low-pass filter (LPF), voltage-controlled oscillator (VCO) and frequency divider (1 / N), such as Figure 1 As shown in Figure a, the phase frequency detector is used to detect the phase error between the input reference clock and the feedback divided clock. The charge pump converts this phase error into a current, and the low-pass filter generates a control voltage. Combined with the divider, this structure can generate a high-frequency clock by multiplying the low-frequency reference clock. It has the advantages of compact structure, stable operation, and convenient frequency tuning. Figure 1 As shown in Figure 2(b), the optimal loop bandwidth of the phase-locked loop (PLL) can be approximately determined by the intersection of the loop module and the voltage-controlled oscillator phase noise curves. This shows that the jitter performance of the PLL is also largely dependent on the noise of the voltage-controlled oscillator. However, different types of voltage-controlled oscillators have their own advantages and disadvantages in terms of power consumption, area, phase noise, tuning range, and multiphase clock generation. Compared to LC voltage-controlled oscillators, ring oscillators offer advantages such as smaller area, wider tuning range, and ease of multiphase clock generation. The poor phase noise of ring oscillators is primarily due to the accumulation of device noise. Therefore, a wide PLL loop bandwidth is required to suppress the ring oscillator's phase noise.

[0003] Compared to a phase-locked loop (PLL), a delay-locked loop (DLL) offers the advantages of a wide frequency response range and low noise. However, in traditional DLL structures, the phase error of the DLL output is difficult to minimize due to circuit mismatch. This typically requires a duty cycle calibration circuit cascaded after the edge combiner, resulting in high costs.

[0004] Therefore, the existing technology still needs to be improved and developed. Summary of the Invention

[0005] In view of the above-mentioned deficiencies in the prior art, the purpose of the present invention is to provide a reference clock frequency multiplication circuit and chip to solve the problem that the phase error of the existing delay-locked loop output is difficult to be reduced due to circuit mismatch, resulting in the need to cascade a duty cycle calibration circuit after the edge combiner.

[0006] The technical solutions of the present invention are as follows: In a first aspect, the present invention provides a reference clock frequency multiplication circuit, comprising: A phase detector for detecting phase differences; a charge pump and a loop filter, wherein the charge pump is connected to the phase detector, and the loop filter is connected to the charge pump, and the charge pump and the loop filter are used to generate a control voltage according to the phase difference detection signal output by the phase detector; a voltage-controlled delay unit, the voltage-controlled delay unit being connected to the loop filter and the phase detector respectively, the voltage-controlled delay unit being configured to receive a reference clock and the control voltage and output a first multi-phase injection clock signal; a multi-phase injection-locked ring oscillator, the multi-phase injection-locked ring oscillator being connected to the voltage-controlled delay unit, the multi-phase injection-locked ring oscillator being configured to receive the control voltage, suppress a phase error of the first multi-phase injection clock signal, and output a second multi-phase injection clock signal; An edge combiner is connected to the multi-phase injection locked ring oscillator, and is used to generate a multiplied frequency clock through the second multi-phase injection clock signal.

[0007] A further configuration of the present invention further includes: a first buffer connected between the voltage-controlled delay unit and the phase detector; A second buffer is connected between the multi-phase injection-locked ring oscillator and the edge combiner.

[0008] According to a further arrangement of the present invention, the voltage-controlled delay unit comprises: a reference clock buffer and a voltage-controlled delay line; The reference clock buffer is connected to the voltage-controlled delay line, and is used to receive a reference clock and convert the reference clock into a differential input signal and input it into the voltage-controlled delay line; The voltage-controlled delay line is connected to the phase detector, and the voltage-controlled delay unit is used to access the differential input signal and output a first multi-phase injection clock signal to the phase detector and the multi-phase injection locked oscillator.

[0009] According to a further configuration of the present invention, the reference clock buffer includes a plurality of cascaded first delay units, each of which outputs a differential clock signal, and the differential clock signals output by each of the first delay units together constitute the first multi-phase injection clock signal.

[0010] According to a further configuration of the present invention, the first delay unit includes: a first inverter, a second inverter, a third inverter, a fourth inverter, a switched capacitor circuit, a fixed capacitor, a first variable capacitor, and a second variable capacitor; The input ends of the first inverter and the second inverter are connected to the differential input signal, and the output ends of the first inverter and the second inverter are connected to the two output ends of the voltage-controlled delay line respectively; The third inverter and the fourth inverter are connected across the two output ends of the voltage-controlled delay line; The fixed capacitor is connected across the two output terminals of the voltage-controlled delay line; The first variable capacitor and the second variable capacitor are connected across the two output terminals of the voltage-controlled delay line; A switched capacitor circuit is connected across two output terminals of the voltage-controlled delay line, and the switched capacitor circuit is used to adjust a delay adjustment range of the first delay unit.

[0011] According to a further configuration of the present invention, the multi-phase injection-locked ring oscillator includes a plurality of cascaded second delay units and a first switch tube and a second switch tube connected to each of the second delay units; The gates of the first switching transistor and the second switching transistor are connected to the first multi-phase injection clock signal, the drain of the first switching transistor is connected to the non-inverting terminal of the second delay unit, the source of the first switching transistor is grounded, the drain of the second switching transistor is connected to the inverting terminal of the second delay unit, and the source of the second switching transistor is grounded; The output end of the second delay unit is connected to the edge combiner; the differential clock signals output by each second delay unit together constitute the second multi-phase injection clock signal.

[0012] According to a further configuration of the present invention, the phase detector comprises: a first trigger, a second trigger, a first NOR gate and an inverter chain; The clock terminals of the first flip-flop and the second flip-flop are connected to the first multi-phase injection clock signal; The inverting output terminals of the first flip-flop and the second flip-flop are connected to the input terminal of the first NOR gate; The output end of the first NOR gate is connected to the input end of the inverter chain group, and the output end of the inverter chain group is connected to the reset end of the first flip-flop and the reset end of the second flip-flop respectively; The output terminal of the first trigger outputs a first switch control signal, and the output terminal of the second trigger outputs a second switch control signal; The first switch control signal and the second switch control signal constitute a phase difference detection signal output by the phase detector.

[0013] According to a further configuration of the present invention, the charge pump includes: a bias circuit, a first current mirror, a second current mirror, a normally open path providing unit and a charge pump unit; The bias circuit is connected to a reference current and is connected to the first current mirror and the second current mirror respectively, and the bias circuit is used to provide a bias voltage for the first current mirror and the second current mirror; The third current mirror is connected to the power supply voltage and is connected to the charge pump unit, and the third current mirror is used to provide an operating current for the charge pump unit; The normally open path providing unit is connected between the first current mirror and the third current mirror, and the normally open path providing unit is used to provide a normally open path for the working current of the charge pump unit; The charge pump unit is connected between the first current mirror and the third current mirror, and is used to generate a control voltage based on the phase difference detection signal output by the phase detector.

[0014] According to a further arrangement of the present invention, the edge combiner comprises: a second NOR gate, a third NOR gate, a fourth NOR gate, a fifth NOR gate, a sixth NOR gate, a seventh NOR gate and an AND gate; The second multi-phase injection clock signal is connected to the input terminals of the second NOR gate, the third NOR gate, the fourth NOR gate and the fifth NOR gate; The output ends of the second NOR gate and the third NOR gate are connected to the input end of the sixth NOR gate respectively; the output ends of the fourth NOR gate and the fifth NOR gate are connected to the input end of the seventh NOR gate respectively; The output end of the sixth NOR gate and the output end of the seventh NOR gate are connected to the input end of the AND gate respectively, and the output end of the AND gate outputs a quadruple frequency clock.

[0015] In a second aspect, the present invention further provides a chip comprising the reference clock frequency multiplication circuit as described above.

[0016] The present invention provides a reference clock frequency multiplication circuit and chip. The reference clock frequency multiplication circuit includes: a phase detector for detecting a phase difference; a charge pump and a loop filter, the charge pump being connected to the phase detector, the loop filter being connected to the charge pump, and the charge pump and the loop filter being configured to generate a control voltage based on a phase difference detection signal output by the phase detector; a voltage-controlled delay unit, the voltage-controlled delay unit being connected to the loop filter and the phase detector, the voltage-controlled delay unit being configured to receive a reference clock and the control voltage and output a first multi-phase injection clock signal; a multi-phase injection-locked ring oscillator, the multi-phase injection-locked ring oscillator being connected to the voltage-controlled delay unit, the multi-phase injection-locked ring oscillator being configured to receive the control voltage, suppress a phase error of the first multi-phase injection clock signal, and output a second multi-phase injection clock signal; and an edge combiner, the edge combiner being connected to the multi-phase injection-locked ring oscillator, the edge combiner being configured to generate a frequency-multiplied clock using the second multi-phase injection clock signal. The present invention adopts a voltage-controlled delay unit to generate a multi-phase injection clock signal, and further adopts a multi-phase injection-locked ring oscillator as the input clock source of an edge combiner to suppress the phase error of the multi-phase injection clock signal generated by the voltage-controlled delay unit, thereby obtaining a frequency-multiplied clock signal with accurate duty cycle and low noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary personnel in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0018] Figure 1 This is the structural block diagram and phase noise characteristic diagram of the phase-locked loop.

[0019] Figure 2 It is a principle block diagram of the reference clock frequency multiplication circuit in the present invention.

[0020] Figure 3 It is the phase noise diagram of the delay-locked loop.

[0021] Figure 4 1 is a circuit schematic diagram of a phase detector and its operation timing diagram in one embodiment of the present invention.

[0022] Figure 5 1 is a working state diagram and a phase detection characteristic curve diagram of a phase detector in one embodiment of the present invention.

[0023] Figure 6 1 is a circuit diagram of a charge pump in one embodiment of the present invention.

[0024] Figure 7 1 is a circuit schematic diagram of a unity-gain buffer constructed using a rail-to-rail operational amplifier in one embodiment of the present invention.

[0025] Figure 8 It is a principle block diagram of a voltage-controlled delay line and a circuit principle diagram of a first delay unit in one embodiment of the present invention.

[0026] Figure 9 It is a principle block diagram of a multi-phase injection-locked ring oscillator in one embodiment of the present invention.

[0027] Figure 10 FIG. 4 is a circuit diagram of an edge combiner in one embodiment of the present invention.

[0028] Figure 11 FIG. 4 is a diagram of the tuning range of the reference clock frequency multiplication circuit in one embodiment of the present invention.

[0029] Figure 12 FIG. 4 is a phase noise diagram of a reference clock frequency multiplication circuit according to an embodiment of the present invention.

[0030] The marks in the accompanying drawings are: 1. Phase detector; 2. Charge pump; 21. Bias circuit; 22. First current mirror; 23. Second current mirror; 24. Third current mirror; 25. Normally open path providing unit; 26. Charge pump unit; 3. Loop filter; 4. Voltage-controlled delay unit; 41. Reference clock buffer; 42. Voltage-controlled delay line; 421. First delay unit; 422. Switched capacitor circuit; 5. Multi-phase injection-locked ring oscillator; 51. Second delay unit; 6. Edge combiner; 7. First buffer; 8. Second buffer. DETAILED DESCRIPTION

[0031] The present invention provides a reference clock frequency multiplication circuit and chip. To clarify the objectives, technical solutions, and effects of the present invention, the present invention is further described below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0032] In the embodiments and patent claims, unless otherwise specified herein, the words "a," "an," "the," and "the" may include plural forms. If the embodiments of the present invention include descriptions of "first," "second," etc., such descriptions are for descriptive purposes only and should not be understood as indicating or implying their relative importance or implicitly specifying the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include at least one of such features.

[0033] It should be further understood that the term "comprising" used in the description of the present invention refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when an element is said to be "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intermediate elements. In addition, "connected" or "coupled" as used herein can include wireless connections or wireless couplings. The term "and / or" as used herein includes all or any units and all combinations of one or more of the items listed in association.

[0034] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art in the art to which the present invention belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with their meanings in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0035] In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0036] The inventors' research has revealed that different types of voltage-controlled oscillators have their own advantages and disadvantages in terms of power consumption, area, phase noise, tuning range, and multi-phase clock generation. Ring oscillators, compared to LC voltage-controlled oscillators, offer advantages such as small area, wide tuning range, and ease of multi-phase clock generation; LC voltage-controlled oscillators generally perform better in terms of phase noise and power consumption. These two structures often struggle to simultaneously meet the requirements of small area, low power consumption, low phase noise, and multi-phase clock generation: the poor phase noise of ring oscillators is primarily due to the accumulation of device noise, while the large area of ​​LC voltage-controlled oscillators is due to the large inductors they require. Therefore, a wide phase-locked loop bandwidth is required to suppress the phase noise of voltage-controlled oscillators, especially ring oscillators. Compared to traditional phase-locked loops, clock generators based on delay-locked loops (DLLs) have excellent jitter performance, with their output jitter roughly approximating the jitter of the reference clock. However, in the traditional delay-locked loop structure, the phase error of the delay-locked loop output is difficult to be low due to circuit mismatch. It is usually necessary to cascade a duty cycle calibration circuit after the edge combiner, which makes the cost high.

[0037] In response to the above technical problems, the present invention provides a reference clock frequency multiplication circuit and chip, which uses a delay-locked loop to generate a high-precision, low-noise multi-phase injection clock signal, and further uses a multi-phase injection-locked ring oscillator as the input clock source of an edge combiner to suppress the phase error of the multi-phase injection clock signal generated by the delay-locked loop, thereby obtaining a frequency-multiplied clock signal with accurate duty cycle and low noise.

[0038] Please also see Figures 2 to 12 , the present invention provides a preferred embodiment of a reference clock frequency multiplication circuit.

[0039] In some embodiments, as Figure 2 As shown, the present invention provides a reference clock frequency multiplication circuit, which includes: a phase detector 1, a charge pump 2, a loop filter 3, a voltage-controlled delay unit 4, a multi-phase injection-locked ring oscillator 5 and an edge combiner 6. The phase detector 1 is used to detect the phase difference; the charge pump 2 is connected to the phase detector 1, and the loop filter 3 is connected to the charge pump 2. The charge pump 2 and the loop filter 3 are used to generate a control voltage Vtune according to the phase difference detection signal output by the phase detector; the voltage-controlled delay unit 4 is connected to the loop filter 3 and the phase detector 1 respectively, and the voltage-controlled delay unit 4 is used to access the reference clock and the control voltage and output a first multi-phase injection clock signal; the multi-phase injection-locked ring oscillator 5 is connected to the voltage-controlled delay line 42, and the multi-phase injection-locked ring oscillator 5 is used to access the control voltage, suppress the phase error of the first multi-phase injection clock signal, and output a second multi-phase injection clock signal; the edge combiner 6 is connected to the multi-phase injection-locked ring oscillator 5, and the edge combiner 6 is used to generate a multiplied frequency clock using the second multi-phase injection clock signal.

[0040] In this embodiment, the voltage-controlled delay unit 4, the phase detector 1, the charge pump 2, and the loop filter 3 constitute a multiphase clock generator. The voltage-controlled delay unit 4 is connected to a crystal oscillator to generate a reference clock, which is converted into a first multiphase injection clock signal (a differential signal) and input into the phase detector 1. The phase detector 1 detects the phase difference of the first multiphase injection clock signal. The charge pump 2 and the loop filter 3 generate a control voltage based on this phase difference, which is input into the voltage-controlled delay unit 4 and the multiphase injection-locked ring oscillator 5, respectively. This ensures that the free-running frequency of the multiphase injection-locked ring oscillator 5 equals the injection clock frequency when the delay-locked loop is locked. The multiphase injection-locked oscillator suppresses the phase error absorbed by the injected first multiphase injection clock and then outputs a second multiphase injection clock signal with higher accuracy to the edge combiner 6, which generates a multiplied frequency clock, for example, a quadrupled frequency clock.

[0041] In the above-mentioned technical solution, the present invention combines a delay-locked loop (DLL) with a multiphase injection-locked ring oscillator (PILO) 5 to overcome the compromise between phase accuracy and phase noise in conventional ILLOs. The DLLL generates a high-precision, low-noise multiphase clock with a wide frequency response range, providing excellent clock jitter performance (jitter accumulation within the open-loop voltage-controlled delay line is limited to the delay line itself, and due to the DLLL's low gain, the phase noise transmitted from the phase detector 1 and charge pump 2 to the output is generally negligible). Output jitter approximates reference clock jitter, eliminating the need for large-area inductors. Clock synthesis is performed through an edge combiner 6, generating a low-jitter, low-spurious multiplied-frequency clock. This offers advantages over PLL or polyphase filter structures in low-frequency applications. Figure 3 The phase noise characteristics of a clock generator based on a delay-locked loop (DLL) are demonstrated, with both the cumulative phase noise associated with the DLL and the phase noise introduced by phase detector 1 and charge pump 2 being very small. Although this structure exhibits a certain jitter amplification effect at out-of-band frequencies, its magnitude is typically extremely small. Compared to traditional PLLs, clock generators based on DLLs exhibit excellent jitter performance, with output jitter roughly approximating the jitter of the reference clock. Furthermore, a multiphase injection-locked ring oscillator 5 is introduced to effectively suppress phase error and reduce duty cycle variations in the output clock, resulting in a high-precision multiphase clock that serves as the input clock source for edge combiner 6, thereby generating a frequency-multiplied clock with accurate duty cycle and lower noise. This structure, combining the DLL with the multiphase injection-locked ring oscillator 5, overcomes the compromise between phase accuracy and phase noise in traditional injection-locked ring oscillators and eliminates the need for a duty cycle calibration circuit cascaded after the edge combiner 6.

[0042] It should be understood that in the multi-phase injection-locked ring oscillator 5, the phase accuracy of the multi-phase clock used as the injection signal does not need to be extremely precise. Due to the low operating frequency and the requirement for an eight-phase injection clock, using a multi-phase filter would require a larger area and result in greater mismatch. Therefore, a delay-locked loop (DLL) is a very suitable method for generating multi-phase clocks.

[0043] In some embodiments, as Figure 2 As shown, the reference clock frequency multiplication circuit further includes: a first buffer 7 and a second buffer 8. The first buffer 7 is connected between the voltage-controlled delay unit 4 and the phase detector 1; the second buffer 8 is connected between the multi-phase injection-locked ring oscillator 5 and the edge combiner 6.

[0044] In this embodiment, the load of each output stage of the voltage-controlled delay unit 4 includes, in addition to the multiphase injection-locked ring oscillator 5, a first buffer 7 for injecting into the input of the phase detector 1. Furthermore, to ensure matching and symmetry of each stage of the voltage-controlled delay unit 4, a second buffer 8 is also cascaded to the output of the multiphase injection-locked ring oscillator 5 in the non-phase-detection phase. The first buffer 7 and the second buffer 8 have the same structure.

[0045] In some embodiments, as Figure 4 As shown in a in FIG, the phase detector 1 includes: a first flip-flop DFF1, a second flip-flop DFF2, a first NOR gate NOR1, and an inverter chain group Delay. The clock terminals of the first flip-flop DFF1 and the second flip-flop DFF2 are connected to the first multi-phase injection clock signal. The inverting output terminals of the first flip-flop DFF1 and the second flip-flop DFF2 are connected to the input terminal of the first NOR gate NOR1. The output terminal of the first NOR gate NOR1 is connected to the input terminal of the inverter chain group Delay, and the output terminal of the inverter chain group Delay is connected to the reset terminals of the first flip-flop DFF1 and the second flip-flop DFF2, respectively. The output terminal of the first flip-flop DFF1 outputs a first switch control signal UP, and the output terminal of the second flip-flop DFF2 outputs a second switch control signal DN. The first switch control signal UP and the second switch control signal DN constitute the phase difference detection signal output by the phase detector 1.

[0046] In this embodiment, phase detector 1 is the core module for phase synchronization in a delay-locked loop (DLLL). By comparing the phase difference between input signals CK1 and CK2, it generates switch control signals UP / DN (pulse signals) for switching charge pump 2. It consists of two rising-edge-triggered D flip-flops with reset terminals (i.e., first flip-flop DFF1 and second flip-flop DFF2), a first NOR gate NOR1, and an inverter chain Delay consisting of an odd-numbered series of reverse-acting inverters. The inverter chain Delay also serves as a delay for the reset signal, with the delay length represented by td. This prevents glitches in the switch control signals UP / DN when the phase difference between input signals CK1 and CK2 is small, rendering them unusable as switch control signals for the subsequent charge pump 2 stage.

[0047] The state of the phase detector 1 is triggered by the rising edge of the two input signals CK1 / CK2. The working principle and timing diagram are as follows: Figure 4As shown in b in FIG, the input signal CK1 is used as a reference clock, and the input signal CK2 is a clock delayed and adjusted by the voltage-controlled delay line 42. When the rising edge of the input signal CK2 arrives, the output of the second flip-flop DFF2 is set to a high level; when the rising edge of the input signal CK2 arrives, the output of the first flip-flop DFF1 is set to a high level; when the outputs of the two D flip-flops are both high, the reset terminals of the two D flip-flops are set to a high level after a certain delay td, and the output terminals of the two D flip-flops are reset to a low level at the same time. The phase detection characteristic curve of the phase detector 1 is shown as follows: Figure 5 As shown, its phase detection range is 4π, Figure 5 Central vertical coordinate represents the average value of the voltage difference at the output of phase detector 1, Figure 5 The horizontal axis Φ is the phase difference between the two signals at the input end of the phase detector.

[0048] In some embodiments, as Figure 6 As shown, the charge pump 2 includes: a bias circuit 21, a first current mirror 22, a second current mirror 23, a normally open path providing unit 24 and a charge pump unit 25; the bias circuit 21 is connected to the reference current I_REF and is connected to the first current mirror 22 and the second current mirror 23 respectively. The bias circuit 21 is used to provide a bias voltage for the first current mirror 22 and the second current mirror 23; the third current mirror 24 is connected to the power supply voltage VDD and is connected to the charge pump unit 26. The third current mirror 24 is used to provide an operating current for the charge pump unit 26; the normally open path providing unit 25 is connected between the first current mirror 21 and the third current mirror 24. The normally open path providing unit 25 is used to provide a normally open path for the operating current of the charge pump unit 26; the charge pump unit 26 is connected between the first current mirror 22 and the third current mirror 24. The charge pump unit 26 is used to generate a control voltage based on the phase difference detection signal output by the phase detector 1.

[0049] Specifically, the bias circuit 21 includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, and a sixth MOS transistor M6. The first current mirror 22 includes a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, and a tenth MOS transistor M10. The second current mirror 23 includes an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, and a fourteenth MOS transistor M14. The third current mirror 24 includes a fifteenth MOS transistor M15, a sixteenth MOS transistor M16, a seventeenth MOS transistor M17, and an eighteenth MOS transistor M18. The normally-open path providing unit 25 includes a nineteenth MOS transistor M19, a twentieth MOS transistor M20, a twenty-first MOS transistor M21, a twenty-second MOS transistor M22, a twenty-third MOS transistor M23, and a twenty-fourth MOS transistor M24. The charge pump unit 26 includes a twenty-fifth MOS transistor M25, a twenty-sixth MOS transistor M26, a twenty-seventh MOS transistor M27, a twenty-eighth MOS transistor M28, a twenty-ninth MOS transistor M29, a thirtieth MOS transistor M30, a thirty-first MOS transistor M31, a thirty-second MOS transistor M32, a thirty-third MOS transistor M33, a thirty-fourth MOS transistor M34, a thirty-fifth MOS transistor M35 and a thirty-sixth MOS transistor M36.

[0050] The drain of the first MOS transistor M1 is connected to the reference current I_REF, the source of the first MOS transistor M1 is connected to the drain of the second MOS transistor M2, the source of the second MOS transistor M2 is grounded, the gate of the first MOS transistor M1 is connected to the gate of the third MOS transistor M3, the gate of the second MOS transistor M2 is connected to the gate of the fourth MOS transistor M4, the drain of the third MOS transistor M3 is connected to the drain of the twelfth MOS transistor M12, the source of the third MOS transistor M3 is connected to the drain of the fourth MOS transistor M4, and the source of the fourth MOS transistor M4 is grounded. The gate of the fifth MOS transistor M5 is connected to the power supply voltage VDD, the drain of the fifth MOS transistor M5 is connected to the drain of the fourteenth MOS transistor M14, the source of the fifth MOS transistor M5 is connected to the drain of the sixth MOS transistor M6, the drain of the twelfth MOS transistor M12 is connected to the drain of the third MOS transistor M3, the source of the twelfth MOS transistor M12 is connected to the drain of the eleventh MOS transistor M11, the gate of the twelfth MOS transistor M12 is connected to the gate of the fourteenth MOS transistor M14, the gate of the eleventh MOS transistor M11 is connected to the gate of the thirteenth MOS transistor M1 The gate of the eleventh MOS transistor M11 is connected to the power supply voltage, the source of the thirteenth MOS transistor M13 is connected to the power supply voltage, the drain of the fourteenth MOS transistor M14 is connected to the drain of the fifth MOS transistor M5, and the source of the sixth MOS transistor M6 is grounded; the source of the fifteenth MOS transistor M15 is connected to the power supply voltage, the drain of the fifteenth MOS transistor M15 is connected to the source of the sixteenth MOS transistor M16, the gate of the fifteenth MOS transistor M15 is connected to the gate of the seventeenth MOS transistor M17; the drain of the sixteenth MOS transistor M16 is connected to the nineteenth MOS transistor M17. The drain of the MOS transistor M19 is connected to the source of the 20th MOS transistor M20, the gate of the 16th MOS transistor M16 is connected to the gate of the 14th MOS transistor M14 and the gate of the 18th MOS transistor M18; the gate of the 19th MOS transistor M19 is connected to the power supply voltage, the source of the 19th MOS transistor M19 is connected to the drain of the 21st MOS transistor M21, the source of the 21st MOS transistor M21 is connected to the source of the 23rd MOS transistor M23, the gate of the 21st MOS transistor M21 is grounded, and the gate of the 23rd MOS transistor M23 is grounded.The drain of the 20th MOS transistor M20 is connected to the source of the 22nd MOS transistor M22, the gate of the 22nd MOS transistor M22 is connected to the power supply voltage, the drain of the 22nd MOS transistor M22 is connected to the drain of the 24th MOS transistor M24, the gate of the 24th MOS transistor M24 is connected to the power supply voltage, the source of the 24th MOS transistor M24 and the drain of the 23rd MOS transistor M23 are connected to the drain of the seventh MOS transistor M7; the common terminal of the 19th MOS transistor M19 and the 21st MOS transistor M21, the common terminal of the source of the 21st MOS transistor M21 and the source of the 23rd MOS transistor M23, the common terminal of the 20th MOS transistor M20 The gate of the seventh MOS tube M7 is connected to the drain of the third MOS tube M3 and the drain of the ninth MOS tube M9, respectively. The source of the seventh MOS tube M7 is connected to the drain of the eighth MOS tube M8, and the gate of the eighth MOS tube M8 is connected to the gates of the sixth MOS tube M6 and the tenth MOS tube M10. The source of the ninth MOS tube M9 is connected to the drain of the tenth MOS tube M10, the source of the tenth MOS tube M10 is grounded, and the drain of the ninth MOS tube M9 is connected to the drain of the third MOS tube M3 and the drain of the ninth MOS tube M9, respectively. The drain of the twenty-ninth MOS transistor M29, the source of the thirtieth MOS transistor M30, the drain of the thirty-fifth MOS transistor M35, and the source of the thirty-sixth MOS transistor M36 are connected; the source of the seventeenth MOS transistor M17 is connected to the power supply voltage, the gate of the seventeenth MOS transistor M17 is connected to the gate of the fifteenth MOS transistor M15, the drain of the seventeenth MOS transistor M17 is connected to the source of the eighteenth MOS transistor M18, the gate of the eighteenth MOS transistor M18 is connected to the gate of the sixth MOS transistor M6, the drain of the eighteenth MOS transistor M18 is connected to the drain of the twenty-fifth MOS transistor M25, the source of the twenty-sixth MOS transistor M26, the drain of the thirty-first MOS transistor M17, and the source of the thirty-second MOS transistor M17. The drain of the MOS transistor M31 is connected to the source of the twelfth MOS transistor M12; the gate of the twenty-fifth MOS transistor M25 is connected to the power supply voltage, the sixth electrode of the twenty-fifth MOS transistor M25 is connected to the drain of the eighteenth MOS transistor M18, the source of the twenty-fifth MOS transistor M25 is connected to the drain of the twenty-seventh MOS transistor M27, the gate of the twenty-seventh MOS transistor M27 is grounded, and the source of the twenty-seventh MOS transistor M27 is connected to the source of the twenty-ninth MOS transistor M29; the drain of the twenty-sixth MOS transistor M26 is connected to the source of the twenty-eighth MOS transistor M28, and the drain of the twenty-eighth MOS transistor M28 is connected to the drain of the thirtieth MOS transistor M30;The common terminal of the source of the twenty-fifth MOS transistor M25 and the drain of the twenty-seventh MOS transistor M27, the common terminal of the drain of the twenty-sixth MOS transistor M26 and the source of the twenty-eighth MOS transistor M28, the common terminal of the source of the twenty-seventh MOS transistor M27 and the source of the twenty-ninth MOS transistor M29, the common terminal of the drain of the twenty-sixth MOS transistor M26 and the source of the twenty-eighth MOS transistor M28, and the common terminal of the drain of the twenty-eighth MOS transistor M28 and the drain of the thirtieth MOS transistor M30 are connected together; the common terminal of the source of the thirty-first MOS transistor M31 and the drain of the thirty-third MOS transistor M33, the common terminal of the source of the thirty-third MOS transistor M33 and the source of the thirty-fifth MOS transistor M35, the common terminal of the drain of the thirty-second MOS transistor M32 and the source of the thirty-fourth MOS transistor M34, and the common terminal of the thirty-fourth MOS transistor M34 and the thirty-sixth MOS transistor M36 are connected together.

[0051] In this embodiment, the charge pump 2 cooperates with the phase detector 1 to convert the switch control signal UP / DN of the output node of the phase detector 1 into an analog voltage or current and input it into the loop filter. By adjusting the phase of the voltage-controlled delay unit 4, the phase synchronization of the two input clocks in the phase detector 1 is finally achieved. It should be noted that some undesirable circuit effects will seriously affect the performance of the charge pump 2 during circuit design, such as clock feedthrough, charge injection / sharing, etc. This embodiment adopts a charge pump 2 with high current matching characteristics, and its structure is as follows: Figure 6 As shown, INP / INPB is a pseudo differential signal converted from the first switch control signal UP output by the phase detector 1. Similarly, INN / INNB is a pseudo differential signal converted from the second switch control signal DN output by the phase detector 1.

[0052] The loop filter 3 is a loop capacitor C1. The charge pump 2 charges and discharges the loop capacitor by outputting switching pulses, thereby achieving the purpose of controlling the voltage across the loop capacitor C1.

[0053] In the circuit of the charge pump 2, the seventh to tenth MOS transistors M7 to M10 form a current mirror structure, and the fifteenth to eighteenth MOS transistors M15 to M18 form a current mirror structure. The first to sixth MOS transistors M1 to M6 and the eleventh to fourteenth MOS transistors M11 to M14 form a bias circuit capable of providing a bias voltage for the current mirror. The seventh MOS transistor M7 and the eighth MOS transistor M8, the fifteenth MOS transistor M15 and the sixteenth MOS transistor M16, and the nineteenth to twenty-fourth MOS transistors M19 to M24 can provide a normally open path for the current of the charge pump 2 and can also improve the stability of the bias voltage. The ninth MOS transistor M9, the tenth MOS transistor M10, the seventeenth MOS transistor M17, the eighteenth MOS transistor M18, and the twenty-fifth MOS transistor M25 to the thirty-sixth MOS transistor M36 are used to implement the main functions of the charge pump 2. The ninth MOS transistor M9 and the tenth MOS transistor M10, as well as the seventeenth MOS transistor M17 and the eighteenth MOS transistor M18, form a current mirror structure to provide an operating current for the charge pump 2 when it is working.

[0054] Among them, the first MOS transistor M1 to the fourth MOS transistor M4, the seventh MOS transistor M7 to the tenth MOS transistor M10, and the fifteenth MOS transistor M15 to the eighteenth MOS transistor M18 in the charge pump 2 are low-voltage cascode current mirrors. Due to their high output impedance, the cascode current mirrors can improve the current matching between the charging path and the discharging path in the charge pump 2. The output voltage range of the charge pump 2 is limited by the voltage dropped across the current mirror. To this end, this embodiment uses a cascode current mirror based on a low-voltage architecture. This not only effectively reduces the voltage loss of the current mirror branches, but also further expands the output voltage range of the charge pump 2 during operation by increasing the output impedance of the current mirror.

[0055] In order to reduce the impact of charge injection and clock feedthrough effects, a transmission gate is used as a structure to control the switch of charge pump 2, such as the 31st MOS tube M31 and the 32nd MOS tube M32 and the 35th MOS tube M35 and the 36th MOS tube M36. During the switch-off process, the electrons in the N tube and the holes in the P tube in the transmission gate are released, and the sum of the equivalent currents of the two is zero, which suppresses charge injection; by applying clock signals with opposite phases to the NMOS and PMOS devices, the coupling and interference of the two on the output node cancel each other out, thereby achieving dynamic compensation of clock feedthrough. To address the charge sharing problem, a rail-to-rail operational amplifier is used to construct a unity gain buffer, which is connected across the charge pump 2 output nodes I_OUT and IOUT_DUM. Its equivalent circuit diagram is shown below. Figure 7As shown in FIG, the potentials of the output nodes I_OUT and IOUT_DUM are forced to be synchronized through the negative feedback mechanism, thereby effectively reducing charge sharing.

[0056] In some embodiments, as Figure 2 and Figure 8 As shown, the voltage-controlled delay unit 4 includes: a reference clock buffer 41 and a voltage-controlled delay line 42; the reference clock buffer 41 is connected to the voltage-controlled delay line 42, and the reference clock buffer 41 is used to access the reference clock and convert the reference clock into a differential input signal and input it into the voltage-controlled delay line 42; the voltage-controlled delay line 42 is connected to the phase detector 1, and the voltage-controlled delay unit 4 is used to access the differential input signal and output the first multi-phase injection clock signal to the phase detector 1 and the multi-phase injection locked oscillator.

[0057] In this embodiment, the reference clock buffer 41 is a large-size buffer, which can ensure that the reference clock has a high driving capability when it is input from the off-chip crystal oscillator to the delay locked loop, and the phase noise does not deteriorate too much after passing through the first buffer 7. At the same time, it can convert the single-ended reference clock into a differential input signal and input it into the voltage-controlled delay line 42. The voltage-controlled delay line 42 is controlled by the control voltage to delay the output of the first multi-phase injection clock signal.

[0058] In some embodiments, as Figure 8 As shown in a, the voltage-controlled delay line 42 includes a plurality of cascaded first delay units 421, each of which outputs a differential clock signal, and the differential clock signals output by each of the first delay units 421 together constitute the first multi-phase injection clock signal.

[0059] In this embodiment, the voltage-controlled delay line 42 is composed of a plurality of cascaded first delay units 421. The input signals at the non-inverting input and the inverting input of each first delay unit 421 are 180° out of phase. For example, the differential signals DL0 and DL180, the differential signals DL225 and DL45, the differential signals DL90 and DL270, and the differential signals DL315 and DL135 all have a 180° phase difference. The last first delay unit 421 outputs differential signals DL180_DUM and DL0_DUM. The output signals of each first delay unit 421 collectively constitute the first multi-phase injection clock signal.

[0060] In some embodiments, as Figure 8As shown in b, the first delay unit 421 includes: a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a switched capacitor circuit 422, a fixed capacitor C0, a first variable capacitor C2, and a second variable capacitor C3. The input ends of the first inverter INV1 and the second inverter INV2 are connected to the differential input signal, and the output ends of the first inverter INV1 and the second inverter INV2 are respectively connected to the two output ends of the voltage-controlled delay line 42; the third inverter INV3 and the fourth inverter INV4 are connected across the two output ends of the voltage-controlled delay line 42; the fixed capacitor is connected across the two output ends of the voltage-controlled delay line 42; the first variable capacitor C2 and the second variable capacitor C3 are connected across the two output ends of the voltage-controlled delay line; and the switched capacitor circuit 422 is connected across the two output ends of the voltage-controlled delay line 42. The switched capacitor circuit 422 is used to adjust the delay adjustment range of the first delay unit 421.

[0061] In this embodiment, the first inverter INV1 and the second inverter INV2 form a pair of large main inverters, while the third inverter INV3 and the fourth inverter INV4 form a pair of small cross-coupled inverters. These two pairs of inverters form a pseudo-differential delay unit based on the cross-coupled inverters, capable of outputting eight clock phases, DL0-DL315. The first inverter INV1 and the second inverter INV2 delay the input signals Vi_p and Vi_n (the input signals Vi_p and Vi_n include the differential signals DL0 and DL180, the differential signals DL225 and DL45, the differential signals DL90 and DL270, and the differential signals DL180_DUM and DL0_DUM) to produce the output signals Vo_p and Vo_n. The third inverter INV3 and the fourth inverter INV4 are connected across the two output terminals of the voltage-controlled delay line 42 to ensure that the two output signals are differential signals. The switched capacitor circuit 422 uses a three-position switch control to expand the delay adjustment range of the pseudo-differential delay unit and avoid large phase errors caused by PVT (process, voltage, and temperature) variations. The continuous delay of the pseudo-differential delay unit is achieved by connecting a first variable capacitor C2, a second variable capacitor C3, and a fixed capacitor C0 between the two output terminals. The control voltage Vtune is connected to the common terminal of the first and second variable capacitors C2 and C2.

[0062] The delay of each stage of the voltage-controlled delay line 42 is expressed as one-eighth of a 100 MHz clock cycle (T100M / 8) in the time domain, and as a 45° phase shift in each stage. Furthermore, in order to lock the delay of each stage to T100M / 8 through a delay-locked loop, a delay unit of the same level is connected after the last delay unit (i.e., Figure 3 The dummy stage delay unit in the voltage-controlled delay line 42 outputs differential signals DL0_DUM and DL180_DUM, which lag one clock cycle behind the differential signals DL0 and DL180, for phase detection. That is, the input signals CK1 / CK2 are the differential signals DL0_DUM and DL180_DUM of the voltage-controlled delay line 42, which are output after passing through the first buffer 7. At the same time, each stage of the voltage-controlled delay line 42 is cascaded with an inverter-based buffer (i.e., the first buffer 7) to shape the output waveform into a square wave, while preventing the symmetry of each stage of the voltage-controlled delay line 42 from being destroyed.

[0063] In some embodiments, as Figure 8 As shown in FIG. 2( b ), the first inverter INV1 includes a 37th MOS transistor M37 and a 38th MOS transistor M38, the second inverter INV2 includes a 39th MOS transistor M39 and a 40th MOS transistor M40, the third inverter INV3 includes a 41st MOS transistor M41 and a 42nd MOS transistor M42, and the fourth inverter INV4 includes a 43rd MOS transistor M43 and a 44th MOS transistor M44.

[0064] The gates of the thirty-seventh MOS transistor M37 and the thirty-eighth MOS transistor M38 are connected to the input signal Vi_p, the drains of the thirty-seventh MOS transistor M37 and the thirty-eighth MOS transistor M38 are connected to the output end of the voltage-controlled delay line 42, the source of the thirty-seventh MOS transistor M37 is connected to the power supply voltage, and the source of the thirty-eighth MOS transistor M38 is grounded; the gates of the thirty-ninth MOS transistor M39 and the fortieth MOS transistor M40 are connected to the input signal Vi_n, the drains of the thirty-ninth MOS transistor M40 and the fortieth MOS transistor M40 are connected to the output end, the source of the thirty-ninth MOS transistor M39 is connected to the power supply voltage, and the source of the fortieth MOS transistor M40 is grounded.

[0065] The gates of the forty-first MOS transistor M41 and the forty-second MOS transistor M42 are connected to the output terminal Vo_p, the drains of the forty-first MOS transistor M41 and the forty-second MOS transistor M42 are connected to the output terminal Vo_n, the source of the forty-first MOS transistor M41 is connected to the power supply voltage, and the source of the forty-second MOS transistor M42 is grounded; the gates of the forty-third MOS transistor M43 and the forty-fourth MOS transistor M44 are connected to the output terminal Vo_n, the drains of the forty-third MOS transistor M43 and the forty-fourth MOS transistor M44 are connected to the output terminal Vo_p, the source of the forty-third MOS transistor M43 is grounded, and the source of the forty-fourth MOS transistor M44 is grounded.

[0066] In some embodiments, as Figure 9 As shown, the multi-phase injection-locked ring oscillator 5 includes a plurality of cascaded second delay units 51 and a first switch tube Q1 and a second switch tube Q2 connected to each second delay unit 51; the gates of the first switch tube Q1 and the second switch tube Q2 are connected to the first multi-phase injection clock signal, the drain of the first switch tube Q1 is connected to the non-inverting terminal of the second delay unit 51, the source of the first switch tube Q1 is grounded, the drain of the second switch tube Q2 is connected to the inverting terminal of the second delay unit 51, and the source of the second switch tube Q2 is grounded; the output end of the second delay unit 51 is connected to the edge combiner 6; the differential clock signal output by each second delay unit 51 together constitutes the second multi-phase injection clock signal.

[0067] In this embodiment, the second delay unit 51 has the same structure as the first delay unit 421, and the control voltage of the multi-phase injection-locked ring oscillator 5 is connected to the control voltage in the delay-locked loop, and the delay of the first delay unit 421 is equal to the delay of the second delay unit 51. The same delay unit and the same control voltage ensure that when injection locking of the delay-locked loop occurs, the free oscillation frequency of the multi-phase injection-locked ring oscillator 5 is equal to the injection clock frequency. The first multi-phase injection clock signal is input to the first and second switching transistors. In this embodiment, the differential signals of the first multi-phase injection clock signal input to the first switching transistor Q1 and the second switching transistor Q2 are represented as INJ0 and INJ180, INJ225 and INJ45180, INJ90 and INJ270, and INJ315 and INJ135, respectively. The differential signals output by the second delay unit 51 at each stage are represented as R0_0 and R0_180, R0_225 and R0_45, R0_90 and R0_270, and R0_315 and R0_135. In one implementation, the input strength of the first multi-phase injection clock signal is 0.3.

[0068] In some embodiments, as Figure 10 As shown, the edge combiner 6 includes: a second NOR gate NOR2, a third NOR gate NOR3, a fourth NOR gate NOR4, a fifth NOR gate NOR5, a sixth NOR gate NOR6, a seventh NOR gate NOR7, and an AND gate AND1. The inputs of the second NOR gate NOR2, the third NOR gate NOR3, the fourth NOR gate NOR4, and the fifth NOR gate NOR5 are connected to the second multi-phase injection clock signal; the outputs of the second NOR gate NOR2 and the third NOR gate NOR3 are respectively connected to the input of the sixth NOR gate NOR6; the outputs of the fourth NOR gate NOR4 and the fifth NOR gate NOR5 are respectively connected to the input of the seventh NOR gate NOR7; the outputs of the sixth NOR gate NOR6 and the seventh NOR gate NOR7 are respectively connected to the input of the AND gate AND1, and the output of the AND gate AND1 outputs a quadruple frequency clock.

[0069] In this embodiment, the edge combiner 6 generates a high-frequency output by edge detection and logical combination of multi-phase signals. In this embodiment, the edge combiner 6 is a circuit that can increase the frequency of the input signal to four times. The first multi-phase injection clock signal is an eight-phase input signal, including inputs V0, V225, V45, V180, V90, V315, V135, and V270. The multi-stage logic gate is composed of a second NOR gate NOR2, a third NOR gate NOR3, a fourth NOR gate NOR4, a fifth NOR gate NOR5, a sixth NOR gate NOR6, a seventh NOR gate NOR7, and an AND gate AND1. Figure 9 As shown, the edge combiner 6 uses eight-phase input signals and multi-level logic gates to achieve efficient quadruple frequency function. Figure 9 As shown, the edges of the eight-phase output clock are evenly distributed on the time axis, ensuring that the pulse sequences of the logic gates do not overlap during edge combination. The input of the edge combiner 6 is the output of the previous-stage multiphase injection-locked ring oscillator 5. The phase error of this set of eight-phase signals is less than 1°. After frequency multiplication, a 400MHz clock with a duty cycle of 50% can be obtained.

[0070] To further illustrate the effect of the present invention, the Figure 2 The reference clock frequency multiplier designed by the present invention is realized based on CMOS technology. The low-frequency part power supply voltage is 1 V. In order to avoid the mismatch between the voltage-controlled delay line and the delay unit of the multi-phase injection-locked ring oscillator due to PVT changes, which leads to changes in the final output frequency and phase error, the low-frequency ring oscillator designed by the present invention expands the frequency range by using a three-bit frequency control word. The frequency tuning range obtained by the final simulation is as follows: Figure 11As shown, the minimum frequency is 89.7MHz and the maximum frequency is 116.7MHz.

[0071] The phase noise of each module output is obtained by delay-locked loop, multi-phase injection-locked ring oscillator and edge combiner. Figure 12 As shown, in Figure 12 In the figure, DL represents the output signal of the first delay unit, CK_400M represents the output signal of the edge combiner, and RO represents the output signal of the second delay unit. The voltage-controlled delay line only delays the reference signal to a certain extent, so its output phase noise increases with the increase of the delay level. The phase noise of the multi-phase injection-locked ring oscillator follows the phase noise of DL135 / 315. The phase noise of the 400MHz clock obtained by the edge-combining quadrupler is 20log(4) higher than that of the multi-phase injection-locked ring oscillator. The phase noise of the 400MHz clock at a frequency offset of 1MHz is -145.7dBc / Hz, and the jitter in the integrated range from 10kHz to 40MHz is 149.7fs.

[0072] In some embodiments, the present invention further provides a chip including the reference clock frequency multiplication circuit described above, which is described in detail as a reference clock frequency multiplication circuit and will not be described in detail here.

[0073] In summary, the reference clock frequency multiplication circuit and chip provided by the present invention have the following beneficial effects: In the multi-phase clock generation circuit, a coarse-precision multi-phase clock generator is used to generate a multi-phase injection signal, namely a delay-locked loop (DLPL). An injection-locked ring oscillator with high multi-phase output phase accuracy is used as the input clock source of the edge logic combination multiplier. This can reduce the duty cycle variation of the output clock and further suppress the phase error of the multi-phase clock to obtain a high-precision multi-phase clock. The multiplied clock is then generated through the edge logic combiner. This structure combining a delay-locked loop and a multi-phase injection-locked ring oscillator can break through the compromise between phase accuracy and phase noise in traditional injection-locked ring oscillators, and does not require a cascaded duty cycle calibration circuit after the edge combiner, thereby reducing costs.

[0074] It should be understood that the application of the present invention is not limited to the above examples. For those skilled in the art, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A reference clock frequency multiplication circuit, characterized in that: include: A phase detector for detecting phase differences; a charge pump and a loop filter, wherein the charge pump is connected to the phase detector, and the loop filter is connected to the charge pump, and the charge pump and the loop filter are used to generate a control voltage according to the phase difference detection signal output by the phase detector; a voltage-controlled delay unit, the voltage-controlled delay unit being connected to the loop filter and the phase detector respectively, the voltage-controlled delay unit being configured to receive a reference clock and the control voltage and output a first multi-phase injection clock signal; a multi-phase injection-locked ring oscillator, the multi-phase injection-locked ring oscillator being connected to the voltage-controlled delay unit, the multi-phase injection-locked ring oscillator being configured to receive the control voltage, suppress a phase error of the first multi-phase injection clock signal, and output a second multi-phase injection clock signal; An edge combiner is connected to the multi-phase injection locked ring oscillator, and is used to generate a multiplied frequency clock through the second multi-phase injection clock signal.

2. The reference clock frequency multiplication circuit according to claim 1, wherein: Also includes: a first buffer connected between the voltage-controlled delay unit and the phase detector; A second buffer is connected between the multi-phase injection-locked ring oscillator and the edge combiner.

3. The reference clock frequency multiplication circuit according to claim 1, wherein: The voltage-controlled delay unit includes: a reference clock buffer and a voltage-controlled delay line; The reference clock buffer is connected to the voltage-controlled delay line, and is used to receive a reference clock and convert the reference clock into a differential input signal and input it into the voltage-controlled delay line; The voltage-controlled delay line is connected to the phase detector, and the voltage-controlled delay unit is used to access the differential input signal and output a first multi-phase injection clock signal to the phase detector and the multi-phase injection locked oscillator.

4. The reference clock frequency multiplication circuit according to claim 3, wherein: The voltage-controlled delay line includes a plurality of cascaded first delay units, each of which outputs a differential clock signal, and the differential clock signals output by each of the first delay units together constitute the first multi-phase injection clock signal.

5. The reference clock frequency multiplication circuit according to claim 4, wherein: The first delay unit includes: a first inverter, a second inverter, a third inverter, a fourth inverter, a switched capacitor circuit, a fixed capacitor, a first variable capacitor and a second variable capacitor; The input ends of the first inverter and the second inverter are connected to the differential input signal, and the output ends of the first inverter and the second inverter are respectively connected to the two output ends of the voltage-controlled delay line; The third inverter and the fourth inverter are connected across the two output ends of the voltage-controlled delay line; The fixed capacitor is connected across the two output terminals of the voltage-controlled delay line; The first variable capacitor and the second variable capacitor are connected across the two output terminals of the voltage-controlled delay line; A switched capacitor circuit is connected across two output terminals of the voltage-controlled delay line, and the switched capacitor circuit is used to adjust a delay adjustment range of the first delay unit.

6. The reference clock frequency multiplication circuit according to claim 1, wherein: The multi-phase injection-locked ring oscillator includes a plurality of cascaded second delay units and a first switch tube and a second switch tube connected to each of the second delay units; The gates of the first switching transistor and the second switching transistor are connected to the first multi-phase injection clock signal, the drain of the first switching transistor is connected to the non-inverting terminal of the second delay unit, the source of the first switching transistor is grounded, the drain of the second switching transistor is connected to the inverting terminal of the second delay unit, and the source of the second switching transistor is grounded; The output end of the second delay unit is connected to the edge combiner; the differential clock signals output by each second delay unit together constitute the second multi-phase injection clock signal.

7. The reference clock frequency multiplication circuit according to claim 1, wherein: The phase detector includes: a first trigger, a second trigger, a first NOR gate and an inverter chain group; The clock terminals of the first flip-flop and the second flip-flop are connected to the first multi-phase injection clock signal; The inverting output terminals of the first flip-flop and the second flip-flop are connected to the input terminal of the first NOR gate; The output end of the first NOR gate is connected to the input end of the inverter chain group, and the output end of the inverter chain group is connected to the reset end of the first flip-flop and the reset end of the second flip-flop respectively; The output terminal of the first trigger outputs a first switch control signal, and the output terminal of the second trigger outputs a second switch control signal; The first switch control signal and the second switch control signal constitute a phase difference detection signal output by the phase detector.

8. The reference clock frequency multiplication circuit according to claim 1, wherein: The charge pump includes: a bias circuit, a first current mirror, a second current mirror, a normally open path providing unit and a charge pump unit; The bias circuit is connected to a reference current and is connected to the first current mirror and the second current mirror respectively, and the bias circuit is used to provide a bias voltage for the first current mirror and the second current mirror; The third current mirror is connected to the power supply voltage and is connected to the charge pump unit, and the third current mirror is used to provide an operating current for the charge pump unit; The normally open path providing unit is connected between the first current mirror and the third current mirror, and the normally open path providing unit is used to provide a normally open path for the working current of the charge pump unit; The charge pump unit is connected between the first current mirror and the third current mirror, and is used to generate a control voltage based on the phase difference detection signal output by the phase detector.

9. The reference clock frequency multiplication circuit according to claim 1, wherein: The edge combiner includes: a second NOR gate, a third NOR gate, a fourth NOR gate, a fifth NOR gate, a sixth NOR gate, a seventh NOR gate and an AND gate; The second multi-phase injection clock signal is connected to the input terminals of the second NOR gate, the third NOR gate, the fourth NOR gate and the fifth NOR gate; The output ends of the second NOR gate and the third NOR gate are connected to the input end of the sixth NOR gate respectively; the output ends of the fourth NOR gate and the fifth NOR gate are connected to the input end of the seventh NOR gate respectively; The output end of the sixth NOR gate and the output end of the seventh NOR gate are connected to the input end of the AND gate respectively, and the output end of the AND gate outputs a quadruple frequency clock.

10. A chip, characterized in that: The method comprises the reference clock frequency multiplication circuit as described in any one of claims 1 to 9.

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