Processing system for audio data

Abstract

The application relates to a processing system of audio data and relates to the technical field of audio processing; the system comprises a first storage module used for storing latest first-level to-be-processed data corresponding to each of received to-be-processed audio data; a filter connected with the first storage module and used for performing audio sampling rate conversion processing on each level of to-be-processed data to obtain each level of sampling rate converted data corresponding to each of the to-be-processed audio data; a second storage module connected with the filter and the first storage module respectively and used for storing the sampling rate converted data; and the second storage module is further used for transmitting the sampling rate converted data to the first storage module as Nth-level to-be-processed data corresponding to each of the to-be-processed audio data; and the sampling rate converted data of each Nth-1 to-be-processed data output by the filter is target processed audio data corresponding to each of the to-be-processed audio data; and the system is beneficial to reducing hardware overhead of audio sampling rate conversion.

Description

Technical Field

[0001] This application relates to the field of audio processing technology, and in particular to an audio data processing system. Background Technology

[0002] Audio sampling rate conversion is the process of converting an audio signal from one sampling rate to another. In related technologies, for upsampled audio signals, low-pass filtering and phase compensation are performed before downsampling. This method of audio sampling rate conversion has high storage requirements and high computational demands, resulting in significant hardware overhead for audio processing systems. Summary of the Invention

[0003] Therefore, it is necessary to provide an audio data processing system that can reduce hardware overhead during the sampling rate conversion of audio data.

[0004] This application provides an audio data processing system, including:

[0005] The first storage module is used to store the first-level data to be processed corresponding to each of the received audio data to be processed, and to update the storage to store the Nth-level data to be processed when receiving any Nth-level data to be processed corresponding to the first-level data to be processed; N≥2 and N is a positive integer;

[0006] The filter, electrically connected to the first storage module, is used to perform audio sampling rate conversion processing on at least each level of the audio data to be processed from the first level to the (N-1)th level of the audio data to be processed, and to obtain the data after sampling rate conversion corresponding to each level of the audio data to be processed.

[0007] The second storage module is electrically connected to the filter and the first storage module, respectively, and is used to store the data after conversion of each level of sampling rate corresponding to each of the audio data to be processed; it is also used to transmit the data after conversion of each level of sampling rate corresponding to each of the audio data to be processed to the first storage module, so as to serve as the Nth level of data to be processed corresponding to each of the audio data to be processed.

[0008] Wherein, the sample rate converted data of the N-1th level of the audio data to be processed corresponding to each of the audio data to be processed output by the filter is the processed target audio data corresponding to each of the audio data to be processed.

[0009] The audio data processing system provided in this application involves at least a first storage module, a filter, and a second storage module. These three modules are electrically connected to each other. The first storage module stores the first-level data to be processed corresponding to each received audio data to be processed, and updates its storage to store the Nth-level data to be processed upon receiving any Nth-level data corresponding to any first-level data. The filter performs audio sampling rate conversion processing on at least each level of the audio data to be processed, from the first-level data to the (N-1)th-level data, to obtain the converted data corresponding to each level of the audio data. The second storage module stores the converted data corresponding to each level of the audio data to be processed; it also processes the converted data corresponding to each level of the audio data to be processed. The data is transmitted to the first storage module as the Nth level data to be processed corresponding to each audio data to be processed. It can be seen that the filter in the audio data processing system provided in this application can obtain the processed target audio data corresponding to the audio data to be processed by performing multi-level audio processing operations on each audio data to be processed. By setting the first storage module and the second storage module to store different data or different types of data in the audio data processing stage, and by using a filter to realize the sequential polling processing of the multi-level data corresponding to the audio data to be processed, it is beneficial to reduce the number of devices required in the audio data processing system for converting the sampling rate of the audio data, that is, it is beneficial to reduce the hardware resource consumption of the audio data processing system, especially by significantly reducing the number of filters required, which is beneficial to reducing the electrical structure complexity of the audio data processing system and also beneficial to reducing the manufacturing cost of the audio data processing system. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A schematic diagram of the audio data processing system provided in the embodiments of this application;

[0012] Figure 2 Another schematic diagram of the audio data processing system provided in the embodiments of this application;

[0013] Figure 3Another schematic diagram of the audio data processing system provided in the embodiments of this application;

[0014] Figure 4 Another schematic diagram of the audio data processing system provided in the embodiments of this application;

[0015] Figure 5 This is a schematic diagram of the filter parameter design in one of the embodiments provided in this application;

[0016] Figure 6 A flowchart illustrating the audio data processing system provided in this application.

[0017] Figure 7 This is a schematic diagram of the operational logic of an audio data processing system provided in the embodiments of this application. Detailed Implementation

[0018] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0020] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another.

[0021] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0022] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0023] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0024] As described in the background section, the audio sampling rate conversion methods provided in related technologies have high storage requirements and high computational demands, resulting in high hardware overhead for audio processing systems. Therefore, it is necessary to provide an audio data processing system that can reduce hardware overhead during the audio data sampling rate conversion process.

[0025] Please refer to Figure 1 This application provides an audio data processing system, comprising:

[0026] The first storage module 11 is used to store the first-level data to be processed corresponding to each of the received audio data to be processed, and to update the storage to store the Nth-level data to be processed when receiving the Nth-level data to be processed corresponding to any first-level data to be processed; N≥2 and N is a positive integer;

[0027] Filter 12 is electrically connected to the first storage module 11 and is used to perform audio sampling rate conversion processing on at least the first level to the (N-1)th level of the audio data to be processed, and to obtain the data after sampling rate conversion corresponding to each level of the audio data to be processed.

[0028] The second storage module 13 is electrically connected to the filter 12 and the first storage module 11 respectively. It is used to store the data after conversion of each level of sampling rate corresponding to each audio data to be processed. It is also used to transmit the data after conversion of each level of sampling rate corresponding to each audio data to be processed to the first storage module 11 as the Nth level of data to be processed corresponding to each audio data to be processed.

[0029] Among them, the sample rate converted data of the N-1 level of the audio data to be processed corresponding to each audio data to be processed output by filter 12 is the processed target audio data corresponding to each audio data to be processed.

[0030] Specifically, the audio data processing system 100 provided in this application includes at least a first storage module 11, a filter 12, and a second storage module 13. The first storage module 11 and the filter 12 may be electrically connected, and the first storage module 11 can be used to transmit data stored in the first storage module 11 to the filter 12. The filter 12 and the second storage module 13 may also be electrically connected, and the filter 12 can be used to transmit the result (data after sampling rate conversion) obtained after processing the data to be processed to the second storage module 13. In addition, the second storage module 13 can also transmit data stored in the second storage module 13 to the filter 12. The second storage module 13 can also be used to transmit data stored in the second storage module 13 to the first storage module 11.

[0031] For example, the first storage module 11 provided in this application can be used to store the received audio data to be processed. The first data received and stored is the first-level data to be processed of each audio data to be processed. After the first-level data to be processed of each audio data to be processed is first transmitted to the filter 12 for audio sampling rate conversion processing, the first-level sample rate converted data corresponding to the first-level data to be processed output by the filter 12 will be obtained. Then, the filter 12 will send the first-level sample rate converted data to the second storage module 13, and the second storage module 13 will store the first-level sample rate converted data and simultaneously transmit the first-level sample rate converted data to the first storage module 11. Upon receiving the first-level sample rate converted data, the first storage module 11 stores the first-level sample rate converted data as the second-level data to be processed. Simultaneously, before storing the second-level data, it deletes the corresponding first-level data to be processed, ensuring that the first storage module 11 always stores only one level of data corresponding to a single audio data to be processed. Furthermore, the second-level data to be processed can be transmitted to the filter 12 via the first storage module 11, or the first-level sample rate converted data can be transmitted to the filter 12 via the second storage module 13, so that the filter 12... Further, the second-level data corresponding to the first-level data to be processed in the currently processed audio data undergoes audio sampling rate conversion processing. After processing the second-level data, filter 12 will obtain the second-level sample rate converted data corresponding to the second-level data to be processed output by filter 12. Then, filter 12 will send the second-level sample rate converted data to the second storage module 13, which will store the second-level sample rate converted data and simultaneously transmit it to the first storage module 11. Upon receiving the second-level sample rate converted data, the first storage module 11 will use the second-level sample rate converted data as... The third-level data to be processed is stored. Before storing the third-level data to be processed, the corresponding second-level data to be processed is deleted, so that the first storage module 11 always stores only one level of data to be processed corresponding to the audio data to be processed. Furthermore, the third-level data to be processed can be transmitted to the filter 12 through the first storage module 11, or the second storage module 13 can transmit the data after the second-level sampling rate conversion as the third-level data to be processed to the filter 12, so that the filter 12 can further perform audio sampling rate conversion processing on the third-level data to be processed corresponding to the second-level data to be processed of the audio data being processed.

[0032] By cooperating with the first storage module 11, the filter 12, and the second storage module 13, and referring to the above-described cyclic processing method for the first to third levels of audio data to be processed, multi-level filtering processing of each level of data to be processed can be achieved.

[0033] The “each audio data to be processed” mentioned above can refer to multiple different audio data to be processed. The current sampling rate of each audio data to be processed can be the same, or it can be set to be different. This application does not make any specific limitation in this regard.

[0034] In an exemplary embodiment, if a certain audio data to be processed only requires two levels of processing by filter 12 to obtain the corresponding target audio data, then, referring to the above embodiment, the data after the second-level sampling rate conversion, or the data after the sampling rate conversion of the (3-1)-level data to be processed, is the processed target audio data corresponding to the audio data to be processed.

[0035] In summary, the filter 12 in the audio data processing system 100 provided in this application can obtain the processed target audio data corresponding to the audio data to be processed by performing multi-level audio processing operations on each audio data to be processed. By setting the first storage module 11 and the second storage module 13 to store different data or different types of data in the audio data processing stage, and by using a filter 12 to perform sequential polling processing on the multi-level data corresponding to the audio data to be processed, it is beneficial to reduce the number of devices required in the audio data processing system 100 for converting the sampling rate of the audio data, that is, to reduce the hardware resource consumption of the audio data processing system 100, especially by significantly reducing the number of filters 12 required, which is beneficial to reducing the electrical structure complexity of the audio data processing system 100 and also to reducing the manufacturing cost of the audio data processing system 100.

[0036] Please refer to Figure 2 In an exemplary embodiment, the audio data processing system 100 provided in this application further includes: a third storage module 17, electrically connected to the filter 12, for storing the number of taps of each level of the filter 12 adapted to perform audio sampling rate conversion processing on each level of data to be processed.

[0037] Specifically, the audio data processing system 100 of this application may be further configured to include a third storage module 17 for providing the number of filter taps required for each level of filter 12 during operation. The third storage module 17 may store the number of filter taps corresponding to multiple filters 12. The third storage module 17 may be configured to be directly electrically connected to the filter 12 and to provide it with an appropriate number of taps (filter coefficients) according to the working requirements of the filter 12.

[0038] As can be seen, by setting up a third storage module 17 separately, this application can reduce the storage capacity requirements of the first storage module 11 and the second storage module 13, and also avoid the high frequency of use of a single storage module when storing multiple types of data in one storage module. This avoids the problem of blocking during data storage and retrieval, and also avoids the problem of cross-interference of data. This is conducive to ensuring the stability and accuracy of data transmission in the audio data processing system 100.

[0039] Furthermore, the filter 12 provided in this application can meet the multi-level processing requirements of a piece of audio data to be processed. For example, if a piece of audio data to be processed needs to undergo 5 levels of processing, it is not necessary to use 5 filters 12, but only 1 filter 12 is needed to complete the 5 levels of processing of the audio data to be processed, and thus obtain the target audio data of the audio data to be processed.

[0040] Furthermore, the filter 12 provided in this application can perform multi-level processing on the relevant audio data to be processed based on the sequential requirements of multi-level processing. During each level of processing, the filter 12 can also be provided with appropriate filter coefficients through the third storage module 17. This ensures that the audio data processing system 100 provided in this application can accurately process the audio data to be processed, and achieves audio data processing using fewer component modules. It also helps to reduce the circuit complexity and manufacturing cost of the audio data processing system 100.

[0041] In an exemplary embodiment, the filter 12 includes a multiplier and an accumulator; wherein the output of the multiplier is electrically connected to the input of the accumulator, the input of the multiplier is used to receive data to be processed at each stage, and the output of the accumulator is used to output the data after sampling rate conversion corresponding to each stage of audio data to be processed.

[0042] Specifically, the filter 12 may include at least a multiplier and an accumulator that are electrically connected. The output of the multiplier may be electrically connected to the input of the accumulator. The input of the multiplier is used to receive audio data to be processed at each level (level 1 to level N). After each level of audio data to be processed is processed by the multiplier and the accumulator respectively and sequentially, the sample rate converted data corresponding to each level of audio data to be processed can be output. The sample rate converted data of level N corresponding to the audio data to be processed output by the filter 12, or the sample rate converted data of level N-1 corresponding to the audio data to be processed, is the processed target audio data corresponding to the audio data to be processed.

[0043] In one exemplary embodiment, please refer to Figures 2-4 The audio data processing system 100 provided in this application further includes:

[0044] The data receiving module 14 is electrically connected to the first storage module 11 and the filter 12 respectively, and includes multiple data receiving channels. Each data receiving channel is used to receive different audio data to be processed and transmit them to the first storage module 11 and the filter 12 respectively.

[0045] The data output module 15 is electrically connected to the filter 12 and includes multiple data output channels. It is used to receive the sample rate converted data of the N-1 level of the audio data to be processed corresponding to each audio data to be processed output by the filter 12, and output the sample rate converted data of the N-1 level of the audio data to be processed corresponding to each audio data to be processed through each data output channel, as the processed target audio data corresponding to each audio data to be processed.

[0046] Specifically, the data receiving module 14 includes a data receiving channel that can be as follows: Figure 4 The pcmfifo_0 to pcmfifo_7 shown, the data output channels included in the data output module 15, can be as follows: Figure 4 The diagram shows fltfifo_0 to fltfifo_7. Among these, the eight data receiving channels shown (pcmfifo_0 to pcmfifo_7) can be used to simultaneously input eight different audio data to be processed. Similarly, the eight data output channels shown (fltfifo_0 to fltfifo_7) can be used to simultaneously output the target audio data corresponding to each of the eight different audio data to be processed.

[0047] When the data receiving module 14 receives each audio data to be processed through its multiple data receiving channels, it will transmit each audio data to be processed to the first storage module 11 and the filter 12 respectively, so that the first storage module 11 can process each audio data to be processed, and at the same time the filter 12 can perform the first-level filtering processing on each audio data to be processed (first-level data to be processed).

[0048] The data output module 15 is used to acquire the sample rate converted data (Nth level sample rate converted data) of the N-1th level audio data to be processed corresponding to each audio data to be processed through its multiple data output channels, that is, to acquire the target audio data corresponding to each audio data to be processed, and then output the target audio data to the outside through each data output channel.

[0049] In an exemplary embodiment, the audio data processing system 100 provided in this application further includes: a filter parameter control module 16, which is electrically connected to the data receiving module 14 and the filter 12 respectively; it is used to determine a sequence of conversion factors of each level of the filter 12 adapted to perform audio sampling rate conversion processing on each level of the audio data to be processed based on the current sampling rate and the target sampling rate of each audio data to be processed; and it is used to determine the filter type parameter of the filter 12 based on at least one of the audio features of the audio data to be processed, the signal index features corresponding to the target sampling rate, and the audio processing resource features of the local end; wherein, the conversion factor sequence includes at least one conversion factor, which is used to characterize the change in the amount of data after the filter 12 performs audio sampling rate conversion processing on the audio data to be processed.

[0050] Specifically, such as Figure 3 As shown, the filter parameter control module 16 can be electrically connected between the data receiving module 14 and the filter 12. Alternatively, the filter parameter control module 16 can be integrated inside the filter 12 as a unit within the filter 12. The filter parameter control module 16 can be configured to receive each audio data to be processed (first-level audio data to be processed), and determine the number of levels of the filter 12 to be used and the conversion factors of each level of the filter 12 based on the current sampling rate and the target sampling rate of each audio data to be processed, so as to obtain a sequence of conversion factors corresponding to each level of the filter 12 suitable for processing each audio data to be processed. Furthermore, the filter parameter control module 16 can also be configured to determine the filter type of each level of the filter 12 by at least one of the audio characteristics of the audio data to be processed, the signal index characteristics corresponding to the target sampling rate, and the audio processing resource characteristics of the local end.

[0051] The conversion factor is used to characterize the ratio of the amount of audio data to be processed before processing to the amount of data after processing when processed by filter 12.

[0052] In one exemplary embodiment, please refer to Figure 3 Reference Figure 4 The first storage module 11 includes a number of data storage channels equal to the number of data receiving channels; each data storage channel is used to store the first-level data to be processed corresponding to the audio data to be processed received by each data receiving channel, and when the Nth-level data to be processed corresponding to any first-level data to be processed is received, it is updated to store the Nth-level data to be processed.

[0053] Specifically, data storage channels such as Figure 4 The ch_0, ch_1, ... shown can be set to have the same number of data storage channels as the number of data receiving channels in the first storage module 11. For example, if there are 8 data receiving channels, then the number of data storage channels can also be set to 8.

[0054] Each data storage channel can be optionally configured to store the first-level unprocessed data corresponding to the audio data to be processed received by each data receiving channel. When the second-level unprocessed data corresponding to the first-level unprocessed data is subsequently received, the previously stored first-level unprocessed data is deleted and replaced with the second-level unprocessed data corresponding to the deleted first-level unprocessed data. When the third-level unprocessed data corresponding to the second-level unprocessed data is subsequently received, the previously stored second-level unprocessed data is deleted and replaced with the third-level unprocessed data corresponding to the deleted second-level unprocessed data.

[0055] That is, in the first storage module 11 provided in this application, each data storage channel will always store only one piece of data.

[0056] like Figure 4 As shown, DHIS RAM represents the aforementioned first storage module 11, DOUT RAM represents the aforementioned second storage module 13, MUL ACC represents the aforementioned filter 12, and COEF RAM represents the aforementioned third storage module 17.

[0057] Please continue to combine Figure 3 Reference Figure 4 In one exemplary embodiment, the number of data receiving channels and data output channels are the same; the data output channel in a matching set of data receiving channels and data output channels is used to output the target audio data corresponding to the audio data to be processed received by the matching data receiving channel.

[0058] Specifically, the data receiving channel and the data output channel can be set to a one-to-one matching correspondence. For example, when pcmfifo_0 and fltfifo_0 are set to match, pcmfifo_0 is used to receive the first audio data to be processed, while fltfifo_0 is used to receive the first target audio data corresponding to the first audio data to be processed, and outputs the first target audio data to the outside of the audio data processing system 100.

[0059] Please continue to combine Figure 3 Reference Figure 4 In one exemplary embodiment, the number of data receiving channels and data output channels is M, where M≥8 and M is a positive integer; multiple data receiving channels and multiple data output channels transmit data based on the first-in-first-out principle.

[0060] Specifically, in addition to setting the number of data receiving channels and data output channels to 8 as mentioned above, the number of data receiving channels and data output channels can be set to more based on demand, so that the audio data processing system 100 provided in this application can receive more audio data to be processed at the same time.

[0061] It should be noted that setting the number of data receiving channels and data output channels to at least 8 is only one optional implementation method provided by this application, but this application does not limit it, and the number of data receiving channels and data output channels can be selected according to the requirements.

[0062] The multiple data receiving channels and multiple data output channels provided in this application can be selected to transmit data based on the first-in-first-out principle.

[0063] Please continue to combine Figure 3 Reference Figure 4 In one exemplary embodiment, the audio data processing system 100 provided in this application further includes:

[0064] The first multiplexing unit has its input terminal electrically connected to the output terminal of the data receiving module 14, and its output terminal electrically connected to the input terminal of the first storage module 11 and the input terminal of the filter 12, respectively.

[0065] The input of the second multiplexing unit is electrically connected to the output of the filter 12, and the output of the second multiplexing unit is electrically connected to the input of the data output module 15.

[0066] Specifically, the first multiplexing unit can be as follows: Figure 4 The output of MUX1, the second multiplexing unit, can be as follows: Figure 4The output MUX2 is configured such that the first multiplexing unit controls which audio data from the multiple audio data to be processed received by the data receiving module 14 is transmitted to the first storage module 11 and the filter 12 at the same time. The second multiplexing unit transmits the target audio data of the audio data to be processed calculated by the filter 12 to the corresponding audio output channel.

[0067] Please continue to combine Figure 3 Reference Figure 4 In one exemplary embodiment, the audio data processing system 100 provided in this application further includes:

[0068] The third multiplexing unit has its input terminals electrically connected to the output terminals of the first multiplexing unit, the first storage module 11, and the second storage module 13, respectively; the output terminal of the third multiplexing unit is electrically connected to the input terminal of the filter 12.

[0069] The fourth multiplexing unit has its input terminal electrically connected to the output terminal of the filter 12, and its output terminal is electrically connected to the input terminal of the second storage module 13 and the input terminal of the second multiplexing unit.

[0070] Specifically, the third multiplexing unit can be as follows: Figure 4 The output of MUX3, the fourth multiplexing unit, can be as follows: Figure 4 The output of MUX4 is as follows: the third multiplexing unit is used to control that at any given time, only one of the first multiplexing unit, the first storage module 11, and the second storage module 13 transmits data to the filter 12; the fourth multiplexing unit is used to output the output data of the filter 12 to the second storage module 13 and the second multiplexing unit respectively when needed, or in other words, at the same time, it is used to select whether to output the output data of the filter 12 to the second storage module 13 or the second multiplexing unit.

[0071] In summary, the first multiplexing unit, the second multiplexing unit, the third multiplexing unit, and the fourth multiplexing unit provided in this application are all used for multiplexing.

[0072] Please combine Figure 3 and Figure 4 The audio data processing system provided in this application can be used to perform sample rate conversion on PCM (Pulse Code Modulation) format audio data with up to 8 channels. Before performing sample rate conversion, a suitable data width for the audio data can be determined to maintain good data processing accuracy and reduce memory costs.

[0073] One embodiment involves converting the audio data's sampling rate to obtain a target audio SNR > 84 dB (decibels). SNR stands for Signal to Noise Ratio. Please refer to further details. Figure 5 Correspondingly, the width of the filter tap coefficients for the multi-rate filter (e.g., FIR filter) used to process audio data can be optionally set to 21 bits; the width of historical data to 18 bits; the width of temporary results to 18 bits; multiplication is 21 bits * 18 bits, and the output is 39 bits. The "39-bit output" is to ensure that the output result does not overflow. The FIR (Finite Impulse Response) filter, also known as a non-recursive filter, is a fundamental component in digital signal processing systems. It can guarantee arbitrary amplitude-frequency characteristics while possessing strictly linear phase-frequency characteristics, and its unit sample response is finite, thus making the filter a stable system.

[0074] The values ​​of the filter tap coefficients are predetermined; historical data can be the output of any filter bank (which can be composed of multiple cascaded filters) after sampling rate conversion; temporary data can be the output of any filter, for example, the output of any one of the multiple cascaded filters.

[0075] like Figure 5 In the illustrated embodiment, when two-stage interpolation is required, if both the first and second-stage interpolation results correspond to 39 bits, the final interpolated value can also be retained as 39 bits. To reduce the amount of data in the result value, this application provides an alternative implementation method that discards the lower 20 bits and the second-highest bit (38th bit) of the result value to obtain the final 18-bit data. The reason for discarding the lower 20 bits and the second-highest bit in the accumulated 39 bits of data to obtain 18-bit audio data is due to dynamic range matching and quantization noise control.

[0076] Specifically, in the filtering operation of the sampling rate conversion, the accumulator outputs 39 bits of data (21 bits of coefficients × 18 bits of data), but the final output must meet the requirements of 18 bits width and SNR > 84dB. The operation flow is as follows: the 39-bit accumulation result is: bit 38 (MSB, Most Significant Bit), bit 37, bit 36, ... bit 1, bit 0 (LSB, Least Significant Bit); discard the lower 20 bits (bits 0-19), and retain bits 38-20 (a total of 19 bits), then discard the second highest bit (bit 37) and retain bit 38 and bits 36-20 (a total of 18 bits).

[0077] The purpose of using a 39-bit accumulator is to prevent overflow, as the filter gain may be greater than 1. The purpose of using an 18-bit output is to match the input data range of downstream modules. Discarding the lower 20 bits eliminates catastrophic noise in the audio data, effectively removing fine quantization noise and reducing the SNR by 256 times. Additionally, discarding the second-highest bit halves the signal power, further reducing the SNR by at least 6dB. Discarding the second-highest bit (bit 37) is equivalent to dividing by 2, compressing the dynamic range, preventing 18-bit overflow, and facilitating gain calibration. Furthermore, while discarding the second-highest bit halves the signal power, this is compensated for by the noise reduction from discarding lower bits. Using an 18-bit output buffer also reduces the cost of related storage hardware.

[0078] In summary, the embodiments provided in this application can retain high-order information while suppressing noise by discarding the lower 20 bits; and can compensate for filter gain and avoid saturation by discarding the second-highest bit.

[0079] After receiving PCM audio data, the 8-channel data input terminals (data input modules) simultaneously transmit the data to MUX1 for multiplexing. One selected audio data point is then output to the DHIS RAM for storage, and simultaneously transmitted to the MUL ACC via MUX3 for further processing. The output of the MUL ACC is then transmitted to the DOUT RAM via MUX4 for storage. The DOUT RAM simultaneously transmits the stored data to the DHIS RAM. Upon receiving new data, the DHIS RAM deletes the corresponding old data. The next stage of data to be processed by the MUL ACC can be transmitted to either the DHIS RAM or the DOUT RAM. Finally, the MUL ACC transmits the target audio data corresponding to each processed audio data point to the audio output terminal (audio output module) via MUX4 and MUX2. In other words, the output of MUX4 is output to the 8-channel data output terminal via MUX2. The COEF RAM is used to store filter coefficients.

[0080] The audio data processing system provided in this application has the following construction requirements (multi-channel parallel processing and data width configuration) and can achieve the corresponding technical effects.

[0081] Multi-channel parallel processing: Channel independence – each channel performs sampling rate conversion (interpolation / decimation) independently, avoiding data cross-interference. Resource sharing – filter coefficients – all channels share the same set of polyphase filter coefficients (21 bits), reducing ROM (Read-Only Memory) usage. Computation unit – employing a time-division multiplexing strategy, all 8 channels share the same set of multiply-accumulate (MAC) units, improving throughput through pipelined scheduling.

[0082] Data width configuration: 21-bit coefficient width to ensure filter frequency response accuracy (passband ripple ≤ 0.01dB, stopband attenuation ≥ 100dB). 18-bit historical data to store previous stage input samples (e.g., retain the first 7 samples for three-stage interpolation). 18-bit temporary results for storing intermediate values ​​in multi-stage filtering; saturated rounding is used to control quantization noise. The multiplier in the arithmetic unit is 21-bit × 18-bit, retaining full precision. The accumulator in the arithmetic unit is 39-bit, truncated to 18 bits after accumulation, covering a dynamic range of ±2. 17 To avoid overflow.

[0083] The audio data processing system provided in this application has the following key performance optimization strategies, including SNR guarantee and RAM cost optimization.

[0084] SNR Guarantee (>84dB): Quantization noise control; coefficient quantization, the noise power introduced by the 21-bit coefficient quantization error is 2. 42 The noise is negligible. Intermediate results are truncated; the 18-bit truncated noise power is 2. 36 The total SNR is calculated using a multi-level noise superposition formula. Anti-aliasing design includes rigorous filtering before extraction to ensure the signal bandwidth is limited to the target Nyquist frequency (24kHz), avoiding aliasing noise.

[0085] RAM cost optimization: Historical data storage. The number of samples to be stored per channel is determined by the number of filter taps (e.g., 7+5+3=15 samples for three-stage interpolation, or 8+6+4=18 samples). Total storage for 8 channels: 8×15×18 bits = 2160 bits ≈ 0.26 KB. Intermediate result reuse: Intermediate results from multi-stage interpolation (e.g., y(n)) are passed through the pipeline without additional storage, reducing buffer requirements.

[0086] Here is an example of an audio sample rate conversion:

[0087] First level: 3x interpolation (phase=3, taps=8).

[0088] Input: Original signal x(n), sampling rate Fs.

[0089] Output: Interpolated signal y(n), with the sampling rate increased to 3Fs.

[0090] The formula is as follows:

[0091] ;

[0092] ;

[0093] .

[0094] Key points include:

[0095] Each input sample generates 3 output samples (corresponding to an interpolation factor of 3).

[0096] An 8-tap filter is used, with different phases (0, 1, 2) corresponding to different coefficient groups hk_0, hk_1, hk_2, where the k value ranges from 0 to 7, to suppress image frequencies.

[0097] Historical data storage: The first 7 input samples (x(n−1) to x(n−7)) need to be retained for calculation.

[0098] The audio data processing system provided in this application has the following implementation method for the computing unit.

[0099] Multiply-Accumulate (MAC) Design: The architecture employs a single-cycle 21×18-bit multiplier and a 39-bit accumulator, supporting 8-channel time-division multiplexing. Timing: Each channel is allocated a fixed time slice (e.g., processing one tap calculation for one channel per clock cycle). The total delay for 8-channel three-stage interpolation is 8×(8+6+4)=144 cycles (pipeline optimizeable to 18 cycles).

[0100] Truncation and rounding strategy: Truncation position: The accumulator output retains the high 18 bits (discarding the low 21 bits), combined with saturation processing to prevent overflow. Rounding method: Truncate by adding a rounding constant 2 to the power of 20 to reduce mean error.

[0101] Regarding the audio data processing system provided in this application, an exemplary embodiment is provided as follows:

[0102] Input: 8-channel PCM data, sampling rate 11.025kHz; Output: 48kHz.

[0103] Interpolation stage:

[0104] First stage (3x interpolation): 11.025kHz input per channel, using an 8-tap polyphase filter (21-bit coefficients), output 33.075kHz.

[0105] Second stage (2x interpolation): Input 33.075kHz, 6-tap filter, output 66.15kHz.

[0106] Third stage (4x interpolation): Input 66.15kHz, 4-tap filter, output 264.6kHz.

[0107] Extraction phase:

[0108] After anti-aliasing filtering, the frequency is decimated by 5.5125 times (264.6kHz to 48kHz) and then merged into the final filtering stage.

[0109] As can be seen, by using a multi-channel shared computing unit (MUL ACC) and optimizing data width and truncation strategies, the system significantly reduces RAM and computing resource consumption while maintaining an SNR > 84dB. Core design features include: multi-level interpolation decomposition to balance computational complexity and accuracy; time-division multiplexing MAC for efficient support of 8-channel parallel processing; and dynamic range management, using 18-bit truncation and rounding to control quantization noise.

[0110] The audio data processing system provided in this application uses memory including, for example, the memory used in the system. Figures 1-4 The table shows three types of memory (storage modules): Coef RAM for storing FIR coefficients; DHIS RAM for storing historical data of the 8-channel multi-filter steps; and Dout RAM for storing temporary results. These three types of memory are used to achieve efficient management of data and coefficients, and their specific configurations are shown in Table 1 below.

[0111] Table 1

[0112]

[0113] The process for verifying the rationality of the design is as follows:

[0114] Coef RAM: Assuming the three-stage interpolation filter requires 8, 6, and 4 taps respectively, the total number of coefficients is 18. The 256-line capacity supports multiple filter configurations (such as multi-channel sharing or adaptation to different input sampling rates), and the redundant design provides flexibility.

[0115] DHIS RAM: 8 channels × 128 historical data records per channel (1024 / 8), meeting the needs of multi-level filtering (e.g., three-level interpolation requires storing the first 7+5+3=15 samples).

[0116] Dout RAM: 256 records support caching of multi-level intermediate results to avoid pipeline blockage.

[0117] This application provides, as follows: Figures 1-4The audio data processing system shown inputs an 8-channel synchronous FIFO and outputs a corresponding synchronous FIFO; the main calculation processes are multiplication and accumulation. Specifically:

[0118] Data flow and synchronization control involve input / output synchronization FIFOs:

[0119] Features: 8 independent FIFO channels (fitffo_0 to fitffo_7) to ensure data continuity and real-time performance.

[0120] Depth requirement: Assuming 48kHz output per channel, the input FIFO depth must cover the worst-case delay (such as the pipeline cycle of multi-stage filtering).

[0121] Bit width: Consistent with PCM data bit width (e.g., 16 / 24 bits), not specified but must match external interface.

[0122] Data flow and synchronization control also involve multiplexers (MUX):

[0123] Function: Time-division multiplexing of 8 channels of data to the shared computing unit (MAC) reduces hardware resource consumption.

[0124] Scheduling strategy: Poll by channel, process 1 tap of 1 channel per cycle, 8 channels × 18 taps = 144 cycles (can be pipelined optimized).

[0125] The design of the computing unit involves a multiply-accumulate unit (MAC):

[0126] Bit width: 21-bit coefficient × 18-bit historical data; 39-bit product, accumulator bit width 39 bits (to prevent overflow).

[0127] Truncation strategy: The accumulated result retains the high 18 bits, combined with rounding (+2). 20 To reduce quantization error and ensure SNR>84dB.

[0128] Throughput: A single MAC supports 8 channels of real-time processing (48kHz×8=384kHz), requiring a clock frequency ≥384kHz×number of taps (e.g., 18 taps converted to 6.912MHz).

[0129] The design of the computational unit also involves the implementation of multiphase filtering, including an example of three-stage interpolation:

[0130] First stage: 3x interpolation, 8 taps, generating 3 phase outputs.

[0131] Second stage: 2x interpolation, 6 taps, generating 2 phase outputs.

[0132] Third stage: 4x interpolation, 4 taps, generating 4 phase outputs.

[0133] Total interpolation factor: 3×2×4=24, supports input sampling rate conversion from 2kHz to 48kHz (if a higher ratio is required, the number of stages needs to be extended).

[0134] The key performance indicators of the audio data processing system provided in this application are shown in Table 2 below.

[0135] Table 2

[0136]

[0137] As can be seen, the audio data processing system provided in this application achieves real-time sampling rate conversion (up to 48kHz) of 8-channel PCM data through multi-level interpolation filtering, shared computing units, and efficient storage management. Key design features include: Hierarchical memory: Coef RAM stores coefficients, DHIS RAM manages historical data, and Dout RAM caches intermediate results. Time-division multiplexing MAC: A single computing unit serves 8 channels, balancing resources and performance. Synchronous FIFO: Ensures stable multi-channel data flow and avoids overflow.

[0138] Please refer to the reference. Figure 6 The audio data processing system provided in this application uses a state machine to control the sampling rate conversion process of 8-channel PCM data. The functions of each state are shown in Table 3 below.

[0139] Table 3

[0140]

[0141] Please refer to Figure 6 According to Table 3 above, the main flow (single-channel) of the state transition logic involves the following transition logic:

[0142] (1) S_IDLE to S_RDPCM conversion:

[0143] Trigger condition: The input FIFO is not empty (pemffio_empty=0).

[0144] Action: Read the PCM data of the current channel.

[0145] (2) S_RDPCM to S_DHIS conversion:

[0146] Triggering condition: Reading complete (status codes 01 to 11).

[0147] Action: Store the data in DHIS RAM and update the history queue.

[0148] (3) The branching conditions for S_DHIS to S_RDDIN / S_MUL conversion include:

[0149] Direct calculation (bypass): If no intermediate data is needed, jump to S_MUL.

[0150] Intermediate data required: Jump to S_RDDIN to read Dout RAM data.

[0151] (4) Convert S_RDDIN to S_MUL:

[0152] Triggering condition: Intermediate data loading complete (status codes 21 to 02).

[0153] Action: Initiate multiplication and accumulation calculation.

[0154] (5) S_MUL to S_SAVE:

[0155] Triggering condition: Multiplication and accumulation completed (Imul_acc_finish=1).

[0156] Action: Save the result to Dout RAM or output to FIFO.

[0157] (6) Triggering conditions for S_SAVE to S_IDLE / Next Channel:

[0158] If the output FIFO is full (outffio_full=1), return S_IDLE and wait.

[0159] Otherwise, switch to the next channel.

[0160] The polling mechanism for multi-channel scheduling: 8 channels are processed in a fixed order (e.g., ch_0→ch_1→…→ch_7).

[0161] Multi-channel scheduling switching timing: After S_SAVE is completed, the channel index is incremented by the next_channel signal, and S_RDPCM is returned to process the next channel.

[0162] Obviously, the audio data processing system provided in this application involves timing optimization, storage management, and exception handling, among which:

[0163] (1) Timing optimization (S_MUL state):

[0164] Data storage: The input and output of the multiply-accumulate (MAC) are both inserted into registers to ensure that the critical path delay is controllable.

[0165] Input registers: storing coefficients (Coef RAM) and historical data (DHIS RAM).

[0166] Output register: Temporarily stores the accumulated result to avoid the clock frequency being affected by combinational logic delays.

[0167] Pipeline design: Multiplication and accumulation operations are pipelined in two stages to improve throughput.

[0168] (2) Storage Management:

[0169] DHIS RAM: Independent storage area for each channel to prevent data interference between channels.

[0170] Update strategy: In the S_DHIS state, new data overwrites the oldest historical sample (FIFO queue).

[0171] Dout RAM: Caches intermediate results of multi-level filtering (such as y(n)), partitioned by channel and step.

[0172] (3) Exception handling:

[0173] Inputting an empty FIFO: Pauses processing of the current channel (returns S_IDLE) until data is ready.

[0174] When the output FIFO is full: pause the writing of results and trigger a flow control signal (such as notifying the upstream to slow down).

[0175] The relevant performance and resource verifications are shown in Table 4 below.

[0176] Table 4

[0177]

[0178] In summary, the audio data processing system provided in this application utilizes a state machine that achieves real-time sampling rate conversion of 8-channel PCM data through refined state partitioning and multi-channel polling scheduling. Key design advantages include: low-latency processing: pipelined multiply-accumulate operations supporting high-frequency clocks; resource efficiency: shared MAC unit and storage interface reducing hardware overhead; and robustness: an abnormal state handling mechanism ensures data integrity.

[0179] Please refer to further details. Figure 6 The relevant production line design is shown in Table 5 below.

[0180] Table 5

[0181]

[0182] Based on Table 5 above, the design of the multi-channel sampling rate conversion pipeline is analyzed, including an overview of the pipeline process, a detailed analysis of the pipeline stages, and performance advantages.

[0183] Pipeline Overview: The pipeline table above (Table 5) shows the multiply-accumulate (MAC) operation flow of the multichannel sampling rate conversion module, covering six clock cycles (Cycle0~Cycle5) from data / coefficient reading to accumulation result generation. The core design achieves high throughput through a four-stage pipeline, with each stage focusing on a specific task, as detailed in Table 6 below.

[0184] Table 6

[0185]

[0186] Detailed pipeline stage analysis includes stages 1 through 4.

[0187] Phase 1: Data and coefficient reading (Cycle0);

[0188] Operation: Read historical data from DHIS RAM (e.g., d0 corresponds to x(n-0), d1 corresponds to x(n-1), etc.). Read filter coefficients from Coef RAM (e.g., h0 corresponds to the coefficient of the current tap).

[0189] Design goals: To prepare data for subsequent calculations and reduce latency through parallel reading. Support for multi-channel time-division multiplexing, with each channel allocated an independent storage area.

[0190] Phase 2: Data register storage (Cycle 1);

[0191] Operation: Store the read data (d0) and coefficient (h0) into the input register (Reg d0, Reg h0).

[0192] Design goals: To insert registers to isolate combinational logic paths and improve timing performance. To ensure stable multiplier inputs and avoid timing violations caused by RAM read delays.

[0193] Phase 3: Multiplication Operations (Cycle 2);

[0194] Operation: Perform a multiplication operation between the 21-bit coefficient (h0) and the 18-bit historical data (d0), and store the result in the product register (r0). For example: r0 <= h0 * d0 (Cycle2), r1 <= h1 * d1 (Cycle3).

[0195] Design goal: To achieve high-speed computation through a dedicated multiplication unit (DSP block). Results are temporarily stored in registers to facilitate pipelined implementation.

[0196] Phase 4: Accumulation operation (Cycle 3~Cycle 5);

[0197] Operation: Accumulate the product results sequentially into the accumulator (sum). For example: Cycle3: sum <= sum + r0, Cycle4: sum <= sum + r1, Cycle5: sum <= sum + r2.

[0198] Design goals: Step-by-step accumulation avoids long paths in a single cycle and increases clock frequency. The accumulator bit width is extended (e.g., 39 bits) to prevent overflow, and finally truncated to an 18-bit output.

[0199] The performance advantages involve high throughput, low latency, and resource optimization, among which:

[0200] High throughput: The pipelined design allows for a multiply-accumulate operation to be completed every 6 cycles, but multi-stage parallelism can achieve a valid output per cycle (assuming the 6-stage pipeline is full). It supports 8-channel real-time processing (48kHz × 8 = 384kHz), requiring a clock frequency of only 384kHz × 6 ≈ 2.3MHz.

[0201] Low latency: Inserting registers shortens the critical path (such as from multiplier input to accumulator output), allowing for higher clock frequencies (up to 100+ MHz in FPGAs).

[0202] Resource optimization: Shared multipliers and memory interfaces reduce DSP and RAM usage. Register insertion avoids complex combinational logic and improves timing convergence.

[0203] Please refer to further details. Figure 7 The audio data processing system provided in this application involves four operational units. The functional unit operation logic includes reading DHIS RAM and COEF RAM, register data from RAM, register multiplication, and register accumulation. This pipeline design efficiently achieves real-time sampling rate conversion of 8-channel PCM data through four-level segmented operations (read, register, multiplication, and accumulation) and multi-channel time-division multiplexing.

[0204] For example, the four arithmetic units may involve an address generation and retrieval unit, a data retrieval and storage unit, and a multiplication and accumulation unit; wherein:

[0205] In the address generation and reading unit, "1'b1" represents a constant 1, used for the address counter's addition operation; "+" indicates an adder that adds the input constant 1 to the current address (addr_dhis and addr_coef) to generate the next address; "D" indicates a flip-flop (Rd) used to store the address; the input terminal (D) receives the adder's output, and the output terminal (Q) outputs the current address and feeds it back to the adder for the next addition operation. addr_dhis and addr_coef are used to access the historical data RAM (DHIS) and coefficient RAM (COEF), respectively.

[0206] In the data read and register unit, dhis_in and coef_in represent the data read from DHIS RAM and COEF RAM, respectively; DHIS RAM and COEF RAM store historical data and filter coefficients, respectively; "D" represents a trigger (Reg) used to register the read data; data_r and coef_r are the registered historical data and coefficients, respectively.

[0207] The multiplication unit, also known as the multiplier (Mul), where "×" indicates the multiplier, multiplies the registered historical data data_r and the coefficient coef_r to obtain the multiplication result result_r.

[0208] The accumulation unit, also known as the adder, consists of "+" indicating that the adder adds the multiplication result result_r to the previous accumulation result sum_r to obtain the new accumulation result; "D" indicates that the adder is used to store the accumulation result; the input terminal (D) receives the output of the adder, and the output terminal (Q) outputs the current accumulation result sum_r and feeds it back to the adder for the next accumulation operation.

[0209] The overall workflow related to the four arithmetic units includes address generation, data reading, data storage, multiplication, and accumulation operations, among which:

[0210] Address generation: The address counter increments continuously, generating addresses for accessing DHIS RAM and COEF RAM;

[0211] Data reading: Based on the generated address, read historical data and coefficients from DHIS RAM and COEF RAM;

[0212] Data storage: The read data is stored in the register and then sent to the multiplier;

[0213] Multiplication: The multiplier performs multiplication on the data stored in the register to obtain the multiplication result;

[0214] Accumulation operation: The result of multiplication is added to the previous accumulation result to obtain a new accumulation result, which is then stored for use in the next accumulation.

[0215] Based on the same inventive concept, this application provides an audio signal processing method for the audio data processing system provided in this application. The method includes: acquiring an audio signal and determining its current sampling rate and target sampling rate; determining a conversion factor sequence for the audio signal based on the current sampling rate and target sampling rate, wherein the conversion factor sequence includes at least one conversion factor, which characterizes the change in data volume after the filter performs conversion processing on the input signal data; determining a filter type for the audio signal according to filter constraints, wherein the filter constraints are obtained based on at least one of the audio characteristics of the audio signal, the signal index characteristics corresponding to the target sampling rate, and the audio processing resource characteristics of the local end; constructing a filter identifier sequence for the audio signal according to the filter type; the filter identifier sequence includes sequentially arranged filter identifiers, the number of which is the same as the number of conversion factors, where the filter identifiers characterize filters belonging to the filter type at the local end; configuring output conversion for the filters represented by the filter identifiers in the filter identifier sequence according to the conversion factors in the conversion factor sequence, obtaining filter configuration results; and sequentially combining the filters at the local end based on the filter configuration results to obtain a filter group, and performing sampling rate conversion processing on the audio signal through the filter group to obtain a target signal that meets the target sampling rate.

[0216] In this context, combining local filters in sequence to form a filter bank refers to setting the order in which each level of filter appears in the audio processing process, according to the required order. A filter bank is essentially a virtual concept.

[0217] In an exemplary embodiment, determining a sequence of conversion factors for an audio signal based on the current sampling rate and the target sampling rate includes: determining an interpolation factor and a decimation factor for the audio signal based on the current sampling rate and the target sampling rate, and obtaining conversion factors based on the interpolation factor and the decimation factor; and combining the conversion factors to obtain a sequence of conversion factors for the audio signal.

[0218] In an exemplary embodiment, constructing a filter identifier sequence for an audio signal according to the filter type includes: determining the number of factors of the conversion factors included in the conversion factor sequence; determining filter identifiers with the same number of factors based on the filter type; and combining the filter identifiers to obtain a filter identifier sequence for the audio signal.

[0219] In an exemplary embodiment, the transformation factor includes an interpolation factor and a decimation factor, and the number of factors includes a first number of interpolation factors and a second number of decimation factors; the filter type includes an interpolation type and a decimation type; determining filter identifiers with the same number of factors based on the filter type includes: determining a first filter identifier with the same number of first factors based on the interpolation type; determining a second filter identifier with the same number of second factors based on the decimation type; and obtaining filter identifiers with the same number of factors based on the first filter identifier and the second filter identifier.

[0220] In an exemplary embodiment, the conversion factor includes an interpolation factor and a decimation factor, and the filter type includes an interpolation type and a decimation type. According to the conversion factors in the conversion factor sequence, output conversion configuration is performed on the filters represented by the filter identifiers in the filter identifier sequence to obtain filter configuration results. This includes: if the filter representing the interpolation type by the interpolation factor meets the trigger configuration condition, output conversion configuration is performed on the first filter according to the interpolation factor to obtain a first configuration result, where the first filter is the filter representing the interpolation type represented by the filter identifier in the filter identifier sequence; if the filter representing the decimation type by the decimation factor meets the trigger configuration condition, output conversion configuration is performed on the second filter according to the decimation factor to obtain a second configuration result, where the second filter is the filter representing the decimation type represented by the filter identifier in the filter identifier sequence; and the filter configuration result is obtained based on the first configuration result and the second configuration result.

[0221] In an exemplary embodiment, the filter types include interpolation type and decimation type; the filter groups are sequentially combined based on the filter configuration results to obtain a filter group, including: determining the target filter and the filter cascading order of the target filter based on the filter configuration results, wherein the filter cascading order includes the first cascading order of the first filter belonging to the interpolation type and the second cascading order of the second filter belonging to the decimation type in the target filter; cascading the first filter according to the first cascading order to obtain an interpolation filter group; cascading the second filter according to the second cascading order to obtain a decimation filter group; and connecting the interpolation filter group and the decimation filter group in sequence to obtain a (virtual) filter group.

[0222] In an exemplary embodiment, the sampling rate conversion processing of an audio signal using a filter bank includes: obtaining the tap number of each target filter in the filter bank; determining the audio processing algorithm corresponding to each target filter based on the tap number of each target filter; and performing sampling rate conversion processing on the audio signal using each target filter, based on the cascade order of each target filter and the audio processing algorithm corresponding to each target filter.

[0223] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0224] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0225] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. An audio data processing system, characterized in that, include: The first storage module is used to store the first-level data to be processed corresponding to each of the received audio data to be processed, and to update the storage to store the Nth-level data to be processed when receiving any of the first-level data to be processed corresponding to the Nth-level data. N≥2 and N is a positive integer; The filter, electrically connected to the first storage module, is used to perform audio sampling rate conversion processing on at least each level of the audio data to be processed from the first level to the (N-1)th level of the audio data to be processed, and to obtain the data after sampling rate conversion corresponding to each level of the audio data to be processed. The second storage module is electrically connected to the filter and the first storage module, respectively, and is used to store the data after conversion of each level of sampling rate corresponding to each of the audio data to be processed; it is also used to transmit the data after conversion of each level of sampling rate corresponding to each of the audio data to be processed to the first storage module, so as to serve as the Nth level of data to be processed corresponding to each of the audio data to be processed. Wherein, the sample rate converted data of the N-1th level of the audio data to be processed corresponding to each of the audio data to be processed output by the filter is the processed target audio data corresponding to each of the audio data to be processed.

2. The audio data processing system according to claim 1, characterized in that, Also includes: The third storage module, electrically connected to the filter, is used to store the number of taps of each level of the filter adapted to perform the audio sampling rate conversion processing on each level of the data to be processed.

3. The audio data processing system according to claim 1, characterized in that, The filter includes a multiplier and an accumulator; wherein the output of the multiplier is electrically connected to the input of the accumulator, the input of the multiplier is used to receive the data to be processed at each stage, and the output of the accumulator is used to output the data after sampling rate conversion corresponding to each stage of the audio data to be processed.

4. The audio data processing system according to claim 1, characterized in that, Also includes: The data receiving module is electrically connected to the first storage module and the filter, and includes multiple data receiving channels. Each data receiving channel is used to receive different audio data to be processed and transmit it to the first storage module and the filter, respectively. The data output module is electrically connected to the filter and includes multiple data output channels; The filter is used to receive the sample rate converted data of the N-1 level to be processed corresponding to each of the audio data to be processed output by the filter, and to output the sample rate converted data of the N-1 level to be processed corresponding to each of the audio data to be processed through each of the data output channels, as the processed target audio data corresponding to each of the audio data to be processed.

5. The audio data processing system according to claim 4, characterized in that, Also includes: A filter parameter control module is electrically connected to the data receiving module and the filter, respectively. Used to determine a sequence of conversion factors for each level of the filter that is adapted to perform audio sampling rate conversion processing on each level of the audio data to be processed, based on the current sampling rate and the target sampling rate of each audio data to be processed; and used to determine the filter type parameter of the filter based on at least one of the audio features of the audio data to be processed, the signal index features corresponding to the target sampling rate, and the audio processing resource features of the local end. The conversion factor sequence includes at least one conversion factor, which is used to characterize the change in the amount of data after the filter performs the audio sampling rate conversion processing on the audio data to be processed.

6. The audio data processing system according to claim 4, characterized in that, The first storage module includes the same number of data storage channels as the data receiving channels; each data storage channel is used to store the first-level data to be processed corresponding to the audio data to be processed received by each data receiving channel, and when the Nth-level data to be processed corresponding to any first-level data to be processed is received, it is updated to store the Nth-level data to be processed.

7. The audio data processing system according to claim 4, characterized in that, The number of data receiving channels and the number of data output channels are the same; The data output channel, one of the matched set of data receiving channels and data output channels, is used to output the target audio data corresponding to the audio data to be processed received by the matched data receiving channel.

8. The audio data processing system according to claim 5, characterized in that, The number of data receiving channels and data output channels is M, where M ≥ 8 and M is a positive integer; The multiple data receiving channels and the multiple data output channels transmit data based on the first-in-first-out principle.

9. The audio data processing system according to claim 4, characterized in that, Also includes: A first multiplexing unit, the input of which is electrically connected to the output of the data receiving module, and the output of which is electrically connected to the input of the first storage module and the input of the filter, respectively. The second multiplexing unit has its input terminal electrically connected to the output terminal of the filter, and its output terminal is electrically connected to the input terminal of the data output module.

10. The audio data processing system according to claim 9, characterized in that, Also includes: The third multiplexing unit has its input terminal electrically connected to the output terminal of the first multiplexing unit, the output terminal of the first storage module, and the output terminal of the second storage module, respectively; the output terminal of the third multiplexing unit is electrically connected to the input terminal of the filter. The fourth multiplexing unit has its input terminal electrically connected to the output terminal of the filter, and its output terminal is electrically connected to the input terminal of the second storage module and the input terminal of the second multiplexing unit, respectively.

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