Silicon carbide trench MOSFET device with three-side trench structure and preparation method thereof

Abstract

The invention provides a silicon carbide trench MOSFET device with a three-side trench structure and a preparation method thereof, and the method comprises the steps: growing a silicon carbide epitaxy on a silicon carbide substrate, and carrying out the injection to form a P-well region; forming a first barrier layer on the P-well region, and performing injection to form a P + region; removing the first barrier layer to form a second barrier layer, and performing injection to form an N + region; removing the second barrier layer, and simultaneously performing rapid thermal annealing on the P-well region, the P + region and the N + region; forming a third barrier layer, and etching to form a gate trench region; removing the third barrier layer, and performing dry-oxygen thermal oxidation to form a gate oxide layer; forming polycrystalline silicon by using chemical vapor deposition; after the polycrystalline silicon is doped, etching is carried out to form a grid electrode; and depositing metal to form a drain electrode and a source electrode, and performing rapid thermal annealing on the drain electrode and the source electrode to form ohmic contact. By arranging the three-side groove structure, the area of the channel is increased, and conduction resistance is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device preparation, and more particularly to a silicon carbide trench MOSFET device with a three-sided trench structure and a preparation method thereof. Background Art

[0002] Silicon carbide (SiC) is a typical wide-bandgap semiconductor material. Its high critical breakdown electric field, high thermal conductivity, and high electron saturation velocity make it an ideal choice for high-voltage, high-temperature, high-frequency, and high-power power electronics. Compared to traditional silicon-based power devices, SiC power devices offer lower conduction losses and faster switching speeds, making them widely applicable in new energy vehicles, photovoltaic inverters, 5G communication base stations, rail transit, and other fields.

[0003] At present, power devices based on 4H-SiC have been commercialized, but they still have the problem of low channel electron mobility. The channel mobility of 4H-SiC MOSFET is usually 20~40cm 2 / V·s, resulting in its excellent material properties cannot be fully utilized.

[0004] In the commercialization of silicon carbide power MOSFETs, the horizontal-channel DTMOS (Double-Trench MOSFET) has secured a niche in low- and medium-voltage applications (typically several hundred volts to 1.2 kV) thanks to its unique structural design and performance advantages. However, its horizontal channel structure and the lateral extension of the silicon carbide are limited by chip area. Currently, commercial products generally offer a withstand voltage below 1.2 kV, making them difficult to use in high-voltage industrial applications. Although a type of trench structure, the horizontal DTMOS (Double-Trench MOSFET) is essentially a planar device with lateral channel current flow, resulting in a relatively high on-resistance.

[0005] The core value of the silicon carbide trench gate MOSFET lies in maximizing the high critical electric field and high electron mobility of the silicon carbide material through the design of embedding the gate into the trench. Unlike the planar gate, whose channel is only distributed on the surface of the chip, the trench gate forms a channel through the side of the vertical trench. Its channel current is vertical, and the total channel length per unit area is greatly increased, which can directly reduce the channel resistance. Although it can significantly reduce the channel resistance compared to the horizontal channel structure MOSFET, its vertical channel is only arranged on both sides of the gate. By optimizing the gate trench structure, the channel structure can be optimized, thereby further reducing the on-resistance.

[0006] Therefore, how to optimize the channel structure is an urgent problem that those skilled in the art need to solve. Summary of the Invention

[0007] In view of this, the present invention provides a silicon carbide trench MOSFET device with a three-sided trench structure and a preparation method. By using a three-sided trench structure to prepare a silicon carbide trench gate MOSFET to form an additional conductive channel, the area of ​​the channel is increased and the on-resistance of the silicon carbide trench gate MOSFET device is reduced.

[0008] To achieve the above object, the present invention provides the following technical solutions: A method for preparing a silicon carbide trench MOSFET device with a three-sided trench structure, comprising: Step S1, epitaxially growing a silicon carbide epitaxial layer on a silicon carbide substrate, and performing multiple aluminum ion implantations or aluminum ion and boron ion co-implantations on the silicon carbide epitaxial layer to form a P-well region; Step S2, forming a first barrier layer on the P-well region, and performing multiple aluminum ion implantations or aluminum ion and boron ion co-implantations to form a P+ region; Step S3, removing the first barrier layer, forming a second barrier layer, and performing multiple nitrogen ion implantations to form an N+ region; Step S4, removing the second barrier layer, and performing rapid thermal annealing on the P-well region, the P+ region, and the N+ region simultaneously; Step S5, forming a third barrier layer, and etching to form a gate trench region; Step S6, removing the third barrier layer, performing RCA cleaning, and then performing dry oxygen thermal oxidation in a furnace tube to remove the oxide layer above the P+ region and the N+ region, and forming a gate oxide layer in the gate trench region; Step S7, performing multi-step deposition on the gate oxide layer using chemical vapor deposition to form polysilicon; after doping the polysilicon, etching is performed to form a gate; In step S8, metal is deposited on the back side of the silicon carbide substrate to form a drain, metal is deposited above the P+ region and part of the N+ region to form a source, and the drain and source are subjected to rapid thermal annealing to form ohmic contacts, thereby preparing a silicon carbide trench MOSFET device with a three-sided trench structure.

[0009] Furthermore, in step S1, the doping concentration of the silicon carbide substrate is 1e 18 cm -3 ~1e 20 cm -3 , thickness is 200µm~1000µm; the doping concentration of silicon carbide epitaxy is 1e 15 cm -3 ~5e 16 cm -3 , thickness is 6µm~40µm; P-well region is formed at 500℃-800℃, with a net acceptor concentration of 5e 16 cm -3 ~5e 17 cm-3 .

[0010] Furthermore, in step S2, a P+ region is formed at 500°C–700°C with a doping concentration of 1e 19 cm -3 ~1e 20 cm -3 , thickness is 0.2µm~0.5µm.

[0011] Furthermore, in step S3, the N+ region is formed at 400°C–600°C with a doping concentration of 1e 19 cm -3 ~1e 20 cm -3 , injection angle 7°–10°, thickness 0.2µm~0.5µm.

[0012] Furthermore, in step S4, the temperature of the rapid thermal annealing is between 1600° C. and 1800° C., an inert atmosphere or a protective atmosphere is used, and the time is between 1 and 10 minutes.

[0013] Furthermore, in step S5, the thickness of the gate trench region is 0.5µm to 1.2µm, and is greater than the thickness of the P-well region (103), which is 0.05µm to 0.5µm.

[0014] Furthermore, in step S6, the temperature of the dry oxygen thermal oxidation is between 1000° C. and 1300° C.; the sidewall thickness of the gate oxide layer is between 0.01 μm and 0.5 μm, and the bottom thickness is between 0.02 μm and 0.7 μm.

[0015] Furthermore, in step S7, the temperature of chemical vapor deposition is between 550°C and 700°C; the polysilicon doping concentration is 1e 18 ~1e 20 cm -3 .

[0016] Furthermore, in step S8, the portion of the N+ region is the center of the N+ region; the temperature of the rapid thermal annealing is between 900° C. and 1100° C., and the time is 30 seconds to 2 minutes.

[0017] The prepared silicon carbide trench MOSFET device with a three-sided trench structure includes a silicon carbide substrate, a silicon carbide epitaxial layer, a P-well region, a P+ region, an N+ region, a gate oxide layer, a gate, a drain and a source. The drain is arranged on the back side of the silicon carbide substrate, the silicon carbide epitaxial layer is arranged on the front side of the silicon carbide substrate, the P-well region is formed on the silicon carbide epitaxial layer, the P+ region and the N+ region are formed on the P-well region, the gate oxide layer is arranged at the center of the P-well region and the N+ region, the gate (108) is arranged on the gate oxide layer, and the source is arranged on the P+ region of the entire region and the N+ region of a part of the region.

[0018] It can be seen from the above technical solution that compared with the prior art, the beneficial effects of the present invention are: 1. The silicon carbide trench MOSFET device prepared by the method of the present invention forms multiple additional conductive channels by using a three-sided trench structure to increase the area of ​​the channel and reduce the on-resistance of the silicon carbide trench MOSFET device.

[0019] 2. The silicon carbide trench MOSFET device prepared by the method of the present invention can adjust the channel resistance by controlling the width of the three-sided trench structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0021] Figure 1 Schematic diagram of the process of the present invention; Figure 2a-Figure 2i for Figure 1 Schematic diagram of the preparation steps of a silicon carbide trench MOSFET device with a three-sided trench structure; In the figure, 101 is a silicon carbide substrate; 102 is a silicon carbide epitaxial layer; 103 is a P-well region; 104 is a P+ region; 105 is an N+ region; 106 is a gate trench region; 107 is a gate oxide layer; 108 is a gate; 109 is a drain; 110 is a source; 21 is a first barrier layer; 22 is a second barrier layer; and 23 is a third barrier layer. DETAILED DESCRIPTION

[0022] In order to further understand the content, features and effects of the present invention, the following embodiments are given as examples and described in detail with reference to the accompanying drawings. It should be noted that the embodiments are illustrative and not restrictive, and the scope of protection of the present invention cannot be limited thereby.

[0023] like Figure 1 As shown, a silicon carbide trench MOSFET device with a three-sided trench structure and a preparation method are disclosed, comprising the following steps: Step S1: The silicon carbide substrate 101 is set to N-type, 4H-SiC or 6H-SiC, with a doping concentration of 1e 18 cm -3 ~1e 20 cm -3, with a thickness of 200µm~1000µm. The doping concentration of the epitaxial growth on the silicon carbide substrate 101 is 1e 15 cm -3 ~5e 16 cm -3 The silicon carbide epitaxial layer 102 with a thickness of 6µm to 40µm, i.e. the drift region, is configured as an N-type. Aluminum ions are implanted into the silicon carbide epitaxial layer 102 multiple times or aluminum ions and boron ions are implanted together to form a P-well region 103; Figure 2a shown.

[0024] Step S2: forming a first barrier layer 21 on the P-well region 103, and performing multiple aluminum ion implantation or aluminum ion and boron ion co-implantation on the unobstructed area of ​​the P-well region 103 to form a P+ region 104; the P+ region 104 is formed by multiple aluminum ion implantation or aluminum ion and boron ion co-implantation at 500°C–700°C, with a doping concentration of 1e 19 cm -3 ~1e 20 cm -3 , thickness is 0.2µm~0.5µm, such as Figure 2b shown.

[0025] The P+ region 104 of the silicon carbide MOSFET device is the core of the body contact region, which is used to achieve a low-resistance connection between the P-well region 103 and the source 110, prevent parasitic BJT conduction and improve device robustness.

[0026] Step S3: remove the first barrier layer 21, form a second barrier layer 22, and perform multiple nitrogen ion implantation on the unblocked area of ​​the P-well region 103 to form an N+ region 105; the N+ region 105 is formed at 400°C–600°C with a doping concentration of 1e 19 cm -3 ~1e 20 cm -3 , using a 7°–10° tilt implantation angle to avoid channeling, with a thickness of 0.2µm~0.5µm, such as Figure 2c shown.

[0027] In step S4, the second barrier layer 22 is removed, and rapid thermal annealing is performed simultaneously on the P-well region 103, the P+ region 104, and the N+ region 105. This rapid thermal annealing is performed at a temperature between 1600°C and 1800°C, using an inert or protective atmosphere, for 1 to 10 minutes to ensure dopant activation and lattice repair while minimizing surface damage. The P-well region 103, the P+ region 104, and the N+ region 105 must be activated in the same annealing step to avoid multiple high-temperature damage.

[0028] Step S5: forming a third barrier layer 23, etching the unblocked areas on the P-well region 103, the P+ region 104, and the N+ region 105 to form a gate trench region 106; the gate trench region 106 has a thickness of 0.5µm to 1.2µm and is 0.05µm to 0.5µm thicker than the thickness of the P-well region 103. Figure 2d-2f The figures are a top view, a front view and a cross-sectional view along the middle, respectively. The etching is performed using inductively coupled plasma etching (ICP) or inductively coupled plasma and reactive ion etching (ICP-RIE).

[0029] In step S6, the third barrier layer 23 is removed and RCA cleaning is performed. After cleaning, dry oxygen thermal oxidation is performed in a furnace tube to remove the oxide layer above the P+ region 104 and the N+ region 105, and a gate oxide layer 107 is formed in the gate trench region 106. The temperature of the dry oxygen thermal oxidation is between 1000° C. and 1300° C. The sidewall thickness of the gate oxide layer 107 is 0.01 μm to 0.5 μm, and the bottom thickness is 0.02 μm to 0.7 μm.

[0030] Step S7, the gate oxide layer 107 is deposited by chemical vapor deposition in multiple steps to form polysilicon; the polysilicon is doped and then etched to form the gate 108; the chemical vapor deposition temperature is between 550°C and 700°C; the polysilicon doping concentration is 1e 18 ~1e 20 cm -3 .like Figure 2g-2h The following are the main view and top view respectively.

[0031] Step S8, depositing metal on the back side of the silicon carbide substrate 101 to form a drain 109, depositing metal on the P+ region 104 and part of the N+ region 105 to form a source 110, and performing rapid thermal annealing on the drain 109 and the source 110 to form an ohmic contact, thereby completing the preparation of a silicon carbide trench gate MOSFET device with a low on-resistance three-sided trench structure. Part of the N+ region 105 is the center of the N+ region 105; the temperature of the rapid thermal annealing is between 900°C and 1100°C, and the time is 30 seconds to 2 minutes. Metal silicide is formed through interface reaction, which reduces the contact resistance and forms an ohmic contact. Figure 2i shown.

[0032] Furthermore, the metal is deposited using physical vapor deposition (PVD), which uses magnetron sputtering to bombard target materials such as Ti, Al and Ni with high-energy ions, causing atoms to sputter and form metal deposits.

[0033] like Figure 2iA silicon carbide trench MOSFET device with a three-sided trench structure is shown, including a silicon carbide substrate 101, a silicon carbide epitaxial extension 102, a P-well region 103, a P+ region 104, an N+ region 105, a gate oxide layer 107, a gate 108, a drain 109 and a source 110. The drain 109 is arranged on the back side of the silicon carbide substrate 101, the silicon carbide epitaxial extension 102 is arranged on the front side of the silicon carbide substrate 101, the P-well region 103 is formed on the silicon carbide epitaxial extension 102, the P+ region 104 and the N+ region 105 are formed on the P-well region 103, the gate oxide layer 107 is arranged at the center of the P-well region 103 and the N+ region 105, the gate 108 is arranged on the gate oxide layer 107, and the source 110 is arranged on the P+ region 104 in the entire area and the N+ region 105 in a part of the area. Specific embodiment 1

[0035] Step S1: Both the silicon carbide substrate 101 and the silicon carbide epitaxial layer 102 are N-type doped. The doping concentration of the silicon carbide substrate 101 is 2e 18 cm -3 , thickness is 350µm; SiC epitaxial 102 doping concentration is 5e 15 cm -3 At 600°C, the silicon carbide epitaxial layer 102 is implanted with aluminum ions or aluminum ions and boron ions are implanted multiple times to form a 0.7µm P-well region 103; the net acceptor concentration of the P-well region 103 is 1e 17 cm -3 .

[0036] Step S2: A first barrier layer 21 is formed on the P-well region 103. At 600°C, multiple aluminum ion implantations or aluminum ion and boron ion co-implantations are performed to form a P+ region 104. The doping concentration of the P+ region 104 is 1e 19 cm -3 , thickness is 0.2µm.

[0037] Step S3: Remove the first barrier layer 21 and form the second barrier layer 22. Then, multiple nitrogen ion implantations are performed at 600°C to form the N+ region 105 with a doping concentration of 1e 19 cm -3 , with a thickness of 0.2µm and implanted at a tilt angle of 7°–10°.

[0038] Step S4: removing the second barrier layer 22 and simultaneously performing rapid thermal annealing for 5 minutes on the P-well region 103 , the P+ region 104 and the N+ region 105 in an inert / protective atmosphere at 1700° C.

[0039] Step S5: Form a third barrier layer 23 and perform etching to form a gate trench region 106. The gate trench region 106 has a thickness of 0.8 µm, which is 0.1 µm thicker than the P-well region 103. The protruding portion of the third barrier layer 23 has a vertical width of 2 µm and a lateral width of 0.5 µm, while the concave portion has a vertical width of 0.5 µm.

[0040] Step S6: Remove the third barrier layer 23 and perform RCA standard cleaning. Then, perform dry oxygen thermal oxidation at 1200°C in a furnace tube, and then remove the oxide layer above the P+ region 104 and N+ region 105 to form a gate oxide layer 107. The sidewall thickness of the gate oxide layer 107 is 0.03µm, and the bottom thickness of the gate oxide layer 107 is 0.05µm. The polysilicon is then doped by multi-step chemical vapor deposition (LPCVD) at 600°C, with a polysilicon doping concentration of 1e 19 cm -3 Finally, the polysilicon is etched to form the gate 108.

[0041] Step S7: Physical vapor deposition (PVD) is performed by magnetron sputtering high-energy ions to bombard a target material, such as Ti, Al, or Ni, causing atoms to be sputtered and deposited onto the backside of the silicon carbide substrate 101 to form the drain 109. The atoms are also sputtered and deposited onto the center of the P+ and N+ source regions to form the source 110. This is followed by a rapid thermal annealing (RTA) at 1000°C for 1 minute to form metal silicide through interfacial reactions, reducing contact resistance and establishing an ohmic contact between the drain 109 and the source 110.

[0042] Compared with the traditional trench structure, the MOSFET device prepared through the above steps has a vertical channel conduction area increased by 37.5% and a channel resistance reduced by 27%. Specific embodiment 2

[0044] Step S1: Both the silicon carbide substrate 101 and the silicon carbide epitaxial layer 102 are N-type doped. The doping concentration of the silicon carbide substrate 101 is 2e 18 cm -3 , thickness is 350µm; SiC epitaxial 102 doping concentration is 5e 15 cm -3 At 600°C, the silicon carbide epitaxial layer 102 is implanted with aluminum ions or aluminum ions and boron ions are implanted multiple times to form a 0.7µm P-well region 103; the net acceptor concentration of the P-well region 103 is 1e 17 cm -3 .

[0045] Step S2: A first barrier layer 21 is formed on the P-well region 103. At 600°C, multiple aluminum ion implantations or aluminum ion and boron ion co-implantations are performed to form a P+ region 104. The doping concentration of the P+ region 104 is 1e 19 cm -3 , thickness is 0.2µm.

[0046] Step S3: Remove the first barrier layer 21 and form the second barrier layer 22. Then, multiple nitrogen ion implantations are performed at 600°C to form the N+ region 105 with a doping concentration of 1e 19 cm -3 , with a thickness of 0.2µm and implanted at a tilt angle of 7°–10°.

[0047] Step S4: removing the second barrier layer 22 and simultaneously performing rapid thermal annealing for 5 minutes on the P-well region 103 , the P+ region 104 and the N+ region 105 in an inert / protective atmosphere at 1700° C.

[0048] Step S5: Form a third barrier layer 23 and perform etching to form a gate trench region 106. The gate trench region 106 has a thickness of 0.8 µm, which is 0.1 µm thicker than the P-well region 103. The protruding portion of the third barrier layer 23 has a vertical width of 2 µm and a lateral width of 0.8 µm, while the concave portion has a vertical width of 0.5 µm.

[0049] Step S6: Remove the third barrier layer 23 and perform RCA standard cleaning. Then, perform dry oxygen thermal oxidation at 1200°C in a furnace tube, and then remove the oxide layer above the P+ region 104 and the N+ region 105 to form a gate oxide layer 107. The sidewall thickness of the gate oxide layer 107 is 0.03µm, and the bottom thickness of the gate oxide layer 107 is 0.05µm. The polysilicon is then doped by chemical vapor deposition at 600°C in multiple steps, and the polysilicon doping concentration is 1e 19 cm -3 Finally, the polysilicon is etched to form the gate 108.

[0050] Step S7: Physical vapor deposition (PVD) is performed by magnetron sputtering high-energy ions to bombard a target material, such as Ti, Al, or Ni, causing atoms to be sputtered and deposited onto the backside of the silicon carbide substrate 101 to form the drain 109. The atoms are also sputtered and deposited onto the center of the P+ and N+ source regions to form the source 110. This is followed by a rapid thermal annealing (RTA) at 1000°C for 1 minute to form metal silicide through interfacial reactions, reducing contact resistance and establishing an ohmic contact between the drain 109 and the source 110.

[0051] Compared with the traditional trench structure, the MOSFET device prepared through the above steps has a vertical channel conduction area increased by 60% and a channel resistance reduced by 37%.

[0052] It can be seen from the above two embodiments that the method of the present invention can adjust the channel resistance by controlling the width of the three-sided trench structure while increasing the channel area and reducing the on-resistance.

[0053] It should be pointed out that the description of the above embodiments is only used to help understand the method of this application and its core idea. For ordinary technicians in this technical field, without departing from the principles of this application, several improvements and modifications can be made to this application, and these improvements and modifications are also within the scope of protection of the claims of this application.

Claims

1. A method for preparing a three-sided trench silicon carbide trench MOSFET device, characterized in that: include: Step S1, epitaxially growing a silicon carbide epitaxial layer (102) on a silicon carbide substrate (101), and performing multiple aluminum ion implantations or aluminum ion and boron ion co-implantations on the silicon carbide epitaxial layer (102) to form a P-well region (103); Step S2, forming a first barrier layer (21) on the P-well region (103), and performing multiple aluminum ion implantations or aluminum ion and boron ion co-implantations to form a P+ region (104); Step S3, removing the first barrier layer (21), forming a second barrier layer (22), and performing multiple nitrogen ion implantations to form an N+ region (105); Step S4, removing the second barrier layer (22), and simultaneously performing rapid thermal annealing on the P-well region (103), the P+ region (104), and the N+ region (105); Step S5, forming a third barrier layer (23), and etching to form a gate trench region (106); Step S6, removing the third barrier layer (23), performing RCA cleaning, and then performing dry oxygen thermal oxidation in a furnace tube to remove the oxide layer above the P+ region (104) and the N+ region (105), and forming a gate oxide layer (107) in the gate trench region (106); Step S7, performing multi-step deposition on the gate oxide layer (107) using chemical vapor deposition to form polysilicon; after doping the polysilicon, etching is performed to form a gate (108); Step S8, depositing metal on the back side of the silicon carbide substrate (101) to form a drain (109), depositing metal on the P+ region (104) and a portion of the N+ region (105) to form a source (110), and performing rapid thermal annealing on the drain (109) and the source (110) to form an ohmic contact, thereby preparing a silicon carbide trench MOSFET device with a three-sided trench structure.

2. The method for preparing a three-sided trench silicon carbide trench MOSFET device according to claim 1, characterized in that: In step S1, the doping concentration of the silicon carbide substrate (101) is 1e 18 cm -3 ~1e 20 cm -3 , with a thickness of 200µm~1000µm; the doping concentration of the silicon carbide epitaxial (102) is 1e 15 cm -3 ~5e 16 cm -3 , with a thickness of 6µm~40µm; the P-well region (103) is formed at 500℃-800℃, and the net acceptor concentration is 5e 16 cm -3 ~5e 17 cm -3 .

3. The method for preparing a three-sided trench silicon carbide trench MOSFET device according to claim 1, characterized in that: In step S2, the P+ region (104) is formed at 500°C–700°C with a doping concentration of 1e 19 cm -3 ~1e 20 cm -3 , thickness is 0.2µm~0.5µm.

4. The method for preparing a silicon carbide trench MOSFET device with a three-sided trench structure according to claim 1, characterized in that: In step S3, the N+ region (105) is formed at 400°C–600°C with a doping concentration of 1e 19 cm -3 ~1e 20 cm -3 , injection angle 7°–10°, thickness 0.2µm~0.5µm.

5. The method for preparing a silicon carbide trench MOSFET device with a three-sided trench structure according to claim 1, characterized in that: In step S4 , the temperature of the rapid thermal annealing is between 1600° C. and 1800° C., an inert atmosphere or a protective atmosphere is used, and the time is between 1 and 10 minutes.

6. The method for preparing a silicon carbide trench MOSFET device with a three-sided trench structure according to claim 1, characterized in that: In step S5, the gate trench region (106) has a thickness of 0.5µm to 1.2µm, and is 0.05µm to 0.5µm thicker than the thickness of the P-well region (103).

7. The method for preparing a silicon carbide trench MOSFET device with a three-sided trench structure according to claim 1, characterized in that: In step S6, the temperature of dry oxygen thermal oxidation is between 1000°C and 1300°C; the sidewall thickness of the gate oxide layer (107) is between 0.01µm and 0.5µm, and the bottom thickness is between 0.02µm and 0.7µm.

8. The method for preparing a silicon carbide trench MOSFET device with a three-sided trench structure according to claim 1, characterized in that: In step S7, the temperature of chemical vapor deposition is between 550°C and 700°C; the polysilicon doping concentration is 1e 18 ~1e 20 cm -3 .

9. The method for preparing a silicon carbide trench MOSFET device with a three-sided trench structure according to claim 1, characterized in that: In step S8, part of the N+ region (105) is the center of the N+ region (105); the temperature of the rapid thermal annealing is between 900° C. and 1100° C., and the time is 30 seconds to 2 minutes.

10. A silicon carbide trench MOSFET device with a three-sided trench structure prepared by the method according to any one of claims 1 to 9, characterized in that: The present invention comprises a silicon carbide substrate (101), a silicon carbide epitaxial growth (102), a P-well region (103), a P+ region (104), an N+ region (105), a gate oxide layer (107), a gate (108), a drain (109) and a source (110), wherein the drain (109) is arranged on the back side of the silicon carbide substrate (101), the silicon carbide epitaxial growth (102) is arranged on the front side of the silicon carbide substrate (101), and the P-well region (103) is formed on the gate oxide layer (107). On the silicon carbide epitaxial layer (102), the P+ region (104) and the N+ region (105) are formed on the P-well region (103), the gate oxide layer (107) is arranged at the center of the P-well region (103) and the N+ region (105), the gate (108) is arranged on the gate oxide layer (107), and the source (110) is arranged on the P+ region (104) in the entire region and the N+ region (105) in a partial region.

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