Optimized II-type superlattice infrared detector chip bottom filling method, preparation method and infrared detector

Abstract

The invention provides an optimized II-type superlattice infrared detector chip bottom filling method, a preparation method and an infrared detector, and belongs to the field of infrared detectors. The problem that the performance of an infrared detector is affected due to the fact that the filling glue filled in an existing bottom filling process is prone to generating holes and finally causes defects during imaging of an infrared focal plane detector chip is solved. The method comprises the following steps that a dielectric layer is deposited on the surface of an epitaxial material after table top etching is completed, and the height of the dielectric layer is larger than the table top etching depth; after the dielectric layer is deposited, the surface of the dielectric layer is polished to be flat; opening holes in the dielectric layer on the surface of the table board; preparing an indium column in the opening of the dielectric layer, and then performing flip-chip bonding interconnection on the indium column at the epitaxial material end and the indium column on the readout circuit; filling bottom filling glue between the dielectric layer and the reading circuit after the reverse welding interconnection, and then curing the filling glue at high temperature; the invention is applied to the type-II superlattice infrared detector.

Description

Technical Field

[0001] The present application relates to the field of infrared detector technology, and in particular to an optimized bottom filling method and preparation method of a type II superlattice infrared detector chip and an infrared detector. Background Art

[0002] Infrared focal plane detectors (IFPDs) play an important role in national security, military equipment, and the national economy. Type II superlattice IFPDs have garnered considerable attention due to their wide spectral response range, high detection sensitivity, fast response speed, low noise levels, and excellent integrability.

[0003] The existing preparation process of type II superlattice infrared focal plane detector chip is as follows: epitaxial material growth, dry etching of the mesa to produce separately isolated pixel points, mesa passivation protection, passivation opening, electrode preparation, indium pillar preparation, reverse soldering interconnection between the epitaxial material end chip and the readout circuit, bottom fill glue filling and curing, and back thinning and polishing.

[0004] After the Type II superlattice infrared focal plane detector chip and the readout circuit are interconnected by reverse soldering, the micro gap between the infrared focal plane detector chip and the readout circuit needs to be filled with low-temperature resistant epoxy resin. The main purpose is to improve the connection strength between the infrared focal plane detector chip and the readout circuit chip, improve the reliability of the entire device, and adapt to the stress changes caused by repeated temperature changes between room temperature and liquid nitrogen temperature. Figure 1 As shown, the shaded part is epoxy resin filling glue.

[0005] In the existing process, when filling with glue, all gaps between the readout circuit and the infrared focal plane detector chip need to be filled. The specific method is to drip epoxy resin onto the edge of the infrared focal plane detector chip and use the capillary phenomenon principle to make the filling glue flow into the gap between the readout circuit and the infrared focal plane detector chip. However, the existing process has a small table spacing, generally 2 to 5 microns, such as Figure 1 As shown, when the filling glue flows in these small-sized mesa isolation grooves, voids are easily generated, which eventually leads to defects in the imaging of the infrared focal plane detector chip and affects the performance of the infrared detector. Summary of the Invention

[0006] In order to solve the above technical problems, the present application proposes an optimized type II superlattice infrared detector chip bottom filling method, preparation method and infrared detector.

[0007] The technical solution adopted in this application is: an optimized method for underfilling a type II superlattice infrared detector chip, comprising the following steps: Step 1: depositing a dielectric layer on the surface of the epitaxial material after the mesa etching is completed, and the height of the dielectric layer is higher than the mesa etching depth; Step 2: After the dielectric layer is deposited, the surface of the dielectric layer is polished and flattened; Step 3: Opening holes in the dielectric layer on the surface of the table; Step 4: Prepare an indium column in the opening of the dielectric layer, and then perform reverse soldering to interconnect the indium column at the epitaxial material end with the indium column on the readout circuit; Step 5: After the reverse soldering is completed, the bottom filler is filled between the dielectric layer and the readout circuit, and then the filler is cured at high temperature.

[0008] Furthermore, the dielectric layer material is silicon oxide or silicon nitride.

[0009] Furthermore, in step 2, the surface of the dielectric layer is polished and flattened by using a chemical mechanical polishing method.

[0010] Furthermore, in step three, holes are opened in the dielectric layer on the mesa surface through the steps of photolithography, reactive ion etching, and desmearing and cleaning.

[0011] Furthermore, in step 4, the indium pillars in the dielectric layer openings are prepared through photolithography, metal deposition, and stripping and cleaning processes.

[0012] Furthermore, the epitaxial material is a superlattice epitaxial material, and its composition is InAs / GaSb.

[0013] A method for preparing an optimized type II superlattice infrared detector comprises the following steps: Step 1: growing a superlattice epitaxial material on a GaSb substrate using a molecular beam epitaxy method; Step 2: Cleaning the epitaxial material; Step 3: mesa etching hard mask deposition; Step 4: mesa photolithography; Step 5: hard mask etching; Step 6: De-glue and clean; Step 7: The epitaxial material is etched, and then the optimized type II superlattice infrared detector chip bottom filling method is used to complete the dielectric layer deposition, polishing, hole opening, indium column preparation, flip-flop interconnection with the readout circuit, and bottom filling glue filling.

[0014] An infrared detector comprises an infrared focal plane detector chip prepared by adopting the preparation method of the optimized type II superlattice infrared detector.

[0015] The beneficial effects of the present application compared to the prior art are: the gaps between the mesas are filled with a dielectric layer using the method of the present application, thereby avoiding the void defects caused by epoxy resin filling the gaps between the mesas, and can greatly optimize the imaging quality of the infrared focal plane detector chip, thereby improving the performance of the infrared detector. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present application will be further described below with reference to the accompanying drawings: Figure 1 This is a schematic diagram of the structure of the connection between the readout circuit and the epitaxial material end chip after filling with glue using the existing process; Figure 2 This is a schematic diagram of the structure after the method of the present application is used to etch the mesa and then deposit a dielectric layer on the surface of the epitaxial material; Figure 3 This is a schematic diagram of the structure after the dielectric layer is deposited and then polished using the method of the present application; Figure 4 This is a schematic diagram of the structure after holes are opened in the mesa dielectric layer using the method of the present application; Figure 5 This is a schematic diagram of the structure after the dielectric layer is opened and filled with bottom filling glue using the method of the present application. DETAILED DESCRIPTION

[0017] like Figures 2 to 5 As shown, the present application provides an optimized method for underfilling a type II superlattice infrared detector chip. The main difference from the existing process lies in the steps after mesa etching. The specific steps include: Step 1: Deposit a dielectric layer on the surface of the epitaxial material after the mesa etching is completed. The dielectric layer material is silicon oxide or silicon nitride, such as Figure 2 As shown, the height of the dielectric layer is higher than the mesa etching depth.

[0018] Step 2: After the dielectric layer is deposited, the dielectric layer surface is polished and leveled by chemical mechanical polishing (CMP). Figure 3 shown.

[0019] Step 3: Open holes in the dielectric layer on the mesa surface through photolithography, RIE etching (Reactive Ion Etching), and degumming and cleaning. Figure 4 shown.

[0020] Step 4: After opening a hole in the mesa dielectric layer, the indium column in the dielectric layer opening is prepared through photolithography, metal deposition, and stripping and cleaning processes. The indium column at the epitaxial material end is then interconnected with the indium column on the readout circuit by reverse soldering.

[0021] Step 5: After soldering the interconnection, fill the bottom with glue and then cure the glue at high temperature. Figure 5As shown in the figure, the shaded part is the filling glue, which is located between the dielectric layer and the readout circuit. Due to the existence of the dielectric layer, the filling of the table gap is avoided, thereby avoiding the hole defects after filling caused by the table gap, thereby optimizing the imaging quality of the infrared focal plane detector chip.

[0022] The following is a detailed description of the method for preparing the complete type II superlattice infrared detector chip involved in this application based on a specific embodiment.

[0023] A method for preparing a type II superlattice infrared detector chip comprises the following steps: Step 1: Grow a superlattice epitaxial material on a GaSb substrate using molecular beam epitaxy. The superlattice epitaxial material composition is InAs / GaSb, and the epitaxial material thickness is 3 μm.

[0024] Step 2: Clean the epitaxial material to ensure that the surface of the epitaxial material is clean and free of dirt. The cleaning solution is acetone, ethanol, and isopropanol, and the cleaning time is 30 minutes.

[0025] Step 3: Mesa etching hard mask deposition. The hard mask is made of silicon oxide and the deposition method is PECVD (Plasma-Enhanced Chemical Vapor Deposition). The deposition thickness is 1 μm.

[0026] Step 4: Mesa photolithography: A photolithographic pattern was obtained using AZ6130 photoresist with a thickness of 3 μm, an exposure dose of 60 mJ, and a development time of 30 s.

[0027] Step 5: Hard mask etching: Use dry etching to etch the hard mask and transfer the photolithography pattern onto the hard mask. The etching gas is carbon tetrafluoride and trifluoromethane, and the etching time is 30 minutes.

[0028] Step 6: Remove the remaining photoresist on the hard mask by cleaning. The cleaning solvent is acetone, heated in a water bath at 70°C, and the cleaning time is 30 minutes.

[0029] Step 7: Etching the epitaxial material: using silicon oxide as a mask, dry etching the epitaxial material. The equipment used is an ICP etching (Inductively Coupled Plasma Etching) equipment. The etching gases are chlorine, boron trichloride, and argon. The etching time is 15 minutes and the etching depth is 3 μm.

[0030] Step 8: Deposition of the dielectric layer. Silicon oxide is deposited using PECVD to a thickness of 4 μm. The dielectric layer deposition procedure is as follows: Silane at a flow rate of 120 sccm and nitrous oxide at a flow rate of 700 sccm, deposition temperature of 300°C, RF power of 20 W, chamber pressure of 1 Torr, and deposition rate of 100 nm / min. "sccm" stands for Standard Cubic Centimeters per Minute, a unit of measurement for gas flow under standard conditions. "Torr" is a unit of vacuum pressure, defined as 1 / 760 of 1 standard atmospheric pressure. Converted to the International System of Units (SI), 1 Torr ≈ 133.322 Pa (Pascal).

[0031] Step 9: Dielectric layer polishing: After the dielectric layer is deposited, the surface of the epitaxial material is polished flat by chemical mechanical polishing using silicon carbide abrasive.

[0032] Step 10: Open hole etching in the dielectric layer. Using the photoresist as a mask, dry etching is performed on the dielectric layer. The dry etching process uses carbon tetrafluoride and trifluoromethane as etching gases, a platform temperature of 20°C, a process chamber pressure of 30 mTorr, and an RF power of 135 W. After the open hole etching, the remaining photoresist on the dielectric layer surface is removed using an acetone solution heated in a water bath at 70°C.

[0033] Step 11: After the dielectric layer is opened, the indium pillar is prepared through photolithography, metal deposition, and stripping and cleaning processes.

[0034] Step 12: The epitaxial material end chip and the readout circuit are interconnected by flip-flop soldering. After the flip-flop soldering, an underfill process is performed, and then the underfill is cured at 80°C for 16 hours to finally obtain the infrared focal plane detector chip.

[0035] Steps 8 to 12 are the implementation steps of a specific embodiment of the optimized type II superlattice infrared detector chip bottom filling method proposed in this application.

[0036] An embodiment of the present application further proposes an infrared detector, which includes an infrared focal plane detection chip obtained by using the above-mentioned method for preparing the type II superlattice infrared detector chip.

[0037] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An optimized method for underfilling a type II superlattice infrared detector chip, characterized by: The following steps are involved: Step 1: depositing a dielectric layer on the surface of the epitaxial material after the mesa etching is completed, and the height of the dielectric layer is higher than the mesa etching depth; Step 2: After the dielectric layer is deposited, the surface of the dielectric layer is polished and flattened; Step 3: Opening holes in the dielectric layer on the surface of the table; Step 4: Prepare an indium column in the opening of the dielectric layer, and then perform reverse soldering to interconnect the indium column at the epitaxial material end with the indium column on the readout circuit; Step 5: After the reverse soldering is completed, the bottom filler is filled between the dielectric layer and the readout circuit, and then the filler is cured at high temperature.

2. The optimized underfill method for a type II superlattice infrared detector chip according to claim 1, characterized in that: The dielectric layer is made of silicon oxide or silicon nitride.

3. The optimized underfill method for a type II superlattice infrared detector chip according to claim 1, characterized in that: In step 2, the surface of the dielectric layer is polished and flattened by using a chemical mechanical polishing method.

4. The optimized underfill method for a type II superlattice infrared detector chip according to claim 1, characterized in that: In step three, holes are opened in the dielectric layer on the surface of the mesa through the steps of photolithography, reactive ion etching, and desmearing and cleaning.

5. The optimized underfill method for a type II superlattice infrared detector chip according to claim 1, characterized in that: In step 4, the indium pillars in the dielectric layer openings are prepared through photolithography, metal deposition, and stripping and cleaning processes.

6. An optimized underfill method for a type II superlattice infrared detector chip according to any one of claims 1 to 5, characterized in that: The epitaxial material is a superlattice epitaxial material with a composition of InAs / GaSb.

7. A method for preparing an optimized type II superlattice infrared detector, characterized in that: The following steps are involved: Step 1: growing a superlattice epitaxial material on a GaSb substrate using a molecular beam epitaxy method; Step 2: Cleaning the epitaxial material; Step 3: mesa etching hard mask deposition; Step 4: mesa photolithography; Step 5: hard mask etching; Step 6: De-glue and clean; Step 7: Etch the epitaxial material, and then use the optimized type II superlattice infrared detector chip bottom filling method described in any one of claims 1 to 5 to complete the dielectric layer deposition, polishing, hole opening, indium column preparation, flip-flop interconnection with the readout circuit, and bottom fill glue filling.

8. An infrared detector, characterized in that: The invention comprises an infrared focal plane detector chip prepared by adopting the preparation method of the optimized type II superlattice infrared detector as claimed in claim 7.

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