High aspect ratio contact etch with additive gas

Abstract

A method of processing a substrate is disclosed, the method comprising: flowing a fluorocarbon, a metal halide, and molecular hydrogen (H2) into a plasma processing chamber configured to hold a substrate, the substrate comprises a dielectric layer which is used as an etching target and comprises silicon oxide and a patterned hard mask which is arranged on the dielectric layer and comprises polycrystalline silicon (poly-Si); generating a plasma in the plasma processing chamber while flowing the gases; and forming high aspect ratio features by exposing the substrate to the plasma to etch recesses in the dielectric layer, wherein a metal-containing passivation layer is formed on the patterned hard mask during the exposure.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims the benefit of U.S. non-provisional application No. 18 / 191,098, filed on March 28, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates generally to methods of processing substrates and, in particular embodiments, to high aspect ratio contact (HARC) etching with additive gases. Background Art

[0004] Typically, semiconductor devices such as integrated circuits (ICs) are manufactured by sequentially depositing and patterning layers of dielectric, conductive, and semiconductor materials on a substrate to form a network of electronic components and interconnecting elements (e.g., transistors, resistors, capacitors, metal lines, contacts, and vias) integrated into a monolithic structure. Many of the processing steps used to form the constituent structures of semiconductor devices are performed using plasma processes.

[0005] The semiconductor industry has repeatedly scaled the minimum feature size in semiconductor devices down to a few nanometers to increase component packing density. Consequently, the semiconductor industry increasingly demands plasma processing technologies that can deliver processes for patterning features with accuracy, precision, and profile control, often at the atomic level. Meeting this challenge, along with the uniformity and repeatability required for high-volume IC manufacturing, requires further innovation in plasma processing technology. Summary of the Invention

[0006] According to an embodiment of the present invention, a method of processing a substrate includes flowing a fluorocarbon, a metal halide, and molecular hydrogen (H2) into a plasma processing chamber configured to hold a substrate, the substrate including a dielectric layer comprising silicon oxide as an etch target and a patterned hard mask comprising polycrystalline silicon (poly-Si) on the dielectric layer; generating a plasma in the plasma processing chamber while flowing the gases; and forming high aspect ratio features by exposing the substrate to the plasma to etch recesses in the dielectric layer, wherein a metal-containing passivation layer is formed on the patterned hard mask during the exposure.

[0007] According to an embodiment of the present invention, a method of processing a substrate includes flowing a fluorocarbon compound and a silane compound into a plasma processing chamber configured to hold a substrate, the substrate including a dielectric layer containing silicon as an etch target and a patterned hard mask on the dielectric layer; generating a plasma in the plasma processing chamber while flowing the gases; and forming high aspect ratio features by exposing the substrate to the plasma to etch recesses in the dielectric layer, wherein a silicon-containing passivation layer is formed on the patterned hard mask during the exposure.

[0008] According to an embodiment of the present invention, a method of processing a substrate includes flowing a fluorocarbon into a plasma processing chamber configured to hold a substrate, the substrate including a dielectric layer as an etching target and a patterned hard mask on the dielectric layer; maintaining a plasma generated by the fluorocarbon in the plasma processing chamber while flowing the fluorocarbon; flowing a metal halide and molecular hydrogen (H2) into the plasma processing chamber while maintaining the plasma; flowing a silane compound into the plasma processing chamber while maintaining the plasma; and forming high aspect ratio features by exposing the substrate to the plasma to etch recesses in the dielectric layer, wherein a passivation layer is formed on the patterned hard mask during the exposure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0010] Figures 1A to 1C A cross-sectional view of an example substrate during a semiconductor fabrication process including a plasma etch process for forming high aspect ratio (HAR) features according to various embodiments is shown. Figure 1A The incoming substrate including the patterned hard mask layer, dielectric layer and etch stop layer (ESL) is shown. Figure 1B shows a substrate during formation of HAR features by a plasma etch process, and Figure 1C shows the substrate after the plasma etching process;

[0011] Figure 2 An energy level diagram showing the adsorption / desorption of metal fluoride species (WF4) on a silicon oxide surface;

[0012] Figure 3 An energy level diagram showing the adsorption / desorption of metal fluoride species (WF4) on the silicon surface;

[0013] Figure 4An energy level diagram showing the formation of a deposition precursor (WF5) from a metal fluoride species (WF6) via heavy particle assisted dissociation.

[0014] Figure 5 An energy level diagram showing the formation of a deposition precursor (SiH3) from a silane species (SiH4) via heavy particle assisted dissociation;

[0015] Figures 6A to 6C A process flow diagram illustrating a method for a plasma etch process for forming HAR features according to various embodiments is shown, wherein Figure 6A Demonstrates an embodiment, Figure 6B Alternative embodiments are presented, and Figure 6C Yet another embodiment is presented; and

[0016] Figure 7 An example plasma processing tool according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0017] The present application relates to the manufacture of semiconductor devices (e.g., integrated circuits including semiconductor devices), and more particularly to high-capacity three-dimensional (3D) memory devices, such as 3D-NAND (or vertical NAND), 3D-NOR, or dynamic random access memory (DRAM) devices. The manufacture of such devices may typically require conformal high aspect ratio (HAR) features (e.g., contact holes) to form circuit elements. Features with an aspect ratio (the ratio of the height of the feature to the width of the feature) greater than 50:1 are generally considered to be high aspect ratio features, and in some cases, manufacturing higher aspect ratios (e.g., 100:1) may be desirable for advanced 3D semiconductor devices. However, conventional HAR etching methods may typically include dozens and sometimes hundreds of processing steps (e.g., used as a cyclic process), which complicates process optimization and reduces etching throughput. In addition, conventional HAR etching methods may often suffer from severe deformation and distortion in the final structure. Therefore, the problems of low wafer throughput, poor uniformity, and missing contacts remain challenging for HAR etching processes. Therefore, a simple but effective HAR process may be desired. Embodiments of the present application disclose methods for fabricating HAR features using a plasma etch process based on fluorocarbons enhanced by additive gases such as metal fluorides and silane compounds. Using the embodiments discussed herein, HAR features with aspect ratios greater than 50:1, for example, between 50:1 and 200:1, can be fabricated.

[0018] The plasma etching methods described in the present disclosure can overcome various challenges posed to plasma etching processes for HAR features. In various embodiments, the plasma etching process can advantageously achieve a high AR of equal to or greater than 100:1 with good selectivity to the hard mask. In particular, the additive gas can improve the mask selectivity (e.g., the etch selectivity to a mask containing polysilicon) by selectively providing a metal-containing or silicon-containing passivation layer on the mask. These methods can be used to etch dielectric layers (such as silicon oxide) with improved selectivity while maintaining a good etch rate. The plasma etching process according to these methods can also be performed in a single step, rather than a cyclic etching process that requires multiple steps.

[0019] In the following, according to various embodiments, Figures 1A to 1C An exemplary plasma etch process via additive gas assistance for forming desired high aspect ratio (HAR) features is discussed. Figure 2 and Figure 3 , the selective deposition of a metal-containing passivation layer on a hard mask relative to an etch target is described using the calculated formation energy of the deposition precursor. Figure 4 and Figure 5 , describes possible reaction pathways for forming metal-containing or silicon-containing deposit precursors. Figures 6A to 6C An example process flow diagram is shown in . Figure 7 An example capacitively coupled plasma (CCP) processing tool for use with the example methods is shown in FIG. All figures are for illustration purposes only and are not drawn to scale.

[0020] Figure 1A A cross-sectional view of an example incoming substrate 100 including a dielectric layer 110 and a patterned hard mask layer 120 is shown, according to various embodiments.

[0021] In one or more embodiments, the substrate 100 may be a silicon wafer or a silicon-on-insulator (SOI) wafer. In some embodiments, the substrate may include a silicon-germanium wafer, a silicon carbide wafer, a gallium arsenide wafer, a gallium nitride wafer, and other compound semiconductors. In other embodiments, the substrate includes heterogeneous layers, such as silicon-germanium-on-silicon, gallium nitride-on-silicon, silicon-carbon-on-silicon, and multilayer silicon on a silicon or SOI substrate.

[0022] In various embodiments, substrate 100 is part of, or includes, a semiconductor device and may have undergone multiple processing steps following, for example, conventional processes. For example, a semiconductor structure may include substrate 100 in which various device regions are formed. At this stage, substrate 100 may include isolation regions such as shallow trench isolation (STI) regions and other regions formed therein. In various embodiments, high aspect ratio (HAR) features may be formed on substrate 100 by the plasma etching methods described in the present disclosure, and may subsequently be used to manufacture 3D memory devices such as 3D-NAND (or vertical NAND), 3D-NOR, or dynamic random access memory (DRAM).

[0023] A dielectric layer 110 may be formed on the substrate 100. In various embodiments, the dielectric layer 110 is a target layer to be patterned into one or more high aspect ratio (HAR) features. In certain embodiments, the HAR features etched into the dielectric layer 110 may be contact holes, slits, or other suitable structures including recesses. In certain embodiments, the dielectric layer 110 may be a silicon oxide layer or other layer that may be useful for DRAM. In alternative embodiments, the dielectric layer 110 may include silicon nitride, silicon oxynitride, an O / N / O / N layer stack (a stack of oxide and nitride layers), or any suitable material that may be used in, for example, a 3D-NAND stack. The dielectric layer 110 may be deposited using appropriate techniques such as vapor deposition (including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD)) and other plasma processes such as plasma enhanced CVD (PECVD) and other processes. In one embodiment, the dielectric layer 110 has a thickness between 1 μm and 10 μm. In another embodiment, the dielectric layer 110 may include a layer stack, wherein each layer of the stack has a thickness between 50 nm and 2.5 μm.

[0024] In some embodiments, the substrate 100 may further include an etch stop layer (ESL) 105 between the substrate 100 and the dielectric layer 110. The ESL 105 may include a dielectric material (e.g., a dielectric material) that provides high etch selectivity during a plasma etching process. Figure 1C ), in order to prevent undesired damage to the substrate 100. In various embodiments, the ESL is merely optional and may not be present on the substrate 100, where the substrate 100 itself may be etch-stopped during the plasma etching process.

[0025] Still refer to Figure 1A, a patterned hard mask layer 120 is formed on the dielectric layer 110. In various embodiments, the patterned hard mask layer 120 may include polysilicon (poly-Si). In one or more embodiments, the patterned hard mask layer 120 may include spin-on carbon, tungsten carbide, boron carbide, or other suitable mask materials. Figure 1A Although not shown in the figures, the patterned hard mask layer 120 may include a stack of layers of different materials (e.g., poly-Si and another material). The patterned hard mask layer 120 may be formed by first depositing a hard mask layer using, for example, a suitable spin coating technique or a vapor deposition technique such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and other plasma processes such as plasma enhanced CVD (PECVD) and other processes. The deposited hard mask layer may then be patterned using a photolithography process and an anisotropic etching process (e.g., using an oxygen-based etching chemistry). The relative thicknesses of the patterned hard mask layer 120 and the dielectric layer 110 may have any suitable relationship. For example, the patterned hard mask layer 120 may be thicker than the dielectric layer 110, thinner than the dielectric layer 110, or the same thickness as the dielectric layer 110. In some embodiments, the patterned hard mask layer 120 has a thickness between 1 μm and 4 μm. In one embodiment, the patterned hard mask layer 120 comprises poly-Si and has a thickness of 2.5 μm and a critical dimension (CD) of 75 nm, but in other embodiments, the thickness and CD of the patterned hard mask layer 120 may each have any suitable value.

[0026] The patterned hard mask layer 120 and the dielectric layer 110 may be considered together as part of the substrate 100. In addition, the substrate 100 may further include other layers. For example, for the purpose of patterning the hard mask layer, there may be a three-layer structure including a photoresist layer, a SiON layer, and an optical planarization layer (OPL).

[0027] Figure 1B The substrate 100 is shown during the formation of HAR features by a plasma etch process.

[0028] According to various embodiments, fabricating HAR features in the dielectric layer 110 may be performed by a plasma etching process using a process gas combination including an additive gas for passivation.

[0029] The plasma etching process may include a reactive ion etching (RIE) process using a halogen-containing etching gas. In various embodiments, the etching gas may contain a hydrofluorocarbon, a combination of a hydrocarbon and a fluorine-containing gas, or a combination of a fluorocarbon and a hydrogen-containing gas. In certain embodiments, one or more fluorocarbons may be used as the main etching gas. In one embodiment, a saturated fluorocarbon, an unsaturated fluorocarbon, or a combination thereof may be included in the process gas. In the present disclosure, an unsaturated fluorocarbon refers to any compound containing carbon and fluorine having at least one carbon-carbon double bond (C=C bond) or triple bond (C≡C bond), and a saturated fluorocarbon refers to any compound containing carbon and fluorine without any C=C bond or C≡C bond. Examples of unsaturated fluorocarbons and saturated fluorocarbons include, but are not limited to, hexafluorobutadiene (C4F6), hexafluoro-2-butyne (C4F6), and hexafluorocyclobutene (C4F6), as well as octafluoropropane (C3F8), perfluorobutane (C4F6), and octafluoropropane (C3F8). 10 ) and perfluoropentane (C5F 12 ).

[0030] In some embodiments, other gases such as inert gases (e.g., Ar, He, or N2) or balancers (e.g., O2 or CO) may also be added to the process gas. In various embodiments, one or more balancers may be included in the process gas used for the plasma etching process in order to control the extent of polymer deposition. Generally, some polymer deposition may be beneficial in providing sidewall passivation for the mask and etch target, but excessive deposition may result in slower etch rates, irregularities in the etch profile, and even blockages. Therefore, polymer deposition may need to be adequately adjusted, for example using a balancer, to achieve a good balance between sidewall passivation and etch rate / profile.

[0031] In this disclosure, any list presenting possible compositions, conditions, or process variations includes any reasonable combination thereof, and thus the term "or" used in the list does not represent any exclusive selection of a particular composition, condition, or process variation. For example, in certain embodiments, argon (Ar) and molecular oxygen (O2) may be included as an inert gas and a balance agent, respectively. In another embodiment, molecular nitrogen (N2) and O2 may be included in the process gas.

[0032] In alternative embodiments, the gas composition may further include a third fluorocarbon. In one embodiment, the third fluorocarbon may be octafluorocyclobutane (C4F8), octafluoro-2-butene (C4F8), hexafluoropropylene (C3F6), carbon tetrafluoride (CF4), or trifluoromethane (CHF3). Although the above examples primarily depict fluorine-based etching gases, other halogen-containing gases (e.g., BCl3, Cl2, and HBr) may also be used.

[0033] While the carbon and fluorine species from these primary etch gases can form a polymer layer that is deposited on the surface and can provide a degree of passivation, the inventors of the present application have determined that the etch process can still suffer from issues such as insufficient mask selectivity and bowing. For example, bowing can still occur, especially if the etch process time is increased to increase the aspect ratio of the feature.

[0034] In order to improve the plasma etching process, various embodiments of the disclosed method utilize the incorporation of additive gases for better passivation. In various embodiments, the additive gas may include a mixture of a metal halide and a hydrogen-containing gas, or a silane compound (silane). In the present disclosure, silane compounds and silane refer to a class of compounds containing silicon and distinguished from SiH4 (which is referred to as monosilane in the present disclosure). The metal halide may contain a refractory metal. In certain embodiments, the metal halide may include tungsten hexafluoride (WF6), molybdenum hexafluoride (MoF6), niobium hexafluoride (NbF6), or tungsten hexachloride (WCl6). In other embodiments, the metal halide may include aluminum or titanium, such as aluminum trichloride (AlCl3) or titanium tetrachloride (TiCl4) in one embodiment. In one or more embodiments, the hydrogen-containing gas may include molecular hydrogen (H2), hydrogen fluoride (HF), hydrogen bromide (HBr), or methane (CH4). In various embodiments, the silane compound may include monosilane (SiH4), disilane (Si2H6), or halogenated silane (SiH x X y ).

[0035] Although not wishing to be bound by any theory, as shown below Figure 5 As further described in Figure 6, the use of a hydrogen-containing gas (e.g., H2) in addition to a metal halide (e.g., WF6) can advantageously enhance the formation of a deposition precursor via heavy particle assisted dissociation. In contrast, when using a silane compound, such a secondary additive (e.g., H2) can be omitted because other plasma species (e.g., fluorine species) can sufficiently induce heavy particle assisted dissociation.

[0036] In one embodiment, the plasma etching process may be an oxide etch for etching silicon oxide using poly-Si as an etch mask and an etching process gas comprising C4F8, C4F6, C3F8, O2, NF3, WF6, and H2. In another embodiment, the plasma etching process may be the same oxide etch, but the etching process gas may comprise C4F8, C4F6, C3F8, O2, NF3, and SiH4.

[0037] In order to favorably affect the plasma etching process, only a small amount of additive gas may be required. In various embodiments, the flow rate of the metal halide (e.g., WF6) can be less than 1% of the total process gas flow, for example, between 0.01% and 1%. In some embodiments, it can be less than 0.3% of the total process gas flow. In another embodiment, the flow rate of the metal halide can be determined relative to a component of the main etching gas (e.g., fluorocarbon), for example, between 1% and 5% of the flow rate of that component. Excessive amounts of metal halide (e.g., >5% of the total gas flow) may result in undesirable deposits on the substrate, chamber walls, and other surfaces in the equipment, and thus minimal metal halide addition can be used in various embodiments.

[0038] In various embodiments, the gas flow rate can be mass-based and controlled by one or more mass flow controllers at the gas inlet system to introduce the gas into the plasma processing chamber. Therefore, unless otherwise specified, the gas flow rate refers to the gas flow rate at the entry point of the plasma processing chamber.

[0039] In some embodiments, the flow rate of the metal halide (e.g., WF6) is less than 2 sccm, for example, between 0.1 sccm and 2 sccm. In some embodiments, the additive gas may be pulsed into the plasma processing chamber rather than a constant flow, which may enable the introduction of an amount of gas that is less than the lower limit of the constant flow rate provided by the mass flow controller.

[0040] Still refer to Figure 1B , a recess 125 can be formed in the dielectric layer 110 by a plasma etching process. The recess 125 can be of any shape and structure, for example, designed to produce a contact hole, a slit, or other suitable structure containing a recess useful for semiconductor device manufacturing. In various embodiments, the feature defined by the recess 125 has a critical dimension (CD) of 200nm or less. In some embodiments, the CD can be between 50nm and 200nm. For example, the feature can include a slit with a CD of approximately 150nm. In an alternative embodiment, the recess 125 can include a hole with a top opening having a diameter of 80nm or less.

[0041] like Figure 1BAs shown in FIG, a passivation layer 130 may be formed on the patterned hard mask layer 120. In various embodiments, the additive gas may change the chemical composition of the passivation layer 130 and result in improved mask selectivity and overall etching performance. Generally, the passivation layer 130 may contain metal or silicon, depending on the type of additive gas (i.e., metal-containing or silicon-containing). For example, a metal or silicon species may be incorporated into a carbon-containing polymer layer. Alternatively, the passivation layer may contain metal fluoride or silicon fluoride. The passivation layer 130 may cover the entire top surface and sidewalls of the patterned hard mask layer 120, as shown in FIG. Figure 1B In some embodiments, the passivation layer 130 may be selectively deposited on the patterned hard mask layer 120 but not on the surface of the dielectric layer 110 within the recess 125 . However, in other embodiments, the passivation layer 130 may also be deposited on a portion of the surface of the dielectric layer 110 .

[0042] Figure 1C The substrate 100 is shown after the plasma etching process is completed.

[0043] The plasma etching process is continued by etching through the entire thickness of the target layer (ie, dielectric layer 110), Figure 1B The recess 125 shown in FIG can be further extended and reach / reach the top surface of the ESL 105, as shown in FIG. Figure 1C As shown in .

[0044] In some embodiments, although Figure 1C Not shown, a polymer passivation layer comprising carbon and fluorine may still be present on the surface of dielectric layer 110 within recess 125, which may provide a degree of sidewall protection. In one embodiment, polymer deposition on the exposed surface of ESL 105 may advantageously enhance the etch stop capability of ESL 105.

[0045] In various embodiments, HAR features (e.g., Figure 1B and Figure 1C ). Various process parameters and processing systems for these methods can be selected so that the plasma etching conditions are suitable for manufacturing HAR features. Factors to consider may include controlled deposition levels, mask selectivity, sidewall passivation in the HAR features, and good CDU. In certain embodiments, the plasma etching process can be advantageously performed as a single step process to form high aspect ratio (HAR) features with aspect ratios of 100:1 or higher. Although a continuous process flow for the plasma etching process may be advantageous, other embodiments are possible in which these methods are applied as part of a cyclic or multi-step process.

[0046] In various embodiments, RF pulses in the kHz range can be used to power the plasma. Using RF pulses can help generate high-energy ions (>keV) in the plasma used for the plasma etch process while reducing charging effects. The charging effect during the process is a phenomenon in which electrons accumulate charge on the insulating material (e.g., silicon oxide of the dielectric layer 110), generating a local electric field that can direct the charged ions to the sidewalls and cause non-vertical etching. Therefore, fine-tuning the power conditions of the plasma etch process can also be important to minimize the widening of the critical dimension (CD) and profile deformation of high aspect ratio (HAR) features. In certain embodiments, a kHz modulated dual-frequency RF generator is used to power the plasma, with a typical pulse duty cycle between 20% and 90%. In one embodiment, bias powers of 40 MHz at 2 kW and 400 kHz at 18 kW can be pulsed at a frequency of 5 kHz and a duty cycle of 50%.

[0047] For plasma etching of dielectric layers using plasma as discussed in various embodiments, capacitively coupled plasma (CCP) may be preferred over inductively coupled plasma (ICP) to achieve better anisotropic etching and improved etch profiles with a controllable deformation range while maintaining good etch selectivity. However, the HARC etching method can be applied to any type of plasma processing system (e.g., CCP, ICP, microwave, etc.).

[0048] Figure 2 An energy level diagram showing the adsorption / desorption of a metal fluoride species (WF4) on a silicon oxide surface.

[0049] Figure 3 An energy level diagram showing the adsorption / desorption of a metal fluoride species (WF4) on a silicon surface.

[0050] The inventors of this application have calculated the adsorption / desorption energy of possible surface species through simulation to demonstrate the influence of additive gas on plasma etching process in various embodiments. Figure 2 and Figure 3As shown in , the desorption energy of the surface metal fluoride species (WF4) from silicon (4.643 eV) is shown to be more than twice the desorption energy of WF4 from silicon oxide (2.248 eV). This significant contrast in desorption energies demonstrates that the surface metal fluoride species (WF4) may be energetically more preferred on silicon than on silicon oxide. Therefore, it can be proposed that a passivation layer comprising a metal fluoride species may selectively appear on a mask material comprising poly-Si rather than an etch target comprising silicon oxide during a plasma etch process. In other words, for a high aspect ratio (HAR) etch process, species from the additive gas may "attach" closer to the top portion of the substrate (e.g., the mask layer) than to the bottom portion of the substrate (e.g., the etch front of the etch target layer). Such selective deposition of the passivation layer can be beneficial in preventing any adverse effects on the oxide etch rate while improving mask selectivity.

[0051] The inventors of the present application further demonstrated through controlled experiments that excellent mask selectivity can be achieved by adding WF6 to a fluorine-based plasma etching process. In one embodiment, a silicon oxide to poly-Si etch selectivity exceeding 180 can be achieved. In another embodiment, the addition of WF6 can increase the oxide to nitride etch selectivity by at least two times.

[0052] Figure 4 An energy level diagram showing the formation of a deposition precursor (WF5) from a metal fluoride species (WF6) via heavy particle assisted dissociation.

[0053] Figure 5 An energy level diagram is shown for the formation of a deposition precursor (SiH3) from a silane species (SiH4) via heavy particle assisted dissociation.

[0054] The inventors of the present application also calculated the formation energy of possible deposition precursors from additive gas components by simulation to demonstrate possible reaction pathways for deposition. Because stable forms of metal halides (e.g., WF6) or silane compounds (e.g., SiH4) may be unlikely to form a deposit layer directly on the surface due to their closed shell structure and the absence of dangling bonds, they may first need to form a deposition precursor under plasma conditions, for example, via dissociation. The inventors of the present application determined that such dissociation can be induced not only by electron impact, but also by collisions with heavy particles (e.g., H atoms). By including secondary additives such as H2, this heavy particle-assisted dissociation can further increase the possibility of metal halide dissociation. In Figure 4The calculated energy level diagram demonstrates a thermodynamically favorable process (-1.125 eV) for the possible deposition precursor (WF5) induced by the reaction between WF6 and H atoms. The activation energy for the formation of the transition state (TS) is also found to be small (0.024 eV). It should be noted that the continuous dissociation via the same heavy particle assisted dissociation (i.e., WF n +H→WF n-1 +HF) may be present and generate reactive deposition precursors. As a result, in various embodiments using secondary additives (such as H2), larger amounts of WF6 can be advantageously generated without increasing the flow rate of WF6 or increasing the source power of the plasma. x Free radicals.

[0055] Compared to metal halides, silane compounds can be dissociated relatively easily without the aid of secondary additive gases. This is because silane compounds can directly react with fluorine species in the plasma to dissociate. Figure 5 The calculated energy level diagram demonstrates a thermodynamically favorable process (-1.418 eV) of the possible deposition precursor (SiH3) induced by the reaction between SiH4 and F atoms. The continuous dissociation via the same heavy particle assisted dissociation (i.e., SiH n +F→SiH n-1 +HF) may be present and generate reactive deposition precursors.

[0056] As described above, various embodiments of methods of plasma etching processes can be used to fabricate HAR features useful for: 3D memory devices (such as 3D-NAND (or vertical NAND), 3D-NOR, or dynamic random access memory (DRAM) devices) or other semiconductor devices (including logic devices). Additive gases that can enhance mask selectivity can include a combination of metal fluorides and hydrogen-containing gases, or silane compounds. In some embodiments, both metal fluorides and silane compounds can be used together for the additive gas. In one embodiment, the process gas can include fluorocarbons, WF6 and SiH4, with or without other gas components (e.g., O2, H2, Ar or NF3). In such an embodiment, the passivation layer formed during the plasma process can include both metal and silicon from the additive gas.

[0057] In other embodiments, the process gas composition can be dynamically adjusted during the plasma etch process. In one or more embodiments, both metal halides and silane compounds can be used in the process gas, and their flow rates can be controlled independently while maintaining a constant total gas flow rate of the process gas. Various other process parameters (such as process time, substrate temperature, plasma source power, and bias power) can also be adjusted according to the process recipe depending on the application.

[0058] Figures 6A to 6C A process flow diagram of a method of a plasma etching process according to various embodiments is shown. The process flow may follow the diagram discussed above ( Figures 1A to 1C ) and therefore will not be described again.

[0059] exist Figure 6A In the process flow 60, a fluorocarbon, a metal halide, and molecular hydrogen (H2) are flowed into a plasma processing chamber configured to hold a substrate including a dielectric layer including silicon oxide as an etch target and a patterned hard mask including polycrystalline silicon (poly-Si) on the dielectric layer (block 610, Figure 1A Subsequently, while flowing the gas, a plasma may be generated in the plasma processing chamber (block 620), and high aspect ratio (HAR) features may be formed by exposing the substrate to the plasma to etch recesses in the dielectric layer, wherein a metal-containing passivation layer is formed on the patterned hard mask during the exposure (block 630, Figure 1B and Figure 1C ).

[0060] exist Figure 6B In another process flow 62, a fluorocarbon compound and a silane compound are flowed into a plasma processing chamber configured to hold a substrate including a dielectric layer containing silicon as an etch target and a patterned hard mask on the dielectric layer (block 612, Figure 1A Subsequently, while flowing the gas, a plasma may be generated in the plasma processing chamber (block 620), and HAR features may be formed by exposing the substrate to the plasma to etch recesses in the dielectric layer, wherein a silicon-containing passivation layer is formed on the patterned hard mask during the exposure (block 632, Figure 1B and Figure 1C ).

[0061] exist Figure 6C In yet another process flow 64, a fluorocarbon is flowed into a plasma processing chamber configured to hold a substrate including a dielectric layer as an etch target and a patterned hard mask on the dielectric layer (block 614, Figure 1A). Subsequently, while flowing the fluorocarbon, a plasma may be generated from the fluorocarbon and maintained in the plasma processing chamber (block 624). While maintaining the plasma, a metal halide and H2 may be flowed into the plasma processing chamber (block 626), and a silane compound may also be flowed into the plasma processing chamber (block 628). Subsequently, HAR features may then be formed by exposing the substrate to the plasma to etch recesses in the dielectric layer, wherein a passivation layer is formed on the patterned hard mask during the exposure (block 634, Figure 1B and Figure 1C ).

[0062] Figure 7 An example capacitively coupled plasma (CCP) processing tool 70 is shown in accordance with an embodiment of the present disclosure.

[0063] For demonstration purposes, Figure 7 A substrate 100 is shown placed on a substrate holder 754 (e.g., a circular electrostatic chuck (ESC)) near the bottom of a plasma processing chamber 710. A heater / cooler 756 surrounding the substrate holder 754 can optionally be used to maintain the substrate 100 at a desired temperature. The temperature of the substrate 100 can be maintained by a temperature controller 740 connected to the substrate holder 754 and the heater / cooler 756. The ESC can be coated with a conductive material (e.g., a carbon-based or metal nitride-based coating) so that electrical connection can be made to the substrate holder 754.

[0064] like Figure 7 As shown in FIG, the substrate support 754 can be the bottom electrode of the plasma processing chamber 710. Figure 7 In the illustrative example shown in FIG, the substrate support 754 is connected to two RF bias power sources 770 and 780 through DC blocking capacitors 790 and 791. In some embodiments, the conductive circular plate near the top of the plasma processing chamber 710 is the top electrode 752. Figure 7 , the top electrode 752 is connected to a DC power source 750 of the plasma processing system 70 .

[0065] Gases can be introduced into the plasma processing chamber 710 via a gas delivery system 720. The gas delivery system 720 includes a plurality of gas flow controllers to control the flow of the various gases into the chamber. Each of the gas flow controllers of the gas delivery system 720 can be assigned to each of the fluorocarbons, noble gases, or balancers. In some embodiments, an optional center / edge divider can be used to independently adjust the gas flow at the center and edge of the substrate 100.

[0066] RF bias power sources 770 and 780 can be used to supply continuous wave (CW) or pulsed RF power to sustain a plasma, such as plasma 760. Plasma 760, shown between the top electrode 752 and the bottom electrode (also substrate support 754), illustrates a plasma generated directly adjacent to the substrate 100 in the plasma processing chamber 710 of the plasma processing system 70. Etching can be performed by exposing the substrate 100 to the plasma 760 while simultaneously powering the substrate support 754 with the RF bias power sources 770, 780 and, optionally, the top electrode 752 with the DC power source 750.

[0067] The configuration of the plasma processing system 70 described above is merely exemplary. In alternative embodiments, various alternative configurations may be used for the plasma processing system 70. For example, instead of Figure 7 In the CCP, an inductively coupled plasma (ICP) can be used, wherein the RF source power is coupled to a planar coil on the top dielectric cover, and the gas inlet or gas outlet can be coupled to the upper wall, etc. In various embodiments, the RF power, chamber pressure, substrate temperature, gas flow rate, and other plasma process parameters can be selected according to the corresponding process recipe. In some embodiments, the plasma processing system 70 can be a resonator such as a helical resonator.

[0068] Although not described herein, embodiments of the present invention may also be applied to remote plasma systems as well as batch systems.For example, a substrate holder may be capable of supporting multiple wafers that rotate about a central axis as the multiple wafers pass through different plasma zones.

[0069] Example embodiments of the present invention are summarized herein. Other embodiments may be understood from the entire specification and claims presented herein.

[0070] Example 1. A method of processing a substrate, the method comprising: flowing a fluorocarbon, a metal halide, and molecular hydrogen (H2) into a plasma processing chamber configured to hold a substrate, the substrate comprising a dielectric layer comprising silicon oxide as an etch target and a patterned hard mask comprising polycrystalline silicon (poly-Si) on the dielectric layer; generating a plasma in the plasma processing chamber while flowing the gases; and forming high aspect ratio features by exposing the substrate to the plasma to etch recesses in the dielectric layer, wherein a metal-containing passivation layer is formed on the patterned hard mask during the exposure.

[0071] Example 2. The method of Example 1, further comprising flowing molecular oxygen (O2).

[0072] Example 3. A method as described in one of Examples 1 or 2, wherein the fluorocarbon comprises C4F6, C4F8, CF4, C3F8, CHF3 or CH2F2.

[0073] Example 4. The method of any one of Examples 1 to 3, wherein the metal halide is tungsten hexafluoride (WF6).

[0074] Example 5. The method of any one of Examples 1 to 4, wherein the metal halide is molybdenum hexafluoride (MoF6), niobium hexafluoride (NbF6), tungsten hexachloride (WCl6), aluminum trichloride (AlCl3) or titanium tetrachloride (TiCl4).

[0075] Example 6. The method of any one of examples 1 to 5, wherein the flow rate of the metal halide is between 0.01% and 1% of the total flow rate of the gases.

[0076] Example 7. The method of any one of examples 1 to 6, wherein the metal halide is flowed intermittently while exposing the substrate to the plasma.

[0077] Example 8. The method of any one of Examples 1 to 7, wherein the dielectric layer comprises a layer stack of silicon oxide and silicon nitride.

[0078] Example 9. The method of any one of Examples 1 to 8, wherein the aspect ratio of the recess is at least 50:1.

[0079] Example 10. A method of processing a substrate, the method comprising: flowing a fluorocarbon compound and a silane compound into a plasma processing chamber configured to hold a substrate, the substrate comprising a dielectric layer containing silicon as an etch target and a patterned hard mask on the dielectric layer; generating a plasma in the plasma processing chamber while flowing the gases; and forming high aspect ratio features by exposing the substrate to the plasma to etch recesses in the dielectric layer, wherein a silicon-containing passivation layer is formed on the patterned hard mask during the exposure.

[0080] Example 11. The method of Example 10, further comprising flowing molecular oxygen (O2).

[0081] Example 12. A method as described in one of Examples 10 or 11, wherein the fluorocarbon comprises C4F6, C4F8, CF4, C3F8, CHF3 or CH2F2.

[0082] Example 13. The method of any one of Examples 10 to 12, wherein the silane compound is monosilane (SiH4).

[0083] Example 14. The method of any one of Examples 10 to 13, wherein the silane compound is disilane (Si2H6) or a silane halide (SiH x X y ).

[0084] Example 15. The method of any one of Examples 10 to 14, wherein the dielectric layer comprises silicon oxide.

[0085] Example 16. The method of any one of Examples 10 to 15, wherein the dielectric layer comprises silicon nitride.

[0086] Example 17. The method of any one of Examples 10 to 16, wherein the patterned hard mask comprises polysilicon (poly-Si).

[0087] Example 18. A method of processing a substrate, the method comprising: flowing a fluorocarbon into a plasma processing chamber, the plasma processing chamber being configured to hold a substrate, the substrate comprising a dielectric layer as an etching target and a patterned hard mask on the dielectric layer; maintaining a plasma generated by the fluorocarbon in the plasma processing chamber while flowing the fluorocarbon; flowing a metal halide and molecular hydrogen (H2) into the plasma processing chamber while maintaining the plasma; flowing a silane compound into the plasma processing chamber while maintaining the plasma; and forming high aspect ratio features by exposing the substrate to the plasma to etch recesses in the dielectric layer, wherein a passivation layer is formed on the patterned hard mask during the exposure.

[0088] Example 19. The method of Example 18, wherein the metal halide, H2, and the silane compound are flowed simultaneously into the plasma processing chamber.

[0089] Example 20. The method of one of Examples 18 or 19, further comprising alternately repeating the flow of the metal halide and H2 and the flow of the silane compound.

[0090] Although the present invention has been described with reference to illustrative embodiments, it is not intended that this description be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the present invention, will be apparent to those skilled in the art by reference to this description. Accordingly, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A method for processing a substrate, the method comprising: flowing a fluorocarbon, a metal halide, and molecular hydrogen (H2) into a plasma processing chamber configured to hold a substrate including a dielectric layer comprising silicon oxide as an etch target and a patterned hard mask comprising polycrystalline silicon (poly-Si) on the dielectric layer; while flowing the gases, generating plasma in the plasma processing chamber; as well as High aspect ratio features are formed by exposing the substrate to the plasma to etch recesses in the dielectric layer, wherein a metal-containing passivation layer is formed on the patterned hard mask during the exposure.

2. The method of claim 1, further comprising flowing molecular oxygen (O2).

3. The method according to claim 1, wherein The fluorocarbon includes C4F6, C4F8, CF4, C3F8, CHF3 or CH2F2.

4. The method according to claim 1, wherein The metal halide is tungsten hexafluoride (WF6).

5. The method according to claim 1, wherein The metal halide is molybdenum hexafluoride (MoF6), niobium hexafluoride (NbF6), tungsten hexachloride (WCl6), aluminum trichloride (AlCl3) or titanium tetrachloride (TiCl4).

6. The method of claim 1, wherein: The flow rate of the metal halide is between 0.01% and 1% of the total flow rate of the gases.

7. The method of claim 1, wherein: The metal halide is intermittently flowed while exposing the substrate to the plasma.

8. The method of claim 1, wherein: The dielectric layer comprises a layer stack of silicon oxide and silicon nitride.

9. The method of claim 1, wherein: The aspect ratio of the recess is at least 50:

1.

10. A method for processing a substrate, the method comprising: flowing a fluorocarbon compound and a silane compound into a plasma processing chamber configured to hold a substrate including a dielectric layer containing silicon as an etch target and a patterned hard mask on the dielectric layer; while flowing the gases, generating plasma in the plasma processing chamber; as well as High aspect ratio features are formed by exposing the substrate to the plasma to etch recesses in the dielectric layer, wherein a silicon-containing passivation layer is formed on the patterned hard mask during the exposure.

11. The method of claim 10, further comprising flowing molecular oxygen (O2).

12. The method of claim 10, wherein: The fluorocarbon includes C4F6, C4F8, CF4, C3F8, CHF3 or CH2F2.

13. The method of claim 10, wherein: The silane compound is monosilane (SiH4).

14. The method of claim 10, wherein: The silane compound is disilane (Si2H6) or halogenated silane (SiH x X y ).

15. The method of claim 10, wherein: The dielectric layer includes silicon oxide.

16. The method of claim 10, wherein: The dielectric layer includes silicon nitride.

17. The method of claim 10, wherein the patterned hard mask comprises polysilicon (poly-Si).

18. A method for processing a substrate, the method comprising: flowing a fluorocarbon into a plasma processing chamber configured to hold a substrate including a dielectric layer targeted for etching and a patterned hard mask on the dielectric layer; maintaining a plasma generated from the fluorocarbon in the plasma processing chamber while flowing the fluorocarbon; flowing a metal halide and molecular hydrogen (H2) into the plasma processing chamber while maintaining the plasma; flowing a silane compound into the plasma processing chamber while maintaining the plasma; as well as High aspect ratio features are formed by exposing the substrate to the plasma to etch recesses in the dielectric layer, wherein a passivation layer is formed on the patterned hard mask during the exposure.

19. The method of claim 18, wherein: The metal halide, H2, and the silane compound are simultaneously flowed into the plasma processing chamber.

20. The method of claim 18, further comprising alternately repeating the flow of the metal halide and H2 and the flow of the silane compound.

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