Numa modeling method, system, and storage medium supporting chi protocol

Abstract

The application provides a NUMA modeling method and system supporting a CHI protocol and a storage medium, and the method comprises the following steps: acquiring a topology structure file used for defining the topology shape of the mutual connection of different grid nodes; dividing the system memory into memory address ranges with the same number as the number of the NUMA architecture nodes to be modeled; constructing a memory controller in the system memory for address allocation according to the memory address ranges; in the topology structure file, dividing the grid nodes into various protocol nodes according to the definition of the CHI protocol, and allocating the protocol nodes to the NUMA architecture nodes to be modeled, and meanwhile, connecting the protocol nodes and the memory controller correspondingly; and establishing link connections for different grid nodes according to the topology structure file, and completing the modeling of the NUMA architecture nodes. The application is beneficial to improving the efficiency of the NUMA architecture exploration work in the processor design process.

Description

Technical Field

[0001] This invention is applicable to the field of processor simulation, and in particular relates to a NUMA modeling method, system and storage medium that supports the CHI protocol. Background Technology

[0002] In multi-core chip architectures, SMP (Symmetric Multiprocessor) architectures suffer from increased memory access latency as the number of cores increases because all cores access memory through a single bus. To address this issue, NUMA (Non-Uniform Memory Access) architectures emerged. This architecture distributes cores across different NUMA nodes, where local memory access within a node is fast, while remote memory access outside the node is slow. When a core requests memory, it prioritizes allocating local memory and only allocates remote memory when local memory is insufficient.

[0003] The CHI (Coherent Hub Interface) protocol is a high-performance coherent bus protocol proposed by ARM and is part of the AMBA 5 standard. It is suitable for interconnecting processor cores, caches, memory controllers and other components in multi-core processor systems, and is especially suitable for large-scale multi-core systems. It defines node types such as RN (Request Node), HN (Home Node), and SN (Slave Node).

[0004] Currently, when exploring different NUMA schemes for multi-core chip architectures to find the optimal performance solution, a problem exists: open-source tools do not yet support NUMA modeling based on the CHI protocol. This is mainly reflected in the fact that existing NUMA models do not implement the communication rules and consistency mechanisms defined by the CHI protocol. This limits the design process of NUMA architectures to some extent. Summary of the Invention

[0005] The present invention aims to solve the technical problem that existing technologies cannot achieve NUMA architecture modeling for the CHI protocol.

[0006] To address the aforementioned technical problems, in a first aspect, the present invention provides a NUMA modeling method supporting the CHI protocol, comprising the following steps:

[0007] S101. Obtain the topology file used to define the topology shape of the interconnections between different mesh nodes;

[0008] S102. Divide the system memory into memory address ranges of the same number as the number of NUMA architecture nodes that need to be modeled.

[0009] S103. Construct a memory controller in the system memory for address allocation based on the memory address range;

[0010] S104. In the topology file, the mesh nodes are divided into multiple protocol nodes according to the definition of the CHI protocol, and the protocol nodes are assigned to the NUMA architecture nodes that need to be modeled. At the same time, the protocol nodes are connected to the memory controller accordingly.

[0011] S105. Based on the topology file, establish link connections for different mesh nodes to complete the modeling of the NUMA architecture nodes.

[0012] Furthermore, in step S102, the entire system memory is divided into memory address ranges of the same number as the number of NUMA architecture nodes to be modeled, using a continuous partitioning method.

[0013] Furthermore, in step S104, the protocol nodes include RNF nodes, HNF nodes, and SNF nodes, wherein:

[0014] When partitioning the HNF node, determine the range of memory addresses to which it needs to be partitioned;

[0015] When partitioning the SNF node, determine the memory controller that it needs to connect to.

[0016] Furthermore, in step S103, the memory controller is constructed in the same number as the number of SNF nodes that need to be partitioned.

[0017] Furthermore, step S105 also includes:

[0018] Modify the device tree file to allocate storage and processor cores to the NUMA architecture nodes that need to be modeled.

[0019] Furthermore, step S105 also includes:

[0020] According to the memory controller, address interleaving is performed in its corresponding NUMA architecture node.

[0021] Furthermore, step S105 also includes:

[0022] Delay configuration is performed for link connections between different mesh nodes.

[0023] Secondly, the present invention also provides a NUMA modeling system supporting the CHI protocol, comprising:

[0024] The topology initialization module is used to obtain a topology file that defines the topology shape for connecting different mesh nodes.

[0025] The memory partitioning module is used to divide the system memory into memory address ranges of the same number as the number of NUMA architecture nodes that need to be modeled.

[0026] A control building module is used to build a memory controller in system memory for address allocation based on the memory address range;

[0027] The node configuration module is used to divide the mesh nodes into multiple protocol nodes according to the definition of the CHI protocol in the topology file, assign the protocol nodes to the NUMA architecture nodes that need to be modeled, and connect the protocol nodes to the memory controller accordingly.

[0028] The network modeling module is used to establish link connections between different mesh nodes based on the topology file, thereby completing the modeling of the NUMA architecture nodes.

[0029] Thirdly, the present invention also provides a computer device, comprising: a memory, a processor, and a NUMA modeling program supporting the CHI protocol stored on the memory and executable on the processor, wherein when the processor executes the NUMA modeling program supporting the CHI protocol, it implements the steps of the NUMA modeling method supporting the CHI protocol as described in any of the above embodiments.

[0030] Fourthly, the present invention also provides a storage medium storing a NUMA modeling program supporting the CHI protocol, wherein when the NUMA modeling program supporting the CHI protocol is executed by a processor, the NUMA modeling program supporting the CHI protocol implements the steps of the NUMA modeling method supporting the CHI protocol as described in any of the above embodiments.

[0031] The beneficial effect achieved by this invention is that it proposes a NUMA modeling method that supports the CHI protocol. This method integrates CHI protocol nodes into the network topology modeling of NUMA architecture nodes through network topology, and each protocol conforms to the specifications, making the modeling process more universal and compatible, which is conducive to improving the efficiency of NUMA architecture exploration in the processor design process. Attached Figure Description

[0032] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings:

[0033] Figure 1 This is a flowchart illustrating the steps of the NUMA modeling method supporting the CHI protocol provided in this embodiment of the invention.

[0034] Figure 2 This is a schematic diagram of the topology provided in an embodiment of the present invention;

[0035] Figure 3 This is a schematic diagram of the structure of a NUMA modeling system supporting the CHI protocol provided in an embodiment of the present invention;

[0036] Figure 4 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0038] Example 1

[0039] Please refer to Figure 1 , Figure 1 This is a flowchart illustrating the steps of the NUMA modeling method supporting the CHI protocol provided in this embodiment of the invention. The NUMA modeling method supporting the CHI protocol includes the following steps:

[0040] S101. Obtain the topology file used to define the topology shape of the interconnections between different mesh nodes.

[0041] Specifically, the topology file defines the network's topology shape. In a classic mesh network, there are fully connected topologies where every node has direct connections to all other nodes, and partially connected topologies where nodes only have direct connections to some of their neighboring nodes. In this embodiment of the invention, for ease of explanation, the topology shape is set to a grid shape, and the number of nodes is described by length and width. For example, a 4×4 topology contains 16 grid nodes, and each grid node is connected to its neighboring nodes.

[0042] S102. Divide the system memory into memory address ranges of the same number as the number of NUMA architecture nodes that need to be modeled.

[0043] For NUMA architecture, the number of memory address ranges in the system memory must be the same as the number of NUMA architecture nodes. For example, if two NUMA architecture nodes need to be built, two memory address ranges need to be constructed. In this case, the system memory address ranges need to be allocated uniformly.

[0044] In step S102, the entire system memory is divided into memory address ranges of the same number as the number of NUMA architecture nodes to be modeled, using a continuous partitioning method. For example, if the system memory has a total size of 8GB, in this embodiment of the invention, to construct two NUMA architecture nodes, the first 4GB is assigned to NUMA node 0, and the last 4GB is assigned to NUMA node 1.

[0045] S103. Construct a memory controller in the system memory for address allocation based on the memory address range.

[0046] S104. In the topology file, the mesh nodes are divided into multiple protocol nodes according to the definition of the CHI protocol, and the protocol nodes are assigned to the NUMA architecture nodes that need to be modeled. At the same time, the protocol nodes are connected to the memory controller.

[0047] In step S104, the protocol nodes include RNF (Request Node Fully-Coherent) nodes, HNF (Home Node Fully-Coherent) nodes, and SNF (Slave Node Fully-Coherent) nodes, wherein:

[0048] When partitioning the HNF node, determine the range of memory addresses to which it needs to be partitioned;

[0049] When partitioning the SNF node, determine the memory controller that it needs to connect to.

[0050] Consistent with existing technology definitions, the RNF, HNF, and SNF nodes in the CHI protocol each undertake different functions, working together to achieve efficient data transfer and cache consistency maintenance in multi-core processor systems. In step S104, based on the number and functional definitions of existing mesh nodes, they are divided into specific CHI protocol nodes, thereby achieving node binding on the determined memory address range and memory controller.

[0051] Correspondingly, in step S103, the memory controller is constructed in the same number as the number of SNF nodes that need to be partitioned.

[0052] S105. Based on the topology file, establish link connections for different mesh nodes to complete the modeling of the NUMA architecture nodes.

[0053] like Figure 2The diagram shows a topology structure. In this embodiment, a 4×4 topology is used as an example. The original topology contains 16 grid nodes. Each grid node establishes a connection with its adjacent nodes. First, the memory address range of the NUMA architecture nodes is allocated in step S102, as follows... Figure 2 The method shown constructs two NUMA architecture nodes, with grid nodes 0-1, 4-5, 8-9, and 12-13 belonging to NUMA architecture node 0, and grid nodes 2-3, 6-7, 10-11, and 14-15 belonging to NUMA node 1.

[0054] Next, CHI protocol nodes are allocated via S104. During implementation, allocation is based on the original physical attributes of each grid node in the original topology. For example, RNF nodes are mainly related to processor cores, HNF nodes are mainly related to memory, and SNF nodes are mainly related to memory controllers. Based on the characteristics of the nodes in the original topology, CHI protocol nodes can also be allocated in the same grid node, including multiple types. After completing the allocation and construction of memory address ranges, memory controllers, and CHI protocol nodes through the above steps, the topology is constructed according to the topology structure file using a certain topology construction tool, thus completing the modeling of the NUMA architecture nodes.

[0055] Step S105 also includes:

[0056] Modify the device tree file to allocate storage and processor cores to the NUMA architecture nodes that need to be modeled.

[0057] Specifically, a Device Tree File (DTree File) is a data structure used to describe hardware device information. Its core function is to inform the kernel, during operating system startup, which hardware devices (such as processor cores and memory) exist in the system, and their configuration parameters (such as addresses, interrupt numbers, and pin connections). This embodiment of the invention constructs NUMA architecture nodes containing CHI protocol nodes based on the original topology file. Therefore, to ensure node availability, the fields of the corresponding Device Tree File need to be modified and replaced after node modeling, enabling the system to correctly identify the NUMA architecture nodes constructed in this embodiment. During implementation, `numa-node-id` is added to the `memory` and `cpu` fields in the Device Tree File to distinguish which NUMA node the memory and processor core belong to.

[0058] Step S105 further includes: performing address interleaving in the corresponding NUMA architecture node according to the memory controller.

[0059] Address interleaving is a technique in computer storage systems that improves performance and parallelism by distributing data storage locations. Since the memory controller itself is used for address allocation, interleaving the addresses of the pre-built memory controller within the corresponding memory address range facilitates the parallel execution of multiple storage operations and avoids bandwidth bottlenecks of a single memory bank.

[0060] Step S105 further includes configuring the latency of the link connections between different mesh nodes.

[0061] Configuring latency for link connections between different grid nodes in a network topology is a key means to optimize network performance, ensure service quality, and improve reliability.

[0062] The beneficial effect achieved by this invention is that it proposes a NUMA modeling method that supports the CHI protocol. This method integrates CHI protocol nodes into the network topology modeling of NUMA architecture nodes through network topology, and each protocol conforms to the specifications, making the modeling process more universal and compatible, which is conducive to improving the efficiency of NUMA architecture exploration in the processor design process.

[0063] Example 2

[0064] This invention also provides a NUMA modeling system 200 that supports the CHI protocol. Please refer to [link / reference]. Figure 3 , Figure 3 This is a schematic diagram of the structure of a NUMA modeling system supporting the CHI protocol provided in an embodiment of the present invention, which includes:

[0065] The topology initialization module 201 is used to obtain a topology structure file for defining the topology shape of the interconnections between different mesh nodes;

[0066] The memory partitioning module 202 is used to divide the system memory into memory address ranges of the same number as the number of NUMA architecture nodes that need to be modeled.

[0067] The control construction module 203 is used to construct a memory controller in the system memory for address allocation based on the memory address range;

[0068] The node configuration module 204 is used to divide the mesh nodes into multiple protocol nodes according to the definition of the CHI protocol in the topology file, and to assign the protocol nodes to the NUMA architecture nodes that need to be modeled. At the same time, the protocol nodes are connected to the memory controller accordingly.

[0069] The network modeling module 205 is used to establish link connections for different mesh nodes based on the topology file, thereby completing the modeling of the NUMA architecture nodes.

[0070] The NUMA modeling system 200 supporting the CHI protocol can implement the steps in the NUMA modeling method supporting the CHI protocol as described in the above embodiments, and can achieve the same technical effect. Referring to the description in the above embodiments, it will not be repeated here.

[0071] Example 3

[0072] This invention also provides a computer device, please refer to... Figure 4 , Figure 4 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. The computer device 300 includes: a memory 302, a processor 301, and a NUMA modeling program supporting the CHI protocol stored in the memory 302 and capable of running on the processor 301.

[0073] The processor 301 calls the NUMA modeling program supporting the CHI protocol stored in the memory 302 and executes the steps in the NUMA modeling method supporting the CHI protocol provided in this embodiment of the invention. Please refer to... Figure 1 Specifically, it includes the following steps:

[0074] S101. Obtain the topology file used to define the topology shape of the interconnections between different mesh nodes.

[0075] S102. Divide the system memory into memory address ranges of the same number as the number of NUMA architecture nodes that need to be modeled.

[0076] In step S102, the entire system memory is divided into memory address ranges of the same number as the number of NUMA architecture nodes to be modeled, using a continuous partitioning method.

[0077] S103. Construct a memory controller in the system memory for address allocation based on the memory address range.

[0078] In step S103, the memory controller is constructed in the same number as the number of SNF nodes that need to be partitioned.

[0079] S104. In the topology file, the mesh nodes are divided into multiple protocol nodes according to the definition of the CHI protocol, and the protocol nodes are assigned to the NUMA architecture nodes that need to be modeled. At the same time, the protocol nodes are connected to the memory controller.

[0080] In step S104, the protocol nodes include RNF nodes, HNF nodes, and SNF nodes, wherein:

[0081] When partitioning the HNF node, determine the range of memory addresses to which it needs to be partitioned;

[0082] When partitioning the SNF node, determine the memory controller that it needs to connect to.

[0083] S105. Based on the topology file, establish link connections for different mesh nodes to complete the modeling of the NUMA architecture nodes.

[0084] Step S105 also includes:

[0085] Modify the device tree file to allocate storage and processor cores to the NUMA architecture nodes that need to be modeled.

[0086] According to the memory controller, address interleaving is performed in its corresponding NUMA architecture node.

[0087] Delay configuration is performed for link connections between different mesh nodes.

[0088] The computer device 300 provided in this embodiment of the invention can implement the steps in the NUMA modeling method supporting the CHI protocol as described in the above embodiments, and can achieve the same technical effect. Referring to the description in the above embodiments, it will not be repeated here.

[0089] Example 4

[0090] This invention also provides a storage medium storing a NUMA modeling program that supports the CHI protocol. When the NUMA modeling program that supports the CHI protocol is executed by a processor, it implements the various processes and steps in the NUMA modeling method that supports the CHI protocol provided in this invention and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0091] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by hardware related to computer programs or instructions. The program can be stored in a computer-readable storage medium. When the NUMA modeling program supporting the CHI protocol is executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0092] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0093] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0094] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form under the guidance of the present invention without departing from the spirit and scope of the claims. All such changes are within the protection scope of the present invention.

Claims

1. A NUMA modeling method supporting the CHI protocol, characterized in that, Includes the following steps: S101. Obtain the topology file used to define the topology shape of the interconnections between different mesh nodes; S102. Divide the system memory into memory address ranges of the same number as the number of NUMA architecture nodes that need to be modeled. S103. Construct a memory controller in the system memory for address allocation based on the memory address range; S104. In the topology file, the mesh nodes are divided into multiple protocol nodes according to the definition of the CHI protocol, and the protocol nodes are assigned to the NUMA architecture nodes that need to be modeled. At the same time, the protocol nodes are connected to the memory controller accordingly. S105. Based on the topology file, establish link connections for different mesh nodes to complete the modeling of the NUMA architecture nodes.

2. The NUMA modeling method supporting the CHI protocol according to claim 1, characterized in that, In step S102, the entire system memory is divided into memory address ranges of the same number as the number of NUMA architecture nodes to be modeled, using a continuous partitioning method.

3. The NUMA modeling method supporting the CHI protocol according to claim 1, characterized in that, In step S104, the protocol nodes include RNF nodes, HNF nodes, and SNF nodes, wherein: When partitioning the HNF node, determine the range of memory addresses to which it needs to be partitioned; When partitioning the SNF node, determine the memory controller that it needs to connect to.

4. The NUMA modeling method supporting the CHI protocol according to claim 3, characterized in that, In step S103, the memory controller is constructed in the same number as the number of SNF nodes that need to be partitioned.

5. The NUMA modeling method supporting the CHI protocol according to claim 1, characterized in that, Step S105 also includes: Modify the device tree file to allocate storage and processor cores to the NUMA architecture nodes that need to be modeled.

6. The NUMA modeling method supporting the CHI protocol according to claim 1, characterized in that, Step S105 also includes: According to the memory controller, address interleaving is performed in its corresponding NUMA architecture node.

7. The NUMA modeling method supporting the CHI protocol according to claim 1, characterized in that, Step S105 also includes: Delay configuration is performed for link connections between different mesh nodes.

8. A NUMA modeling system supporting the CHI protocol, characterized in that, include: The topology initialization module is used to obtain a topology file that defines the topology shape for connecting different mesh nodes. The memory partitioning module is used to divide the system memory into memory address ranges of the same number as the number of NUMA architecture nodes that need to be modeled. A control building module is used to build a memory controller in system memory for address allocation based on the memory address range; The node configuration module is used to divide the mesh nodes into multiple protocol nodes according to the definition of the CHI protocol in the topology file, assign the protocol nodes to the NUMA architecture nodes that need to be modeled, and connect the protocol nodes to the memory controller accordingly. The network modeling module is used to establish link connections between different mesh nodes based on the topology file, thereby completing the modeling of the NUMA architecture nodes.

9. A computer device, characterized in that, include: The system includes a memory, a processor, and a NUMA modeling program supporting the CHI protocol stored on the memory and executable on the processor. When the processor executes the NUMA modeling program supporting the CHI protocol, it implements the steps of the NUMA modeling method supporting the CHI protocol as described in any one of claims 1-7.

10. A storage medium, characterized in that, The storage medium stores a NUMA modeling program that supports the CHI protocol. When the NUMA modeling program that supports the CHI protocol is executed by the processor, it implements the steps in the NUMA modeling method that supports the CHI protocol as described in any one of claims 1-7.

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