A high-performance CPU-GPU cooperative processing architecture of an audio integrated signal processor

Abstract

The application discloses a kind of high-performance CPU-GPU collaborative processing architecture of audio integrated signal processor, belong to audio integrated signal processing technical field, this architecture is based on dynamic priority scheduling model, through hierarchical resource management and protocol level optimization, the efficient cooperation of CPU and GPU is realized, hardware layer uses multi-GPU cluster and distributed storage node, support high concurrency task processing;Transport layer fuses RapidIO and Ethernet protocol, respectively adapts short frame control signal and long packet data stream;Application layer calculates task resource demand by dynamic priority weight, and combines normalization allocation algorithm to guarantee the low latency of key task.The architecture in the scene of audio signal processing, task scheduling efficiency is improved by 40%, short frame transmission delay is as low as 0.5, long data stream throughput reaches 100Gbps, can satisfy the real-time and calculation accuracy demand under complex acoustic environment.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of audio integrated signal processing, and particularly relates to a high-performance CPU-GPU cooperative processing architecture of an audio integrated signal processor. BACKGROUND

[0002] Water acoustic signal processing technology is an important means to solve underwater detection problems. Through the study of the sound propagation characteristics in the ocean and the acoustic characteristics of the target in reverberation and noise, the water acoustic signal processing technology completes target detection, target parameter estimation and target identification in a strong interference background.

[0003] In underwater communication, ocean monitoring and underwater acoustic navigation systems, the audio signal processing has very high requirements for computing real-time, throughput and accuracy, and the traditional architecture faces the following challenges: in the traditional heterogeneous computing, the CPU is responsible for task scheduling and logical control, and the GPU undertakes parallel computing, but the two often cause insufficient resource utilization due to data transmission bottlenecks or unreasonable task allocation; the existing scheduling algorithms (such as polling and static priority) cannot dynamically respond to sudden high-priority tasks (such as radar beam control instructions), resulting in large time delay fluctuations of critical tasks and difficulty in meeting the microsecond-level real-time requirements; the audio processing scene needs to simultaneously transmit short frame control signals (such as beam pointing parameters) and long packet data streams (such as original audio signals), and a single network protocol (such as pure Ethernet or RapidIO) cannot balance low latency and high throughput; the traditional centralized architecture is prone to system crashes when the GPU node or storage fails, and the computing power expansion depends on hardware stacking, which is costly.

[0004] Therefore, it is necessary to propose a high-performance CPU-GPU cooperative processing architecture of an audio integrated signal processor to solve the above problems. SUMMARY

[0005] Therefore, the purpose of the present application is to provide a high-performance CPU-GPU cooperative processing architecture of an audio integrated signal processor, which breaks through the traditional performance bottleneck through heterogeneous protocol fusion, dynamic priority scheduling and hierarchical resource management, and provides a reliable technical foundation for high-precision real-time audio processing.

[0006] To achieve the above purpose, the present application provides the following technical scheme:

[0007] The present application provides a high-performance CPU-GPU cooperative processing architecture of an audio integrated signal processor, which comprises: at least one chassis unit, each chassis unit integrating multiple groups of heterogeneous computing units, the heterogeneous computing unit comprising a main processing chip directly connected by a high-speed data transmission interface between a multi-core CPU and a GPU;

[0008] Board-level communication interface, including an intra-board NVLink 3.0 interface with a bandwidth of ≥200 GB / s, an inter-board 40G / 10G Ethernet interface, and an SRIO 4x interface, for selecting a transmission mode according to the size of a data packet;

[0009] Cross-crate communication network, interconnecting multiple crate units through a fiber switch, and performing RDMA zero-copy transmission through an optical fiber based on the RoCE v2 protocol;

[0010] Task scheduling middleware, an extended scheduler based on the Kubernetes architecture, configured with a dynamic priority policy, and generating a task allocation matrix according to the real-time requirements and computational complexity of signal processing tasks;

[0011] Communication agent module, for deploying a protocol conversion gateway, supporting bidirectional conversion between RapidIO and Ethernet protocols, and inserting a link state prediction field in the data packet header, and dynamically selecting the optimal transmission path according to the congestion probability and bit error rate;

[0012] Resource optimization module, for dynamic allocation of communication resources, and allocating bandwidth to each container according to the task allocation matrix;

[0013] Verification and fault tolerance subsystem, for performing variable packet length stress testing, generating a latency-throughput curve, and selecting a transmission protocol according to real-time requirements: when the real-time requirement is ≤1 ms, the SRIO protocol is forcibly enabled; when a GPU failure is detected, a task checkpoint is saved to a shared memory pool, and execution is resumed in a standby container, with a recovery delay of ≤50 ms.

[0014] Further, the dynamic priority policy of the task scheduling middleware is implemented through the following steps:

[0015] Task classifier: divides underwater acoustic signal processing tasks into real-time, quasi-real-time, and offline categories; according to the real-time requirements and computational complexity of signal processing tasks Generate a task allocation matrix, and the decision function of the task allocation matrix is:

[0016]

[0017] wherein, is the task priority weight value, is the inverse of the task deadline, is the logarithm of the task computation amount, is the proportion of idle GPU resources, to ensure that tasks near the deadline are executed in priority, to logarithmically compress high-computation tasks, to dynamically balance GPU load, , , is a weight coefficient, satisfying + + =1;

[0018] Resource predictor: train LSTM model based on historical load data, predict GPU memory occupancy and CPU thread utilization within the next 5s;

[0019] Scheduling decision engine: combine task category and resource prediction results to generate task to computing resource mapping table, preferentially allocate beamforming algorithm to CPU core and convolutional neural network inference to GPU instance.

[0020] Further, the resource optimization module performs dynamic allocation of communication resources based on a bandwidth allocation algorithm, wherein the allocation mechanism is: 20% of the total bandwidth is fixedly reserved for real-time tasks; when a high-priority task requests bandwidth, the allocated bandwidth resources of low-priority tasks are forcibly reclaimed;

[0021] wherein the bandwidth allocation algorithm is:

[0022]

[0023] wherein, is the amount of resources allocated to the current task, is the task priority weight value, is the total amount of system allocatable resources, is the sum of all task priority weights, wherein, is the total number of tasks, is the task index.

[0024] Further, the energy consumption control strategy of the resource optimization module includes: when the system load is <30%, turn off redundant GPU instances and reduce the CPU main frequency to 60% of the baseline value through the DVFS technology.

[0025] Further, the transmission mode of the board-level communication interface includes: when the data packet size L is ≥2MB, enable the 4-channel binding mode of the SRIO 4x interface; when the data packet size L is <256KB, enable the SRIO single-channel mode; and allocate 1 backup channel for each SRIO interface, and when the main channel error rate is greater than 10-12, automatically switch to the backup channel.

[0026] Further, the protocol selection decision tree of the verification and fault tolerance subsystem is generated through the following rules:

[0027] First-level judgment: if the application layer is marked as a critical task, then RapidIO is forcibly selected;

[0028] Second level judgment: if the data integrity requirement is greater than or equal to 99.999%, the ACK retransmission mechanism of RapidIO is enabled;

[0029] Third level judgment: if the throughput requirement is greater than 40Gbps, the multi-path Ethernet load balancing is enabled.

[0030] Further, the cross-crate communication network supports hardware-level timestamp synchronization, with synchronization accuracy less than or equal to 10ns; the timestamp synchronization mechanism is implemented as follows:

[0031] Hardware synchronization: nanosecond-level clock synchronization is achieved through the White Rabbit protocol;

[0032] Software compensation: a delay calibration module is inserted in the data packet processing pipeline, and the calculation formula is:

[0033]

[0034] In the formula, is the receiving end timestamp, is the sending end timestamp, is the calibrated time.

[0035] Further, the processing method of the high-performance CPU-GPU cooperative processing architecture of the audio integrated signal processing machine includes the following steps:

[0036] S1: Process the audio signal through multi-core CPU and GPU cooperation, wherein the multi-core CPU performs real-time beamforming calculation based on the AVX-512 instruction set; the GPU performs convolutional neural network inference based on the CUDA parallel architecture; real-time monitoring of the temperature gradient of the CPU and GPU is performed, and when the temperature difference is greater than or equal to 5℃, adaptive wind speed adjustment is triggered to optimize heat dissipation;

[0037] S2: Select the transmission mode according to the data packet size: when the data packet size L is greater than or equal to 2MB, the 4-channel binding mode of the SRIO 4x interface is enabled; when the data packet size L is less than 256KB, the SRIO single-channel mode is enabled; in cross-crate communication: RDMA zero-copy transmission is performed through optical fiber based on the RoCEv2 protocol; a link state prediction field is inserted in the data packet header, and the optimal transmission path is dynamically selected according to the congestion probability and bit error rate;

[0038] S3: Dynamic scheduling according to the task allocation matrix decision function, predicting the GPU memory occupancy rate in the next 5 seconds based on the LSTM model, and allocating tasks according to the prediction results: beamforming tasks are allocated to the CPU for execution; convolutional neural network inference tasks are allocated to the GPU for execution;

[0039] S4: Dynamically allocate the total bandwidth according to the priority weight ratio:

[0040]

[0041] And reserve 20% bandwidth as an emergency channel for real-time tasks; when the system load < 30%, close the redundant GPU instance, and reduce the CPU frequency to 60% of the benchmark value through the DVFS technology;

[0042] S5: Perform variable packet length stress test, generate delay-throughput curve, and select transmission protocol according to real-time requirement: when the real-time requirement is ≤1ms, SRIO protocol is enabled; when GPU failure is detected, trigger incremental checkpoint saving mechanism: only save updated data block, and store it in distributed shared memory pool through LZ4 compression, ensure that the recovery delay is ≤50ms.

[0043] Further, the training method of the LSTM model comprises: the input features are GPU memory occupancy rate, task queue length and calculation load type in the past 60 seconds; the output is the memory occupancy rate prediction value in the future 5 seconds, and the training loss function adopts mean square error optimization.

[0044] Further, the incremental checkpoint saving mechanism comprises: identifying the updated data block through a hash algorithm, and only compressing and storing the newly added or modified data block; when recovering, quickly locate and decompress the data block according to the hash index, and load it to the available computing node in parallel.

[0045] The beneficial effects of the present application are:

[0046] 1. The dynamic allocation algorithm based on priority weight realizes fine-grained management of GPU memory and bandwidth, the resource utilization rate is improved by 35% compared with the traditional polling strategy, and long-term occupation of resources by low-priority tasks is avoided; in a complex noise environment, the sound signal processing speed is improved to the millisecond level, and the task completion rate is ≥99%, which provides a reliable hardware and algorithm cooperation basis for high-precision real-time acoustic analysis;

[0047] 2. The short frame control signal is transmitted through the RapidIO protocol, and the delay is as low as 0.5 (64B packet length), which meets the microsecond-level real-time requirement; the high-priority task allocation error is less than 5%;

[0048] 3. The Ethernet (RoCEv2) protocol supports long packet data stream (such as audio original signal) transmission, and the throughput is close to 100Gbps under 8KB packet length, which is improved by 60% compared with the traditional TCP / IP;

[0049] 4. The transmission layer protocol redundancy design (RapidIO and Ethernet backup each other) can still maintain more than 80% basic performance when a single protocol fails; the resource recycling mechanism avoids the risk of memory leakage;

[0050] 5. The task scheduling middleware supports dynamic state migration and can adapt to sudden task loads; the hardware layer can linearly expand computing power by adding GPU nodes.

[0051] Additional advantages, objects, and features of the application will be set forth in the following specification and will become apparent to those skilled in the art from the following description, or can be learned by practice of the application. The advantages of the application will be realized and attained by the structure particularly pointed out in the specification. BRIEF DESCRIPTION OF DRAWINGS

[0052] In order to make the purposes, technical solutions and beneficial effects of the present application clearer, the present application provides the following drawings for illustration:

[0053] Figure 1 The figure is a high-performance CPU-GPU cooperative processing architecture framework of an audio integrated signal processor of an embodiment of the present application. DETAILED DESCRIPTION

[0054] As shown in Figure 1 , the present application provides a high-performance CPU-GPU cooperative processing architecture of an audio integrated signal processor, which comprises:

[0055] An open hardware architecture is composed of at least one chassis unit, each chassis unit integrates multiple groups of heterogeneous computing modules, each group of heterogeneous computing modules contains: a main processing chip set: 1 multi-core CPU and 1 GPU are directly connected through a PCIe 4.0x16 bus, the CPU supports an AVX-512 instruction set and an L3 cache≥30MB, the GPU supports a CUDA parallel computing architecture and is configured with a display memory bandwidth≥1.5TB / s; a board-level communication interface: including an intra-board NVLink 3.0 interface (bandwidth≥200GB / s), an inter-board 40G / 10G Ethernet interface and an SRIO 4x interface, wherein the SRIO interface supports a dynamic channel binding technology, and the maximum aggregated bandwidth≥100Gbps; the transmission mode of the board-level communication interface is: when the data packet size L≥2MB, the 4-channel binding mode of the SRIO 4x interface is enabled; when the data packet size L<256KB, the SRIO single-channel mode is enabled; and each SRIO interface is allocated 1 backup channel, when the main channel error rate , the backup channel is automatically switched to;

[0056] A cross-chassis communication network interconnects multiple chassis units through a fiber switch, realizes cross-chassis communication by adopting a RDMA over Converged Ethernet (RoCE v2) protocol, supports zero-copy data transmission and hardware-level timestamp synchronization, and the synchronization accuracy≤10ns;

[0057] The containerized software framework comprises a task scheduling middleware and a communication agent module, wherein the task scheduling middleware is based on an extended scheduler of a Kubernetes architecture, a dynamic priority strategy is configured, and a task allocation matrix is generated according to the real-time requirement (1ms~10s) and the calculation complexity (FLOPs) of the signal processing task, wherein the dynamic priority strategy is realized through the following steps:

[0058] The task classifier divides the underwater acoustic signal processing task into real-time, quasi-real-time and offline categories; according to the real-time requirement and the calculation complexity of the signal processing task The task allocation matrix is generated, and the decision function of the task allocation matrix is:

[0059]

[0060] In the formula, is the task priority weight value, is the reciprocal of the task deadline, is the logarithm of the task calculation amount, is the proportion of GPU idle resources, is to ensure that tasks near the deadline are executed in priority, is to logarithmically compress high-computing tasks, is to dynamically balance the GPU load, , , is the weight coefficient, satisfying + + =1;

[0061] The resource predictor is based on historical load data to train an LSTM model to predict GPU memory occupancy and CPU thread utilization within 5s in the future;

[0062] The scheduling decision engine generates a mapping table of tasks to computing resources in combination with the task category and the resource prediction result, and preferentially allocates beamforming algorithms to CPU cores and convolutional neural network inference to GPU instances;

[0063] The communication agent module is used to deploy a protocol conversion gateway, supports bidirectional conversion between RapidIO and Ethernet protocols, and inserts a dynamic routing identifier in the data packet header, wherein the identifier contains link state prediction information (congestion probability, bit error rate);

[0064] The resource optimization module is used for dynamic allocation of communication resources. It allocates bandwidth to each container based on the task priority matrix. The resource optimization module performs dynamic allocation of communication resources based on a bandwidth allocation algorithm. The allocation mechanism is as follows: 20% of the total bandwidth is reserved for real-time tasks; when a high-priority task requests bandwidth, the bandwidth resources already allocated to low-priority tasks can be forcibly reclaimed. The bandwidth allocation algorithm is as follows:

[0065]

[0066] In the formula, The amount of resources allocated to the current task. This represents the task priority weight value. This represents the total amount of resources that can be allocated to the system. The sum of the priority weights of all tasks, where, The total number of tasks. For task indexing;

[0067] The energy consumption control strategy of the resource optimization module is as follows: when the system load is less than 30%, redundant GPU instances are shut down, and the CPU frequency is reduced to 60% of the baseline value through DVFS technology.

[0068] The verification and fault tolerance subsystem is used to perform variable packet length (512B~8MB) stress tests, generate latency-throughput curves, and select the transmission protocol according to real-time requirements: when the real-time requirement is ≤1ms, the SRIO protocol is forcibly enabled; when a GPU failure is detected, the task checkpoint is triggered, saved to the shared memory pool, and resumed in the backup container, with a recovery latency of ≤50ms.

[0069] The protocol selection decision tree of the verification and fault tolerance subsystem is generated according to the following rules:

[0070] First-level judgment: If the application layer is marked as a critical task, then RapidIO will be forced to be selected;

[0071] Second-level judgment: If the data integrity requirement is ≥99.999%, then enable RapidIO's ACK retransmission mechanism;

[0072] Level 3 judgment: If the throughput requirement is >40Gbps, then enable multipath Ethernet load balancing.

[0073] In one embodiment of the present invention, the cross-chassis communication network supports hardware-level timestamp synchronization with a synchronization accuracy of ≤10ns; the timestamp synchronization mechanism is implemented as follows:

[0074] Hardware synchronization: Nanosecond-level clock synchronization is achieved through the White Rabbit protocol;

[0075] Software compensation: insert a delay calibration module in the data packet processing pipeline, the calculation formula is:

[0076]

[0077] In the formula, is the time stamp of the receiving end, is the time stamp of the sending end, is the calibrated time.

[0078] The processing method of the high-performance CPU-GPU cooperative processing architecture of the audio integrated signal processor of the application comprises the following steps:

[0079] S1: cooperative processing of audio signals through multi-core CPU and GPU, wherein the multi-core CPU performs real-time beamforming calculation based on the AVX-512 instruction set; the GPU performs convolutional neural network inference based on the CUDA parallel architecture; the temperature gradient of the CPU and the GPU is monitored in real time, and when the temperature difference is greater than or equal to 5 DEG C, adaptive wind speed adjustment is triggered to optimize heat dissipation;

[0080] S2: select the transmission mode according to the data packet size: when the data packet size L is greater than or equal to 2MB, enable the 4-channel binding mode of the SRIO 4x interface; when the data packet size L is less than 256KB, enable the single-channel mode of the SRIO; in cross-cabinet communication: perform RDMA zero-copy transmission through optical fiber based on the RoCEv2 protocol; insert a link state prediction field in the data packet header, and dynamically select the optimal transmission path according to the congestion probability and the bit error rate;

[0081] The insertion method of the link state prediction field comprises: updating the prediction value by using an exponential weighted moving average algorithm according to the historical transmission data to calculate the congestion probability; monitoring the bit error rate in the optical fiber link in real time, and when the bit error rate , automatically switch to the backup channel;

[0082] S3: dynamically schedule according to the task allocation matrix decision function, predict the GPU memory occupancy rate in the next 5 seconds based on the LSTM model, and allocate tasks according to the prediction results: allocate the beamforming task to the CPU for execution; allocate the convolutional neural network inference task to the GPU for execution;

[0083] The training method of the LSTM model comprises: the input features are the GPU memory occupancy rate, the task queue length and the calculation load type in the past 60 seconds; the output is the memory occupancy rate prediction value in the future 5 seconds, and the training loss function adopts mean square error (MSE) optimization;

[0084] S4: dynamically allocate the total bandwidth according to the priority weight ratio:

[0085]

[0086] And reserve 20% bandwidth as an emergency channel for real-time tasks; when the system load < 30%, close the redundant GPU instance, and reduce the CPU frequency to 60% of the benchmark value through the DVFS technology;

[0087] S5: Perform variable packet length (512B~8MB) stress test, generate latency-throughput curve, and select transmission protocol according to real-time requirements: when the real-time requirement is ≤1ms, enable SRIO protocol; when GPU failure is detected, trigger incremental checkpoint saving mechanism: only save updated data blocks, and store them in distributed shared memory pool through LZ4 compression, ensuring that the recovery delay is ≤50ms;

[0088] Among them, the incremental checkpoint saving mechanism includes: identifying the updated data block through a hash algorithm, and only compressing and storing the newly added or modified data block; when recovering, quickly locate and decompress the data block according to the hash index, and load it to the available computing node in parallel.

[0089] The application realizes the cooperative processing of high performance and low latency through the CPU-GPU heterogeneous computing of the processing module, the dynamic routing optimization of the data transmission module, and the intelligent allocation of the task scheduling middleware; Dynamic resource adaptation: the resource optimization module dynamically adjusts the bandwidth and energy consumption in combination with the real-time load state, balances the system efficiency and stability; Industrial reliability: the verification module ensures the transmission reliability and task continuity in complex environments through the protocol decision tree and fault tolerance mechanism.

[0090] Finally, it should be explained that the above preferred embodiments are only used to illustrate the technical solutions of the application and are not limited. Although the application has been described in detail through the above preferred embodiments, those skilled in the art should understand that various changes can be made in form and details without departing from the scope defined by the claims of the application.

Claims

1. A high-performance CPU-GPU co-processing architecture for an integrated audio signal processor, characterized in that, include: At least one chassis unit, each chassis unit integrating multiple heterogeneous computing units, the heterogeneous computing units including a main processing chip directly connected to a multi-core CPU and a GPU via a high-speed data transmission interface; Board-level communication interfaces include an onboard NVLink 3.0 interface with a bandwidth of ≥200GB / s, an inter-board 40G / 10G Ethernet interface, and an SRIO 4x interface, used to select the transmission mode according to the data packet size; A cross-chassis communication network interconnects multiple chassis units through fiber optic switches, and performs RDMA zero-copy transmission via fiber optics based on the RoCE v2 protocol. A task scheduling middleware, a scheduler based on the Kubernetes architecture extension, which configures dynamic priority policies and generates a task allocation matrix based on the real-time requirements and computational complexity of signal processing tasks. The communication proxy module is used to deploy the protocol conversion gateway, which supports bidirectional conversion between RapidIO and Ethernet protocols, and inserts a link state prediction field into the data packet header to dynamically select the optimal transmission path based on the congestion probability and bit error rate. The resource optimization module is used for dynamic allocation of communication resources, allocating bandwidth to each container according to the task allocation matrix. The verification and fault tolerance subsystem is used to perform variable packet length stress tests, generate latency-throughput curves, and select the transmission protocol according to real-time requirements: when the real-time requirement is ≤1ms, the SRIO protocol is forcibly enabled; when a GPU failure is detected, the task checkpoint is triggered, saved to the shared memory pool, and resumed in the backup container, with a recovery latency of ≤50ms. The dynamic priority strategy of the task scheduling middleware is implemented through the following steps: Task classifier: Divides underwater acoustic signal processing tasks into real-time, near-real-time, and offline categories; based on the real-time requirements and computational complexity of the signal processing tasks. Generate a task assignment matrix, the decision function of which is: In the formula, This represents the task priority weight value. It is the reciprocal of the task deadline. The logarithm of the computational amount of the task. This represents the percentage of idle GPU resources. To ensure that tasks nearing their deadlines are executed first, To perform logarithmic compression on computationally intensive tasks, To dynamically balance GPU load, , , Let be the weighting coefficient, satisfying + + =1; Resource Predictor: Trains an LSTM model based on historical load data to predict GPU memory usage and CPU thread utilization within the next 5 seconds; Scheduling decision engine: Combining task categories and resource prediction results, it generates a mapping table from tasks to computing resources, prioritizing the allocation of beamforming algorithms to CPU cores and convolutional neural network inference to GPU instances.

2. The high-performance CPU-GPU collaborative processing architecture of the audio integrated signal processor according to claim 1, characterized in that, The resource optimization module dynamically allocates communication resources based on a bandwidth allocation algorithm. The allocation mechanism is as follows: 20% of the total bandwidth is reserved for real-time tasks; when a high-priority task requests bandwidth, the bandwidth resources already allocated to low-priority tasks can be forcibly reclaimed. The bandwidth allocation algorithm is as follows: In the formula, The amount of resources allocated to the current task. This represents the task priority weight value. This represents the total amount of resources that can be allocated by the system. The sum of the priority weights of all tasks, where, For the total number of tasks, For task indexing.

3. The high-performance CPU-GPU collaborative processing architecture of the audio integrated signal processor according to claim 2, characterized in that, The energy consumption control strategy of the resource optimization module includes: shutting down redundant GPU instances when the system load is less than 30%, and reducing the CPU frequency to 60% of the baseline value through DVFS technology.

4. The high-performance CPU-GPU collaborative processing architecture of the audio integrated signal processor according to claim 3, characterized in that, The board-level communication interface transmission modes include: when the data packet size L ≥ 2MB, the SRIO 4x interface 4-channel bonding mode is enabled; when the data packet size L < 256KB, the SRIO single-channel mode is enabled; and one backup channel is allocated to each SRIO interface, with the primary channel bit error rate... When necessary, it will automatically switch to the backup channel.

5. The high-performance CPU-GPU collaborative processing architecture of the audio integrated signal processor according to claim 4, characterized in that, The protocol selection decision tree for the verification and fault-tolerant subsystem is generated using the following rules: First-level judgment: If the application layer is marked as a critical task, then RapidIO will be forced to be selected; Second-level judgment: If the data integrity requirement is ≥99.999%, then enable RapidIO's ACK retransmission mechanism; Level 3 judgment: If the throughput requirement is >40Gbps, then enable multipath Ethernet load balancing.

6. The high-performance CPU-GPU collaborative processing architecture of the audio integrated signal processor according to claim 5, characterized in that, Cross-chassis communication networks support hardware-level timestamp synchronization with a synchronization accuracy of ≤10ns; the timestamp synchronization mechanism is implemented as follows: Hardware synchronization: Nanosecond-level clock synchronization is achieved through the White Rabbit protocol; Software compensation: A delay calibration module is inserted into the packet processing pipeline. The calculation formula is as follows: In the formula, For the receiving end timestamp, For the sender's timestamp, This is the calibrated time.

7. The high-performance CPU-GPU collaborative processing architecture of the audio integrated signal processor according to claim 6, characterized in that, The processing method includes the following steps: S1: Audio signals are processed in collaboration between a multi-core CPU and a GPU. The multi-core CPU performs real-time beamforming calculations based on the AVX-512 instruction set, while the GPU performs convolutional neural network inference based on the CUDA parallel architecture. The temperature gradient between the CPU and GPU is monitored in real time, and when the temperature difference is ≥5℃, adaptive fan speed adjustment is triggered to optimize heat dissipation. S2: Select transmission mode based on data packet size: When the data packet size L≥2MB, enable the 4-channel bonding mode of the SRIO 4x interface; when the data packet size L<256KB, enable the SRIO single-channel mode; in cross-chassis communication: RDMA zero-copy transmission is performed through optical fiber based on the RoCE v2 protocol; a link state prediction field is inserted into the data packet header, and the optimal transmission path is dynamically selected based on the congestion probability and bit error rate; S3: Dynamically schedule tasks based on the task allocation matrix decision function, predict the GPU memory usage rate within the next 5 seconds based on the LSTM model, and allocate tasks according to the prediction results: allocate beamforming tasks to the CPU for execution; allocate convolutional neural network inference tasks to the GPU for execution; S4: Dynamically allocate total bandwidth according to priority weight ratio: Reserve 20% bandwidth as an emergency channel for real-time tasks; when the system load is less than 30%, shut down redundant GPU instances and reduce the CPU frequency to 60% of the baseline value using DVFS technology; S5: Perform variable packet length stress tests, generate latency-throughput curves, and select the transmission protocol according to real-time requirements: When the real-time requirement is ≤1ms, the SRIO protocol is forcibly enabled; when a GPU failure is detected, an incremental checkpoint saving mechanism is triggered: only the updated data blocks are saved and stored in a distributed shared memory pool through LZ4 compression to ensure that the recovery latency is ≤50ms.

8. The high-performance CPU-GPU collaborative processing architecture of the audio integrated signal processor according to claim 7, characterized in that, The training method for the LSTM model includes: input features are GPU memory usage, task queue length and computational load type over the past 60 seconds; output is the predicted memory usage for the next 5 seconds; and the training loss function is optimized using mean squared error.

9. The high-performance CPU-GPU collaborative processing architecture of the audio integrated signal processor according to claim 8, characterized in that, The incremental checkpoint saving mechanism includes: identifying updated data blocks using a hash algorithm, compressing and storing only newly added or modified data blocks; and quickly locating and decompressing data blocks by hash index during recovery, and loading them in parallel to available computing nodes.

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