Hybrid power module comprising buffer unit and manufacturing method thereof

Abstract

The present invention provides a hybrid power module comprising a buffer unit and a manufacturing method thereof, the module comprising: a single or a plurality of power subunits embedded in a PCB, each power subunit comprising a copper groove structure, and a Si MOSFET chip and a SiC JFET chip stacked in the copper groove structure; an electrode plate is arranged on the Si MOSFET chip, and one end of the electrode plate is connected with the SiC JFET chip; and the RC buffer unit and the thermosensitive element are arranged on the PCB and are connected with the power subunit. According to the invention, the high-voltage SiC JFET chip and the low-voltage Si MOSFET chip are stacked together, so that parasitic parameters between chips in the power subunit are effectively avoided; the design space is optimized by changing the electrode leading-out mode of the vertical device. The RC buffer unit is integrated near the chip on the PCB, so that dV / dt is effectively suppressed, and voltage overshoot and ringing of the system in the high-frequency switching process are relieved. According to the invention, the thermosensitive element is vertically arranged at the top of the chip, so that the contradiction between the electrical isolation of the temperature sensing detection circuit and the temperature monitoring accuracy of the chip is solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor power module control, and in particular to a hybrid power module including a buffer unit and a manufacturing method thereof. Background Art

[0002] As the power density and switching frequency of power semiconductors continue to increase, higher requirements are placed on module packaging to fully utilize the chip performance of third-generation semiconductors. The hybrid packaging module proposed in CN110226226A and US11227819B2 utilizes the low on-resistance, high switching frequency, and high voltage withstand characteristics of SiC JFETs, as well as the flexible gate voltage turn-on characteristics and high gate reliability of low-voltage Si MOSFETs or GaN HEMTs. This hybrid packaging module eliminates the gate reliability issues of SiC MOSFETs and is more flexible in the selection of drive gate voltages. It can adapt to various drive voltage platforms of the client, effectively reducing the client's product development costs and shortening the development cycle. However, because this cascode hybrid packaging has an additional chip compared to the packaging of a single SiC MOSFET, the electrical interconnection path between the two chips introduces additional parasitic parameters.

[0003] like Figure 1 As shown in Figure 2, there are two main physical layouts for existing hybrid packages: discrete and stacked. Discrete cascodes utilize side-by-side chips, where the SiC JFET is typically secured to the package leadframe via silver sintering, while the low-voltage MOSFET is mounted on a metal-plated ceramic isolator. Two independent sets of wires connect the JFET source / MOSFET drain and the MOSFET source / pin, respectively. In contrast, stacked cascodes eliminate the wires between the JFET source and MOSFET drain, reducing the impact of stray inductance while utilizing thinner wires to optimize electrical performance.

[0004] Since both devices are vertical devices, both layout methods generally require the use of a lead frame to lead out the various electrodes of the chip. The parasitic parameters on the lead frame affect the performance of the product to a certain extent. The use of a frame to lead out the electrodes limits the wiring method of the client during use, which may also introduce more parasitic parameters into the client's circuit.

[0005] Because the switching speed of the Cascode JFET is too fast, and the turn-off speed is faster than the turn-on speed, excessive turn-off voltage overshoot and ringing phenomenon are prone to occur. The charging process of the Cascode output capacitor does not involve the gate current, and adjusting the Cascode gate resistance cannot directly adjust the switching voltage rate of change (dV / dt). Although the gate resistance can adjust the switching speed of the Cascode JFET, thereby indirectly adjusting the switching current pressure swing rate di / dt. But its effect is poor, because when the Cascode gate resistance is large enough, although it can suppress dV / dt, it will cause the switching delay time to be too long and increase the switching loss.

[0006] The chip in the embedded power module is directly embedded in the PCB, but it also brings new problems, such as the CTE difference between the chip and the copper material near the chip, the polymer material in the PCB, etc. The thermal expansion difference between each part and the high-frequency switching of the chip will bring thermal stress and cold-hot alternating impact during service. This stress alternating impact is more obvious in the embedded module, and the chip and each connection interface in the packaging system face greater challenges.

[0007] In addition, the junction temperature monitoring of the power module has always been concerned in the application process, so many power modules have thermistors or diodes inside. These electronic components often need insulation or electrical isolation protection, and are generally arranged far away from the chip and in the same horizontal plane. Affected by the flow condition of the heat dissipation fluid, and there is a heat conduction time difference between the chip and the thermosensitive element, the junction temperature cannot be accurately predicted in time. Some manufacturers directly integrate temperature sensing diodes on the chip, which will occupy the effective flow area of the chip, affect the performance of the chip, and greatly increase the cost of the chip. SUMMARY

[0008] The present application provides a hybrid power module comprising a buffer unit and a manufacturing method thereof to overcome the deficiencies of the prior art.

[0009] To achieve the above-mentioned purpose, the present application provides a hybrid power module comprising a buffer unit, which comprises:

[0010] A single or multiple power sub-units embedded in a PCB board, comprising: a copper groove structure, SiMOSFET chips and SiC JFET chips stacked in the copper groove structure; an electrode sheet is arranged on the SiMOSFET chip, and one end of the electrode sheet is connected with the SiC JFET chip;

[0011] An RC buffer unit is arranged on the PCB board and connected with the power sub-unit.

[0012] Preferably, the SiMOSFET chip and the SiC JFET chip both have an N-terminal and a P-terminal, the P-terminal of the SiMOSFET chip is connected to the N-terminal of the SiC JFET chip; and the P-terminal of the SiC JFET chip is connected to the copper groove structure.

[0013] Preferably, the side of the copper groove structure is provided with an adhesion enhancement groove for enhancing the bonding strength.

[0014] Preferably, the copper slot structure is an integrated thin copper sheet, and the RC buffer unit includes: a resistor and a capacitor connected in series, which are arranged at both ends of the copper slot structure.

[0015] Preferably, the copper slot structure is a copper-clad substrate, the end of the copper-clad substrate is connected to a copper block, and the copper block is connected to the RC buffer unit through a copper-filled blind via; the copper-clad substrate includes: an upper copper layer, a ceramic layer and a lower copper layer stacked together.

[0016] Preferably, the electrode sheet includes: a gate electrode sheet and an N-pole electrode sheet, the gate electrode sheet is connected to the gate of the SiMOSFET chip, and the N-pole electrode sheet is connected to the source of the SiMOSFET chip.

[0017] Preferably, one end of the N-pole electrode sheet is connected to the gate of the SiC JFET chip.

[0018] Preferably, the hybrid power module is encapsulated using epoxy molding compound.

[0019] Preferably, the thermal element is provided on the PCB and is located on top of the Si MOSFET chip and connected thereto.

[0020] The present invention also provides a method for manufacturing a hybrid power module including a buffer unit, the specific steps of which include:

[0021] S1: manufacturing power subunits;

[0022] The P-terminal of the SiC JFET chip is attached to the groove of the copper groove structure, wherein the copper groove structure is oxygen-free copper;

[0023] Attaching a SiMOSFET chip to the N-terminal of a SiC JFET chip; Arranging an electrode sheet on the SiMOSFET chip, wherein the electrode sheet is a thin copper sheet, and connecting the N-terminal of the SiMOSFET chip to the gate terminal of the SiC JFET chip to lead to electrode interfaces at the N-terminal and gate terminals of the SiMOSFET chip;

[0024] Perform transfer molding or lamination molding;

[0025] S2: PCB embedded packaging and integration;

[0026] Power sub-unit embedding: the finished power sub-unit is transfer-molded or laminated, and embedded in the PCB;

[0027] Laser drilling is performed;

[0028] Copper deposition hole filling: the electrodes of the power sub-unit are led to the PCB circuit layout layer through laser drilling by using a copper deposition process;

[0029] PCB whole-layer copper deposition;

[0030] Circuit etching;

[0031] After the brown oxidation treatment, PCB pressing, windowing and surface treatment are performed;

[0032] The driving circuit, RC buffer element and thermal element are arranged on the PCB layout layer.

[0033] The application provides a hybrid power module comprising a buffer unit and a manufacturing method thereof, which has the beneficial effect that a high-voltage SiC JFET chip and a low-voltage Si MOSFET chip are stacked together to form a hybrid packaged power module unit, the parasitic parameters between the two chips are reduced as much as possible, and the electrode lead-out mode of the vertical device is changed, thereby providing more optimization space for user end packaging design.

[0034] 1. The SiC JFET chip and Si MOSFET chip hybrid packaged power unit replaces SiC MOSFET to provide more flexible and convenient driving voltage selection for users, reduce user end system cost and product development cycle. Among them, the high-voltage SiC JFET and the low-voltage Si MOSFET are stacked and packaged to form a power sub-unit, the vertical device packaging characteristics of the chip are changed, and then the power sub-unit is arranged in the PCB, so that the parasitic parameters in the system are reduced, the performance and efficiency of the power module are improved, the reliability of the gate of the power sub-unit is guaranteed, and there is no anxiety about parasitic false turn-on.

[0035] 2. The stacked hybrid packaging effectively avoids the parasitic parameters between the chips in the power unit, and the electrode sheet arranges the P end, the N end and the gate of the power sub-unit on the same horizontal plane, so that the subsequent chip interconnection is more flexible, and a more flexible electrical interface is provided for the packaging design and circuit integration of the user end, thereby effectively reducing the parasitic parameters of the entire circuit system and improving the performance and efficiency of the system.

[0036] 3. Fabricating the chips in the cascode structure into stacked subunits effectively reduces the overall size of the embedded PCB module while also avoiding the need for multiple chips to be concentrated on the same metal plate or DBC circuit board during circuit connection and construction. Distributing the cascode structure's power subunits throughout the PCB effectively reduces thermal stress near the chip and throughout the entire PCB, improving module reliability.

[0037] 4. To address the problem of Cascode JFET switching speed being too fast, the present invention directly integrates an RC buffer unit on the PCB. The buffer unit is directly integrated near the chip and can effectively suppress dV / dt and alleviate voltage overshoot and ringing.

[0038] 5. Directly embedding the thermal sensor directly above the chip reduces the distance between the thermal sensor and the chip, minimizing the heat conduction time and temperature difference between the chip and the thermal sensor. This approach also avoids the reduction in the chip's effective flow area and the resulting performance degradation that occurs with on-chip integration. This approach balances chip temperature prediction accuracy, cost, and performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 Figures 1 and 2 show two types of existing hybrid packaging. (a) shows a discrete hybrid packaging power module, and (b) shows a stacked hybrid packaging power module.

[0040] Figure 2 A circuit schematic diagram of a power subunit in a hybrid power module including a buffer unit provided by the present invention;

[0041] Figure 3 A schematic diagram of placing a chip on a copper slot structure with grooves through one or more sintering steps in a hybrid power module including a buffer unit provided by the present invention;

[0042] Figure 4 A schematic diagram of internal components of a power subunit in a hybrid power module including a buffer unit provided by the present invention;

[0043] Figure 5 A cross-sectional view of a power subunit in a hybrid power module including a buffer unit provided by the present invention;

[0044] Figure 6 A schematic diagram of a finished product of a power subunit in a hybrid power module including a buffer unit provided by the present invention;

[0045] Figure 7A schematic diagram of the power sub-module transfer mold and embedding PCB in the manufacturing method of the hybrid power module with buffer unit provided by the present application;

[0046] Figure 8 A schematic diagram of laser drilling on the power sub-module in the manufacturing method of the hybrid power module with buffer unit provided by the present application;

[0047] Figure 9 A schematic diagram of copper filling in the manufacturing method of the hybrid power module with buffer unit provided by the present application;

[0048] Figure 10 A schematic diagram of PCB whole layer copper filling in the manufacturing method of the hybrid power module with buffer unit provided by the present application;

[0049] Figure 11 A schematic diagram of circuit etching in the manufacturing method of the hybrid power module with buffer unit provided by the present application;

[0050] Figure 12 A schematic diagram of wiring lamination and pad windowing in the manufacturing method of the hybrid power module with buffer unit provided by the present application;

[0051] Figure 13 A schematic diagram of circuit layout and RC, temperature sensing element integration in the manufacturing method of the hybrid power module with buffer unit provided by the present application;

[0052] Figure 14 A schematic diagram of another embodiment of copper slot structure in the manufacturing method of the hybrid power module with buffer unit provided by the present application. DETAILED DESCRIPTION

[0053] The above embodiments and characteristics in the embodiments can be combined with each other without conflict under the premise of not violating the principles of the present application.

[0054] It should be noted that the diagrams provided in the following embodiments only schematically illustrate the basic concepts of the present application, and only the components related to the present application are shown in the diagrams, rather than the number, shape and size of the components in actual implementation. The shapes, number and proportions of the components in actual implementation can be arbitrarily changed, and the component layout pattern can be more complex.

[0055] All directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, horizontal, vertical...) are only used to explain the relative position relationship, movement status, etc. between the components in a certain specific posture. If the specific posture changes, the directional indication will also change accordingly.

[0056] Due to installation errors and other reasons, the parallel relationship referred to in the embodiments of the present invention may actually be an approximately parallel relationship, and the perpendicular relationship may actually be an approximately perpendicular relationship.

[0057] like Figures 2 to 6 As shown, the present invention provides a hybrid power module (hereinafter referred to as "hybrid power module") including a buffer unit, which includes: a power subunit and an RC buffer unit. One or more power subunits are embedded in a PCB board, including: a copper slot structure (Copper), a Si MOSFET chip and a SiC JFET chip stacked in the copper slot structure; an electrode sheet (Copper clip) is provided on the Si MOSFET chip, and one end of the electrode sheet is connected to the SiC JFET chip. The RC buffer unit and thermistor (such as NTC, PTC, temperature-sensing diode, etc.) are arranged on the PCB board and connected to the power subunit.

[0058] Specifically, the present invention arranges the power subunit (Power Unit) in the PCB, making the PCB wiring more flexible, effectively reducing the conductive path, and realizing stacked wiring to offset the inductance, thereby reducing the parasitic parameters in the system and improving the performance and efficiency of the power module. In order to solve the problem of too fast switching speed of Cascode JFET, the present invention directly integrates the RC buffer unit on the PCB. The capacitor C in the buffer unit is buffer With resistor R buffer Direct integration near the chip enables close proximity, effectively suppressing dV / dt and mitigating voltage overshoot and ringing during high-frequency switching. The NTC thermistor is placed directly above the chip, enabling close vertical placement and enabling instant, reliable, and low-cost chip junction temperature monitoring.

[0059] The schematic diagram of the connection between the power sub-unit and the RC buffer unit is as follows Figure 2 As shown in FIG, by connecting the RC snubber unit to both ends of the power sub-unit, dV / dt is suppressed, and the voltage overshoot and ringing of the system during high-frequency switching are alleviated.

[0060] In this embodiment, both the SiMOSFET chip and the SiC JFET chip have an N-terminal and a P-terminal. The P-terminal of the SiMOSFET chip is connected to the N-terminal of the SiC JFET chip; the P-terminal of the SiC JFET chip is connected to the copper trench structure.

[0061] Specifically, each chip in this hybrid power module has an N-terminal at the top and a P-terminal at the bottom. Stacking the SiMOSFET chip, SiCJFET chip, and copper trench structure reduces parasitic parameters between the chips and, through the chip stacking arrangement, reduces chip footprint. Furthermore, the P-terminal of the SiC JFET chip is connected to the copper trench structure, allowing it to be routed to the top surface of the power subunit through the copper trench structure.

[0062] In this embodiment, the side of the copper groove structure is provided with an adhesion enhancement groove (adhesion enhancement groove) to enhance the bonding strength. Specifically, the hybrid power module is encapsulated with epoxy molding compound (EMC). The interface strength between the molding compound and the copper material is relatively weak, and the CTE difference between the two materials will cause the device to fail due to delamination during service due to thermal stress caused by temperature changes. Grooving the copper material can effectively form a latch structure, increase the attachment area and adhesion, and avoid delamination of the molding compound. In addition, in order to further enhance the interfacial bonding strength between the epoxy molding compound and the copper material, the copper material can be surface treated, such as by plasma cleaning, providing a plating layer, applying a strengthening organic layer, etc. to enhance adhesion.

[0063] In this embodiment, the copper clip includes a gate electrode clip and an N-pole electrode clip. The gate electrode clip is connected to the gate of the Si MOSFET chip, and the N-pole electrode clip is connected to the source of the Si MOSFET chip. One end of the N-pole electrode clip is connected to the gate of the SiC JFET chip.

[0064] Specifically, by laying out an electrode clip (copper clip) on the SiMOSFET, where the electrode clip is a thin copper sheet, the N-terminal of the SiMOSFET chip can be connected to the gate G2 of the SiC JFET chip, and the electrode user interface of the N-terminal of the SiMOSFET chip and the gate G1 can be brought out, making the chip interconnection more flexible and providing a more flexible electrical interface for the user-side packaging design and circuit integration, thereby effectively reducing the parasitic parameters of the entire circuit system and improving the performance and efficiency of the system.

[0065] In this embodiment, the copper slot structure is an integrated thin copper sheet, and the RC buffer unit includes a resistor and a capacitor connected in series, which are disposed at both ends of the copper slot structure.

[0066] Specifically, the P-terminal of the SiC JFET chip is connected to the top surface of the power subunit through a copper trench structure. It is then connected to an RC snubber, achieving an electrical connection between the power subunit and the RC snubber. During operation, the RC snubber effectively suppresses dV / dt, mitigating voltage overshoot and ringing during high-frequency switching. The closer the RC snubber is to the chip within the power subunit, the better the effect. This distance can be customized based on the actual application scenario.

[0067] In this embodiment, the thermistor is mounted on a PCB, located on top of and connected to the SiMOSFET chip. Specifically, the present invention utilizes embedded packaging to place the thermistor directly above the chip. Due to the reduced distance, the heat conduction time difference between the chip and the thermistor is minimized, enabling timely and accurate junction temperature prediction while minimizing the chip's effective flow area. This resolves the conflict between electrical isolation of the temperature sensing circuit and chip temperature monitoring accuracy, providing users with a more immediate and accurate junction temperature prediction model.

[0068] Based on the above hybrid power module including a buffer unit, the present invention also provides a manufacturing method corresponding to the structure, the specific steps of which include:

[0069] S1: manufacturing power subunits;

[0070] S1.1: Attach the P-terminal of the SiC JFET chip to the groove of the copper groove structure by welding or sintering, wherein the copper groove structure is oxygen-free copper;

[0071] S1.2: Attach the Si MOSFET chip to the N-terminal of the SiC JFET chip by welding or sintering. If technical or equipment conditions permit, this step can be performed simultaneously with step S1.1. This one-step connection process can effectively increase production capacity and reduce costs.

[0072] S1.3: Lay out the electrode sheet on the Si MOSFET chip. The electrode sheet is a thin copper sheet. The electrode sheet connects the N-end of the Si MOSFET chip to the gate end of the SiC JFET chip to lead out the electrode interface of the N-end and gate end of the SiMOSFET chip. The connection between the electrode sheet and the chip is by welding or sintering. If the technical or equipment conditions permit, this step can be implemented simultaneously with step S1.1 or step S1.2 during the specific operation. The one-step connection process can effectively improve production capacity and reduce costs.

[0073] S1.4: Perform transfer molding or lamination molding to protect the chip. The subsequent embedding process in step S2 can be directly laminated. The adhesion enhancement groove on the copper groove structure effectively increases the bonding strength between the EMC and the copper material, preventing delamination of the EMC.

[0074] S2: PCB embedded packaging and integration, such as Figures 7-13 shown.

[0075] S2.1: Power sub-unit embedding: The completed (i.e., welded or sintered) power sub-unit is transferred to a mold and plastic package to protect the chip and embed it into the PCB board to prepare for the chip circuit integration.

[0076] S2.2: Perform laser drilling to ensure that each electrode on the power unit is effectively exposed to prepare for subsequent electrical connections.

[0077] S2.3: Copper filling: Use the copper filling process to lead each electrode of the power sub-unit to the PCB circuit wiring layer through laser drilling;

[0078] S2.4: Copper deposition on the entire PCB layer; electroplating is performed on the entire PCB board to thicken the copper layer to meet the circuit conductivity and mechanical strength requirements. After electroplating, the board is cleaned to remove the residual plating solution on the surface.

[0079] S2.5: Circuit etching: perform film lamination, exposure, development, etching, and film removal to complete the visible circuit connection on the PCB board surface.

[0080] S2.6: After the browning process, the PCB is pressed, windowed, and surface treated. The semi-finished PCB with the embedded chip is stacked with the prepreg, ensuring the correct positioning of each layer. The prepreg cures under high temperature and pressure, tightly bonding with the PCB and providing insulation and structural protection for the wiring layer. Pad windowing, solder mask fabrication, character printing, and pad surface treatments such as immersion gold, tin spraying, and OSP (organic solderability preservative) are also performed on the surface.

[0081] S2.7: Arrange the driving circuit and RC buffer components on the PCB wiring layer. Arrange the driving circuit, RC buffer components, thermistors (such as temperature sensing resistors or temperature sensing diodes, etc.) on the PCB wiring layer. The circuit layout can be flexibly designed according to user needs. For example, multiple power sub-units can be embedded in the PCB and connected in series and parallel to form an application scenario that adapts to larger current and voltage levels. The circuit topology printed on the PCB can also be flexibly designed, including single switch, half-bridge, H-bridge, three-phase inverter, Boost, Buck, Buck-Boost, single-word three-level, T-word three-level and other circuit topologies. Taking advantage of the unique wiring advantages of PCB, these circuit topologies can have extremely low parasitic parameters, improving the performance and efficiency of electronic components.

[0082] like Figure 14 As shown, in another embodiment of the present invention, the copper groove structure is a copper-clad substrate, the end of the copper-clad substrate is connected to a copper block, and the copper block is connected to the RC buffer unit through a copper-filled blind via; the copper-clad substrate includes: an upper copper layer, a ceramic layer and a lower copper layer stacked together.

[0083] Specifically, this embodiment replaces the thin copper sheet with a DBC (copper-clad substrate) with copper spacers sintered at both ends. The DBC is a three-layer structure, with copper layers on the top and bottom, and a ceramic layer in the middle. The ceramic can be silicon nitride, aluminum oxide, aluminum nitride, or modified ceramics doped with other elements. This embodiment increases cost, but provides insulation on the back of the chip and effectively dissipates heat, facilitating thermal design optimization at the user end and further improving the performance and efficiency of the hybrid power module.

[0084] Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

Claims

1. A hybrid power module comprising a buffer unit, characterized in that: include: A single or multiple power subunits, embedded in a PCB, comprising: a copper slot structure, a SiMOSFET chip and a SiC JFET chip stacked within the copper slot structure; an electrode sheet is provided on the SiMOSFET chip, one end of which is connected to the SiC JFET chip; The RC buffer unit and the thermal element are arranged on the PCB board and connected to the power sub-unit.

2. The hybrid power module comprising a buffer unit according to claim 1, wherein: The SiMOSFET chip and the SiC JFET chip both have an N-terminal and a P-terminal. The P-terminal of the SiMOSFET chip is connected to the N-terminal of the SiC JFET chip; the P-terminal of the SiCJFET chip is connected to the copper groove structure.

3. The hybrid power module comprising a buffer unit according to claim 2, wherein: The side of the copper groove structure is provided with an adhesion enhancement groove for enhancing the bonding strength.

4. The hybrid power module comprising a buffer unit according to claim 3, wherein: The copper slot structure is an integrated thin copper sheet, and the RC buffer unit includes a resistor and a capacitor connected in series, which are arranged at both ends of the copper slot structure.

5. The hybrid power module comprising a buffer unit according to claim 1, wherein: The copper trough structure is a copper-clad substrate, the end of the copper-clad substrate is connected to a copper block, and the copper block is connected to the RC buffer unit through a copper-filled blind via; the copper-clad substrate includes: an upper copper layer, a ceramic layer and a lower copper layer stacked together.

6. The hybrid power module comprising a buffer unit according to claim 1, wherein: The electrode sheet includes a gate electrode sheet and an N-pole electrode sheet. The gate electrode sheet is connected to the gate of the SiMOSFET chip, and the N-pole electrode sheet is connected to the source of the SiMOSFET chip.

7. The hybrid power module comprising a buffer unit according to claim 6, wherein: One end of the N-pole electrode sheet is connected to the gate of the SiC JFET chip.

8. The hybrid power module comprising a buffer unit according to claim 1, wherein: The hybrid power module is encapsulated with epoxy molding compound.

9. The hybrid power module comprising a buffer unit according to claim 1, wherein: The thermal element is arranged on the PCB and is located on the top of the SiMOSFET chip and connected thereto.

10. A method for manufacturing a hybrid power module including a buffer unit, characterized in that: The specific steps include: S1: manufacturing power subunits; The P-terminal of the SiC JFET chip is attached to the groove of the copper groove structure, wherein the copper groove structure is oxygen-free copper; Attaching a SiMOSFET chip to the N-terminal of a SiC JFET chip; Arranging an electrode sheet on the SiMOSFET chip, wherein the electrode sheet is a thin copper sheet, and connecting the N-terminal of the SiMOSFET chip to the gate terminal of the SiC JFET chip to lead to electrode interfaces at the N-terminal and gate terminals of the SiMOSFET chip; Perform transfer molding or lamination molding; S2: PCB embedded packaging and integration; Power sub-unit embedding: The finished power sub-unit is transferred to a plastic package or laminated to be embedded in the PCB board; Perform laser drilling; Copper plating and hole filling: The electrodes of the power sub-unit are led to the PCB circuit wiring layer through laser drilling using the copper plating process; PCB whole layer copper deposition; Circuit etching; After browning treatment, PCB pressing, window opening and surface treatment are carried out; Arrange the driving circuit, RC buffer components and thermal sensors on the PCB wiring layer.

Images