Anti-latch-up contact structure used in tripe well process and preparation method of anti-latch-up contact structure

Abstract

The invention discloses an anti-latch-up contact structure for a tripe well process and a preparation method thereof. The anti-latch-up contact structure comprises a deep well region of a first conductive type on a semiconductor substrate; forming a second conductive type well region in the first conductive type deep well region, manufacturing an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) of a second conductive type channel in the first conductive type deep well region, and manufacturing an MOSFET of a first conductive type channel in the second conductive type well region; for a contact region of a first conductive type deep well region, a circle of potential floating second conductive type well region is designed as a latch-up prevention protection ring structure. The characteristics of a tripe-well CMOS (Complementary Metal-Oxide-Semiconductor Transistor) integration process with a deep well structure are utilized, photoetching layers and process steps of the integration process do not need to be additionally increased, the layout design has compatibility, the structure is simple, integration is easy, and the method is suitable for a complex integrated circuit with a special isolation requirement.

Description

Technical Field

[0001] The present invention relates to the field of CMOS integrated circuit manufacturing, in particular to an anti-latch-up contact structure used in a triple well process and a preparation method thereof. Background Art

[0002] Advanced CMOS, RF CMOS, and some embedded memory processes often require specialized features such as fully isolated NMOS devices, substrate noise isolation, and negative power supply isolation. Triple-well technology is a common technique developed to address these isolation requirements. This technology adds a buried N-well (buried N-well) as a third well to the traditional twin-well (N-well / P-well) CMOS process, forming a three-layer structure. Integrated circuit processes with this three-layer structure are referred to as triple-well processes.

[0003] The latch-up effect refers to the phenomenon in CMOS integrated circuits where the interaction of parasitic bipolar junction transistors forms a low-impedance path between the power supply and ground, causing large current to flow, resulting in IC failure or burnout.

[0004] With technological development, the application of triple wells has evolved. Triple wells generally refer to N-wells with a certain depth, that is, N-wells with a junction depth deeper than conventional N-wells (deep N-wells), which are denoted as deep N-wells. The depth can accommodate conventional P-wells, allowing NMOS and PMOS devices and related circuits to be fabricated within the deep N-well. This will also create a new parasitic latch-up structure, introducing the risk of latch-up failure.

[0005] Due to the limited junction depth of the deep N-well and the large parasitic resistance of the well, there is a risk of parasitic latch-up structures being triggered. Furthermore, compared to the parasitic latch-up structures in bulk silicon CMOS, the parasitic latch-up path in the triple well is closer to the surface, making current prone to local concentration, increasing the risk of latch-up failure. For example, in circuits with large potential fluctuations or in space radiation environments with single-particle transient triggering currents, this structure poses a risk of latch-up triggering. Therefore, for triple well applications where there is a risk of latch-up structures being triggered, the device structure can be optimized to reduce the risk of latch-up triggering. Summary of the Invention

[0006] The object of the present invention is to provide an anti-latch-up contact structure for use in a triple well process and a preparation method thereof, so as to improve the reliability of certain circuit structures in the triple well process.

[0007] The technical solution for achieving the purpose of the present invention is: a latch-up prevention contact structure for a triple well process, the structure comprising: a first conductive type deep well region on a semiconductor substrate; forming a second conductive type well region within the first conductive type deep well region, fabricating a MOSFET with a second conductive type channel within the first conductive type deep well region, and fabricating a MOSFET with a first conductive type channel within the second conductive type well region; a parasitic PNPN structure exists between adjacent P-type MOSFETs and N-type MOSFETs, and a circle of a second conductive type ring structure with a floating potential is designed for the contact area of ​​the first conductive type deep well region as a latch-up prevention protection ring.

[0008] Furthermore, the guard ring is a well of opposite conductivity type in the first conductivity type deep well region.

[0009] Furthermore, the guard ring is not provided with a potential contact area, and the potential of the guard ring in the application circuit is floating. Potential floating means that the area is not connected to a specific potential in the circuit.

[0010] Furthermore, the guard ring surrounds the deep well body contact region.

[0011] Furthermore, the boundary of the deep well contact region is tangent to the inner boundary of the guard ring.

[0012] Furthermore, the guard ring structure surrounds the deep well body contact region, and the guard ring junction depth is greater than the body contact junction depth.

[0013] The present invention also provides a method for preparing an anti-latch-up contact structure, comprising the following steps:

[0014] Step 101: fabricating an N-type well of a certain depth on a P-type semiconductor substrate by photolithography, ion implantation, and thermal diffusion processes, referred to as a deep N-well, and fabricating a P-type channel MOSFET in the deep N-well.

[0015] Step 102: A P-type well (denoted as P-well) is fabricated in the deep N-well by photolithography, ion implantation, and diffusion thermal processes. An N-channel MOSFET is fabricated in the P-well. During the same photolithography and implantation steps as the P-well fabrication steps, a ring of P-well structures is fabricated in the deep N-well contact region to surround the deep N-well contact region. The boundary of the deep N-well contact region on the layout is tangent to the inner boundary of the P-well guard ring.

[0016] Step 103, fabricating an active area and an isolation area of ​​an integrated circuit on the surface of the silicon wafer;

[0017] Step 104, forming a gate insulating layer and a gate electrode on the surface;

[0018] Step 105, making N-type implants for NMOS source / drain and PMOS body contacts; continuing to make P-type implants for PMOS source / drain and NMOS body contacts; the boundary of the deep N-well body contact is tangent to the inner boundary of the P-well guard ring;

[0019] Step 106 , making contact electrodes for the gate, source, drain and well on the device surface. The P-well guard ring does not make electrode contacts, that is, the P-well potential is floating.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] (1) The latch-up prevention guard ring structure proposed in the present invention utilizes the inherent characteristics of the triple-well CMOS integration process with a deep well structure, does not require additional lithography layers and process steps in the integration process, has compatible layout design, simple structure, and is easy to integrate. It is particularly suitable for complex integrated circuits with positive power supply voltage, negative power supply voltage, or special isolation requirements.

[0022] (2) The anti-latch-up guard ring structure proposed in the present invention keeps the carrier collection path away from the surface, reduces the emission efficiency of the parasitic transistor, and plays an anti-latch-up role.

[0023] (3) The anti-latch-up guard ring structure proposed in the present invention can also be used in anti-radiation reinforcement circuit design. For complex circuits using deep-well triple-well technology, it can provide anti-single-particle latch-up reinforcement and reduce the risk of single-particle latch-up failure. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 4 is a cross-sectional schematic diagram of a contact structure for preventing latch-up in a triple well process according to an embodiment of the present invention.

[0025] Figure 2 It is a plan view or a schematic layout diagram of a contact structure for preventing latch-up in a triple well process according to an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The present invention proposes an optimized body contact structure for MOS devices in a triple well process and a method for preparing the same. The structure comprises: a first conductive type deep well region of a certain depth on a semiconductor substrate; a second conductive type well region formed within the first conductive type deep well region, wherein a MOSFET with a second conductive type channel can be fabricated within the first conductive type deep well region, and a MOSFET with a first conductive type channel can be fabricated within the second conductive type well region. A parasitic PNPN structure exists between adjacent P-type MOSFETs and N-type MOSFETs; a circle of second conductive type well regions with floating potential is designed for the contact area of ​​the first conductive type deep well region as a latch-up protection ring structure. Floating potential refers to the region not being connected to a specific potential in the circuit, such as a power supply or ground potential.

[0027] The guard ring is a well of opposite conductivity type in a deep well. It utilizes the characteristics of the triple-well CMOS integration process with a deep well structure. Based on the same lithography and implantation steps of the well fabrication steps of opposite conductivity type in the deep well, a circle of well structure of opposite conductivity type is simultaneously fabricated in the deep well contact area. That is, no additional lithography layers and process steps of the integration process are required. The layout design is compatible, the structure is simple, and it is easy to integrate. It is particularly suitable for complex integrated circuits with special isolation requirements, and improves the circuit operation stability.

[0028] The anti-latch-up guard ring has no potential contact area, that is, the potential of the guard ring in the application circuit is floating. Potential floating means that the area is not connected to a specific potential in the circuit, such as power supply or ground potential.

[0029] The anti-latch-up guard ring structure surrounds the deep well body contact area. The boundary of the deep well contact area (active area) is tangent to the inner boundary of the guard ring. A small gap or overlap may be retained. The guard ring width can adopt the minimum size of the opposite conductivity type well design rule in the deep well in the process integration design rule.

[0030] The anti-latch-up guard ring structure surrounds the deep-well body contact area. Since the guard ring adopts the opposite conductivity type well structure in the deep well, the guard ring junction depth is greater than the conventional body contact (pick-up) junction depth, so that the carrier collection path is far away from the surface, reducing the emission efficiency of the parasitic transistor and playing an anti-latch-up role.

[0031] The anti-latch-up guard ring structure has an anti-latch-up effect and can also be used in anti-radiation hardening circuit design. For complex circuits using a deep-well triple-well process, it has an anti-single-particle latch-up reinforcement effect, reducing the risk of single-particle latch-up failure.

[0032] The following, combined with the accompanying drawings and specific embodiments, further details the anti-latch-up contact structure for triple-well processes proposed by the present invention. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clarify the purpose of illustrating the embodiments of the present invention.

[0033] Example

[0034] This embodiment is a latch-up protection ring structure in a deep N-well triple-well CMOS structure on a P-type conductive substrate. Figure 1 As shown, the plane structure (plane layout diagram) is as follows Figure 2 As shown. Figure 1 In the figure, the PMOS source P+, ​​deep N-well, and P-well form a parasitic lateral PNP transistor, and the NMOS source N+, P-well, and deep N-well form a parasitic vertical NPN transistor. The latch-up effect is usually triggered by the reverse-biased avalanche current or displacement current of the P-well / deep N-well junction. This trigger current flows through the P-well, which collects hole carriers. If too many hole carriers accumulate under the NMOS source N+, it will trigger the parasitic vertical NPN transistor to turn on. Similarly, this trigger current flows through the deep N-well, which collects electron carriers. If too many electron carriers accumulate under the PMOS source P+, ​​it will trigger the parasitic lateral PNP transistor to turn on. The turning on of both transistors will cause the PNPN thyristor current to flow, which is the latch-up effect, as shown in Figure 2. Figure 1 By setting a floating P-well protection ring in the deep N-well contact area, as shown in the dotted line. Figure 1 As shown, the parasitic PNP transistor amplification factor can be reduced, thereby suppressing the simultaneous opening of the two transistors and avoiding triggering the latch current. Figure 1 In the figure, the isolation structures of the integrated circuit, such as shallow trench isolation (STI) structure and local field oxidation (LOCOS) structure, are not drawn to simplify the schematic diagram. The brief process implementation steps are as follows:

[0035] Step 101 : An N-type well is fabricated on a P-type semiconductor substrate by ion implantation and thermal diffusion, which is referred to as a deep N-well.

[0036] In step 102, a P-type well (P-well) is formed in the deep N-well through ion implantation and diffusion thermal processes. During this P-well fabrication step, a ring of P-well structures is formed in the deep N-well contact area, surrounding the deep N-well contact region. On the layout, the boundary of the N-well contact region (active area) is tangent to the inner boundary of the P-well guard ring, with a slight gap or overlap.

[0037] Step 103: Based on the MOSFET fabrication requirements, the active region of the integrated circuit and shallow trench isolation (STI) or local field oxidation (LOCOS) isolation regions are fabricated on the silicon wafer surface. This step can also be moved forward to step 101.

[0038] Step 104 , continue to form a gate insulating layer (gate oxide) and a gate electrode (polycrystalline) on the surface.

[0039] Step 105: Continue making N-type implants for the NMOS source / drain and PMOS body contacts; continue making P-type implants for the PMOS source / drain and NMOS body contacts. As described in step 102, the deep N-well body contact boundary is tangent to the inner boundary of the P-well guard ring, with a slight gap or overlap. The P-well guard ring width can be the minimum P-well width specified in the design rules.

[0040] Step 106: Fabricate contact electrodes for the gate, source, drain, and well on the device surface. The schematic diagram does not depict the electrode structure. In this process step, the P-well guard ring does not make electrode contacts, meaning the P-well potential is floating.

[0041] The above embodiment is an anti-latch-up guard ring structure in a deep N-well triple-well CMOS structure on a P-type conductive substrate. For the anti-latch-up guard ring structure in a deep P-well triple-well CMOS structure on an N-type conductive substrate, according to the present invention, the conductivity type is replaced, that is, the guard ring of the deep P-well body contact is replaced with an N-well in the deep P-well.

[0042] Although specific embodiments of the present invention have been described above, those skilled in the art will appreciate that these are merely illustrative and that the scope of the present invention is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, and such changes and modifications are intended to fall within the scope of the present invention.

[0043] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above explanations shall fall within the scope of protection of the claims.

Claims

1. An anti-latch-up contact structure for triple well process, characterized in that: The structure includes: a first conductive type deep well region on a semiconductor substrate; a second conductive type well region is formed in the first conductive type deep well region, a MOSFET with a second conductive type channel is fabricated in the first conductive type deep well region, and a MOSFET with a first conductive type channel is fabricated in the second conductive type well region; a parasitic PNPN structure exists between adjacent P-type MOSFETs and N-type MOSFETs, and a circle of a second conductive type ring structure with floating potential is designed for the contact area of ​​the first conductive type deep well region as a protection ring to prevent latch-up.

2. The anti-latch-up contact structure for triple well process according to claim 1, wherein: The guard ring is a well of opposite conductivity type in the first conductivity type deep well region.

3. The anti-latch-up contact structure for triple well process according to claim 1, wherein: The guard ring is not provided with a potential contact area, and the potential of the guard ring in the application circuit is floating. Potential floating means that the area is not connected to a specific potential in the circuit.

4. The anti-latch-up contact structure for triple well process according to claim 1, wherein: The guard ring surrounds the deep well body contact region.

5. The anti-latch-up contact structure for triple well process according to claim 4, wherein: The boundary of the deep well contact region is tangent to the inner boundary of the guard ring.

6. The anti-latch-up contact structure for triple well process according to claim 1, wherein: The guard ring structure surrounds the deep well body contact region, and the guard ring junction depth is greater than the body contact junction depth.

7. A method for preparing the anti-latch-up contact structure according to claim 1, characterized in that: The steps include: Step 101: fabricating an N-type well of a certain depth on a P-type semiconductor substrate by photolithography, ion implantation, and thermal diffusion processes, referred to as a deep N-well, and fabricating a P-type channel MOSFET in the deep N-well. Step 102 , a P-type well is fabricated in the deep N-well by photolithography, ion implantation, and thermal diffusion processes, which is referred to as a P-well, and an N-channel MOSFET is fabricated in the P-well; During the same photolithography and implantation process as the P-well fabrication step, a circle of P-well structures is fabricated in the deep N-well contact area to surround the deep N-well contact area. The boundary of the deep N-well contact area on the layout is tangent to the inner boundary of the P-well guard ring; Step 103, fabricating an active area and an isolation area of ​​an integrated circuit on the surface of the silicon wafer; Step 104, forming a gate insulating layer and a gate electrode on the surface; Step 105, making N-type implants for NMOS source / drain and PMOS body contacts; continuing to make P-type implants for PMOS source / drain and NMOS body contacts; the boundary of the deep N-well body contact is tangent to the inner boundary of the P-well guard ring; Step 106 , making contact electrodes for the gate, source, drain and well on the device surface. The P-well guard ring does not make electrode contacts, that is, the P-well potential is floating.

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