Image sensor

Abstract

The invention provides an image sensor. The image sensor comprises a substrate; the transmission gate is located on the substrate, and the floating diffusion region is located in the substrate on one side of the transmission gate; the source following grid electrode is located on the substrate, and the source following source region and the source following drain region are located in the substrate on the two sides of the source following grid electrode respectively; the MOM capacitor is located on the side, away from the substrate, of the transmission grid electrode and the source following grid electrode, and the floating diffusion region and the source following source region are electrically connected through the MOM capacitor. According to the invention, the MOM capacitor is connected between the floating diffusion region and the source following source region, so that the parasitic capacitance of the floating diffusion region can be reduced, the charge conversion gain of the floating diffusion region can be increased, and the signal-to-noise ratio of the device can be improved, thereby improving the reading noise reduction capability of the image sensor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an image sensor. Background Art

[0002] CMOS image sensors (Complementary Metal Oxide Semiconductor Image Sensor, CIS) have the advantages of high integration, low power supply voltage and low technical threshold. They are widely used in consumer electronics, autonomous driving, biometrics or security and other fields. The noise of CIS products is mainly composed of shot noise, dark noise and read noise. Shot noise usually accounts for a large proportion and is related to light intensity. Light intensity is proportional to the amount of charge. In low-light applications, dark noise and read noise account for a significant proportion. Therefore, increasing the charge conversion gain (CG) of the floating diffusion (FD) region and improving the device signal-to-noise ratio are the keys to reducing noise in low-light applications. If the parasitic capacitance of the floating diffusion region is large, it will affect the charge conversion gain of the floating diffusion region, and ultimately affect the image sensor's read noise reduction capability. Summary of the Invention

[0003] The object of the present invention is to provide an image sensor, increase the charge conversion gain of a floating diffusion region, and improve the read noise reduction capability of the image sensor.

[0004] In order to achieve the above object, the present invention provides an image sensor, comprising:

[0005] substrate;

[0006] a transmission gate located on the substrate;

[0007] a floating diffusion region located in the substrate on one side of the transmission gate;

[0008] A source follower gate is located on the substrate;

[0009] A source-follower source region and a source-follower drain region are respectively located in the substrate on both sides of the source-follower gate;

[0010] A MOM capacitor is located on a side of the transmission gate and the source-follower gate away from the substrate, and the floating diffusion region and the source-follower-source region are electrically connected through the MOM capacitor.

[0011] Optionally, the image sensor according to claim 1 is characterized in that the MOM capacitor includes a first metal part and a second metal part, and the first metal part and the second metal part constitute a same-layer interdigital structure.

[0012] Optionally, the first metal portion is electrically connected to the floating diffusion region via a first electrical connection, and the second metal portion is electrically connected to the source-follower-source region via a second electrical connection.

[0013] Optionally, the floating diffusion region includes a first P-type doping region and a first N-type doping region, the first N-type doping region is located on the surface of the first P-type doping region, and the first metal part is electrically connected to the first N-type doping region through the first electrical connector.

[0014] Optionally, it further includes an interlayer dielectric layer and a first oxide layer, wherein the interlayer dielectric layer covers the substrate, the transfer gate and the source follower gate, and the surface of the interlayer dielectric layer is flat, and the first oxide layer is located on the interlayer dielectric layer.

[0015] Optionally, the first metal portion and the second metal portion are located in the first oxide layer, and the first oxide layer between the first metal portion and the second metal portion serves as an oxide of the MOM capacitor.

[0016] Optionally, the first metal portion and the second metal portion penetrate the first oxide layer along a thickness direction of the first oxide layer.

[0017] Optionally, a photodiode is also included, wherein the photodiode and the floating diffusion region are respectively located in the substrate on both sides of the transmission gate, and the photodiode includes a second P-type doping region and a second N-type doping region that are in contact with each other, and the second N-type doping region is located above the second P-type doping region.

[0018] Optionally, a third P-type doping region is further included, and the source-follow-source region and the source-follow-drain region are located on the surface of the third P-type doping region.

[0019] Optionally, a trench isolation structure is further included, located in the substrate to isolate the floating diffusion region and the third P-type doping region.

[0020] The image sensor provided by the present invention includes: a substrate; a transmission gate located on the substrate, and a floating diffusion region located in the substrate on one side of the transmission gate; a source-follower gate located on the substrate, and a source-follower source region and a source-follower drain region located in the substrate on both sides of the source-follower gate; a MOM capacitor located on a side of the transmission gate and the source-follower gate away from the substrate, and the floating diffusion region and the source-follower source region are electrically connected via the MOM capacitor. In the present invention, by inserting the MOM capacitor between the floating diffusion region and the source-follower source region, the parasitic capacitance of the floating diffusion region can be reduced, the charge conversion gain of the floating diffusion region can be increased, and the device signal-to-noise ratio can be improved, thereby improving the read noise reduction capability of the image sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A partial three-dimensional schematic diagram of an image sensor provided by an embodiment of the present invention.

[0022] Figure 2 A partial cross-sectional schematic diagram of an image sensor provided by one embodiment of the present invention.

[0023] Figure 3 A schematic diagram of the structure of a MOM capacitor in an image sensor provided by one embodiment of the present invention.

[0024] Figure 4 A circuit diagram of an image sensor provided according to an embodiment of the present invention.

[0025] Wherein, the accompanying drawings are marked as follows:

[0026] 10-substrate; 12-trench isolation structure; 20-floating diffusion region; 21-first P-type doping region; 22-first N-type doping region; 31-second P-type doping region; 32-second N-type doping region; 33-pinning layer; 41-third P-type doping region; 42-third N-type doping region; 43-fourth N-type doping region; 50-second oxide layer; 61-transmission gate; 62-source follower gate; 63-sidewall; 71-first electrical connection; 72-second electrical connection; 80-MOM capacitor; 81-first metal portion; 82-second metal portion; 83-first oxide layer; 90-interlayer dielectric layer. DETAILED DESCRIPTION

[0027] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.

[0028] As used in the present invention, the singular forms "a", "an", and "the" include plural objects, the term "or" is generally used to include the meaning of "and / or", the term "several" is generally used to include the meaning of "at least one", and the term "at least two" is generally used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features specified as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0029] Figure 1This is a partial three-dimensional schematic diagram of the image sensor provided in this embodiment. Figure 2 This is a partial cross-sectional schematic diagram of the image sensor provided in this embodiment, wherein Figure 2 for Figure 1 The cross-sectional diagram along the section line A1A2 is shown in the figure. Figure 1 In order to clearly illustrate the connection relationship between the MOM capacitor, the floating diffusion region and the source follower source region, Figure 1 The interlayer dielectric layer and the first oxide layer are not shown in FIG. Figure 2 Indicated in the middle.

[0030] Please refer to Figure 1 and Figure 2 This embodiment provides an image sensor including a substrate 10, a transfer gate 61, a floating diffusion region 20, a source-follower gate 62, a source-follower source region 32, a source-follower drain region 33, a metal-oxide-metal (MOM) capacitor 80, and a photodiode. Substrate 10 may be, but is not limited to, a silicon substrate, a gallium arsenide substrate, a germanium substrate, a silicon-germanium substrate, or a fully depleted silicon-on-insulator substrate. The transfer gate 61 is located on the substrate 10, and the floating diffusion region 20 and the photodiode are respectively located in the substrate 10 on both sides of the transfer gate 61; wherein, the floating diffusion region 20 includes a first P-type doping region 21 and a first N-type doping region 22, and the first N-type doping region 22 is located on the surface of the first P-type doping region 21, that is, the depth of the first P-type doping region 21 is greater than the depth of the first N-type doping region 22; the photodiode includes a second P-type doping region 31 and a second N-type doping region 32 in contact with each other, and the second N-type doping region 32 is located above the second P-type doping region 31, and there is a distance between the second P-type doping region 31 and the first P-type doping region 21, and the second N-type doping region 32 can have a distance between it and the first P-type doping region 21 (as shown in the figure), or the second N-type doping region 32 can be in contact with the first P-type doping region 21, and a pinning layer 33 is formed on the surface of the second N-type doping region 32. The transfer transistor includes a transfer gate 61 , a transfer drain region and a transfer source region. The first N-type doping region 22 serves as the transfer drain region, and the second N-type doping region 32 serves as the transfer source region.

[0031] The source-follower transistor includes a source-follower gate 62, a source-follower source region, and a source-follower drain region. The source-follower gate 62 is located on a substrate 10. The source-follower source region and the source-follower drain region are respectively located in the substrate 10 on both sides of the source-follower gate 62. A third P-type doping region 41 is formed in the substrate 10. A third N-type doping region 42 and a fourth N-type doping region 43 are formed on the surface of the third P-type doping region 41. That is, the depth of the third P-type doping region 41 is greater than the depths of the third N-type doping region 42 and the fourth N-type doping region 43. The third N-type doping region 42 serves as a source-follower source region, and the fourth N-type doping region 43 serves as a source-follower drain region. The third N-type doping region 42 and the fourth N-type doping region 43 are located in the substrate 10 on both sides of the source-follower gate 62. A trench isolation structure 12 is formed between the first P-type doping region 21 and the third P-type doping region 41 to isolate the first P-type doping region 21 from the third P-type doping region 41. Sidewall spacers 63 are formed on sidewalls of the transfer gate 61 and the source follower gate 62 . A second oxide layer 50 is formed on the substrate 10 . The transfer gate 61 , the source follower gate 62 and the sidewall spacers 63 are all located on the second oxide layer 50 .

[0032] The MOM capacitor 80 is located on a side of the transmission gate 61 and the source follower gate 62 away from the substrate 10 (located above the transmission gate 61 and the source follower gate 62 in the figure), and the floating diffusion region 20 and the source follower source region (the third N-type doped region 42) are electrically connected through the MOM capacitor 80. In the present embodiment, an interlayer dielectric layer 90 and a first oxide layer 83 are also included. The interlayer dielectric layer 90 covers the substrate 10, the transmission gate 61 and the source follower gate 62, and the surface of the interlayer dielectric layer 90 is flat. The first oxide layer 83 is located on the interlayer dielectric layer 90. The MOM capacitor 80 is located in the first oxide layer 83. The MOM capacitor 80 is electrically connected to the floating diffusion region 20 and the source follower source region (the third N-type doped region 42) through an electrical connector provided. The material of the interlayer dielectric layer 90 can be silicon nitride, and the material of the first oxide layer 83 can be silicon oxide.

[0033] Figure 3 This is a schematic diagram of the structure of the MOM capacitor in the image sensor provided in this embodiment. Figure 3 The MOM capacitor includes a first metal portion 81 and a second metal portion 82. The first metal portion 81 and the second metal portion 82 are located in the first oxide layer 83. The first metal portion 81 and the second metal portion 82 are finger-shaped, and the first metal portion 81 and the second metal portion 82 constitute a same-layer interdigitated structure. The first metal portion 81 and the second metal portion 82 are metal wires. The first metal portion 81 and the second metal portion 82 penetrate the first oxide layer 83 along the thickness direction of the first oxide layer 83 (such as Figure 2 The first metal portion 81 shown penetrates the first oxide layer 83 , and the first oxide layer 83 between the first metal portion 81 and the second metal portion 82 serves as the oxide of the MOM capacitor 80 .

[0034] Please continue to refer to Figure 1 , the first metal portion 81 is electrically connected to the first N-type doping region 22 through the first electrical connection 71, so as to realize the electrical connection between the MOM capacitor 80 and the floating doping region 20; the second metal portion 82 is electrically connected to the source-following source region (the third N-type doping region 42) through the second electrical connection 72, so as to realize the electrical connection between the MOM capacitor 80 and the source-following source region; wherein the first electrical connection 71 penetrates the interlayer dielectric layer 90 and the second oxide layer 50 and contacts the first N-type doping region 22, and the second electrical connection 72 penetrates the interlayer dielectric layer 90 and the second oxide layer 50 and contacts the source-following source region ( Figure 1 3D schematic diagram, which does not clearly illustrate the second electrical connection 72 and the source-follow-source region contact. In fact, the second electrical connection 72 penetrates the second oxide layer 50 and contacts the source-follow-source region).

[0035] In this embodiment, the image sensor further includes a reset transistor and a selection transistor, which are not shown in the drawings.

[0036] Figure 4 This is the circuit diagram of the image sensor provided in this embodiment. Please refer to Figure 4 , Figure 4 The figure illustrates the connection relationship between the photodiode PD, transfer transistor TX, reset transistor RST, source follower transistor SF, selection transistor RS, floating diffusion area FD and MOM capacitor. The transfer transistor TX is connected between the photodiode PD and the floating diffusion area FD, and the transfer transistor TX controls the transmission of electrons in the photodiode PD to the floating diffusion area FD; the reset transistor RST is connected between the floating diffusion area FD and the voltage source VDD, and the reset transistor RST controls the read reset of the image sensor; the source follower transistor SF and the selection transistor RS are connected in series between the voltage source VDD and the output terminal Output, controlling the selection output of the electrical signal in the voltage source VDD, and the gate of the source follower transistor SF is connected to the floating diffusion area FD; the MOM capacitor is connected between the floating diffusion area FD and the source area of ​​the source follower transistor SF, which can reduce the parasitic capacitance of the floating diffusion area FD, increase the charge conversion gain of the floating diffusion area FD, and improve the device signal-to-noise ratio, thereby improving the read noise reduction capability of the image sensor.

[0037] In summary, the image sensor provided by the present invention includes: a substrate; a transmission gate located on the substrate, and a floating diffusion region located in the substrate on one side of the transmission gate; a source follower gate located on the substrate, and a source follower source region and a source follower drain region respectively located in the substrate on both sides of the source follower gate; a MOM capacitor located on a side of the transmission gate and the source follower gate away from the substrate, and the floating diffusion region and the source follower source region are electrically connected via the MOM capacitor. In the present invention, by inserting a MOM capacitor between the floating diffusion region and the source follower source region, the parasitic capacitance of the floating diffusion region can be reduced, the charge conversion gain of the floating diffusion region can be increased, and the device signal-to-noise ratio can be improved, thereby improving the read noise reduction capability of the image sensor.

[0038] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other changes to the technical solution and technical content disclosed in the present invention shall be deemed to be within the scope of the present invention and still fall within the scope of protection of the present invention.

Claims

1. An image sensor, characterized in that: include: substrate; a transmission gate located on the substrate; a floating diffusion region located in the substrate on one side of the transmission gate; A source follower gate is located on the substrate; A source-follower source region and a source-follower drain region are respectively located in the substrate on both sides of the source-follower gate; A MOM capacitor is located on a side of the transmission gate and the source-follower gate away from the substrate, and the floating diffusion region and the source-follower-source region are electrically connected through the MOM capacitor.

2. The image sensor according to claim 1, wherein The MOM capacitor includes a first metal portion and a second metal portion, wherein the first metal portion and the second metal portion form a same-layer interdigital structure.

3. The image sensor according to claim 2, wherein: The first metal portion is electrically connected to the floating diffusion region via a first electrical connection, and the second metal portion is electrically connected to the source-follower-source region via a second electrical connection.

4. The image sensor according to claim 3, wherein The floating diffusion region includes a first P-type doping region and a first N-type doping region, the first N-type doping region is located on the surface of the first P-type doping region, and the first metal portion is electrically connected to the first N-type doping region through the first electrical connector.

5. The image sensor according to claim 2, wherein: It also includes an interlayer dielectric layer and a first oxide layer, the interlayer dielectric layer covers the substrate, the transfer gate and the source follower gate, and the surface of the interlayer dielectric layer is flat, and the first oxide layer is located on the interlayer dielectric layer.

6. The image sensor according to claim 5, wherein: The first metal portion and the second metal portion are located in the first oxide layer, and the first oxide layer between the first metal portion and the second metal portion serves as an oxide of the MOM capacitor.

7. The image sensor according to claim 6, wherein: The first metal portion and the second metal portion penetrate the first oxide layer along a thickness direction of the first oxide layer.

8. The image sensor according to claim 1, wherein It also includes a photodiode, wherein the photodiode and the floating diffusion region are respectively located in the substrate on both sides of the transmission gate, and the photodiode includes a second P-type doping region and a second N-type doping region in contact with each other, and the second N-type doping region is located above the second P-type doping region.

9. The image sensor according to claim 1, wherein It also includes a third P-type doping region, and the source-follow-source region and the source-follow-drain region are located on the surface of the third P-type doping region.

10. The image sensor according to claim 9, wherein A trench isolation structure is also included, which is located in the substrate to isolate the floating diffusion region and the third P-type doping region.

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