Low-noise reference circuit based on Zener diode

Abstract

The invention relates to a low-noise reference circuit based on a Zener diode, which is composed of a PTAT current generating circuit, a CTAT current generating circuit and a temperature coefficient eliminating circuit, the Zener diode adopts built-in bias current, in the circuit, positive temperature characteristics and negative temperature characteristics of different components are fully utilized to offset each other, and in the circuit, the positive temperature characteristic and the negative temperature characteristic of the CTAT current generating circuit are utilized to offset each other; and secondly, a negative feedback circuit is designed to correct the working state of the Zener diode in real time, and it is ensured that the Zener diode works in a linear state and operates stably. And low-temperature drift, high-linearity and high-precision output of the circuit is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, in particular to a low-noise reference circuit based on a Zener diode. Technical Background

[0002] The process innovation of Zener diodes makes the output voltage noise of Zener diodes in the reverse breakdown region lower and less susceptible to package stress, which has obvious advantages in indicators such as thermal hysteresis and long-term drift. However, the bias current of Zener diodes is easily affected by temperature, resulting in a positive correlation between the voltage of the Zener diode and temperature. The bias current that changes with temperature will cause the voltage in the reverse breakdown region of the Zener diode to change nonlinearly with temperature. This nonlinear change ultimately leads to a decrease in output accuracy and an increase in noise in the reference power supply circuit. Simple voltage-stabilizing circuits based on Zener diodes are difficult to meet the requirements of increasingly high-precision and advanced control circuits. To ensure that the Zener diode operates in a linear state and operates stably in the reverse breakdown region, a low-noise reference circuit based on a Zener diode is proposed. It is composed of a PTAT current generating circuit, a CTAT current generating circuit, and a temperature coefficient elimination circuit. The Zener diode adopts a built-in bias current. The circuit fully utilizes the positive and negative temperature characteristics of different components to offset each other, so that the overall circuit has a zero temperature coefficient characteristic. At the same time, a negative feedback circuit is designed to correct the working state of the Zener diode in real time, ensuring that the Zener diode operates in a linear state and operates stably. Summary of the Invention

[0003] The purpose of the present invention is to solve the technical problems such as poor linearity, high output noise, and poor temperature drift characteristics that exist in actual use of power supply circuits using Zener diodes.

[0004] The technical solution adopted in the present invention is as follows:

[0005] A low-noise reference circuit based on a Zener diode of the present invention comprises a PTAT current generating circuit, a CTAT current generating circuit and a temperature coefficient elimination circuit.

[0006] (1) The PTAT current generating circuit includes: PMOS tubes MP1, MP2, MP3, MP4, NMOS tubes MN1, MN2, MN3, PNP transistors Q1, Q2, Q3, Q4 and resistors R1, R2, R3; it is used to provide a driving signal with a negative temperature coefficient characteristic for the temperature coefficient elimination circuit; at the same time, the circuit has a negative feedback function, which monitors the output state of the temperature coefficient elimination circuit in real time, adjusts the driving current in real time after feedback, and suppresses the nonlinear change of the output.

[0007] (2), the CTAT current generating circuit comprises: PMOS MP7, MP8, MP11, MP12, NMOS MN5, PNP transistor Q5, and resistor R4; the circuit receives the driving signal of the PTAT current generating circuit, utilizes the negative temperature coefficient characteristic between the base and the emitter of the transistor, provides a bias current with a negative temperature coefficient to the Zener diode in the temperature coefficient eliminating circuit, so that the working current of the Zener diode has zero temperature coefficient.

[0008] (3), the temperature coefficient eliminating circuit comprises: PMOS MP5, MP6, MP9, MP10, Zener diode D1, D2, resistor R5, R6, R7, and capacitor C1; the circuit receives the driving signal of the PTAT current generating circuit after amplification, the current flowing through the resistor R5 has a positive temperature coefficient, simultaneously provides another positive temperature coefficient bias current for the Zener diode, and the node B voltage generates the output voltage Vout after being divided by R6, R7.

[0009] On the basis of the above technical scheme, there are the following further technical schemes:

[0010] (1) The PTAT current generating circuit is composed of PMOS tubes MP1, MP2, MP3, MP4, NMOS tubes MN1, MN2, MN3, PNP transistors Q1, Q2, Q3, Q4 and resistors R1, R2, R3; the source of the PMOS tube MP3 is connected to the input power supply VDD, the gate of MP3 is connected to the drain of MP3, the source of MP4, the drain of MP5 and the drain of MP7; the source of the PMOS tube MP4 is connected to the gate of MP3 and the drain of MP3, the gate of MP4 is connected to the drain of MP4, the gate of MP6, the gate of MP8 and the drain of the NMOS tube MN3; the gate of the NMOS tube MN3 is connected to the drain of the PMOS tube MP2 and the collector of the transistor Q2, the source of the NMOS tube MN3 is connected to one end of the resistor R3 and the base of the transistor Q2; the source of the PMOS tube MP1 is connected to the source of MP2 and the reference node B (the other end of the resistor R5 and one end of the resistor R6) ); the gate of the PMOS transistor MP1 is connected to the gate of MP2; the drain of the PMOS transistor MP1 is connected to the collector of the transistor Q1; the drain of the PMOS transistor MP2 is connected to the collector of the transistor Q2 and the gate of the NMOS transistor MN3; one end of the resistor R3 is connected to the source of the NMOS transistor MN3 and the base of the transistor Q2, and the other end of the resistor R3 is connected to the drain of the NMOS transistor MN1, the gate of MN1, the gate of MN2, and the base of the transistor Q1; the emitter of the transistor Q1 is connected to the emitter of Q2 and the drain of the NMOS transistor; the source of the NMOS transistor MN1 is connected to the collector of the transistor Q3, the base of Q3, and the base of Q4; the source of the NMOS transistor MN2 is connected to the collector of the transistor Q4; the emitter of the transistor Q3 is connected to one end of the resistor R1; the other end of the resistor R1 is connected to the input power supply 0V; the emitter of the transistor Q4 is connected to one end of the resistor R2; and the other end of the resistor R2 is connected to the power supply 0V.

[0011] (2) The CTAT current generating circuit is composed of PMOS tubes MP7, MP8, MP11, MP12, NMOS tube MN5, PNP transistor Q5 and resistor R4; the source of PMOS tube MP7 is connected with input power supply VDD, the gate of MP7 is connected with the gate of temperature coefficient eliminating circuit MP5 and the gate of PTAT current generating circuit MP3, the drain of MP7 is connected with the source of MP8; the gate of MP8 is connected with the gate of temperature coefficient eliminating circuit MP6, the gate of PTAT current generating circuit MP4, the drain of MP4 and the drain of MN3, the drain of MP8 is connected with the collector of transistor Q5 and the gate of MN4; the base of transistor Q5 is connected with the source of MN4 and one end of resistor R4, the emitter of transistor Q5 is connected with input power supply 0V; the source of PMOS tube MP11 is connected with input power supply VDD, the gate of MP11 is connected with the drain of MP11, the source of MP12 and the gate of temperature coefficient eliminating circuit MP9; the source of MP12 is connected with the drain of MP11, the gate of MP11 and the gate of temperature coefficient eliminating circuit MP9, the gate of MP12 is connected with the drain of MP12, the drain of MN4 and the gate of temperature coefficient eliminating circuit MP10, the gate of MN4 is connected with the collector of transistor Q5 and the drain of MP8; the source of MN4 is connected with the base of transistor Q5 and the other end of resistor R4; the other end of resistor R4 is connected with power supply 0V.

[0012] (3) The temperature coefficient elimination circuit is composed of PMOS tubes MP5, MP6, MP9, MP10, Zener diodes D1, D2, resistors R5, R6, R7, and capacitor C1; the source of the PMOS tube MP5 is connected to the input voltage VDD, the gate of MP5 is connected to the gate of the CTAT current generating circuit MP7, the gate of the PTAT current generating circuit MP3, the drain of MP3, and the source of MP4, and the drain of MP5 is connected to the source of MP6; the gate of MP6 is connected to the gate of the CTAT current generating circuit MP8, the gate of the PTAT current generating circuit MP4, the drain of MM3, and the source of MP4; the drain of MP6 is connected to one end of the resistor R5, the cathode of the Zener diode D1, and the drain of MP10; the other end of the resistor R5 (reference node B) is connected to one end of the resistor R6, The source of the PTAT current generating circuit MP1 and the source of MP2 are connected; the other end of the resistor R6 (output end Vout) is connected to one end of the resistor R7 and one end of the capacitor C1; the other end of R7 and the other end of the capacitor C1 are connected to the input voltage 0V; the cathode of the Zener diode D1 is connected to the drain of MP6, one end of the resistor R5, and the drain of MP10; the anode of the Zener diode D1 is connected to the cathode of D2, and the anode of D2 is connected to the input power supply 0V; the source of MP9 is connected to the input voltage VDD, the gate of MP9 is connected to the gate of the CTAT current generating circuit MP11, the drain of MP11, and the source of MP12, the drain of MP9 is connected to the source of MP10, and the gate of MP10 is connected to the gate of the CTAT current generating circuit MP12, the drain of MP12, and the drain of MN4.

[0013] The present invention's PTAT current generation circuit, CTAT current generation circuit, and temperature coefficient cancellation circuit constitute a low-noise Zener diode-based reference circuit. The Zener diode utilizes a built-in bias current. The circuit fully utilizes the positive and negative temperature characteristics of different components to offset each other, achieving a zero temperature coefficient for the overall circuit. A negative feedback circuit simultaneously corrects the Zener diode's operating state in real time, ensuring linear and stable operation. This circuit achieves the design requirements of high precision, low temperature drift, low noise, and high linearity. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 FIG2 is a schematic diagram of a low-noise reference circuit based on a Zener diode according to the present invention;

[0015] Figure 2 Shown is the simulation result of the output voltage changing with temperature according to the present invention;

[0016] Figure 3 Shown are the output noise simulation results of the present invention.

[0017] Specific implementation:

[0018] The present invention provides a low noise reference circuit based on a Zener diode, the principle diagram of which is shown in FIG. Figure 1 As shown, it includes a PTAT current generating circuit, a CTAT current generating circuit, and a temperature coefficient elimination circuit.

[0019] (1) Schematic diagram as follows Figure 1 As shown, the PTAT current generating circuit includes: PMOS transistors MP1, MP2, MP3, MP4, NMOS transistors MN1, MN2, MN3, PNP transistors Q1, Q2, Q3, Q4 and resistors R1, R2, R3; it is used to provide a drive signal with a negative temperature coefficient characteristic for the temperature coefficient cancellation circuit; at the same time, the circuit has a negative feedback function, which monitors the output state of the temperature coefficient cancellation circuit in real time, adjusts the drive current in real time after feedback, and suppresses nonlinear changes in the output. The specific structure is as follows: the source of the PMOS tube MP3 is connected to the input power supply VDD, the gate of MP3 is connected to the drain of MP3, the source of MP4, the drain of MP5, and the drain of MP7; the source of the PMOS tube MP4 is connected to the gate of MP3 and the drain of MP3, the gate of MP4 is connected to the drain of MP4, the gate of MP6, the gate of MP8, and the drain of the NMOS tube MN3; the gate of the NMOS tube MN3 is connected to the drain of the PMOS tube MP2 and the collector of the transistor Q2, the source of the NMOS tube MN3 is connected to one end of the resistor R3 and the base of the transistor Q2; the source of the PMOS tube MP1 is connected to the source of MP2 and the reference node B (the other end of the resistor R5 and one end of the resistor R6); the gate of the PMOS tube MP1 is connected to the gate of MP2; the drain of the PMOS tube MP1 is connected to the transistor Q 1 collector; the drain of the PMOS transistor MP2 is connected to the collector of the transistor Q2 and the gate of the NMOS transistor MN3; one end of the resistor R3 is connected to the source of the NMOS transistor MN3 and the base of the transistor Q2, and the other end of the resistor R3 is connected to the drain of the NMOS transistor MN1, the gate of MN1, the gate of MN2, and the base of the transistor Q1; the emitter of the transistor Q1 is connected to the emitter of Q2 and the drain of the NMOS transistor; the source of the NMOS transistor MN1 is connected to the collector of the transistor Q3, the base of Q3, and the base of Q4; the source of the NMOS transistor MN2 is connected to the collector of the transistor Q4; the emitter of the transistor Q3 is connected to one end of the resistor R1; the other end of the resistor R1 is connected to the input power supply 0V; the emitter of the transistor Q4 is connected to one end of the resistor R2; the other end of the resistor R2 is connected to the power supply 0V.

[0020] (2) Schematic diagram as follows Figure 1As shown, the CTAT current generating circuit includes: PMOS transistors MP7, MP8, MP11, MP12, NMOS transistor MN5, PNP transistor Q5, and resistor R4. The circuit receives a drive signal from the PTAT current generating circuit and, utilizing the negative temperature coefficient characteristic between the transistor base and emitter, provides a bias current with a negative temperature coefficient to the Zener diode in the temperature coefficient cancellation circuit, thereby offsetting the positive temperature coefficient characteristic of the Zener diode. The specific structure is as follows: the source of the PMOS transistor MP7 is connected to the input power supply VDD, the gate of MP7 is connected to the gate of the temperature coefficient cancellation circuit MP5 and the gate of the PTAT current generating circuit MP3, and the drain of MP7 is connected to the source of MP8; the gate of MP8 is connected to the gate of the temperature coefficient cancellation circuit MP6, the gate of the PTAT current generating circuit MP4, the drain of MP4, and the drain of MN3; the drain of MP8 is connected to the collector of transistor Q5 and the gate of MN4; the base of transistor Q5 is connected to the source of MN4 and one end of resistor R4, and the emitter of transistor Q5 is connected to the input power supply 0V. The source of the PMOS transistor MP11 is connected to the input power supply VDD, the gate of MP11 is connected to the drain of MP11, the source of MP12, and the gate of the temperature coefficient cancellation circuit MP9; the source of MP12 is connected to the drain of MP11, the gate of MP11, and the gate of the temperature coefficient cancellation circuit MP9; the gate of MP12 is connected to the drain of MP12, the drain of MN4, and the gate of the temperature coefficient cancellation circuit MP10; the gate of MN4 is connected to the collector of the transistor Q5 and the drain of MP8; the source of MN4 is connected to the base of the transistor Q5 and one end of the resistor R4; the other end of the resistor R4 is connected to the power supply 0V.

[0021] (3) Schematic diagram as follows Figure 1As shown, the temperature coefficient elimination circuit includes: PMOS tubes MP5, MP6, MP9, MP10, Zener diodes D1, D2, resistors R5, R6, R7, and capacitor C1; the circuit receives the driving signal amplified by the PTAT current generating circuit, to provide another bias current for the Zener diode, the cathode voltage of the Zener diode has a positive temperature coefficient, the current flowing through the resistor R5 has a positive temperature coefficient, the node B voltage is zero temperature coefficient, the node B voltage is divided by R6, R7 to generate an output voltage Vout. The specific structure is as follows: the source electrode of the PMOS tube MP5 is connected with the input voltage VDD, the gate electrode of the MP5 is connected with the gate electrode of the CTAT current generating circuit MP7, the gate electrode of the PTAT current generating circuit MP3, the drain electrode of the MP3, and the source electrode of the MP4, the drain electrode of the MP5 is connected with the source electrode of the MP6; the gate electrode of the MP6 is connected with the gate electrode of the CTAT current generating circuit MP8, the gate electrode of the PTAT current generating circuit MP4, the drain electrode of the MP3, and the source electrode of the MP4; the drain electrode of the MP6 is connected with one end of the resistor R5, the cathode of the Zener diode D1, and the drain electrode of the MP10; the other end of the resistor R5 (reference node B) is connected with one end of the resistor R6, the source electrode of the PTAT current generating circuit MP1, and the source electrode of the MP2; the other end of the resistor R6 (output terminal Vout) is connected with one end of the resistor R7 and one end of the capacitor C1; the other end of the resistor R7 and the other end of the capacitor C1 are connected with the input voltage 0V; the cathode of the Zener diode D1 is connected with the drain electrode of the MP6, one end of the resistor R5, and the drain electrode of the MP10; the anode of the Zener diode D1 is connected with the cathode of the D2, and the anode of the D2 is connected with the input power 0V; the source electrode of the MP9 is connected with the input voltage VDD, the gate electrode of the MP9 is connected with the gate electrode of the CTAT current generating circuit MP11, the drain electrode of the MP11, and the source electrode of the MP12, the drain electrode of the MP9 is connected with the source electrode of the MP10, and the gate electrode of the MP10 is connected with the gate electrode of the CTAT current generating circuit MP12, the drain electrode of the MP12, and the drain electrode of the MN4.

[0022] 7. Design calculation

[0023] In the working temperature range, the base to emitter voltage of the transistor is negative temperature coefficient, and when the two transistors work at different current densities, the difference between the base to emitter voltages is proportional to the absolute temperature. The amplifier composed of the NMOS tubes MP1, MP2 and the transistors Q1, Q2 works in negative feedback, and the node A is virtual ground, and is the base to emitter voltage of the PNP transistor Q1, Q2, and the asymmetry of Q1 and Q2 makes and not equal, and the voltage difference across the resistor R3 is , and the PTAT current generated by the PTAT current generating circuit is :

[0024]

[0025] Wherein:

[0026]

[0027] Wherein k is Boltzmann constant, q is the charge of an electron, N is the ratio of Q1 and Q2 collector area.

[0028] Q3, MN1, R1 and Q4, MN2, R2 constitute a current mirror, The above amplifier is a tail current source, Q4, MN2 proportional to the PTAT current to get the current :

[0029]

[0030] MP3, MP4 proportional to the PTAT current on MP1, MP2, get the current :

[0031]

[0032] From the base to the emitter voltage V BE5 And the resistance R4 generates a current :

[0033]

[0034] MP9, MP10 and MP11, MP12 constitute a current mirror:

[0035]

[0036] The current flowing through the resistance R6, R7 :

[0037]

[0038] The current flowing through the resistance R5 The sum of the current flowing to the amplifier tail current and the current flowing to the resistance R6, R7:

[0039]

[0040] Zener diode D1, D2 works in the reverse breakdown region, the current :

[0041]

[0042] The temperature coefficient of the current Term can be ignored, The positive and negative temperature coefficients of the current can be achieved by adjusting R3, R4, and adjusting the P in the current mirror proportional coefficient of MP3, MP4 and MP1, MP2. The temperature coefficient can determine the Zener diode operating voltage V Z The relationship with temperature is V Z (T), without additional current bias circuit, the node B voltage is obtained :

[0043]

[0044] V OUT It is the output voltage with zero temperature coefficient. V can be ignored when taking the derivative with respect to temperature T. OUT Item, V B Taking the derivative with respect to temperature T, we get:

[0045]

[0046] By adjusting the current mirror multiple M and the resistance value of resistor R5, the zero temperature coefficient voltage V B , V B After resistor voltage division, output V OUT , resistor R7 in parallel with capacitor C1 reduces output noise, and low noise output can be achieved without external capacitors.

[0047] 8. Beneficial effects

[0048] (1) The present invention solves the technical problems of poor temperature drift characteristics and low linearity of Zener diodes during operation.

[0049] (2) The temperature coefficient elimination circuit uses a self-biased reference current to provide bias current for the Zener diode. The positive and negative temperature coefficients cancel each other out, making the circuit have a zero temperature coefficient characteristic. The negative feedback loop in the circuit monitors the output power drift in real time and corrects the working state of the Zener diode in real time. Figure 2 Figure 3 As shown, compared with the reference voltage power supply, the present invention further improves the output accuracy of the Zener diode reference circuit, reduces the output noise, and the bias current with zero temperature coefficient minimizes the nonlinearity of the Zener diode voltage changing with temperature.

[0050] (3) The use of self-biased reference current technology reduces design complexity, modular manufacturing cost and debugging cost. At the same time, the use of self-biased reference current makes the circuit more reliable.

Claims

1. A low-noise reference circuit based on a Zener diode, comprising a PTAT current generating circuit, a CTAT current generating circuit, and a temperature coefficient cancellation circuit, characterized in that: (1) The PTAT current generating circuit includes: PMOS tubes MP1, MP2, MP3, MP4, NMOS tubes MN1, MN2, MN3, PNP transistors Q1, Q2, Q3, Q4 and resistors R1, R2, R3; it provides driving signals for the temperature coefficient elimination circuit and the CTAT current generating circuit; at the same time, the circuit has a negative feedback function, which monitors the output state of the temperature coefficient elimination circuit in real time and suppresses the nonlinear change of the output; (2) The CTAT current generating circuit includes: PMOS transistors MP7, MP8, MP11, MP12, NMOS transistor MN4, PNP transistor Q5, and resistor R4; the circuit receives the driving signal of the PTAT current generating circuit, and uses the negative temperature coefficient characteristic between the base and emitter of the transistor to provide a bias current with a negative temperature coefficient to the Zener diode in the temperature coefficient elimination circuit, thereby offsetting the positive temperature coefficient characteristic of the Zener diode; (3) The temperature coefficient elimination circuit includes: PMOS tubes MP5, MP6, MP9, MP10, Zener diodes D1, D2, resistors R5, R6, R7, and capacitor C1; after receiving the driving signal of the PTAT current generating circuit and amplifying it, the circuit provides a bias current for the Zener diode. At the same time, the CTAT current generating circuit generates another bias current with negative temperature characteristics. The cathode voltage of the Zener diode is divided by R5, R6, and R7 to generate the output voltage Vout.

2. The low-noise reference circuit based on a Zener diode according to claim 1, characterized in that: The PTAT current generating circuit includes: PMOS transistors MP1, MP2, MP3, MP4, NMOS transistors MN1, MN2, MN3, PNP transistors Q1, Q2, Q3, Q4 and resistors R1, R2, R3; the source of the PMOS transistor MP3 is connected to the input power supply VDD, the gate of MP3 is connected to the drain of MP3 and the source of MP4; the gate of the PMOS transistor MP4 is connected to the drain of MP4 and the drain of the NMOS transistor MN3; the gate of the NMOS transistor MN3 is connected to the drain of the PMOS transistor MP2 and the collector of the transistor Q2, the source of the NMOS transistor MN3 is connected to one end of the resistor R3 and the base of the transistor Q2; the source of the PMOS transistor MP1 is connected to the source of MP2 as a reference node B, the gate of the PMOS transistor MP1 is connected to the gate of MP2; the drain of the PMOS transistor MP1 is connected to the gate of Connected to the collector of transistor Q1; the drain of PMOS transistor MP2 is connected to the collector of transistor Q2 and the gate of NMOS transistor MN3; one end of resistor R3 is connected to the source of NMOS transistor MN3 and the base of transistor Q2, and the other end of resistor R3 is connected to the drain of NMOS transistor MN1, the gate of MN1, the gate of MN2, and the base of transistor Q1; the emitter of transistor Q1 is connected to the emitter of Q2 and the drain of NMOS transistor MN2; the source of NMOS transistor MN1 is connected to the collector of transistor Q3, the base of Q3, and the base of Q4; the source of NMOS transistor MN2 is connected to the collector of transistor Q4; the emitter of transistor Q3 is connected to one end of resistor R1, and the other end of resistor R1 is connected to the input power supply 0V; the emitter of transistor Q4 is connected to one end of resistor R2; the other end of resistor R2 is connected to the power supply 0V.

3. The low-noise reference circuit based on a Zener diode according to claim 1, wherein: The CTAT current generating circuit is composed of PMOS tubes MP7, MP8, MP11, MP12, NMOS tube MN4, PNP transistor Q5, and resistor R4; the source of PMOS tube MP7 is connected to the input power supply VDD, the gate of MP7 is connected to the gate of temperature coefficient elimination circuit MP5 and the gate of PTAT current generating circuit MP3, and the drain of MP7 is connected to the source of MP8; the gate of MP8 is connected to the gate of temperature coefficient elimination circuit MP6 and the gate of PTAT current generating circuit MP4, and the drain of MP8 is connected to the collector of transistor Q5 and the gate of MN4; the base of transistor Q5 is connected to the source of MN4 and one end of resistor R4 The emitter of transistor Q5 is connected to the input power supply 0V; the source of PMOS tube MP11 is connected to the input power supply VDD, the gate of MP11 is connected to the drain of MP11, the source of MP12, and the gate of temperature coefficient elimination circuit MP9; the source of MP12 is connected to the drain of MP11, the gate of MP11, and the gate of temperature coefficient elimination circuit MP9, the gate of MP12 is connected to the drain of MP12, the drain of MN4, and the gate of temperature coefficient elimination circuit MP10, the gate of MN4 is connected to the collector of transistor Q5 and the drain of MP8; the source of MN4 is connected to the base of transistor Q5 and one end of resistor R4; the other end of resistor R4 is connected to the power supply 0V.

4. The low-noise reference circuit based on a Zener diode according to claim 1, wherein: The temperature coefficient elimination circuit is composed of PMOS tubes MP5, MP6, MP9, MP10, Zener diodes D1, D2, adjustable resistors R5, R6, R7, and capacitor C1; the source of the PMOS tube MP5 is connected to the input voltage VDD, the gate of MP5 is connected to the gate of the CTAT current generating circuit MP7 and the gate of the PTAT current generating circuit MP3, and the drain of MP5 is connected to the source of MP6; the gate of MP6 is connected to the gate of the CTAT current generating circuit MP8 and the gate of the PTAT current generating circuit MP4; the drain of MP6 is connected to one end of the resistor R5, the cathode of the Zener diode D1, and the drain of MP10; the other end of the resistor R5 is connected to one end of the resistor R6, the source of the PTAT current generating circuit MP1, and the source of MP2; the other end of the resistor R6 is connected as the output end Vout to one end of the resistor R7 and one end of the capacitor C1; the other end of R7 and the other end of the capacitor C1 are connected to the input voltage 0V The anode of the Zener diode D1 is connected to the cathode of D2, and the anode of D2 is connected to the input power supply 0V; the source of MP9 is connected to the input voltage VDD, the gate of MP9 is connected to the gate of the CTAT current generating circuit MP11, the drain of MP9 is connected to the source of MP10, and the gate of MP10 is connected to the gate of the CTAT current generating circuit MP12; in the temperature coefficient elimination circuit, the PMOS tubes MP5 and MP6 receive the driving signal from the PTAT current generating circuit, and generate a Zener diode bias current after amplification. This bias current has a negative temperature coefficient characteristic and is corrected by negative feedback. At the same time, the PMOS tubes MP9 and MP10 receive the driving signal from the CTAT current generating circuit, and generate another bias current after amplification. This bias current also has a negative temperature characteristic. The positive and negative temperature coefficients of these two currents cancel each other out, so that the static bias current of the Zener diode has a zero temperature coefficient, and the cathode voltage V Z The current flowing through resistor R5 is a positive temperature coefficient current. The two cancel each other out to make node B have a zero temperature coefficient. After the node B voltage is divided by resistors R6 and R7, the output voltage Vout is generated, achieving ultra-low temperature drift characteristics and very ideal linearity of the entire circuit, greatly reducing the circuit output noise.

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