Charge pump control circuit, chip and electronic equipment

Abstract

The invention provides a charge pump control circuit, a chip and electronic equipment, and relates to the technical field of power management chips, and the circuit comprises a voltage division circuit, a reference voltage generation circuit, a comparison circuit and a charge pump circuit. The voltage division circuit comprises an input end, a first control end and a second control end, the input end is used for accessing auxiliary voltage, the first control end is used for accessing charge pump voltage, and the second control end is used for accessing power supply voltage; the voltage division circuit generates divided voltage; the reference voltage generation circuit generates a first reference voltage and a second reference voltage. The comparison circuit compares the divided voltage with the first reference voltage and the second reference voltage to obtain corresponding control signals; the charge pump circuit boosts based on the power supply voltage according to the control signal to obtain a charge pump voltage. The current required by the voltage division circuit is provided through the auxiliary voltage, and the charge pump voltage is only used for providing the control voltage signal of the voltage division circuit, so that the current load of the charge pump voltage is reduced, and the power consumption is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of power management chips, and in particular to a charge pump control circuit, chip, and electronic equipment. Background Art

[0002] A charge pump (CP), also known as a switched capacitor voltage converter, is a high-efficiency converter that uses capacitor energy storage to convert DC voltage. It is widely used in fast charging applications for mobile devices such as mobile phones, tablets, and smart watches.

[0003] See also Figure 1 , Figure 1 A circuit topology diagram of a charge pump provided for related technology, such as Figure 1 As shown, the output voltage VCP_OUT is divided by the first voltage-dividing resistor R01 and the second voltage-dividing resistor R02 to obtain a first voltage Vdiv. The expression of the first voltage Vdiv is:

[0004] Wherein, r02 is the resistance value of the second voltage-dividing resistor R02, and r02 is the resistance value of the first voltage-dividing resistor R01.

[0005] The hysteresis comparator CMP0 compares the first voltage Vdiv with the first and second thresholds VREF1 and VREF2 to generate a comparison voltage VCOMP. The comparison voltage VCOMP controls the output of the selector MUX0. For example, when the comparison voltage VCOMP is low, the output of the selector MUX0 is the first threshold VREF1, meaning that the selector MUX0 selects the first threshold VREF1. When the comparison voltage VCOMP is high, the output of the selector MUX0 is the second threshold VREF2, meaning that the selector MUX0 selects the second threshold VREF2. The output of the hysteresis comparator CMP0 is electrically connected to the enable terminal EN0 of the charge pump CP0. When the comparison voltage VCOMP is high, the charge pump CP0 is enabled; when the comparison voltage VCOMP is low, the charge pump CP0 is disabled. The comparison voltage VCOMP controls the operating state of the charge pump CP0. The output voltage VCP_OUT of the charge pump CP0 is transmitted to the load, providing the required load current I_load.

[0006] First and second voltage-divider resistors R01 and R02 are electrically connected to the output of charge pump CP0. Current Idiv flowing through first and second voltage-divider resistors R01 and R02 is calculated as VCP_OUT / (r01+r02). This current causes the output voltage VCP_OUT of charge pump CP0 to decrease more rapidly, leading to more frequent on and off times for the charge pump. This increases the power consumption of the entire charge pump circuit. Reducing the power consumption of the entire charge pump circuit is a critical issue that needs to be addressed. Summary of the Invention

[0007] The present application provides a charge pump control circuit, a chip, and an electronic device to reduce the overall power consumption of the circuit.

[0008] In a first aspect, the present application provides a charge pump control circuit, the charge pump control circuit comprising: a voltage divider circuit, a reference voltage generating circuit, a comparison circuit, and a charge pump circuit; the voltage divider circuit and the reference voltage generating circuit are both electrically connected to the comparison circuit, and the charge pump circuit is electrically connected to the comparison circuit and the voltage divider circuit respectively;

[0009] The voltage divider circuit includes an input terminal, a first control terminal, and a second control terminal, wherein the input terminal is used to access an auxiliary voltage, the first control terminal is used to access a charge pump voltage, and the second control terminal is used to access a power supply voltage;

[0010] The voltage divider circuit is used to generate a divided voltage and transmit the divided voltage to the comparison circuit;

[0011] The reference voltage generating circuit is configured to generate a first reference voltage and a second reference voltage, and transmit the first reference voltage and the second reference voltage to the comparison circuit;

[0012] The comparison circuit is configured to compare the divided voltage with the first reference voltage and the second reference voltage respectively to obtain corresponding control signals, and transmit the control signals to the charge pump circuit;

[0013] The charge pump circuit is configured to boost the power supply voltage according to the control signal to obtain the charge pump voltage.

[0014] In one possible design, the voltage divider circuit further includes: a first transistor, a second transistor, a first resistor, and a second resistor;

[0015] The second end of the first transistor is electrically connected to the input end for receiving the auxiliary voltage, the control end of the first transistor is electrically connected to the first control end for receiving the charge pump voltage, and the first end of the first transistor is electrically connected to the first end of the first resistor;

[0016] The second end of the first resistor is electrically connected to the first end of the second transistor, the control end of the second transistor is electrically connected to the second control end, and is used to receive a power supply voltage; the second end of the second transistor is electrically connected to the first end of the second resistor and serves as an output end of the voltage divider circuit, and is used to output a divided voltage;

[0017] A second end of the second resistor is grounded.

[0018] In one possible design, the reference voltage generating circuit includes: a third transistor, a fourth transistor, a third resistor, and a fourth resistor;

[0019] The first end of the third transistor is electrically connected to the power supply voltage, and the second end of the third transistor is electrically connected to the control end of the third transistor, the second end of the fourth transistor, and the control end of the fourth transistor respectively;

[0020] The first end of the fourth transistor is electrically connected to the first end of the third resistor and serves as the first output end of the reference voltage generating circuit, for outputting the second reference voltage;

[0021] The second end of the third resistor is electrically connected to the first end of the fourth resistor and serves as a second output end of the reference voltage generating circuit, for outputting the first reference voltage;

[0022] A second end of the fourth resistor is grounded.

[0023] In one possible design, the comparison circuit includes: a multiplexer and a comparator;

[0024] The first input terminal of the multiplexer is used to access the second reference voltage, the second input terminal of the multiplexer is used to access the first reference voltage, and the output terminal of the multiplexer is electrically connected to the non-inverting input terminal of the comparator;

[0025] The inverting input terminal of the comparator is electrically connected to the output terminal of the voltage divider circuit for receiving the divided voltage;

[0026] The output end of the comparator is electrically connected to the control end of the multiplexer and serves as the output end of the comparison circuit for outputting the control signal.

[0027] In one possible design, the charge pump circuit includes: a charge pump and a load capacitor;

[0028] The enable terminal of the charge pump is used to receive the control signal, the clock signal terminal of the charge pump is used to receive the clock signal, and the output terminal of the charge pump is electrically connected to the first terminal of the load capacitor for outputting the charge pump voltage;

[0029] A second terminal of the load capacitor is grounded.

[0030] In one possible design, the first transistor is an N-type MOS transistor, and the second transistor is a P-type MOS transistor.

[0031] In a possible design, the third transistor is a P-type MOS transistor, and the fourth transistor is an N-type MOS transistor.

[0032] In one possible design, the charge pump voltage is equal to twice the power supply voltage.

[0033] In a second aspect, the present application provides a chip, comprising: the charge pump control circuit as described in the first aspect.

[0034] In a third aspect, the present application provides an electronic device, which includes: the chip as described in the second aspect above.

[0035] Beneficial effects of the embodiments of the present application:

[0036] In an embodiment of the present application, a voltage divider circuit generates a divided voltage, a reference voltage generating circuit generates a first reference voltage and a second reference voltage, and a comparison circuit compares the divided voltage with the first reference voltage and the second reference voltage, respectively, to obtain corresponding control signals. The control signals are used to control the operating state of the charge pump circuit, thereby boosting the power supply voltage to obtain the charge pump voltage. An auxiliary voltage AUX_CP generated by an auxiliary charge pump provides the current required by the voltage divider circuit. The charge pump voltage CP_OUT is only used to provide the control voltage signal for the voltage divider circuit. The required current is very small, resulting in extremely low loss of the charge pump voltage CP_OUT by the voltage divider circuit, reducing the current load of the charge pump voltage CP_OUT and, in turn, the rate of decrease of the charge pump voltage CP_OUT, significantly extending the time the charge pump is in the off state and reducing the power consumption of the entire charge pump circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0038] Figure 1 A circuit topology diagram of a charge pump provided for related technology;

[0039] Figure 2 A voltage waveform diagram provided for related technology;

[0040] Figure 3 A schematic diagram of the circuit structure of a charge pump control circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] In this application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a alone, b alone, or c alone can represent: a alone, b alone, c alone, a and b in combination, a and c in combination, b and c in combination, or a, b, and c in combination, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance.

[0042] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limiting the present application.

[0043] The terms "connected" and "connect" should be interpreted broadly. For example, "connected" or "connected" in a circuit structure can refer not only to a physical connection, but also to an electrical connection or a signal connection. For example, it can be a direct connection, i.e., a physical connection, or an indirect connection through at least one intermediate component, as long as the circuit is interconnected. It can also refer to internal connectivity between two components. Signal connection can refer not only to signal connection through circuits but also to signal connection through media, such as radio waves. Those skilled in the art will understand the specific meanings of the above terms in this application on a case-by-case basis.

[0044] See also Figure 1 , a charge pump circuit provided by the related art, when the circuit is working, the waveforms of the first threshold VREF1, the second threshold VREF2, the comparison voltage VCOMP and the output voltage VCP_OUT are shown in FIG. Figure 2 , Figure 2 is the waveform corresponding to the voltage of the key node mentioned above, such as Figure 2As shown, since the first threshold VREF1 and the second threshold VREF2 are the two threshold voltages of the hysteresis comparator CMP0, the hysteresis comparator CMP0 compares the first voltage Vdiv with the first threshold VREF1 and the second threshold VREF2. The output voltage VCP_OUT of the charge pump CP0 is a variable voltage, and the corresponding divided first voltage Vdiv is also a variable voltage. According to the expression of the first voltage Vdiv, the hysteresis comparator CMP0 compares the first voltage Vdiv with the first threshold VREF1 and the second threshold VREF2. This is equivalent to the hysteresis comparator CMP0 comparing the output voltage VCP_OUT with K times the first threshold VREF1 and K times the second threshold VREF2, where K = (r01 + r02) / r02, r02 is the resistance value of the second voltage divider resistor R02, and r01 is the resistance value of the first voltage divider resistor R01.

[0045] See also Figure 2 When the output voltage VCP_OUT is lower than K times the first threshold VREF1, at this time, since the output result of the selector MUX0 is the first threshold VREF1, the comparison voltage VCOMP is at a high level, the charge pump CP0 is enabled, and the output voltage VCP_OUT starts to increase; the output result of the selector MUX0 switches to the second threshold VREF2. When the output voltage VCP_OUT is higher than K times the second threshold VREF2, the comparison voltage VCOMP is at a low level, the charge pump CP0 is turned off, and the output voltage VCP_OUT starts to slowly decrease based on the loss of the load; the output result of the selector MUX0 switches to the first threshold VREF1 again. When the output voltage VCP_OUT is lower than K times the first threshold VREF1 again, the comparison voltage VCOMP is at a high level, the charge pump CP0 is enabled again, and the above operation is repeated.

[0046] See also Figure 1 and Figure 2 When the load current I_load is relatively low, the output voltage VCP_OUT decreases very slowly, the comparison voltage VCOMP remains low most of the time, and the charge pump CP0 remains off for a long time. The charge pump turns on only when the output voltage VCP_OUT is lower than VREF1*(r01+r02) / r02, and turns off when the output voltage VCP_OUT is higher than VREF2*(r01+r02) / r02. By intermittently enabling the charge pump, circuit power consumption can be reduced.

[0047] Also, see Figure 1The first voltage-dividing resistor R01 and the second voltage-dividing resistor R02 are electrically connected to the output end of the charge pump CP0, that is, the output voltage VCP_OUT is divided to obtain the first voltage Vdiv. The current consumed by the first voltage-dividing resistor R01 and the second voltage-dividing resistor R02 is Idiv=VCP_OUT / (r01+r02), where r02 is the resistance value of the second voltage-dividing resistor R02 and r01 is the resistance value of the first voltage-dividing resistor R01.

[0048] Due to the existence of this current, the output voltage VCP_OUT of the charge pump CP0 drops faster, causing the charge pump to be turned on and off more frequently, thereby increasing the power consumption of the entire charge pump circuit and causing the overall power consumption of the charge pump circuit provided by the related technology to be larger.

[0049] In order to further reduce the power consumption of the charge pump circuit as a whole, the present application provides a charge pump control circuit, see Figure 3 , Figure 3 A circuit structure diagram of a charge pump control circuit provided in an embodiment of the present application is shown in FIG. Figure 3 As shown, the charge pump control circuit 1000 may include: a voltage divider circuit 100, a reference voltage generating circuit 200, a comparison circuit 300 and a charge pump circuit 400; the voltage divider circuit 100 and the reference voltage generating circuit 200 are both electrically connected to the comparison circuit 300, and the charge pump circuit 400 is respectively electrically connected to the comparison circuit 300 and the voltage divider circuit 100.

[0050] The voltage divider circuit 100 includes an input terminal IN1, a first control terminal C1, and a second control terminal C2. The input terminal IN1 is used to access the auxiliary voltage AUX_CP, the first control terminal C1 is used to access the charge pump voltage CP_OUT, and the second control terminal C2 is used to access the power supply voltage VCC.

[0051] The voltage divider circuit 100 is used to generate a divided voltage VDIV and transmit the divided voltage VDIV to the comparison circuit 300 .

[0052] The reference voltage generating circuit 200 is configured to generate a first reference voltage VREFL and a second reference voltage VREFH, and transmit the first reference voltage VREFL and the second reference voltage VREFH to the comparing circuit 300 .

[0053] The comparison circuit 300 is used to compare the divided voltage VDIV with the first reference voltage VREFL and the second reference voltage VREFH respectively to obtain a corresponding control signal COMP_OUT, and transmit the control signal COMP_OUT to the charge pump circuit 400 .

[0054] The charge pump circuit 400 is configured to boost the power supply voltage VCC according to the control signal COMP_OUT to obtain a charge pump voltage CP_OUT.

[0055] The voltage divider circuit 100 in the embodiment of the present application may include an input terminal IN1, a first control terminal C1, and a second control terminal C2, wherein the input terminal IN1 is used to access the auxiliary voltage AUX_CP, the auxiliary voltage AUX_CP provides the current required by the voltage divider circuit 100, and the voltage value of the auxiliary voltage AUX_CP is close to the voltage value of the charge pump voltage CP_OUT. Preferably, the voltage value of the auxiliary voltage AUX_CP can be set to be equal to the voltage value of the charge pump voltage CP_OUT. When the voltage value of the auxiliary voltage AUX_CP is equal to the voltage value of the charge pump voltage CP_OUT, the control of the charge pump circuit by the voltage divider voltage VDIV can be more accurately achieved.

[0056] In actual project applications, an auxiliary charge pump can be used to provide the auxiliary voltage AUX_CP. Since the auxiliary voltage AUX_CP is used to generate the divided voltage VDIV in the voltage divider circuit, the current required by the auxiliary charge pump to provide the voltage divider circuit 100 is very small, and there is no high requirement for the accuracy of the auxiliary voltage AUX_CP provided by the auxiliary charge pump. Therefore, the operating frequency of the auxiliary charge pump can be set very low to reduce the dynamic power consumption of the auxiliary charge pump. The first control terminal C1 is used to connect to the charge pump voltage CP_OUT, and the second control terminal C2 is used to connect to the power supply voltage VCC to provide a control voltage signal for the voltage divider circuit.

[0057] Since the current required by the voltage divider circuit 100 is provided by the auxiliary voltage AUX_CP and is unrelated to the charge pump voltage CP_OUT, the voltage of the charge pump voltage CP_OUT output by the charge pump circuit 400 will not be consumed. The charge pump voltage CP_OUT is only used to provide a control voltage signal for the voltage divider circuit. The required current is very small, so that the loss of the charge pump voltage CP_OUT by the voltage divider circuit is extremely low, and the falling speed of the charge pump voltage CP_OUT is slower, and the proportion of time that the charge pump circuit 400 is in the on state is lower, that is, the dynamic power consumption is lower, thereby achieving the purpose of reducing the power consumption of the entire charge pump circuit.

[0058] Furthermore, the voltage divider circuit 100 transmits the generated divided voltage VDIV to the comparison circuit 300. The reference voltage generation circuit 200 also generates a first reference voltage VREFL and a second reference voltage VREFH and transmits them to the comparison circuit 300.

[0059] The comparison circuit 300 compares the divided voltage VDIV with the first reference voltage VREFL and the second reference voltage VREFH respectively, and obtains a corresponding control signal COMP_OUT according to the comparison result. The control signal COMP_OUT is transmitted to the charge pump circuit 400 to control the working state of the charge pump circuit 400.

[0060] Finally, the charge pump circuit 400 boosts the power supply voltage VCC according to the control signal COMP_OUT to obtain a charge pump voltage CP_OUT to provide the current required by the load.

[0061] In an embodiment of the present application, a voltage divider circuit generates a divided voltage, a reference voltage generating circuit generates a first reference voltage and a second reference voltage, and a comparison circuit compares the divided voltage with the first reference voltage and the second reference voltage, respectively, to obtain corresponding control signals. The control signals are used to control the operating state of the charge pump circuit, thereby boosting the power supply voltage to obtain the charge pump voltage. An auxiliary voltage AUX_CP generated by an auxiliary charge pump provides the current required by the voltage divider circuit. The charge pump voltage CP_OUT is only used to provide the control voltage signal for the voltage divider circuit. The required current is very small, resulting in extremely low loss of the charge pump voltage CP_OUT by the voltage divider circuit. This, in turn, results in a slower decrease in the charge pump voltage CP_OUT, a lower proportion of the time the charge pump circuit is in the on state, and thus lower dynamic power consumption, thereby reducing the power consumption of the entire charge pump circuit.

[0062] In one possible embodiment, see Figure 3 The voltage divider circuit 100 further includes: a first transistor NM1, a second transistor PM1, a first resistor R1, and a second resistor R2.

[0063] The second end of the first transistor NM1 is electrically connected to the input end IN1 for receiving the auxiliary voltage AUX_CP. The control end of the first transistor NM1 is electrically connected to the first control end C1 for receiving the charge pump voltage CP_OUT. The first end of the first transistor NM1 is electrically connected to the first end of the first resistor R1.

[0064] The second end of the first resistor R1 is electrically connected to the first end of the second transistor PM1, and the control end of the second transistor PM1 is electrically connected to the second control end C2 for receiving the power supply voltage VCC. The second end of the second transistor PM1 is electrically connected to the first end of the second resistor R2 and serves as the output end of the voltage divider circuit 100 for outputting the divided voltage VDIV.

[0065] A second end of the second resistor R2 is grounded.

[0066] In the present application, the first transistor NM1 and the second transistor PM1 may be bipolar transistors or field-effect transistors, etc. For example, when the first transistor NM1 and the second transistor PM1 are bipolar transistors, their control terminals refer to the base of the bipolar transistor, the first terminals may be the collector or emitter of the bipolar transistor, and the corresponding second terminals may be the emitter or collector of the bipolar transistor; when the first transistor NM1 and the second transistor PM1 are field-effect transistors, their control terminals refer to the gate of the field-effect transistor, the first terminals may be the drain or source of the field-effect transistor, and the corresponding second terminals may be the source or drain of the field-effect transistor.

[0067] In one possible embodiment, see Figure 3 , the reference voltage generating circuit 200 may include: a third transistor PM2, a fourth transistor NM2, a third resistor R3 and a fourth resistor R4.

[0068] A first end of the third transistor PM2 is electrically connected to the power supply voltage VCC, and a second end of the third transistor PM2 is electrically connected to the control end of the third transistor PM2, the second end of the fourth transistor NM2, and the control end of the fourth transistor NM2 respectively.

[0069] A first end of the fourth transistor NM2 is electrically connected to a first end of the third resistor R3 and serves as a first output end of the reference voltage generating circuit 200 for outputting the second reference voltage VREFH.

[0070] The second end of the third resistor R3 is electrically connected to the first end of the fourth resistor R4 and serves as a second output end of the reference voltage generating circuit 200 for outputting the first reference voltage VREFL.

[0071] A second terminal of the fourth resistor R4 is grounded.

[0072] The third transistor PM2 and the fourth transistor NM2 in the present application may be bipolar transistors or field-effect transistors, etc. For example, when the third transistor PM2 and the fourth transistor NM2 are bipolar transistors, their control terminals refer to the base of the bipolar transistor, the first terminals may be the collector or emitter of the bipolar transistor, and the corresponding second terminals may be the emitter or collector of the bipolar transistor; when the third transistor PM2 and the fourth transistor NM2 are field-effect transistors, their control terminals refer to the gate of the field-effect transistor, the first terminals may be the drain or source of the field-effect transistor, and the corresponding second terminals may be the source or drain of the field-effect transistor.

[0073] In one possible embodiment, see Figure 3 , the comparison circuit 300 may include: a multiplexer MUX and a comparator CMP.

[0074] The first input terminal P1 of the multiplexer MUX is used to access the first reference voltage VREFL, the second input terminal P2 of the multiplexer MUX is used to access the second reference voltage VREFH, and the output terminal S2 of the multiplexer MUX is electrically connected to the non-inverting input terminal of the comparator CMP.

[0075] An inverting input terminal of the comparator CMP is electrically connected to an output terminal of the voltage divider circuit 100 for receiving the divided voltage VDIV.

[0076] The output terminal of the comparator CMP is electrically connected to the control terminal S1 of the multiplexer MUX and serves as the output terminal of the comparison circuit 300 for outputting the control signal COMP_OUT.

[0077] In the embodiment of the present application, the comparator CMP may be a hysteresis comparator, and the first reference voltage VREFL and the second reference voltage VREFH provide a threshold voltage of the hysteresis comparator.

[0078] The multiplexer MUX controls the selection path of the output terminal S2 based on the voltage signal input to the control terminal S1. For example, when the voltage signal input to the control terminal S1 of the multiplexer MUX is at a high level, the output terminal S2 selects the second input terminal P2 as the output path. That is, the multiplexer MUX selects the second reference voltage VREFH as the output result, thereby causing the comparator CMP to use the second reference voltage VREFH as the threshold voltage for comparison with the divided voltage VDIV. When the voltage signal input to the control terminal S1 of the multiplexer MUX is at a low level, the output terminal S2 selects the first input terminal P1 as the output path. That is, the multiplexer MUX selects the first reference voltage VREFL as the output result, thereby causing the comparator CMP to use the first reference voltage VREFL as the threshold voltage for comparison with the divided voltage VDIV.

[0079] The output end of the comparator CMP is electrically connected to the control end S1 of the multiplexer MUX. The output result of the comparator CMP (ie, the control signal COMP_OUT) is used as the control signal of the control end S1 of the multiplexer MUX. The gating path of the multiplexer MUX is controlled by the control signal COMP_OUT.

[0080] In one possible embodiment, see Figure 3 The charge pump circuit 400 includes a charge pump CP and a load capacitor CLOAD.

[0081] The enable terminal EN of the charge pump CP is used to access the control signal COMP_OUT, the clock signal terminal CK of the charge pump CP is used to access the clock signal CLK, and the output terminal OUT of the charge pump CP is electrically connected to the first end of the load capacitor CLOAD for outputting the charge pump voltage CP_OUT.

[0082] The second terminal of the load capacitor CLOAD is grounded.

[0083] Based on the above embodiments, it can be seen that the voltage divider circuit 100 , the reference voltage generating circuit 200 and the comparison circuit 300 constitute a control circuit for controlling the working state of the charge pump circuit 400 .

[0084] The charge pump circuit 400 in the present application can control itself to be in an on or off state according to the level state of the control signal COMP_OUT, and boost the power supply voltage under normal working conditions to obtain a charge pump voltage CP_OUT to power the load and provide the current ILOAD required by the load.

[0085] In a possible embodiment, the first transistor NM1 is an N-type MOS transistor, and the second transistor PM1 is a P-type MOS transistor.

[0086] When the first transistor NM1 is an N-type MOS transistor, the control end of the first transistor NM1 refers to the gate of the N-type MOS transistor, the first end of the first transistor NM1 is the source of the N-type MOS transistor, and the corresponding second end of the first transistor NM1 is the drain of the N-type MOS transistor.

[0087] When the second transistor PM1 is a P-type MOS transistor, the control end of the second transistor PM1 refers to the gate of the P-type MOS transistor, the first end of the second transistor PM1 is the source of the P-type MOS transistor, and the corresponding second end of the second transistor PM1 is the drain of the P-type MOS transistor.

[0088] In a possible embodiment, the third transistor PM2 is a P-type MOS transistor, and the fourth transistor NM2 is an N-type MOS transistor.

[0089] When the third transistor PM2 is a P-type MOS transistor, the control end of the third transistor PM2 refers to the gate of the P-type MOS transistor, the first end of the third transistor PM2 is the source of the P-type MOS transistor, and the corresponding second end of the third transistor PM2 is the drain of the P-type MOS transistor.

[0090] When the fourth transistor NM2 is an N-type MOS transistor, the control end of the fourth transistor NM2 refers to the gate of the N-type MOS transistor, the first end of the fourth transistor NM2 is the source of the N-type MOS transistor, and the corresponding second end of the fourth transistor NM2 is the drain of the N-type MOS transistor.

[0091] Based on all the above embodiments, see Figure 3For the charge pump control circuit in the embodiment of the present application, in the voltage divider circuit 100, since the control terminal of the first transistor NM1 is connected to the charge pump voltage CP_OUT, and the control terminal of the second transistor PM1 is connected to the power supply voltage VCC, the expression of the divided voltage VDIV can be obtained as follows:

[0092]

[0093] In formula (1), r1 is the resistance value of the first resistor R1, r2 is the resistance value of the second resistor R2, VGSn is the voltage difference between the gate and the source of the first transistor NM1 (i.e., the gate-source voltage of the first transistor NM1), and VGSp is the voltage difference between the gate and the source of the second transistor PM1 (i.e., the gate-source voltage of the second transistor PM1).

[0094] In the reference voltage generating circuit 200, the expression of the second reference voltage VREFH can be obtained as follows:

[0095] VREFH=VCC-VGSp-VGSn (2)

[0096] In formula (2), VGSp is the voltage difference between the gate and source of the third transistor PM2 (i.e., the gate-source voltage of the third transistor PM2), and VGSn is the voltage difference between the gate and source of the fourth transistor NM2 (i.e., the gate-source voltage of the fourth transistor NM2).

[0097] It is understood that in the embodiments of the present application, the gate-source voltages of the N-type MOS transistors are set to be equal, and the gate-source voltages of the P-type MOS transistors are also set to be equal. When the first transistor NM1 is an N-type MOS transistor, the second transistor PM1 is a P-type MOS transistor, the third transistor PM2 is a P-type MOS transistor, and the fourth transistor NM2 is an N-type MOS transistor, the gate-source voltage of the first transistor NM1 is set to be equal to the gate-source voltage of the fourth transistor NM2, and the gate-source voltage of the second transistor PM1 is set to be equal to the gate-source voltage of the third transistor PM2. Therefore, in both formulas (1) and (2), VGSn is used to represent the gate-source voltage of the N-type MOS transistor, and VGSp is used to represent the gate-source voltage of the P-type MOS transistor.

[0098] According to formula (1) and formula (2), when the resistance value of the first resistor R1 is equal to the resistance value of the second resistor R2, that is, r1=r2, and when the divided voltage VDIV is equal to the second reference voltage VREFH, the following expression can be obtained:

[0099] CP_OUT-VCC-VGSn-VGSp=VCC-VGSp-VGSn (3)

[0100] You can get:

[0101] CP_OUT=2*VCC (4)

[0102] In a possible embodiment, according to formula (4), the charge pump voltage CP_OUT may be equal to twice the power supply voltage VCC.

[0103] The charge pump control circuit in the present application can achieve the function of doubling the power supply voltage VCC. The charge pump circuit boosts the power supply voltage VCC according to the control signal COMP_OUT to obtain a charge pump voltage CP_OUT, wherein the charge pump voltage CP_OUT can be equal to twice the power supply voltage VCC. In addition, according to formulas (1) to (4), by adjusting the resistance value of the first resistor R1, the resistance value of the second resistor R2, and the topology of the reference voltage generation circuit, the charge pump voltage CP_OUT can be adjusted to be around twice the power supply voltage VCC.

[0104] In addition, the first reference voltage VREFL can be set according to design requirements. Usually, the first reference voltage VREFL can be set to be slightly lower than the second reference voltage VREFH.

[0105] The charge pump control circuit provided in the embodiment of the present application is compared with the charge pump circuit provided in the related art. Figure 1 and Figure 3 By comparison, it can be seen that the present application changes the sampling method of the output voltage of the charge pump in the related art, and optimizes the method of dividing the output voltage VCP_OUT by the first voltage-dividing resistor R01 and the second voltage-dividing resistor R02 in the related art to a method of controlling the gates of the first transistor NM1 and the second transistor PM1 respectively by the charge pump voltage CP_OUT and the power supply voltage VCC. The auxiliary voltage AUX_CP is also provided by the auxiliary charge pump to provide the required current for the voltage-dividing circuit 100. Since the charge pump voltage CP_OUT is only used to provide the control voltage signal of the voltage-dividing circuit, the required current is very small, so that the loss of the charge pump voltage CP_OUT by the voltage-dividing circuit is extremely low, reducing the current load of the charge pump voltage CP_OUT, and thereby reducing the falling speed of the charge pump voltage CP_OUT, greatly extending the time that the charge pump CP is in the off state, and reducing the power consumption of the entire charge pump circuit.

[0106] An embodiment of the present application further provides a chip, comprising: the charge pump control circuit as described above.

[0107] The chip may be a charge pump.

[0108] An embodiment of the present application also provides an electronic device, including: the chip as described above.

[0109] Electronic devices may include, but are not limited to: adapters, chargers, tablets, smart home devices, vehicles, and wearable devices.

[0110] Finally, it should be noted that the above embodiments are merely specific implementations of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A charge pump control circuit, characterized in that: The charge pump control circuit includes: a voltage divider circuit, a reference voltage generating circuit, a comparison circuit and a charge pump circuit; the voltage divider circuit and the reference voltage generating circuit are both electrically connected to the comparison circuit, and the charge pump circuit is electrically connected to the comparison circuit and the voltage divider circuit respectively; The voltage divider circuit includes an input terminal, a first control terminal, and a second control terminal, wherein the input terminal is used to access an auxiliary voltage, the first control terminal is used to access a charge pump voltage, and the second control terminal is used to access a power supply voltage; The voltage divider circuit is used to generate a divided voltage and transmit the divided voltage to the comparison circuit; The reference voltage generating circuit is configured to generate a first reference voltage and a second reference voltage, and transmit the first reference voltage and the second reference voltage to the comparison circuit; The comparison circuit is configured to compare the divided voltage with the first reference voltage and the second reference voltage respectively to obtain corresponding control signals, and transmit the control signals to the charge pump circuit; The charge pump circuit is configured to boost the power supply voltage according to the control signal to obtain the charge pump voltage.

2. The charge pump control circuit according to claim 1, wherein: The voltage divider circuit further includes: a first transistor, a second transistor, a first resistor and a second resistor; The second end of the first transistor is electrically connected to the input end for receiving the auxiliary voltage, the control end of the first transistor is electrically connected to the first control end for receiving the charge pump voltage, and the first end of the first transistor is electrically connected to the first end of the first resistor; The second end of the first resistor is electrically connected to the first end of the second transistor, the control end of the second transistor is electrically connected to the second control end, and is used to receive a power supply voltage; the second end of the second transistor is electrically connected to the first end of the second resistor and serves as an output end of the voltage divider circuit, and is used to output a divided voltage; A second end of the second resistor is grounded.

3. The charge pump control circuit according to claim 1, wherein: The reference voltage generating circuit includes: a third transistor, a fourth transistor, a third resistor and a fourth resistor; The first end of the third transistor is electrically connected to the power supply voltage, and the second end of the third transistor is electrically connected to the control end of the third transistor, the second end of the fourth transistor, and the control end of the fourth transistor respectively; The first end of the fourth transistor is electrically connected to the first end of the third resistor and serves as the first output end of the reference voltage generating circuit, for outputting the second reference voltage; The second end of the third resistor is electrically connected to the first end of the fourth resistor and serves as a second output end of the reference voltage generating circuit, for outputting the first reference voltage; A second end of the fourth resistor is grounded.

4. The charge pump control circuit according to claim 1, wherein: The comparison circuit includes: a multiplexer and a comparator; The first input terminal of the multiplexer is used to access the second reference voltage, the second input terminal of the multiplexer is used to access the first reference voltage, and the output terminal of the multiplexer is electrically connected to the non-inverting input terminal of the comparator; The inverting input terminal of the comparator is electrically connected to the output terminal of the voltage divider circuit for receiving the divided voltage; The output end of the comparator is electrically connected to the control end of the multiplexer and serves as the output end of the comparison circuit for outputting the control signal.

5. The charge pump control circuit according to claim 1, wherein: The charge pump circuit includes: a charge pump and a load capacitor; The enable terminal of the charge pump is used to receive the control signal, the clock signal terminal of the charge pump is used to receive the clock signal, and the output terminal of the charge pump is electrically connected to the first terminal of the load capacitor for outputting the charge pump voltage; The second end of the load capacitor is grounded.

6. The charge pump control circuit according to claim 2, wherein: The first transistor is an N-type MOS transistor, and the second transistor is a P-type MOS transistor.

7. The charge pump control circuit according to claim 3, wherein: The third transistor is a P-type MOS transistor, and the fourth transistor is an N-type MOS transistor.

8. The charge pump control circuit according to claim 1, wherein: The charge pump voltage is equal to twice the power supply voltage.

9. A chip, characterized in that: include: The charge pump control circuit according to any one of claims 1 to 8.

10. An electronic device, characterized in that: include: The chip as claimed in claim 9.

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