Impedance determination method and device, computer equipment, readable storage medium and program product

Abstract

The invention relates to an impedance determination method and device, computer equipment, a readable storage medium and a program product. The method comprises the steps that first eye diagrams of an on-chip terminal are acquired, and the first eye diagrams are eye diagrams of an electric signal under target equalizer parameter conditions corresponding to candidate impedance values of the on-chip terminal; each candidate impedance value corresponds to a target equalizer parameter; according to a first preset condition and the eye diagram parameters in the first eye diagrams, obtaining a target eye diagram from the first eye diagrams; wherein the first preset condition represents a screening condition related to the eye pattern parameter; and taking the candidate impedance value corresponding to the target eye diagram as a target impedance value. According to the method, the target impedance value is adopted to design the chip system, so that the performance of the chip is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of On-Die Termination (ODT), and particularly relates to an impedance determination method and device, a computer device, a computer readable storage medium and a computer program product. BACKGROUND

[0002] In a high-speed DDR (Double Data Rate) memory system, termination impedance is a key design parameter to ensure signal integrity. It is used to suppress signal reflection and ringing, thereby ensuring the stability of data in high-speed transmission. The data speed of the chip input / output interface (I / O) is accelerating with the increasing demand for chip computing power and the faster and faster operation of chip cores, which brings new challenges to high-speed chip design.

[0003] In the traditional technology, the ODT impedance value is matched by built-in calibration engines or external reference resistors.

[0004] However, the impedance determined by the traditional impedance matching method of the on-die termination cannot meet the performance requirements of the chip. SUMMARY

[0005] Therefore, it is necessary to provide an impedance determination method, device, computer device, computer readable storage medium and computer program product capable of improving the performance of a chip to solve the above technical problems.

[0006] In a first aspect, the present application provides an impedance determination method, which comprises:

[0007] obtaining each first eye diagram of an on-die termination, wherein the first eye diagram is an eye diagram of an electrical signal under the condition of each target equalizer parameter corresponding to each candidate impedance value of the on-die termination; each candidate impedance value corresponds to a target equalizer parameter;

[0008] obtaining a target eye diagram from each first eye diagram according to a first preset condition and an eye diagram parameter in each first eye diagram; wherein the first preset condition represents a screening condition related to the eye diagram parameter;

[0009] taking the candidate impedance value corresponding to the target eye diagram as a target impedance value.

[0010] In one of the embodiments, the obtaining each first eye diagram of the on-die termination comprises:

[0011] obtaining each candidate impedance value of the on-die termination, each candidate impedance value corresponding to different candidate equalizer parameters;

[0012] for each of the candidate impedance values, obtaining a second eye diagram of the electrical signal under different candidate equalizer parameters corresponding to the candidate impedance value;

[0013] for each of the candidate impedance values, obtaining a second eye diagram of the electrical signal under different candidate equalizer parameters corresponding to the candidate impedance value;

[0014] In one of the embodiments, the obtaining a second eye diagram of the electrical signal under different candidate equalizer parameters corresponding to the candidate impedance value comprises:

[0015] processing the electrical signal in a target time period through different candidate equalizer parameters corresponding to each of the candidate impedance values to obtain each single-bit impulse response curve;

[0016] determining each of the second eye diagrams according to each of the single-bit impulse response curves.

[0017] In one of the embodiments, the determining each of the second eye diagrams according to each of the single-bit impulse response curves comprises:

[0018] for each of the single-bit impulse response curves, analyzing the single-bit impulse response curve through a peak distortion analysis algorithm to obtain a second eye diagram under each of the candidate equalizer parameters corresponding to each of the candidate impedance values.

[0019] In one of the embodiments, the analyzing the single-bit impulse response curve through the peak distortion analysis algorithm to obtain a second eye diagram under each of the candidate equalizer parameters corresponding to each of the candidate impedance values comprises:

[0020] taking a voltage maximum value of the single-bit impulse response curve as a main tap, and obtaining a front tap and a rear tap of the main tap in the target time period;

[0021] respectively calculating an inter-symbol interference of the front tap and an inter-symbol interference of the rear tap; the inter-symbol interference includes a positive inter-symbol interference and a negative inter-symbol interference;

[0022] determining a lower boundary of the second eye diagram through the positive inter-symbol interference and the main tap, and determining an upper boundary of the second eye diagram through the negative inter-symbol interference and the main tap;

[0023] determining the second eye diagram according to the upper boundary and the lower boundary.

[0024] In one of the embodiments, the eye diagram parameter includes at least one of an eye width, an eye height, jitter, a bit error rate, power consumption, and a voltage level.

[0025] In a second aspect, the present application provides an impedance determination device, which comprises:

[0026] an acquisition module configured to acquire first eye diagrams of the on-chip terminal, wherein the first eye diagram is an eye diagram of an electrical signal under a condition of a target equalizer parameter corresponding to each candidate impedance value of the on-chip terminal; each candidate impedance value corresponds to a target equalizer parameter;

[0027] a target eye diagram determination module configured to acquire a target eye diagram from the first eye diagrams according to a first preset condition and an eye diagram parameter in the first eye diagrams; wherein the first preset condition represents a screening condition related to the eye diagram parameter;

[0028] a target impedance value determination module configured to determine the candidate impedance value corresponding to the target eye diagram as a target impedance value.

[0029] In a third aspect, the present application provides a computer device, which comprises a memory and a processor, the memory stores a computer program, and the processor implements the steps of the above method when executing the computer program.

[0030] In a fourth aspect, the present application provides a computer readable storage medium, which stores a computer program, and the computer program implements the steps of the above method when executed by a processor.

[0031] In a fifth aspect, the present application provides a computer program product, which comprises a computer program, and the computer program implements the steps of the above method when executed by a processor.

[0032] The impedance determination method, device, computer device, computer readable storage medium and computer program product can first acquire first eye diagrams of the on-chip terminal, wherein the first eye diagram is an eye diagram of the electrical signal under conditions of each candidate impedance value of the on-chip terminal corresponding to each target equalizer parameter; second, according to the first preset condition and the eye diagram parameters in the first eye diagrams, a target eye diagram is acquired from the first eye diagrams; the target equalizer parameter corresponding to the target eye diagram is obtained under the target equalizer parameter dimension; and finally, the candidate impedance value corresponding to the target eye diagram is taken as a target impedance value. That is, by screening the combination of the equalizer parameter and the impedance value of the ODT, a target impedance under a group of target equalizer parameters is obtained, which can compensate for channel loss through the target equalizer parameter, restore the electrical signal quality, eliminate the reflection noise of the electrical signal with restored quality through the target impedance value, and maximize the integrity of the electrical signal. Therefore, the chip system is designed according to the target impedance value that maximizes the integrity of the electrical signal, thereby improving the performance of the chip. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the drawings needed to be used in the description of the embodiments of the present application or the related art will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other related drawings can also be obtained without creative labor.

[0034] Figure 1 An application environment diagram of the impedance determination method in one embodiment;

[0035] Figure 2 A flowchart of the impedance determination method in one embodiment;

[0036] Figure 3 An eye diagram of the impedance value under the condition of a 2-inch transmission line channel attenuation in one embodiment;

[0037] Figure 4 An eye diagram of the impedance value under the condition of a 3-inch transmission line channel attenuation in one embodiment;

[0038] Figure 5 An eye diagram of the impedance value under the condition of a 4-inch transmission line channel attenuation in one embodiment;

[0039] Figure 6 An eye diagram of the impedance value under the condition of a 9-inch transmission line channel attenuation in one embodiment;

[0040] Figure 7Channel attenuation curves for different frequencies; a is the channel attenuation curve for 4dB @10GHz; b is the channel attenuation curve for 4.5dB @10GHz; c is the channel attenuation curve for 5.5dB @10GHz; d is the channel attenuation curve for 8dB @10GHz;

[0041] Figure 8 Power consumptions corresponding to different impedance values under different channel attenuation conditions; a is the power consumption corresponding to different impedance values under 4dB @10GHz condition; b is the power consumption corresponding to different impedance values under 4.5dB @10GHz condition; c is the power consumption corresponding to different impedance values under 5.5dB @10GHz condition; d is the power consumption corresponding to different impedance values under 8dB @10GHz condition;

[0042] Figure 9 Voltage levels corresponding to different impedance values under different channel attenuation conditions; a is the voltage level corresponding to different impedance values under 4dB @10GHz condition; b is the voltage level corresponding to different impedance values under 4.5dB @10GHz condition; c is the voltage level corresponding to different impedance values under 5.5dB @10GHz condition; d is the voltage level corresponding to different impedance values under 8dB @10GHz condition;

[0043] Figure 10 Eye widths corresponding to different impedance values under different channel attenuation conditions; a is the eye width corresponding to different impedance values under 4dB @10GHz condition; b is the eye width corresponding to different impedance values under 4.5dB @10GHz condition; c is the eye width corresponding to different impedance values under 5.5dB @10GHz condition; d is the eye width corresponding to different impedance values under 8dB @10GHz condition;

[0044] Figure 11 Eye heights corresponding to different impedance values under different channel attenuation conditions; a is the eye height corresponding to different impedance values under 4dB @10GHz condition; b is the eye height corresponding to different impedance values under 4.5dB @10GHz condition; c is the eye height corresponding to different impedance values under 5.5dB @10GHz condition; d is the eye height corresponding to different impedance values under 8dB @10GHz condition;

[0045] Figure 12 Flowchart for obtaining the first eye diagram of the on-chip termination in an embodiment;

[0046] Figure 13 Diagram of the single-bit impulse response curve in an embodiment;

[0047] Figure 14 Flowchart for obtaining the second eye diagram by the peak distortion analysis algorithm in an embodiment;

[0048] Figure 15 A schematic diagram of front-tap, main-tap, back-tap and inter-symbol interference in an embodiment;

[0049] Figure 16 A schematic diagram of the worst eye diagram in an embodiment;

[0050] Figure 17 A schematic diagram of the flow of the impedance determination method in another embodiment;

[0051] Figure 18 A block diagram of the structure of the impedance determination apparatus in an embodiment;

[0052] Figure 19 An internal structure diagram of the computer device in an embodiment. DETAILED DESCRIPTION

[0053] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0054] The impedance determination method provided by the embodiments of the present application can be applied in an application environment as shown in FIG. 1. Figure 1 The terminal 102 communicates with the server 104 through a network. The data storage system can store data required to be processed by the server 104. The data storage system can be integrated on the server 104, or placed on a cloud or other network server. The server 104 obtains each first eye diagram of the on-chip terminal sent by the terminal 102, wherein the first eye diagram is an eye diagram of the electrical signal under the condition of each target equalizer parameter corresponding to each candidate impedance value of the on-chip terminal; each candidate impedance value corresponds to a target equalizer parameter; a target eye diagram is obtained from each first eye diagram according to a first preset condition and an eye diagram parameter in each first eye diagram; the first preset condition represents a screening condition related to the eye diagram parameter; and a candidate impedance value corresponding to the target eye diagram is taken as a target impedance value. The terminal 102 can be, but is not limited to, various personal computers, notebook computers, smart phones, tablet computers, Internet of Things devices and portable wearable devices. The Internet of Things device can be a smart speaker, a smart television, a smart air conditioner, a smart vehicle-mounted device, a projection device, etc. The portable wearable device can be a smart watch, a smart bracelet, a head-mounted device, etc. The head-mounted device can be a virtual reality (VR) device, an augmented reality (AR) device, smart glasses, etc. The server 104 can be a standalone physical server, a server cluster or a distributed system composed of multiple physical servers, or a cloud server providing cloud computing services.

[0055] It should be noted that the first eye diagram of each on-die terminal can also be obtained by the terminal 102, and the target eye diagram is obtained from the first eye diagram according to the first preset condition and the eye diagram parameter in the first eye diagram; and the candidate impedance value corresponding to the target eye diagram is taken as the target impedance value.

[0056] In an exemplary embodiment, as shown in Figure 2 , an impedance determination method is provided, and the method is applied to the server 104 in Figure 1 for example, and includes the following steps S202 to S206. Among them:

[0057] In step S202, the first eye diagram of each on-die terminal is obtained; the first eye diagram is an eye diagram of an electrical signal under the condition of each target equalizer parameter corresponding to each candidate impedance value of the on-die terminal; and each candidate impedance value corresponds to a target equalizer parameter.

[0058] The on-die termination (ODT) is a terminal resistance technology integrated in the chip, which is used to match the characteristic impedance of the transmission line and suppress signal reflection. By connecting the on-die terminal with an impedance value such as 50Ω in the chip, the chip input impedance is matched with the transmission line impedance, the reflected energy is absorbed by the resistance, and the signal waveform is cleaner.

[0059] The eye diagram is a graph used to evaluate the quality of the electrical signal, and the first eye diagram is a graph used to evaluate the quality of the electrical signal under the condition of each target equalizer parameter corresponding to each candidate impedance value of the on-die terminal.

[0060] Exemplarily, before the server obtains the first eye diagram of each on-die terminal, the server needs to set the candidate impedance value of the ODT in advance, such as 10Ω, 20Ω, 30Ω, 40Ω, 50Ω, 60Ω and 70Ω, and each candidate impedance value corresponds to a target equalizer parameter, such as the target equalizer parameter EQ101 corresponding to the candidate impedance value 10Ω; the target equalizer parameter EQ202 corresponding to the candidate impedance value 20Ω; the target equalizer parameter EQ303 corresponding to the candidate impedance value 30Ω; the target equalizer parameter EQ404 corresponding to the candidate impedance value 40Ω; the target equalizer parameter EQ505 corresponding to the candidate impedance value 50Ω; the target equalizer parameter EQ606 corresponding to the candidate impedance value 60Ω; and the target equalizer parameter EQ707 corresponding to the candidate impedance value 70Ω. Among them, the target equalizer parameter refers to the equalizer configuration combination that can maximize the signal quality under a specific channel condition.

[0061] Furthermore, the server generates a first first eye diagram based on the electrical signal under the condition that the target equalizer parameter corresponding to the candidate impedance value is 10Ω is the equalizer parameter EQ101; the server generates a second first eye diagram based on the electrical signal under the condition that the target equalizer parameter corresponding to the candidate impedance value is 20Ω is the equalizer parameter EQ202; the server generates a third first eye diagram based on the electrical signal under the condition that the target equalizer parameter corresponding to the candidate impedance value is 30Ω is the equalizer parameter EQ303; the server generates a fourth first eye diagram based on the electrical signal under the condition that the target equalizer parameter corresponding to the candidate impedance value is 40Ω is the equalizer parameter EQ404; the server generates a fifth first eye diagram based on the electrical signal under the condition that the target equalizer parameter corresponding to the candidate impedance value is 50Ω is the equalizer parameter EQ505; the server generates a sixth first eye diagram based on the electrical signal under the condition that the target equalizer parameter corresponding to the candidate impedance value is 60Ω is the equalizer parameter EQ606; and the server generates a seventh first eye diagram based on the electrical signal under the condition that the target equalizer parameter corresponding to the candidate impedance value is 70Ω is the equalizer parameter EQ707.

[0062] For example, the impedance of the on-chip termination is a resistor network set at the end (or in the middle) of a signal transmission line by a DDR memory controller or DRAM chip to match the characteristic impedance of the transmission line. The server can simultaneously obtain seven first-eye diagrams for each target equalizer parameter condition corresponding to each candidate impedance value (10Ω, 20Ω, 30Ω, 40Ω, 50Ω, 60Ω, and 70Ω) for the on-chip termination; the seven first-eye diagrams can also be obtained sequentially in the order in which the first-eye diagrams were generated. Electrical signals are transmitted through different transmission lines, such as a 2-inch transmission line (2in-channel), a 3-inch transmission line (3in-channel), a 4-inch transmission line (4in-channel), and a 9-inch transmission line (9in-channel). The attenuation of a 2-inch transmission line at 10GHz is 4dB; the attenuation of a 3-inch transmission line at 10GHz is 4.5dB; the attenuation of a 4-inch transmission line at 10GHz is 5.5dB; and the attenuation of a 9-inch transmission line at 10GHz is 8dB. GHz is the unit of frequency, and dB is the decibel value, which indicates the attenuation value of the channel.

[0063] like Figure 3 As shown in FIG, the electrical signal is transmitted through a 2-inch transmission line (2in-channel), and seven first-eye diagrams of the target equalizer parameter conditions corresponding to the candidate impedance values ​​of 10Ω, 20Ω, 30Ω, 40Ω, 50Ω, 60Ω, and 70Ω are shown; Figure 4As shown, the electrical signal is transmitted in a 3-inch transmission line (3in-channel), and seven eye diagrams are obtained under the conditions of the target equalizer parameters corresponding to the candidate impedance values 10Ω, 20Ω, 30Ω, 40Ω, 50Ω, 60Ω and 70Ω, respectively, as shown in Figure 5 As shown, the electrical signal is transmitted in a 4-inch transmission line (4in-channel), and seven eye diagrams are obtained under the conditions of the target equalizer parameters corresponding to the candidate impedance values 10Ω, 20Ω, 30Ω, 40Ω, 50Ω, 60Ω and 70Ω, respectively, as shown in Figure 6 As shown, the electrical signal is transmitted in a 9-inch transmission line (9in-channel), and seven eye diagrams are obtained under the conditions of the target equalizer parameters corresponding to the candidate impedance values 10Ω, 20Ω, 30Ω, 40Ω, 50Ω, 60Ω and 70Ω, respectively.

[0064] Exemplarily, the server obtains seven eye diagrams of the electrical signal transmitted in a 2-inch transmission line (2in-channel) under the conditions of the target equalizer parameters corresponding to the candidate impedance values 10Ω, 20Ω, 30Ω, 40Ω, 50Ω, 60Ω and 70Ω, i.e., as shown in Figure 3 The server obtains seven eye diagrams of the electrical signal transmitted in a 3-inch transmission line (3in-channel) under the conditions of the target equalizer parameters corresponding to the candidate impedance values 10Ω, 20Ω, 30Ω, 40Ω, 50Ω, 60Ω and 70Ω, i.e., as shown in Figure 4 The server can also obtain seven eye diagrams as shown in Figure 5 The server can also obtain seven eye diagrams as shown in Figure 6 The server can also obtain seven eye diagrams as shown in

[0065] As shown in a, b, c and d in Figure 7 represent the attenuation amplitude curves of the channels of the transmission lines with different lengths (2 inches, 3 inches, 4 inches and 9 inches, respectively) under the condition of 10 GHz.

[0066] It should be noted that the candidate impedance values of the ODT in the embodiment can be any impedance values conforming to the actual situation of the chip, and the number of the candidate impedance values is also not limited, but any number conforming to the actual situation of the chip, such as n, n being a positive integer.

[0067] In step S204, the target eye diagram is obtained from the first eye diagrams according to the first preset condition and the eye diagram parameters in the first eye diagrams.

[0068] The first preset condition represents a screening condition related to the eye diagram parameters.

[0069] For example, the server pre-configures screening conditions related to eye diagram parameters according to the instructions; eye diagram parameters may include eye width, eye height, eye crossing point, overshoot, undershoot, rise time, fall time, total jitter, eye opening determined by eye width and eye height, power consumption, and voltage level, etc. For example, the server pre-configures screening conditions related to eye diagram parameters according to the instructions, such as maximum eye height, maximum eye width, maximum eye width and maximum eye height, minimum power consumption under the premise of meeting the eye diagram quality threshold, minimum total jitter, and other eye diagram parameter conditions.

[0070] like Figure 8 Where a represents the power consumption at different impedance values ​​at 4dB@10GHz; b represents the power consumption at different impedance values ​​at 4.5dB@10GHz; c represents the power consumption at different impedance values ​​at 5.5dB@10GHz; and d represents the power consumption at different impedance values ​​at 8dB@10GHz.

[0071] like Figure 9 Where a represents the voltage level corresponding to different impedance values ​​under the condition of 4dB@10GHz; b represents the voltage level corresponding to different impedance values ​​under the condition of 4.5dB@10GHz; c represents the voltage level corresponding to different impedance values ​​under the condition of 5.5dB@10GHz; d represents the voltage level corresponding to different impedance values ​​under the condition of 8dB@10GHz.

[0072] like Figure 10 Where a represents the eye width corresponding to different impedance values ​​at 4 dB @ 10 GHz; b represents the eye width corresponding to different impedance values ​​at 4.5 dB @ 10 GHz; c represents the eye width corresponding to different impedance values ​​at 5.5 dB @ 10 GHz; and d represents the eye width corresponding to different impedance values ​​at 8 dB @ 10 GHz.

[0073] like Figure 11 In the figure, a represents the eye height corresponding to different impedance values ​​at 4 dB @ 10 GHz; b represents the eye height corresponding to different impedance values ​​at 4.5 dB @ 10 GHz; c represents the eye height corresponding to different impedance values ​​at 5.5 dB @ 10 GHz; and d represents the eye height corresponding to different impedance values ​​at 8 dB @ 10 GHz.

[0074] For example, the server obtains seven first-eye images of target equalizer parameter conditions corresponding to candidate impedance values ​​of 10Ω, 20Ω, 30Ω, 40Ω, 50Ω, 60Ω, and 70Ω, which are transmitted through a 2-inch transmission line (2in-channel). Figure 3 The channel attenuation curve is shown in the following figure. Figure 7 As shown in a, 2in-channel = 4dB@10GHz; the power consumption corresponding to the candidate impedance values ​​of 10Ω, 20Ω, 30Ω, 40Ω, 50Ω, 60Ω and 70Ω is as followsFigure 8 As shown in a of FIG. 10, the voltage levels corresponding to the candidate impedance values 10Ω, 20Ω, 30Ω, 40Ω, 50Ω, 60Ω and 70Ω are as shown in a of FIG. 10. Figure 9 As shown in a of FIG. 10, the eye widths corresponding to the candidate impedance values 10Ω, 20Ω, 30Ω, 40Ω, 50Ω, 60Ω and 70Ω are as shown in a of FIG. 10. Figure 10 As shown in a of FIG. 10, the eye heights corresponding to the candidate impedance values 10Ω, 20Ω, 30Ω, 40Ω, 50Ω, 60Ω and 70Ω are as shown in a of FIG. 10. Figure 11 As shown in a of FIG. 10, the first preset condition assumes the maximum eye height, and the first eye pattern with the maximum eye height is selected as the target eye pattern, as shown in a of FIG. 10. Figure 11 As shown in a of FIG. 10, the eye height corresponding to 50Ω is the maximum, and thus the first eye pattern corresponding to 50Ω is the target eye pattern.

[0075] Exemplarily, the server obtains the seven first eye patterns of the target equalizer parameter conditions corresponding to the candidate impedance values 10Ω, 20Ω, 30Ω, 40Ω, 50Ω, 60Ω and 70Ω through the transmission of the electrical signal in a 3in-channel, i.e., as shown in the seven first eye patterns of FIG. 11. Figure 4 As shown in a of FIG. 11, the channel attenuation curve is as shown in b of FIG. 11, and 3in-channel=4.5dB@10GHz. Figure 7 As shown in b of FIG. 11, the power consumptions corresponding to the candidate impedance values 10Ω, 20Ω, 30Ω, 40Ω, 50Ω, 60Ω and 70Ω are as shown in b of FIG. 11. Figure 8 As shown in b of FIG. 11, the voltage levels corresponding to the candidate impedance values 10Ω, 20Ω, 30Ω, 40Ω, 50Ω, 60Ω and 70Ω are as shown in b of FIG. 11. Figure 9 As shown in b of FIG. 11, the eye widths corresponding to the candidate impedance values 10Ω, 20Ω, 30Ω, 40Ω, 50Ω, 60Ω and 70Ω are as shown in b of FIG. 11. Figure 10 As shown in b of FIG. 11, the eye heights corresponding to the candidate impedance values 10Ω, 20Ω, 30Ω, 40Ω, 50Ω, 60Ω and 70Ω are as shown in b of FIG. 11. Figure 11 As shown in b of FIG. 11, if the first preset condition is that the eye pattern quality meets the quality threshold, the target impedance value is determined according to the minimum power consumption; if each first eye pattern meets the eye pattern quality threshold, the eye pattern with the minimum power consumption is selected as the target eye pattern, as shown in b of FIG. 11. Figure 8 As shown in b of FIG. 11, the power consumption corresponding to 70Ω is the minimum, and thus the first eye pattern corresponding to 70Ω is the target eye pattern.

[0076] It is worth noting that under different channel attenuations, the smaller the candidate impedance value, the greater the power consumption, the higher the voltage level, and the larger the eye width; but not the smaller the impedance value, the smaller the eye height, so when setting the first preset condition and the second preset condition, attention should be paid when setting the eye height, not the larger the candidate impedance value, the larger the eye height. As shown in a of FIG. 12. Figure 11a, b, c, the eye height increases as the candidate impedance value increases, but the eye height is the largest at 50 Ω, and decreases at 60 Ω and 70 Ω. As shown in FIG. 2, d, the eye height increases as the candidate impedance value increases, and reaches the maximum eye height at 30 Ω, and then gradually decreases as the candidate impedance value increases. Figure 11

[0077] Step S206, the candidate impedance value corresponding to the target eye diagram is taken as the target impedance value.

[0078] The target impedance value refers to a candidate impedance value that can enable the chip system to achieve minimum signal reflection and optimal signal integrity.

[0079] For example, the server obtains seven first eye diagrams corresponding to the target equalizer parameter conditions of the candidate impedance values 10 Ω, 20 Ω, 30 Ω, 40 Ω, 50 Ω, 60 Ω and 70 Ω when the electrical signal is transmitted in a 2-inch transmission line (2in-channel), i.e., the seven first eye diagrams as shown in FIG. 2. Figure 3 The server takes the first eye diagram corresponding to 50 Ω as the target eye diagram, and takes 50 Ω as the target impedance value.

[0080] For example, the server obtains seven first eye diagrams corresponding to the target equalizer parameter conditions of the candidate impedance values 10 Ω, 20 Ω, 30 Ω, 40 Ω, 50 Ω, 60 Ω and 70 Ω when the electrical signal is transmitted in a 3-inch transmission line (3in-channel), i.e., the seven first eye diagrams as shown in FIG. 3. Figure 4 The server takes the first eye diagram corresponding to 70 Ω as the target eye diagram, and takes 70 Ω as the target impedance value.

[0081] The determination process of the target eye diagram under the conditions of 4in-channel=5.5dB@10GHz and 9in-channel=8dB@10GHz is the same.

[0082] ​In the above impedance determination method, first, each first eye diagram of the on-chip terminal is acquired, wherein the first eye diagram is an eye diagram of the electrical signal under the condition of each candidate impedance value of the on-chip terminal corresponding to each target equalizer parameter; second, according to the first preset condition and the eye diagram parameters in each first eye diagram, a target eye diagram is acquired from each first eye diagram; the target eye diagram corresponding to the target equalizer parameter is obtained under the condition of the target equalizer parameter; and finally, the candidate impedance value corresponding to the target eye diagram is taken as a target impedance value, that is, through the screening of the combination of the equalizer parameter and the impedance value of the ODT, a target impedance under a group of target equalizer parameters is obtained, which can compensate for channel loss through the target equalizer parameter and restore the quality of the electrical signal; the reflection noise of the electrical signal with restored quality can also be eliminated through the target impedance value; the integrity of the electrical signal is maximally ensured; therefore, the chip system is designed according to the target impedance value that maximally ensures the integrity of the electrical signal, so as to improve the performance of the chip.

[0083] In one exemplary embodiment, as shown in Figure 12 each first eye diagram of the on-chip terminal is acquired, including steps S1202 to S1206. Among them:

[0084] Step S1202, each candidate impedance value of the on-chip terminal is acquired, and each candidate impedance value corresponds to different candidate equalizer parameters.

[0085] Exemplarily, each candidate impedance value corresponds to a different range of candidate equalizer parameters. The server acquires the candidate equalizer parameter EQ101 corresponding to the candidate impedance value 10Ω; the candidate equalizer parameter EQ102; the candidate equalizer parameter EQ103; acquires the candidate equalizer parameter EQ201 corresponding to the candidate impedance value 20Ω; the candidate equalizer parameter EQ202; the candidate equalizer parameter EQ203. For each candidate impedance value, the candidate impedance value 30Ω is acquired, wherein the candidate impedance value can also be 40Ω, 50Ω, 60Ω and 70Ω, and any other value, such as 45Ω, 90Ω, 100Ω, etc.

[0086] Step S1204, for each candidate impedance value, the second eye diagram of the electrical signal under the condition of different candidate equalizer parameters corresponding to the candidate impedance value is acquired.

[0087] Among them, the second eye diagram is an eye diagram generated by evaluating the quality of the electrical signal under the condition of each candidate equalizer parameter corresponding to each candidate impedance value of the on-chip terminal.

[0088] Exemplarily, the electrical signal is transmitted through a 9-foot transmission line, and for each candidate impedance value, the server obtains three second eye diagrams under the conditions of candidate equalizer parameters EQ101 corresponding to the candidate impedance value 10Ω, candidate equalizer parameters EQ102, and candidate equalizer parameters EQ103; the server obtains three second eye diagrams under the conditions of candidate equalizer parameters EQ201 corresponding to the candidate impedance value 20Ω, candidate equalizer parameters EQ202, and candidate equalizer parameters EQ203; and the eye diagrams under the conditions of candidate equalizer parameters corresponding to other candidate impedance values are obtained in the same manner. Taking an example of 3 candidate equalizer parameters corresponding to each candidate impedance value, the server obtains 21 second eye diagrams.

[0089] It should be noted that the number of candidate equalizer parameters corresponding to each candidate impedance value is not specifically limited, and the number of candidate equalizer parameters corresponding to each candidate impedance value can be the same or different, as long as it meets the actual situation. For example, x candidate equalizer parameters correspond to one candidate impedance value, and y candidate equalizer parameters correspond to another candidate impedance value, where x and y are positive integers, and x≠y.

[0090] In step S1206, for each second eye diagram corresponding to each candidate impedance value, a first eye diagram corresponding to each second eye diagram is obtained according to a second preset condition and the values of the second eye diagram parameters in each second eye diagram.

[0091] The second preset condition represents a screening condition related to the eye diagram parameters. The eye diagram parameters can also include inter-symbol interference in the eye diagram or maximum eye opening, etc. The second preset condition can be, for example, according to the inter-symbol interference in the eye diagram, or for example, according to the maximum eye opening, etc.

[0092] Exemplarily, for each candidate impedance value, for example, 3 second eye diagrams corresponding to 10Ω, a first eye diagram is obtained from the 3 second eye diagrams according to the second preset condition, for example, the maximum eye opening, and the second eye diagram parameters in the 3 second eye diagrams. The process of determining the first eye diagram from the second eye diagrams corresponding to other candidate impedance values is the same. The eye diagram parameters included in the first preset condition and the second preset condition can be the same or different.

[0093] In another embodiment, for each candidate impedance value, the coefficient initial value of the equalizer parameter is set, and the value of the coefficient is changed step by step until the preset condition is met, which is the target equalizer parameter. The server directly obtains the first eye diagram of each candidate impedance value under the condition of the respective target equalizer parameter.

[0094] In this embodiment, by selecting the first eye diagram under the condition of the best equalizer parameter corresponding to each candidate impedance value from the second eye diagrams of multiple candidate equalizer parameters corresponding to each candidate impedance value, it can be ensured that each first eye is in the dimension of the target equalizer parameter.

[0095] In an example embodiment, the acquiring the second eye diagram of the electrical signal under the different candidate equalizer parameter conditions corresponding to the candidate impedance values comprises: processing the electrical signal in the target time period by the different candidate equalizer parameters corresponding to each candidate impedance value to obtain each single-bit impulse response curve; and determining each second eye diagram according to the single-bit impulse response curves.

[0096] The target time period can be one time interval, denoted as 1UI (Unit Interval), or a plurality of time intervals. The single-bit impulse response curve is used to analyze the dynamic response characteristic curve of the circuit to a single binary signal transition (e.g., from 0 to 1 or from 1 to 0). By inputting a "step signal" (instantaneous transition), the change of the output signal over time is observed to reveal the behavior of the signal in the transmission process, such as only one binary signal 1 in a long sequence and the rest binary signals are 0; or only one binary signal 0 in a long sequence and the rest binary signals are 1.

[0097] For example, the server acquires an electrical signal in 1UI as a long sequence, such as 00000100000000000000, Figure 13 The single-bit impulse response curve output for the electrical signal as a long sequence. The server processes the long sequence 00000100000000000000 by the different candidate equalizer parameters corresponding to each candidate impedance value, such as filtering, to obtain each single-bit impulse response curve. The server determines the second eye diagram corresponding to each single-bit impulse response curve according to each acquired single-bit impulse response curve.

[0098] Further, if a candidate impedance value, such as 10Ω, corresponds to 3 candidate equalizer parameters, the long sequence in 1UI is processed by each candidate equalizer parameter to obtain 3 single-bit impulse response curves corresponding to the candidate impedance value 10Ω; and the second eye diagram corresponding to the candidate impedance value 10Ω is determined according to the 3 single-bit impulse response curves.

[0099] It should be noted that the second eye diagram corresponding to other candidate impedance values can be obtained in the same way.

[0100] In this embodiment, each second eye diagram is determined by each single-bit impulse response curve. The analysis time of the single-bit impulse response curve is much smaller than the analysis time of the data stream, so that the time in the second eye diagram generation process can be reduced.

[0101] In an exemplary embodiment, each second eye diagram is determined based on each single-bit impulse response curve, including: for each single-bit impulse response curve, the single-bit impulse response curve is analyzed by a peak distortion analysis algorithm to obtain a second eye diagram under each candidate equalizer parameter corresponding to each candidate impedance value.

[0102] Among them, Peak Distortion Analysis (PDA) is a deterministic analysis method used to evaluate the worst-case impact of inter-symbol interference (ISI) in digital communication systems. By calculating the maximum possible interference of adjacent symbols on the current symbol, it predicts the distortion limit of the signal at the receiving end, thereby generating an eye diagram reflecting system performance or evaluating signal integrity.

[0103] Exemplarily, for each single-bit impulse response curve, the server analyzes the single-bit impulse response curve through the PDA to obtain a second eye diagram under each candidate equalizer parameter corresponding to each candidate impedance value.

[0104] Exemplarily, the server may also analyze the single-bit impulse response curve by using a statistical eye diagram analysis method or a time domain simulation method to obtain a second eye diagram under each candidate equalizer parameter corresponding to each candidate impedance value.

[0105] In this embodiment, by calculating the worst-case scenario, the limits of signal distortion can be clearly displayed, forming a worst-case second eye diagram. The analog signal's performance under the most unfavorable combination of noise, jitter, and timing offset ensures that the chip design can still operate stably in extreme scenarios.

[0106] In an exemplary embodiment, Figure 14 As shown, the single-bit impulse response curve is analyzed by the peak distortion analysis algorithm to obtain the second eye diagram under each candidate equalizer parameter corresponding to each candidate impedance value, including steps S1402 to S1408.

[0107] Step S1402 : The voltage maximum value of the single-bit impulse response curve is used as a main tap, and a front tap and a rear tap of the main tap within a target time period are obtained.

[0108] Taps refer to weight coefficients in an equalizer or filter, which are used to weight and adjust the input electrical signal to compensate for channel distortion. Each tap corresponds to the response of the electrical signal at a specific time offset (such as the current symbol, the previous symbol, or the next symbol). In DDR memory interfaces, adjusting equalizer taps suppresses backscatter caused by reflections.

[0109] Main cursor refers to the response position of the current symbol in the equalizer, corresponding to the main peak of the channel impulse response. It is the amplitude value of the signal at the ideal sampling time (usually the center of the symbol), which directly affects the accuracy of the decision result.

[0110] As shown in FIG. 1, a single-bit pulse response curve is shown. The server obtains the voltage maximum value of the single-bit pulse response curve as the main cursor cursor, and obtains the front cursor precursor and the rear cursor postcursor of the main cursor cursor within 1UI. In the time axis order, the first point is the front cursor precursor; the 3rd-7th points are the rear cursor postcursor. Figure 15

[0111] Step S1404, the inter-symbol interference of the front cursor and the rear cursor is calculated respectively; the inter-symbol interference includes positive inter-symbol interference and negative inter-symbol interference.

[0112] The inter-symbol interference (ISI, Inter-Symbol Interference) is also called code interference. It refers to the phenomenon that, in the transmission process of a digital signal, due to the non-ideal channel characteristics (such as bandwidth limitation and multipath effect), the signal waveform of the current code is extended in the time domain, and overlaps with the adjacent codes, thereby interfering with the correct reception of the subsequent codes. The inter-symbol interference ISI includes positive inter-symbol interference ISI+ and negative inter-symbol interference ISI-.

[0113] As shown in FIG. 1, the server calculates the ISI+ and ISI- of the front cursor, and calculates the ISI+ and ISI- of the rear cursor. In the time axis order, the first point, i.e., the front cursor precursor, has positive inter-symbol interference ISI+; the third point, i.e., the rear cursor postcursor, has negative inter-symbol interference ISI-; the fourth point, i.e., the rear cursor postcursor, has positive inter-symbol interference ISI+; the fifth point, i.e., the rear cursor postcursor, has negative inter-symbol interference ISI-; the sixth point and the seventh point, i.e., the rear cursor postcursor, have positive inter-symbol interference ISI+. Figure 15

[0114] Step S1406, the lower boundary of the second eye diagram is determined by the positive inter-symbol interference and the main cursor, and the upper boundary of the second eye diagram is determined by the negative inter-symbol interference and the main cursor.

[0115] As shown in FIG. 1, the server sums and accumulates the positive inter-symbol interference ISI+ to obtain The negative inter-symbol interference ISI- is accumulated and summed to obtain ​​The server may first accumulate and sum the negative inter-symbol interference ISI- and then take the absolute value after the accumulation; or it may first take the absolute value of the negative inter-symbol interference ISI- and then accumulate it.

[0116] Further, if Figure 16 As shown, the upper and lower boundaries corresponding to the orange dotted lines are the upper and lower boundaries of the eye diagram corresponding to the main tap. The upper boundary of the eye diagram corresponding to the main tap cursor is recorded as worst_ed (1,:); the lower boundary of the corresponding eye diagram is recorded as worst_ed (2,:). Other marking forms can also be used, and the specific marking is not limited. The server uses the upper boundary of the main tap corresponding to worst_ed (1,:), and Add together to determine the upper boundary of the second eye diagram worst_ed (1,:) + ; through the lower boundary of the main tap corresponding to worst_ed(2,:), and Add together to determine the lower boundary of the second eye diagram worst_ed (2,:) + .

[0117] Exemplarily, the server sums and accumulates the positive intersymbol interference ISI+ and takes the absolute value to obtain | |;Sum and accumulate the negative inter-symbol interference ISI- and take the absolute value to get | |. The server can first perform the accumulation of inter-symbol interference and then take the absolute value; it can also take the absolute value of each inter-symbol interference and then accumulate it. The server obtains the upper and lower boundaries of the eye diagram corresponding to the main tap. The server compares the upper boundary corresponding to the main tap with | |Subtract and get the upper boundary of the second eye diagram. | add to determine the lower boundary of the second eye diagram. It should be noted that due to is always positive, so =| |.

[0118] Step S1408: Determine a second eye pattern according to the upper boundary and the lower boundary.

[0119] For example, the server calculates the upper boundary of the second eye diagram based on worst_ed(1,:)+ and the lower boundary of the second eye diagram worst_ed(2,:)+ , determine the second eye diagram. Figure 16 As shown in the figure, the eye diagram enclosed by the upper and lower boundaries corresponding to the green solid line is the worst eye diagram, that is, the second eye diagram.

[0120] In this embodiment, the worst case is calculated by using inter-symbol interference, which can clearly show the limit boundary of signal distortion and form the second eye diagram in the worst case.

[0121] In an exemplary embodiment, the eye diagram parameter includes at least one of eye width, eye height, jitter, bit error rate, power consumption, and voltage level.

[0122] For example, eye diagram parameters include at least one of eye width (denoted as eye width); eye height (denoted as eye height); jitter (denoted as jitter); bit error rate (denoted as BER); power consumption (denoted as power); and voltage level (denoted as voltage level). Eye diagram parameters may also include eye crossing point (denoted as eye crossing point) and eye opening (denoted as eye opening). Eye height refers to the vertical height of the eye opening in the eye diagram, representing the maximum amplitude difference of the electrical signal. Eye width refers to the horizontal width of the eye opening in the eye diagram, indicating the optimal sampling time range for the signal. Jitter refers to the timing variation of the electrical signal, manifested as the deviation of the electrical signal edge from the ideal position. Bit error rate is an important metric for measuring the performance of digital communication systems. It represents the ratio of the number of bits received in error at the receiving end to the total number of bits transmitted. Power consumption refers to the power consumption of the on-chip terminal. Voltage level refers to the voltage level received by the on-chip terminal. The crossing point refers to the intersection of the rising and falling edges of the signal in the eye diagram, typically located at the center of the eye diagram. Eye opening refers to the degree to which the "eye" in the eye diagram is open, usually expressed as the product or ratio of eye height and eye width.

[0123] In this embodiment, the target impedance can be screened under the target equalizer dimension according to the eye diagram parameters.

[0124] In an exemplary embodiment, Figure 17 As shown. The server obtains candidate impedances for matching the ODT when configuring electrical signals for transmission in transmission lines of different sizes, for example, the candidate impedance values ​​are 10Ω, 20Ω, 30Ω, 40Ω, 50Ω, 60Ω, and 70Ω. Each candidate impedance value corresponds to a different range of candidate equalizer parameters. Assume that each candidate impedance value corresponds to three candidate equalizer parameters. The candidate impedance value 10Ω corresponds to candidate equalizer parameters EQ101, EQ102, and EQ103. The server obtains candidate equalizer parameters EQ201, EQ202, and EQ203 corresponding to the candidate impedance value 20Ω. ... The server obtains candidate equalizer parameters EQ701, EQ702, and EQ707 corresponding to the candidate impedance value 70Ω. Since the candidate impedance values ​​30Ω, 40Ω, 50Ω, and 60Ω correspond to three candidate equalizer parameters, the acquisition process is not further described and is represented by ....

[0125] The server obtains a long sequence of electrical signals in 1UI, such as 00000100000000000000, Figure 13 The server obtains a long sequence of electrical signals in 1UI, such as 00000100000000000000,

[0126] The server obtains a long sequence of electrical signals in 1UI, such as 00000100000000000000, The server obtains a long sequence of electrical signals in 1UI, such as 00000100000000000000, The server obtains a long sequence of electrical signals in 1UI, such as 00000100000000000000, Figure 16 The server obtains a long sequence of electrical signals in 1UI, such as 00000100000000000000, The server obtains a long sequence of electrical signals in 1UI, such as 00000100000000000000, The server obtains a long sequence of electrical signals in 1UI, such as 00000100000000000000, The server obtains a long sequence of electrical signals in 1UI, such as 00000100000000000000, The server obtains a long sequence of electrical signals in 1UI, such as 00000100000000000000, The server obtains a long sequence of electrical signals in 1UI, such as 00000100000000000000, The server obtains a long sequence of electrical signals in 1UI, such as 00000100000000000000, Figure 16 The server obtains a long sequence of electrical signals in 1UI, such as 00000100000000000000, The server obtains a long sequence of electrical signals in 1UI, such as 00000100000000000000,

[0127] For each candidate impedance value, three second eye diagrams corresponding to 10Ω, for example, are generated. According to a second preset condition, such as the maximum eye opening, and second eye diagram parameters in the three second eye diagrams, one of the three second eye diagrams is selected as a first eye diagram. The process of determining the first eye diagram from the second eye diagrams corresponding to other candidate impedance values is the same. The second preset condition represents a filtering condition related to the eye diagram parameters. The first eye diagram is an eye diagram of the electrical signal under the condition of each target equalizer parameter corresponding to each candidate impedance value of the terminal in the chip. The eye diagram parameters include at least one of the eye width, the eye height, the jitter, the bit error rate, the power consumption, and the voltage level. If the first eye diagram cannot be determined from the three second eye diagrams corresponding to a candidate impedance value according to the second preset condition, the candidate equalizer parameter is adjusted, and each new second eye diagram corresponding to the adjusted candidate equalizer parameter is continuously generated until the first eye diagram is selected from each new second eye diagram.

[0128] The server pre-configures the filtering condition related to the eye diagram parameters as the first preset condition according to the instruction. The eye diagram parameters can include the eye width, the eye height, the eye crossing point, the overshoot, the undershoot, the rise time, the fall time, the total jitter, the eye opening degree determined according to the eye width and the eye height, the power consumption, and the voltage level, and the like. For example, the maximum eye height, the maximum eye width, the maximum eye width and the maximum eye height, the minimum power consumption, the minimum total jitter, and other eye diagram parameter conditions under the premise of meeting the quality threshold of the eye diagram quality. The first preset condition represents a filtering condition related to the eye diagram parameters. The first preset condition and the second preset condition can include the same or different eye diagram parameters.

[0129] The server obtains seven first eye diagrams corresponding to the target equalizer parameter conditions of the candidate impedance values 10Ω, 20Ω, 30Ω, 40Ω, 50Ω, 60Ω, and 70Ω when the electrical signal is transmitted through a 9-inch transmission line (9in-channel), that is, as shown in Figure 6 The channel attenuation curve is shown as d in Figure 7 , and 9in-channel=8dB@10GHz. As shown in d in Figure 8 , the power consumption corresponding to the candidate impedance values 10Ω, 20Ω, 30Ω, 40Ω, 50Ω, 60Ω, and 70Ω under 8dB@10GHz. As shown in d in Figure 9 , the voltage level corresponding to 10Ω, 20Ω, 30Ω, 40Ω, 50Ω, 60Ω, and 70Ω under 8dB@10GHz. As shown in d in Figure 10 , the eye width corresponding to 10Ω, 20Ω, 30Ω, 40Ω, 50Ω, 60Ω, and 70Ω under 8dB@10GHz. As shown in d in Figure 11d in the table represents the eye height corresponding to 10Ω, 20Ω, 30Ω, 40Ω, 50Ω, 60Ω and 70Ω under 8dB@10GHz and 10Ω. If the first preset condition is the lowest power consumption under the premise of meeting the quality threshold of the eye diagram quality, if the seven first eye diagrams all meet the eye diagram quality threshold, the eye diagram with the lowest power consumption is selected as the target eye diagram, as shown in Figure 8 70Ω corresponds to the lowest power consumption, so the first eye diagram corresponding to 70Ω is the target eye diagram, and the candidate impedance value corresponding to the target eye diagram is taken as the target impedance value. If the target eye diagram cannot be determined according to the first preset condition in the seven first eye diagrams corresponding to each candidate impedance value of the target equalizer, the candidate impedance value of the ODT is reconfigured, and the new impedance value is continuously generated in each new second eye diagram corresponding to different candidate equalizer parameters, and a new first eye diagram is selected from each new second eye diagram, until the target eye diagram can be determined from the new first eye diagram.

[0130] It is worth noting that under different channel attenuations, the smaller the candidate impedance value, the greater the power consumption, the higher the voltage level, and the larger the eye width. However, it is not necessarily that the smaller the impedance value, the smaller the eye height, so when setting the first preset condition and the second preset condition, attention should be paid when setting the eye height. It is not necessarily that the larger the candidate impedance value, the larger the eye height. As shown in Figure 11 a, b and c in the table, as the candidate impedance value increases, the eye height increases, but the eye height is the largest at 50Ω, and decreases at 60Ω and 70Ω. As shown in Figure 11 d in the table, as the candidate impedance value increases, the eye height increases, and the eye height reaches the maximum value at 30Ω, and then gradually decreases as the candidate impedance value increases.

[0131] It should be understood that although each step in the flowchart involved in each of the above embodiments is displayed in sequence according to the arrow, these steps are not necessarily executed in sequence according to the arrow. Unless otherwise stated herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, at least part of the steps in the flowchart involved in each of the above embodiments can include multiple steps or stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or steps or stages in other steps.

[0132] Based on the same inventive concept, the embodiments of the present application also provide an impedance determination device for implementing the above-mentioned impedance determination method. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme described in the above method, so the specific limitations in one or more impedance determination device embodiments provided below can refer to the limitations of the impedance determination method in the above text, which will not be repeated here.

[0133] In one example embodiment, as shown in Figure 18 An impedance determination apparatus is provided, comprising: an obtaining module 1801, a target eye diagram determination module 1802, and a target impedance value determination module 1803, wherein:

[0134] The obtaining module 1801 is configured to obtain a plurality of first eye diagrams of the on-chip termination, wherein each first eye diagram is an eye diagram of the electrical signal under a plurality of target equalizer parameters corresponding to a plurality of candidate impedance values of the on-chip termination; each candidate impedance value corresponds to a target equalizer parameter.

[0135] The target eye diagram determination module 1802 is configured to obtain a target eye diagram from the plurality of first eye diagrams according to a first preset condition and an eye diagram parameter in each of the plurality of first eye diagrams; wherein the first preset condition represents a screening condition related to the eye diagram parameter.

[0136] The target impedance value determination module 1803 is configured to determine a candidate impedance value corresponding to the target eye diagram as a target impedance value.

[0137] In one example embodiment, the obtaining module 1801 is further configured to obtain a plurality of candidate impedance values of the on-chip termination, each candidate impedance value corresponding to different candidate equalizer parameters; for each candidate impedance value, obtain a plurality of second eye diagrams of the electrical signal under the different candidate equalizer parameters corresponding to the candidate impedance value; for each second eye diagram corresponding to each candidate impedance value, obtain a corresponding first eye diagram from the plurality of second eye diagrams according to a second preset condition and a value of a second eye diagram parameter in each of the plurality of second eye diagrams, wherein the second preset condition represents a screening condition related to the eye diagram parameter.

[0138] In one example embodiment, the obtaining module 1801 is further configured to process the electrical signal in a target time period by the different candidate equalizer parameters corresponding to each candidate impedance value to obtain a plurality of single-bit impulse response curves; and determine the plurality of second eye diagrams according to the plurality of single-bit impulse response curves.

[0139] In one example embodiment, the obtaining module 1801 is further configured to, for each single-bit impulse response curve, analyze the single-bit impulse response curve by a peak distortion analysis algorithm to obtain a second eye diagram under each candidate equalizer parameter corresponding to each candidate impedance value.

[0140] In an example embodiment, the acquisition module 1801 is further configured to take the voltage maximum of the single-tap impulse response curve as a main tap, and acquire a front tap and a back tap of the main tap in a target time period; calculate the intersymbol interference of the front tap and the back tap, respectively; the intersymbol interference includes positive intersymbol interference and negative intersymbol interference; determine the upper boundary of the second eye diagram through the positive intersymbol interference and the main tap, and determine the lower boundary of the second eye diagram through the negative intersymbol interference and the main tap; and determine the second eye diagram according to the upper boundary and the lower boundary.

[0141] In an example embodiment, the eye diagram parameter includes at least one of an eye width, an eye height, jitter, a bit error rate, power consumption, and a voltage level.

[0142] The above-mentioned various modules in the impedance determination apparatus can be realized by software, hardware, and combinations thereof, in whole or in part. The above-mentioned various modules can be embedded in or independent of a processor in a computer device in hardware form, or can be stored in a memory in a computer device in software form, so as to be called and executed by a processor to perform the operations corresponding to the above-mentioned various modules.

[0143] In an example embodiment, a computer device is provided, which can be a server, and an internal structure diagram thereof can be as shown in Figure 19 The computer device includes a processor, a memory, an input / output interface (I / O), and a communication interface. The processor, the memory, and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The database of the computer device is configured to store eye diagram parameter data. The input / output interface of the computer device is configured to exchange information between the processor and external devices. The communication interface of the computer device is configured to communicate with external terminals through a network connection. The computer program is executed by the processor to implement an impedance determination method.

[0144] Those skilled in the art can understand that Figure 19 The structure shown in the above-mentioned

[0145] In an embodiment, a computer device is also provided, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps in the above method embodiments when executing the computer program.

[0146] In an embodiment, a computer readable storage medium is provided, which stores a computer program, and the computer program is executed by a processor to implement the steps in the above method embodiments.

[0147] In an embodiment, a computer program product is provided, comprising a computer program, and the computer program is executed by a processor to implement the steps in the above method embodiments.

[0148] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when executed, can include the processes of the above-mentioned embodiment methods. Any reference to memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. The non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. The volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration but not limitation, the RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The database involved in the embodiments provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided in the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., without being limited thereto.

[0149] The technical features of the above embodiments can be combined in any way. To make the description concise, not all possible combinations of the technical features in the above embodiments are described, but as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present application.

[0150] The above-described embodiments are merely illustrative of several embodiments of the present application, and the description is relatively specific and detailed, but should not be understood as a limitation on the scope of the patent. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the scope of the present application. Therefore, the scope of protection of the present application should be subject to the appended claims.

Claims

1. A method for determining impedance, characterized in that: The method comprises: Obtaining first eye diagrams of the on-chip terminal, wherein the first eye diagrams are eye diagrams of the electrical signal under conditions of target equalizer parameters corresponding to candidate impedance values ​​of the on-chip terminal; each candidate impedance value corresponds to a target equalizer parameter; Obtaining a target eye diagram from each of the first eye diagrams according to a first preset condition and eye diagram parameters in each of the first eye diagrams; wherein the first preset condition represents a screening condition related to the eye diagram parameters; The candidate impedance value corresponding to the target eye diagram is used as a target impedance value.

2. The method according to claim 1, characterized in that The obtaining of each first eye image of the on-chip terminal includes: Acquire each candidate impedance value of the on-chip terminal, each candidate impedance value corresponding to a different candidate equalizer parameter; For each candidate impedance value, obtaining a second eye diagram of the electrical signal under different candidate equalizer parameter conditions corresponding to the candidate impedance value; For each second eye diagram corresponding to each candidate impedance value, the corresponding first eye diagram is obtained from each second eye diagram according to a second preset condition and a value of a second eye diagram parameter in each second eye diagram, wherein the second preset condition represents a screening condition related to the eye diagram parameter.

3. The method according to claim 2, characterized in that The acquiring of a second eye diagram of the electrical signal under different candidate equalizer parameter conditions corresponding to the candidate impedance value includes: Processing the electrical signal within the target time period using the different candidate equalizer parameters corresponding to each candidate impedance value to obtain each single-bit impulse response curve; Determine each of the second eye diagrams according to each of the single-bit impulse response curves.

4. The method according to claim 3, characterized in that The determining of each second eye diagram according to each single-bit impulse response curve includes: For each of the single-bit impulse response curves, the single-bit impulse response curve is analyzed by a peak distortion analysis algorithm to obtain a second eye diagram under each of the candidate equalizer parameters corresponding to each of the candidate impedance values.

5. The method according to claim 4, characterized in that The analyzing the single-bit impulse response curve by a peak distortion analysis algorithm to obtain a second eye diagram under each candidate equalizer parameter corresponding to each candidate impedance value includes: Taking the voltage maximum value of the single-bit impulse response curve as a main tap, and obtaining a front tap and a rear tap of the main tap within the target time period; Calculating the inter-symbol interference of the front tap and the rear tap respectively; the inter-symbol interference includes positive inter-symbol interference and negative inter-symbol interference; Determining a lower boundary of the second eye diagram by using the positive intersymbol interference and the main tap, and determining an upper boundary of the second eye diagram by using the negative intersymbol interference and the main tap; The second eye pattern is determined according to the upper boundary and the lower boundary.

6. The method according to any one of claims 1 to 5, characterized in that The eye diagram parameters include at least one of eye width, eye height, jitter, bit error rate, power consumption, and voltage level.

7. An impedance determination device, characterized in that: The device comprises: an acquisition module, configured to acquire first eye diagrams of the on-chip terminal, wherein the first eye diagrams are eye diagrams of the electrical signal under conditions of target equalizer parameters corresponding to candidate impedance values ​​of the on-chip terminal; each candidate impedance value corresponds to a target equalizer parameter; a target eye diagram determining module, configured to obtain a target eye diagram from each of the first eye diagrams according to a first preset condition and eye diagram parameters in each of the first eye diagrams; wherein the first preset condition represents a screening condition related to the eye diagram parameters; The target impedance value determining module is configured to use the candidate impedance value corresponding to the target eye diagram as the target impedance value.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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