Detection and protection circuit system of amplifier

Abstract

The invention discloses a detection and protection circuit system of an amplifier, which is characterized in that a protection circuit system consisting of an over-temperature protection circuit (OTP), an over-current protection circuit (OCP), an over-voltage protection circuit (OVP), an electromagnetic interference (EMI) protection circuit and an ESD protection circuit is used, and a band-gap reference circuit BG and the over-temperature protection circuit are connected in series to form a whole which is connected in parallel with a core of the amplifier; meanwhile, the overcurrent protection circuit is connected to the output end of the amplifier in parallel, the overvoltage protection circuit is connected with the electromagnetic interference protection circuit in series and arranged at the input end of the amplifier, and the ESD protection circuit is connected with the power port in series. The over-temperature protection circuit mainly aims at an output heat source power tube and an input heat source differential pair. The over-current protection is to protect the output power tube, and if the over-temperature protection is triggered, the FLAG outputs an over-temperature protection signal. And the ESD protection is used for protecting electrostatic discharge of IO and POWER ports.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of high-voltage and high-output current power amplifier, and particularly relates to a detection and protection circuit system of an amplifier. BACKGROUND

[0002] The protection circuit design of an amplifier is a very important link in the amplifier, and without a good protection circuit, even the best performance is also empty talk. Many existing designs have problems such as incomplete protection scenarios and insufficient protection performance. For example, the common high-voltage and high-current protection circuit cannot meet the use requirements of the amplifier under extreme working conditions. And the common protection circuit will appear protection failure when working under extreme temperature, extreme current, extreme voltage, electromagnetic, static electricity and other conditions.

[0003] Therefore, the prior art still needs to be improved and improved. SUMMARY

[0004] In view of the above problems in the prior art, the purpose of the present application is to provide a detection and protection circuit system of an amplifier, which aims to solve the problem that the protection circuit of the amplifier in the prior art will appear protection failure under extreme working conditions.

[0005] In order to achieve the above purpose, the present application adopts the following technical scheme: A detection and protection circuit system of an amplifier, comprising an over-temperature protection circuit, an over-current protection circuit, an over-voltage protection circuit, an electromagnetic interference protection circuit, an ESD protection circuit and a bandgap reference circuit BG, the bandgap reference circuit BG and the over-temperature protection circuit are connected in series to form a whole parallel to the core of the amplifier, and the over-current protection circuit is connected in parallel at the output end of the amplifier, the over-voltage protection circuit and the electromagnetic interference protection circuit are connected in series and arranged at the input end of the amplifier, and the ESD protection circuit is connected in series with the power port.

[0006] Further, the over-current protection circuit comprises a power supply VCC, a comparator FN_CMP, a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5 and a sixth NMOS tube MN6. The power supply VCC is connected with the source and substrate of the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3 and the fourth PMOS transistor MP4, the gate of the first PMOS transistor MP1 is connected to the drain of the third PMOS transistor MP3, the drain of the first PMOS transistor MP1 is connected to the drain of the second NMOS transistor MN2 and the input of the comparator FN_CMP, the gate of the third PMOS transistor MP3 is connected to the output of the comparator FN_CMP, the source and drain of the third NMOS transistor MN3, the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 are connected to form a three-layer common source and common gate structure, and the drain of the third NMOS transistor MN3 is connected to the IB port of the comparator FN_CMP. The gate of the first NMOS transistor MN1 is connected to the drain of the sixth NMOS transistor MN6, the source of the first NMOS transistor MN1 is connected to the drain of the second PMOS transistor MP2, the second PMOS transistor MP2 is connected in a diode connection mode, the gate of the sixth NMOS transistor MN6 is connected to the output of the comparator FP_CMP, the source and drain of the fourth PMOS transistor MP4, the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are connected to form a common source and common gate structure, and the IB port of the comparator FP_CMP is connected.

[0007] Further, the bandgap reference circuit comprises a VDD5V, a VSTR, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a twenty-first PMOS transistor MP21, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9 and a first capacitor C1. The source and substrate of the seventh PMOS transistor MP7, the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 are connected to the VDD5V, the base and the collector of the first transistor Q1 are connected, and the base and the collector of the first transistor Q1 are connected to the VSTR, the emitter of the first transistor Q1 is connected to the first resistor R1, the second resistor R2 and the emitter of the sixth transistor Q6, the collector of the second transistor Q2 is connected to the other end of the first resistor R1, the collector of the third transistor Q3 is connected to the other end of the second resistor R2 and the base of the fifth transistor Q5, one end of the third resistor R3 is connected to the emitter of the second transistor Q2, the other end of the third resistor R3 is connected to the emitter of the third transistor Q3, and the fourth resistor R4 is connected to the emitter of the third transistor Q3. The emitter of the fourth transistor Q4 is connected with the drain of the seventh NMOS MN7, and the collector is connected with the drain of the seventh PMOS MP7. The emitter of the fifth transistor Q5 is connected with the drain of the eighth NMOS MN8, and the collector is connected with the drain of the eighth PMOS MP8.

[0008] One end of the first capacitor C1 is connected with the collector of the fifth transistor Q5, and the other end is connected with the drain of the ninth PMOS MP9. The fifth resistor R5 and the sixth resistor R6 are connected in series, and the connected node is connected with the base of the second transistor Q2 and the third transistor Q3. The seventh resistor R7, the eighth resistor R8 and the ninth resistor R9 are connected in series. The connection position of the seventh resistor R7 and the eighth resistor R8 is recorded as VT140, and the connection node of the eighth resistor R8 and the ninth resistor R9 is recorded as VT160.

[0009] Further, the over-temperature protection circuit comprises: VDD5V, the ninth PMOS MP9, the tenth PMOS MP10, the eleventh PMOS MP11, the twelfth PMOS MP12, the thirteenth PMOS MP13, the fourteenth PMOS MP14, the fifteenth PMOS MP15, the sixteenth PMOS MP16, the seventeenth PMOS MP17, the eighteenth PMOS MP18, the nineteenth PMOS MP19, the twentieth PMOS MP20, the ninth NMOS MN9, the tenth NMOS MN10, the eleventh NMOS MN11, the twelfth NMOS MN12, the thirteenth NMOS MN13, the fourteenth NMOS MN14, the fifteenth NMOS MN15, the sixteenth NMOS MN16, the seventeenth NMOS MN17, the eighteenth NMOS MN18, the nineteenth NMOS MN19, the twentieth NMOS MN20, the twenty-first NMOS MN21, the twenty-second NMOS MN22, the twenty-third NMOS MN23, the twenty-fourth NMOS MN24, the twenty-fifth NMOS MN25, the twenty-sixth NMOS MN26, the twenty-seventh NMOS MN27, the twenty-eighth NMOS MN28, and a Schmitt trigger. The source and substrate of the thirteenth PMOS tube MP13, the fifteenth PMOS tube MP15, the seventeenth PMOS tube MP17, the nineteenth PMOS tube MP19 and the twentieth PMOS tube MP20 are connected with VDD5V, the source and drain of the thirteenth PMOS tube MP13 and the fourteenth PMOS tube MP14 are connected to form a two-layer common-source common-gate structure, the source and drain of the fifteenth PMOS tube MP15 and the sixteenth PMOS tube MP16 are connected to form a two-layer common-source common-gate structure, the source and drain of the seventeenth PMOS tube MP17 and the eighteenth PMOS tube MP18 are connected to form a two-layer common-source common-gate structure, and the source and drain of the nineteenth PMOS tube MP19 and the twentieth PMOS tube MP20 are connected to form a two-layer common-source common-gate structure; The gate of the ninth PMOS tube MP9 is connected with the gate of the sixteenth NMOS tube MN16, and the drain of the ninth PMOS tube MP9 is connected with the drain of the sixteenth NMOS tube MN16 to form an inverter structure, the gate of the tenth PMOS tube MP10 is connected with the gate of the twenty-first NMOS tube MN21, and the drain of the tenth PMOS tube MP10 is connected with the drain of the twenty-first NMOS tube MN21 to form an inverter structure, and the output of the inverter structure is output through the reverse output end as TEMP_HI through a Schmidt trigger; The gates of the twenty-sixth NMOS tube MN26, the twenty-seventh NMOS tube MN27 and the twenty-eighth NMOS tube MN28 are connected, the source of the eleventh PMOS tube MP11 and the twelfth PMOS tube MP12 are connected together, the drain of the eleventh PMOS tube MP11 is connected with the drain of the twenty-second NMOS tube MN22, the drain of the twenty-fifth NMOS tube MN25, the drain of the twenty-sixth NMOS tube MN26, the gate of the twenty-third NMOS tube MN23, the gate of the twenty-fourth NMOS tube MN24, the gate of the ninth NMOS tube MN9 and the gate of the thirteenth NMOS tube MN13, and the drain of the twelfth PMOS tube MN12 is connected with the drain of the twenty-first NMOS tube MN21, the drain of the tenth NMOS tube MN10, the gate of the twenty-third NMOS tube MN23 and the gate of the eleventh NMOS tube MN11; The gate of the twelfth NMOS tube MN12 is connected with the gate of the twenty-sixth NMOS tube MN26, and the drain of the thirteenth NMOS tube MN13 is connected with the source of the twelfth NMOS tube MN12; The source and drain of the fifteenth NMOS tube MN15 and the fourteenth NMOS tube MN14 are connected to form a two-layer common-source common-gate structure, and the source and drain of the seventeenth NMOS tube MN17 and the eighteenth NMOS tube MN18 are connected to form a two-layer common-source common-gate structure; The source of the nineteenth NMOS transistor MN19 and the twentieth NMOS transistor MN20 is connected, and is connected to the gate of the twelfth PMOS transistor MP12, the gate of the nineteenth NMOS transistor MN19 is connected with the same phase output end of the Schmitt trigger, and the gate of the twentieth NMOS transistor MN20 is connected with the reverse output end of the Schmitt trigger.

[0010] Further, the series circuit of the overvoltage protection circuit and the electromagnetic interference protection circuit comprises: VCC, VIN, the first diode D1, the second diode D2, the third diode D3, the third capacitor C3, the fourth capacitor C4, the fourth diode D4, the tenth resistor R10, the eleventh resistor R11. VCC is connected with the reverse end of the third diode D3, VSS is connected with the positive end of the fourth capacitor C4, the third capacitor C3 and the fourth diode D4, the reverse end of the fourth diode D4 is connected with the same phase end of the third diode D3 and one end of the eleventh resistor R11, and is connected with VIN. The first diode D1 and the second diode D2 are connected in reverse parallel, and are connected in series with the tenth resistor R10 and the third capacitor C3, and the eleventh resistor R11 and the fourth capacitor C4 are connected in series.

[0011] Further, the ESD protection circuit comprises at least three ESD devices, VCC BUS, VSS BUS and an isolation resistor, the drains of two ESD devices are connected with an IO PAD input, the sources of the two ESD devices are connected with VCC BUS and VSS BUS respectively, and the IOPAD input is connected with the drain of one ESD device through the isolation resistor.

[0012] The technical scheme adopted by the present application has the following beneficial effects: In the present application, a protection circuit system composed of an over-temperature protection circuit (OTP), an over-current protection circuit (OCP), an over-voltage protection circuit (OVP), an electromagnetic interference (EMI) protection circuit and an ESD protection circuit is used. The electromagnetic interference protection circuit and the over-voltage protection circuit are located at the input end of the amplifier, the over-temperature protection circuit is mainly aimed at the output heat source power tube and the input heat source differential pair. The over-current protection is for protecting the output power tube, and if the over-temperature protection is triggered, an over-temperature protection signal will be output by FLAG. The ESD protection is for protecting the static discharge of IO and POWER ports. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 The structure schematic diagram of the over-current protection circuit provided by the present application is shown in the figure. Figure 2 The structure schematic diagram of the band gap reference circuit provided by the present application is shown in the figure. Figure 3A structure schematic diagram of an over-temperature protection circuit provided by the present application is shown in the figure; Figure 4 A structure schematic diagram of an electromagnetic interference protection and over-voltage protection circuit provided by the present application is shown in the figure; Figure 5 A structure schematic diagram of an ESD protection circuit provided by the present application is shown in the figure; Figure 6 A structure schematic diagram of an amplifier detection and protection circuit system provided by the present application is shown in the figure. DETAILED DESCRIPTION

[0014] In order to make the purpose, technical solutions and effects of the present application more clear and explicit, the present application is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are only used to explain the present application and do not limit the present application.

[0015] An amplifier detection and protection circuit system includes an over-temperature protection circuit, an over-current protection circuit, an over-voltage protection circuit, an electromagnetic interference protection circuit, an ESD protection circuit and a bandgap reference circuit BG. The bandgap reference circuit BG and the over-temperature protection circuit are connected in series to form an integral whole parallel to the core of the amplifier. Meanwhile, the over-current protection circuit is connected in parallel to the output end of the amplifier. The over-voltage protection circuit and the electromagnetic interference protection circuit are connected in series and arranged at the input end of the amplifier. The ESD protection circuit is connected in series with the power port.

[0016] In the present application, a protection circuit system composed of an over-temperature protection circuit (OTP), an over-current protection circuit (OCP), an over-voltage protection circuit (OVP), an electromagnetic interference (EMI) protection circuit and an ESD protection circuit is used. The electromagnetic interference protection circuit and the over-voltage protection circuit are located at the input end of the amplifier. The over-temperature protection circuit is mainly aimed at the output heat source power tube and the input heat source differential pair. The over-current protection is for protecting the output power tube. If the over-temperature protection is triggered, an over-temperature protection signal will be output by FLAG. The ESD protection is for protecting the static discharge of the IO and POWER ports.

[0017] In the present embodiment, referring to Figure 1 , the over-current protection circuit includes a power supply VCC, a comparator FN_CMP, a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5 and a sixth NMOS tube MN6. The source and substrate of the power supply VCC are connected to the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3 and the fourth PMOS transistor MP4, the gate of the first PMOS transistor MP1 is connected to the drain of the third PMOS transistor MP3, the drain of the first PMOS transistor MP1 is connected to the drain of the second NMOS transistor MN2 and the input of the comparator FN_CMP, the gate of the third PMOS transistor MP3 is connected to the output of the comparator FN_CMP, the source and drain of the third NMOS transistor MN3, the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 are connected to form a three-layer common source and common gate structure, and the drain of the third NMOS transistor MN3 is connected to the IB port of the comparator FN_CMP. The gate of the first NMOS transistor MN1 is connected to the drain of the sixth NMOS transistor MN6, the source of the first NMOS transistor MN1 is connected to the drain of the second PMOS transistor MP2, the second PMOS transistor MP2 is in a diode connection mode, the gate of the sixth NMOS transistor MN6 is connected to the output of the comparator FP_CMP, the source and drain of the fourth PMOS transistor MP4, the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are connected to form a common source and common gate structure, and the IB port of the comparator FP_CMP is connected.

[0018] When the output current exceeds 450 mA, the voltage drop of MN2 or MP2 increases, so that the FN_CMP V1 and the FP_CMP V1 reach the flip threshold value, a current limiting signal is generated, so that the gate voltage of the output power transistor is clamped, and the output current is limited to 450 mA.

[0019] The basic principle of the overcurrent protection is to detect the gate voltage of the complementary push-pull structure transistor through MP1 and MN1. When the current of the output complementary push-pull structure transistor increases, the gate voltage of MP1 decreases and the gate voltage of MN1 increases. When the gate voltage reaches the current limiting threshold value, the drain voltage of the diode-connected MP2 in series with the gate voltage decreases, the drain voltage of MN2 increases, and the drain voltage of MP2 is sent to the input of the P input of the comparator for comparison, and the drain voltage of MN2 is sent to the input of the N input of the comparator for comparison. The other input voltage of the comparator is generated by a diode-connected MOS transistor biased by a current source. The drain voltage of the MOS is relatively stable compared with MP2 and MN2, and is basically not affected by the output stage current, and is used as the flip voltage of the comparator.

[0020] When the output current reaches the specified limiting current value, the drain voltage of MP2 decreases to the flip threshold value, and the drain voltage of MN2 increases to the flip threshold value, thereby generating an overcurrent protection signal to the gates of MP3 and MN6, so that the gate of the complementary push-pull structure transistor is pulled to be close to VCC and VSS, so that the current value no longer increases.

[0021] In the embodiment, referring to Figure 2 , the bandgap reference circuit comprises: VDD5V, VSTR, seventh PMOS tube MP7, eighth PMOS tube MP8, twenty-first PMOS tube MP21, seventh NMOS tube MN7, eighth NMOS tube MN8, first transistor Q1, second transistor Q2, third transistor Q3, fourth transistor Q4, fifth transistor Q5, sixth transistor Q6, first resistor R1, second resistor R2, third resistor R3, fourth resistor R4, fifth resistor R5, sixth resistor R6, seventh resistor R7, eighth resistor R8, ninth resistor R9, first capacitor C1; Wherein, the source of the seventh PMOS tube MP7, the eighth PMOS tube MP8 and the ninth PMOS tube MP9 is connected with the substrate and VDD5V, the base and the collector of the first transistor Q1 are connected, and the first transistor Q1 is connected to VSTR, the emitter of the first transistor Q1 is connected to the first resistor R1, the second resistor R2 and the emitter of the sixth transistor Q6, the collector of the second transistor Q2 is connected to the other end of the first resistor R1, the collector of the third transistor Q3 is connected to the other end of the second resistor R2 and the base of the fifth transistor Q5, one end of the third resistor R3 is connected to the emitter of the second transistor Q2, the other end of the third resistor R3 is connected to the emitter of the third transistor Q3, and the fourth resistor R4 is connected to the emitter of the third transistor Q3. The emitter of the fourth transistor Q4 is connected with the drain of the seventh NMOS tube MN7, and the collector thereof is connected with the drain of the seventh PMOS tube MP7, the emitter of the fifth transistor Q5 is connected with the drain of the eighth NMOS tube MN8, and the collector thereof is connected with the drain of the eighth PMOS tube MP8.

[0022] One end of the first capacitor C1 is connected with the collector of the fifth transistor Q5, and the other end thereof is connected with the drain of the ninth PMOS tube MP9, wherein the fifth resistor R5 and the sixth resistor R6 are connected in series, and the connected node is connected with the base of the second transistor Q2 and the third transistor Q3; The seventh resistor R7, the eighth resistor R8 and the ninth resistor R9 are connected in series, the seventh resistor R7 and the eighth resistor R8 are connected at a position marked as VT140, and the eighth resistor R8 and the ninth resistor R9 are connected at a node marked as VT160.

[0023] In addition, referring to Figure 3, the over-temperature protection circuit comprises: VDD5V, ninth PMOS MP9, tenth PMOS MP10, eleventh PMOS MP11, twelfth PMOS MP12, thirteenth PMOS MP13, fourteenth PMOS MP14, fifteenth PMOS MP15, sixteenth PMOS MP16, seventeenth PMOS MP17, eighteenth PMOS MP18, nineteenth PMOS MP19, twentieth PMOS MP20, ninth NMOS MN9, tenth NMOS MN10, eleventh NMOS MN11, twelfth PMOS MN12, thirteenth NMOS MN13, fourteenth NMOS MN14, fifteenth NMOS MN15, sixteenth NMOS MN16, seventeenth NMOS MN17, eighteenth NMOS MN18, nineteenth NMOS MN19, twentieth NMOS MN20, twenty-first NMOS MN21, twenty-second NMOS MN22, twenty-third NMOS MN23, twenty-fourth NMOS MN24, twenty-fifth NMOS MN25, twenty-sixth NMOS MN26, twenty-seventh NMOS MN27, twenty-eighth NMOS MN28, Schmitt trigger; Wherein, VDD5V is connected with the source and substrate of thirteenth PMOS MP13, fifteenth PMOS MP15, seventeenth PMOS MP17, nineteenth PMOS MP19 and twentieth PMOS MP20, the source and drain of thirteenth PMOS MP13 and fourteenth PMOS MP14 are connected to form two-layer common-source common-gate structure, the source and drain of fifteenth PMOS MP15 and sixteenth PMOS MP16 are connected to form two-layer common-source common-gate structure, the source and drain of seventeenth PMOS MP17 and eighteenth PMOS MP18 are connected to form two-layer common-source common-gate structure, the source and drain of nineteenth PMOS MP19 and twentieth PMOS MP20 are connected to form two-layer common-source common-gate structure; The gate of ninth PMOS MP9 is connected with the gate of sixteenth NMOS MN16, the drain of ninth PMOS MP9 is connected with the drain of sixteenth NMOS MN16 to form inverter structure, the gate of tenth PMOS MP10 is connected with the gate of twenty-first NMOS MN21, the drain of tenth PMOS MP10 is connected with the drain of twenty-first NMOS MN21 to form inverter structure, the output of inverter structure is output through reverse output end of Schmitt trigger as TEMP_HI; The gate of the twenty-sixth NMOS transistor MN26, the twenty-seventh NMOS transistor MN27 and the twenty-eighth NMOS transistor MN28 is connected, the source of the eleventh PMOS transistor MP11 and the twelfth PMOS transistor MP12 is connected together, the drain of the eleventh PMOS transistor MP11 is connected with the drain of the twenty-second NMOS transistor MN22, the drain of the twenty-fifth NMOS transistor MN25, the drain of the twenty-sixth NMOS transistor MN26, the gate of the twenty-third NMOS transistor MN23, the gate of the twenty-fourth NMOS transistor MN24, the gate of the ninth NMOS transistor MN9 and the gate of the thirteenth NMOS transistor MN13, the drain of the twelfth PMOS transistor MN12 is connected with the drain of the twenty-first NMOS transistor MN21, the drain of the tenth NMOS transistor MN10, the gate of the twenty-third NMOS transistor MN23 and the gate of the eleventh NMOS transistor MN11; The gate of the twelfth NMOS transistor MN12 is connected with the gate of the twenty-sixth NMOS transistor MN26, and the drain of the thirteenth NMOS transistor MN13 is connected with the source of the twelfth NMOS transistor MN12; The fifteenth NMOS transistor MN15 and the fourteenth NMOS transistor MN14 are connected in series to form a two-layer common-source common-gate structure, and the seventeenth NMOS transistor MN17 and the eighteenth NMOS transistor MN18 are connected in series to form a two-layer common-source common-gate structure; The source of the nineteenth NMOS transistor MN19 and the twentieth NMOS transistor MN20 is connected, and connected to the gate of the twelfth PMOS transistor MP12, the gate of the nineteenth NMOS transistor MN19 is connected with the same phase output end of the Schmitt trigger, and the gate of the twentieth NMOS transistor MN20 is connected with the reverse output end of the Schmitt trigger.

[0024] The over-temperature protection uses the Brokaw bandgap reference source circuit structure as the reference voltage source, wherein OP in the amplifier is a five-transistor amplifier using a transistor as a differential transistor, compared with a simple amplifier using a common NMOS as a differential pair, the performance is significantly improved, and the use of a transistor as a differential transistor can also be matched with the transistor in the Brokaw bandgap reference source to form a PCELL, which is convenient for layout drawing and matching.

[0025] The design uses two series-connected diodes connected vertical NPN transistors as temperature measuring elements, and uses the negative temperature coefficient of the NPN transistor V BE to detect the chip temperature.

[0026] The logic unit of the over-temperature protection circuit is mainly composed of a comparator and a Schmitt trigger. The 160-degree flip voltage (VT160) corresponding to the rising temperature and the 140-degree flip voltage (VT140) corresponding to the falling temperature are generated by a bandgap reference voltage source based on the output voltage division that does not change with temperature. Based on the hysteresis comparison characteristic of the Schmitt trigger, a set of NMOS switches are used to select the VT160 voltage or the VT140 voltage as the comparison voltage of the comparator: the 160-degree corresponding flip voltage is selected when the temperature rises, and the 140-degree corresponding flip voltage is selected when the temperature falls.

[0027] In this embodiment, referring to Figure 4 , the series circuit of the over-voltage protection circuit and the electromagnetic interference protection circuit includes: VCC, VIN, first diode D1, second diode D2, third diode D3, third capacitor C3, fourth capacitor C4, fourth diode D4, tenth resistor R10, eleventh resistor R11; VCC is connected to the reverse end of the third diode D3, VSS is connected to the positive end of the fourth capacitor C4, the third capacitor C3 and the fourth diode D4, the reverse end of the fourth diode D4 is connected to the same phase end of the third diode D3 and one end of the eleventh resistor R11, and is connected to VIN; The first diode D1 and the second diode D2 are connected in reverse parallel, and are connected in series with the tenth resistor R10 and the third capacitor C3, and the eleventh resistor R11 and the fourth capacitor C4 are connected in series.

[0028] Electromagnetic interference and over-voltage protection circuit. The design uses a low-pass filter at the input end for EMI protection. In order to reduce the influence of the pole generated by the EMI protection circuit on the stability of the amplifier, it is necessary to push the pole of the low-pass filter outside the main pole of the amplifier: where R is the filter resistance, C is the filter capacitance, GBW is the gain-bandwidth product of the operational amplifier, g m is the transconductance of the operational amplifier, C L is the value of the load capacitance. By changing the value of the filter capacitance C, the pole of the low-pass filter is pushed outside the main pole of the amplifier.

[0029] In addition, the related thermal noise generated by the resistance in the RC low-pass filter will increase the total input reference noise, and the noise spectral density of the resistance and the input transistor is approximately: where g m is the transconductance of the operational amplifier, is the thermal noise coefficient, CL is the load capacitance, and C is the filter capacitance value.

[0030] The filter capacitor C cannot be too small.

[0031] The input overvoltage protection mode as shown in Figure 4 is to add a pair of reverse parallel embedded voltage diodes between the positive and negative input terminals, and assist with a current limiting resistor, which can be shared with the EMI protection circuit resistance. At the same time, ESD protection tubes are added between VCC and VSS to prevent the input from exceeding the power rail (VCC, VSS) and breaking down the MOS.

[0032] Further, referring to Figure 5 , the ESD protection circuit includes at least three ESD devices, VCC BUS, VSS BUS, and an isolation resistor. The drains of two ESD devices are connected to the IO PAD input, and the sources of the two ESD devices are connected to the VCC BUS and the VSS BUS, respectively. The IO PAD input is connected to the drain of an ESD device through the isolation resistor.

[0033] The ESD protection circuit uses a classic two-level protection structure. In order to meet the design target of HBM≥6KV and MM≥500V, the metal width directly connected between the pad and the ESD protection device should be at least 20 microns, and the resistance of the BUS line from the IO unit to the VDD and VSS units should not exceed 0.5 ohms. In the case where the BUS distance from the VCC and VSS units to the IO unit is designed to be less than 2000μm, according to the sheet resistance of the next top metal being 100mohm / □, it can be calculated that the BUS width should be greater than 50μm.

[0034] From the above, it can be seen that the over-temperature protection circuit in the present application makes MN19 conduct when the temperature rises above 160 degrees to generate an over-temperature protection signal to disconnect the amplifier core and the bias circuit, and the amplifier output heat source power tube is short-circuited. When the chip cools down and the temperature decreases to less than 140 degrees, MN20 is turned on to generate a recovery signal, so that the amplifier can work again.

[0035] When the output current exceeds 450mA, the voltage drop across MN2 or MP2 increases, causing FN_CMPV1 and FP_CMPV1 to reach the flip threshold, generating a current limiting signal, so that the output power tube gate voltage is clamped and the output current is limited to 450mA.

[0036] When the input voltage exceeds VCC and VSS, diodes D1 and D2 clamp the input signal to VCC+0.7V and VSS-0.7V.

[0037] The electromagnetic interference protection can filter the input electromagnetic interference signal through two groups of low-pass filters composed of R1C2 and R2C1, so as to avoid interference caused by entering the amplifier core.

[0038] The ESD protection can be released by the reverse breakdown ESD tube to short circuit the static signal input from the IO port.

[0039] The design method of the protection circuit system composed of the over-temperature protection circuit (OTP), the over-current protection circuit (OCP), the over-voltage protection circuit (OVP), the electromagnetic interference (EMI) protection circuit and the ESD protection circuit improves the protection mechanism of the protection circuit, and avoids the protection failure of the protection circuit of the amplifier under extreme working conditions.

Claims

1. A detection and protection circuit system for an amplifier, characterized in that: It includes an over-temperature protection circuit, an over-current protection circuit, an over-voltage protection circuit, an electromagnetic interference protection circuit, an ESD protection circuit and a bandgap reference circuit BG. The bandgap reference circuit BG and the over-temperature protection circuit are connected in series to form a whole and are connected in parallel with the core of the amplifier. At the same time, the over-current protection circuit is connected in parallel to the output end of the amplifier, the over-voltage protection circuit and the electromagnetic interference protection circuit are connected in series and are set at the input end of the amplifier, and the ESD protection circuit is connected in series with the power port.

2. The amplifier detection and protection circuit system according to claim 1, characterized in that: The overcurrent protection circuit includes a power supply VCC, a comparator FN_CMP, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, and a sixth NMOS transistor MN6; The power supply VCC is connected to the source and substrate of the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4. The gate of the first PMOS transistor MP1 is connected to the drain of the third PMOS transistor MP3. The drain of the first PMOS transistor MP1 is connected to the drain of the second NMOS transistor MN2 connected via a diode and the input of the comparator FN_CMP. The gate of the third PMOS transistor MP3 is connected to the output of the comparator FN_CMP. The source and drain of the third NMOS transistor MN3, the fourth NMOS transistor MN4, and the fifth NMOS transistor MN5 are connected to form a three-layer cascode structure. The drain of the third NMOS transistor MN3 is connected to the IB port of the comparator FN_CMP. The gate of the first NMOS transistor MN1 is connected to the drain of the sixth NMOS transistor MN6, and the source of the first NMOS transistor MN1 is connected to the drain of the second PMOS transistor MP2. The second PMOS transistor MP2 is connected in a diode-connected manner. The gate of the sixth NMOS transistor MN6 is connected to the output of the comparator FP_CMP. The source and drain of the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, and the sixth PMOS transistor MP6 are connected to form a cascode structure, which is connected to the IB port of FP_CMP.

3. The amplifier detection and protection circuit system according to claim 1, wherein: The bandgap reference circuit includes: VDD5V, VSTR, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a twenty-first PMOS transistor MP21, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a first capacitor C1; The sources of the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, and the ninth PMOS transistor MP9 are connected to the substrate and VDD5V. The base and collector of the first transistor Q1 are connected and connected to VSTR. The emitter of the first transistor Q1 is connected to the first resistor R1, the second resistor R2, and the emitter of the sixth transistor Q6. The collector of the second transistor Q2 is connected to the other end of the first resistor R1. The collector of the third transistor Q3 is connected to the other end of the second resistor R2 and the base of the fifth transistor Q5. One end of the third resistor R3 is connected to the emitter of the second transistor Q2. The other end of the third resistor R3 is connected to the emitter of the third transistor Q3. Meanwhile, the fourth resistor R4 is connected to the emitter of the third transistor Q3. The emitter of the fourth transistor Q4 is connected to the drain of the seventh NMOS transistor MN7, and the collector thereof is connected to the drain of the seventh PMOS transistor MP7. The emitter of the fifth transistor Q5 is connected to the drain of the eighth NMOS transistor MN8, and the collector thereof is connected to the drain of the eighth PMOS transistor MP8. One end of the first capacitor C1 is connected to the collector of the fifth transistor Q5, and the other end is connected to the drain of the ninth PMOS transistor MP9, wherein the fifth resistor R5 and the sixth resistor R6 are connected in series, and the connection node is connected to the bases of the second transistor Q2 and the third transistor Q3; The seventh resistor R7, the eighth resistor R8, and the ninth resistor R9 are connected in series. The connection position of the seventh resistor R7 and the eighth resistor R8 is recorded as VT140, and the connection node of the eighth resistor R8 and the ninth resistor R9 is recorded as VT160.

4. The amplifier detection and protection circuit system according to claim 1, wherein: The over-temperature protection circuit includes: VDD5V, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a fifteenth PMOS transistor MP15, a sixteenth PMOS transistor MP16, a seventeenth PMOS transistor MP17, an eighteenth PMOS transistor MP18, a nineteenth PMOS transistor MP19, a twentieth PMOS transistor MP20, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a twelfth PMOS transistor MN12, a tenth a third NMOS transistor MN13, a fourteenth NMOS transistor MN14, a fifteenth NMOS transistor MN15, a sixteenth NMOS transistor MN16, a seventeenth NMOS transistor MN17, an eighteenth NMOS transistor MN18, a nineteenth NMOS transistor MN19, a twentieth NMOS transistor MN20, a twenty-first NMOS transistor MN21, a twenty-second NMOS transistor MN22, a twenty-third NMOS transistor MN23, a twenty-fourth NMOS transistor MN24, a twenty-fifth NMOS transistor MN25, a twenty-sixth NMOS transistor MN26, a twenty-seventh NMOS transistor MN27, a twenty-eighth NMOS transistor MN28, and a Schmitt trigger; VDD5V is connected to the source and substrate of the thirteenth PMOS transistor MP13, the fifteenth PMOS transistor MP15, the seventeenth PMOS transistor MP17, the nineteenth PMOS transistor MP19, and the twentieth PMOS transistor MP20. The source and drain of the thirteenth PMOS transistor MP13 and the fourteenth PMOS transistor MP14 are connected to form a two-layer cascode structure. The source and drain of the fifteenth PMOS transistor MP15 and the sixteenth PMOS transistor MP16 are connected to form a two-layer cascode structure. The source and drain of the seventeenth PMOS transistor MP17 and the eighteenth PMOS transistor MP18 are connected to form a two-layer cascode structure. The source and drain of the nineteenth PMOS transistor MP19 and the twentieth PMOS transistor MP20 are connected to form a two-layer cascode structure. The gate of the ninth PMOS transistor MP9 is connected to the gate of the sixteenth NMOS transistor MN16, and the drain of the ninth PMOS transistor MP9 is connected to the drain of the sixteenth NMOS transistor MN16, forming an inverter structure. The gate of the tenth PMOS transistor MP10 is connected to the gate of the twenty-first NMOS transistor MN21, and the drain of the tenth PMOS transistor MP10 is connected to the drain of the twenty-first NMOS transistor MN21, forming an inverter structure. The output of the inverter structure passes through a Schmitt trigger and is outputted as TEMP_HI through the inverting output terminal. The gates of the twenty-sixth NMOS transistor MN26, the twenty-seventh NMOS transistor MN27, and the twenty-eighth NMOS transistor MN28 are connected; the eleventh PMOS transistor MP11 is connected to the source of the twelfth PMOS transistor MP12; the drain of the eleventh PMOS transistor MP11 is connected to the drain of the twenty-second NMOS transistor MN22, the drain of the twenty-fifth NMOS transistor MN25, the drain of the twenty-sixth NMOS transistor MN26, the gate of the twenty-third NMOS transistor MN23, the gate of the twenty-fourth NMOS transistor MN24, the gate of the ninth NMOS transistor MN9, and the gate of the thirteenth NMOS transistor MN13; the drain of the twelfth PMOS transistor MN12 is connected to the drain of the twenty-first NMOS transistor MN21, the drain of the tenth NMOS transistor MN10, the gate of the twenty-third NMOS transistor MN23, and the gate of the eleventh NMOS transistor MN11; The gate of the twelfth NMOS transistor MN12 is connected to the gate of the twenty-sixth NMOS transistor MN26 , and the drain of the thirteenth NMOS transistor MN13 is connected to the source of the twelfth NMOS transistor MN12 ; The source and drain of the fifteenth NMOS transistor MN15 and the fourteenth NMOS transistor MN14 are connected to form a two-layer cascode structure; the source and drain of the seventeenth NMOS transistor MN17 and the eighteenth NMOS transistor MN18 are connected to form a two-layer cascode structure; The nineteenth NMOS transistor MN19 is connected to the source of the twentieth NMOS transistor MN20 and to the gate of the twelfth PMOS transistor MP12. The gate of the nineteenth NMOS transistor MN19 is connected to the non-inverting output terminal of the Schmitt trigger, and the gate of the twentieth NMOS transistor MN20 is connected to the inverting output terminal of the Schmitt trigger.

5. The amplifier detection and protection circuit system according to claim 1, wherein: The series circuit of the overvoltage protection circuit and the electromagnetic interference protection circuit includes: VCC, VIN, a first diode D1, a second diode D2, a third diode D3, a third capacitor C3, a fourth capacitor C4, a fourth diode D4, a tenth resistor R10, and an eleventh resistor R11; VCC is connected to the reverse terminal of the third diode D3, VSS is connected to the fourth capacitor C4, the third capacitor C3, and the forward terminal of the fourth diode D4, the reverse terminal of the fourth diode D4 is connected to the non-inverting terminal of the third diode D3 and one end of the eleventh resistor R11, and is further connected to VIN; The first diode D1 and the second diode D2 are connected in anti-parallel, and are connected to the tenth resistor R10 and the third capacitor C3 in series, and the eleventh resistor R11 and the fourth capacitor C4 in series.

6. The amplifier detection and protection circuit system according to claim 1, wherein: The ESD protection circuit includes at least three ESD devices, VCC BUS, VSS BUS, and isolation resistors. The drains of the two ESD devices are connected to the IO PAD input. The source ends of the two ESD devices are connected to the VCC BUS and the other to the VSS BUS. The IO PAD input is connected to the drain of one ESD device after passing through the isolation resistor.

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