MOSFET structure with gate nanosheet and fabrication process thereof

Abstract

The present application relates to the technical field of MOS semiconductor, and discloses a MOSFET structure with gate nanosheet and a manufacturing process thereof, which comprises a plurality of mutually parallel MOS cells, a single MOS cell comprising a drain, a semiconductor epitaxial layer, a gate, a gate oxide layer and a source, the semiconductor epitaxial layer comprising an N substrate layer, an N drift layer, an N well layer, a P+ layer and a P well layer, and the gate comprising a gate cover layer and a gate nanosheet; the gate nanosheet in a single MOS cell has a plurality of gate nanosheets, and the plurality of gate nanosheets are horizontally matrix distributed, and the gate nanosheet extends to the inside of the gate cover layer and directly contacts with the gate cover layer. The present application realizes higher current driving density and better switching characteristics by the three-dimensional embedded contact of the horizontally matrix distributed nanosheet gate and the high-conductivity cover layer, significantly enhances the channel electrostatic control ability, and reduces the gate resistance, thereby breaking through the physical limitation of the traditional planar device.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of MOS semiconductor technology, and in particular to a MOSFET structure with gate nanosheet and a manufacturing process thereof. BACKGROUND

[0002] With the miniaturization of semiconductor devices approaching the physical limit, traditional planar gate and FinFET structures face the challenges of weakened gate control ability and significantly intensified short channel effect at nodes below 5 nanometers. Although nanosheet transistors with a full-encircling gate (GAA) improve gate control ability through a three-dimensional channel, the existing structure still has key bottlenecks: first, the contact resistance between the nanosheet gate and the external electrode is high, which restricts the drive current density; second, a high-density nanosheet array is prone to cause local concentration of electric field in high-voltage applications, leading to premature breakdown of the drift region, and the conventional guard ring design is difficult to balance the improvement of withstand voltage and the optimization of on-resistance (Rdson); third, uneven terminal electric field distribution induces edge breakdown, limiting high-voltage reliability. In addition, the existing manufacturing process lacks sufficient precision in the coordinated control of complex three-dimensional gate integration and customized doping, affecting performance uniformity.

[0003] An existing patent discloses a MOSFET with a GAA structure (CN118299423A), which includes a silicon substrate, a semiconductor layer including a source region, a drain region, and a nanowire channel, a gate oxide layer, a gate polysilicon fully surrounding the nanowire channel, a source electrode, and a drain electrode. The semiconductor layer and the silicon substrate are integrally formed as a silicon wafer. The GAA structure of the existing patent is not optimized for high-voltage applications, and uneven electric field distribution in the drift region can easily lead to local breakdown. Moreover, the existing patent uses a traditional polysilicon gate in direct contact with metal, resulting in high gate resistance. SUMMARY

[0004] The present application provides a MOSFET structure with gate nanosheet and a manufacturing process thereof to solve the existing technical problems, solving the problem of uneven electric field distribution in the drift region leading to local breakdown.

[0005] To solve the above technical problems, according to one aspect of the present application, more specifically, a MOSFET structure with gate nanosheet includes a plurality of parallel MOS cells, each MOS cell includes a drain, a semiconductor epitaxial layer, a gate, a gate oxide layer, and a source, the semiconductor epitaxial layer includes an N substrate layer, an N drift layer, an N well layer, a P+ layer, and a P well layer, and the gate includes a gate cover layer and a gate nanosheet.

[0006] There are a plurality of gate nanosheets in each MOS cell, and the plurality of gate nanosheets are distributed in a horizontal matrix, the gate nanosheet extends to the inside of the gate cover layer and directly contacts it.

[0007] Further, the gate nanosheet is made of P-type polysilicon.

[0008] Further, the gate covering layer is made of one of titanium nitride or tungsten nitride.

[0009] Further, the inside of the N drift layer in a single MOS cell and directly below the gate nanosheet is formed with a P-type guard ring by ion implantation.

[0010] The number and position of the P-type guard ring only correspond to the number and position of the gate nanosheet in the middle region.

[0011] Further, the P-type guard ring further includes a convex guard ring.

[0012] Among them, the cross-sectional profile of all convex guard ring regions in a single MOS cell is in the shape of a middle downward convex.

[0013] Further, the inside of the N drift layer and below the convex guard ring is formed with an N+ covering layer by ion implantation, and the two ends of the N+ covering layer are in direct contact with the P well layer.

[0014] Further, both sides of the N substrate layer in a single MOS cell are provided with a P-type matrix region, which is composed of a plurality of P-type gates arranged in an array.

[0015] Further, the top end of the P-type gate extends to the inside of the N drift layer, and the bottom end of the P-type gate is in ohmic contact with the drain.

[0016] A manufacturing process of a MOSFET structure with a gate nanosheet, the specific steps including:

[0017] S1, taking an N-type substrate layer as a starting substrate, epitaxially growing an N drift layer and an N well layer thereon, and forming a P well layer and a P+ layer by ion implantation;

[0018] S2, depositing and patterning a sacrificial material layer on the epitaxial layer to define a plurality of channel regions distributed horizontally in a matrix; by selective epitaxy or deposition process, forming a semiconductor material layer which is a gate nanosheet in the channel region, and making it suspended over the epitaxial layer by etching process;

[0019] S3, growing a gate oxide layer on the surface of the suspended semiconductor material layer in full area; then depositing a conductive material of the gate nanosheet to fill and wrap the suspended structure, and removing the excess material by back etching process;

[0020] S4, depositing a material of a gate cover layer on the structure containing the gate nanosheet; patterning the gate cover layer through a photolithography and etching process, ensuring that the end of the gate nanosheet extends and is embedded into the patterned gate cover layer to form direct electrical and physical contact with the gate cover layer;

[0021] S5, forming ohmic contact regions of the source and the drain on both sides of the gate structure through an ion implantation and annealing process;

[0022] S6, depositing an interlayer dielectric layer, forming a contact hole through photolithography and etching, and depositing a metal to fill the contact hole, and finally forming the source, the drain and the gate cover layer.

[0023] The MOSFET structure with a gate nanosheet and the manufacturing process thereof provided by the application have the following effects compared with the prior art:

[0024] 1. The three-dimensional embedded contact of the horizontally matrix-distributed nanosheet gate and the high-conductivity cover layer significantly enhances the channel electrostatic control capability, reduces the gate resistance, realizes higher current driving density and better switching characteristics, and breaks through the physical limitation of the traditional planar device.

[0025] 2. The P-type guard ring selectively arranged in the application cooperates with the convex structure to optimize the drift region electric field distribution, accurately suppresses the electric field peak below the gate nanosheet, improves the device voltage withstand capability while avoiding additional loss of on-resistance, and solves the local breakdown risk of the high-density nanosheet array.

[0026] 3. The N+ cover layer and the convex guard ring constitute the carrier "shunting-shielding" double mechanism, which accelerates the electron to pass through the high-voltage drift region to reduce the dynamic resistance, eliminates the floating effect by connecting the P-well layer, and significantly improves the switching stability and high-frequency response characteristics of the device.

[0027] 4. The arrayed P-type matrix region reconstructs the terminal electric field distribution of the device, disperses the edge electric field peak to eliminate the terminal breakdown risk, provides vertical current bypass to reduce the overall on-resistance, and uses the array heat dissipation advantage to improve the reliability under large current working conditions.

[0028] 5. The application realizes high-precision manufacturing of complex three-dimensional structures through the synergistic innovation of sacrificial layer release, full-surrounding gate integration and customized doping through the whole process flow, guarantees the process compatibility, and provides a solution with high density, high voltage withstand and low loss for high-voltage and high-power applications. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 is a schematic diagram of the first embodiment in the application;

[0030] Figure 2A schematic diagram of Example Two in the present application;

[0031] Figure 3 A schematic diagram of Example Three in the present application;

[0032] Figure 4 A schematic diagram of Example Four in the present application;

[0033] Figure 5 A schematic diagram of Example Five in the present application.

[0034] In the figure: 1, drain; 2, gate cover layer; 3, gate nanosheet; 4, gate oxide layer; 5, source; 6, N substrate layer; 7, N drift layer; 8, N well layer; 9, P+ layer; 10, P well layer; 11, P type guard ring; 12, N+ cover layer; 13, P type matrix area; 1101, convex guard ring. DETAILED DESCRIPTION

[0035] In order to make the technical scheme of the present application clearer, the present application will be further described in detail below in combination with the drawings and specific examples.

[0036] As shown in the figure, a manufacturing process of a MOSFET structure with a gate nanosheet, the specific steps include: Figure 1 Step one, taking the N type substrate layer 6 as the starting substrate, sequentially epitaxially growing the N drift layer 7 and the N well layer 8 thereon, and forming the P well layer 10 and the P+ layer 9 through ion implantation; forming an optimized carrier concentration distribution on the N substrate 6 through sequential epitaxial growth (N drift layer 7 to N well layer 8) and selective ion implantation (P well layer 10 or P+ layer 9), to provide a low defect substrate for the nanosheet channel, and at the same time lay the foundation for the device voltage resistance and conduction characteristics.

[0037] Step two, depositing and patterning a sacrificial material layer on the epitaxial layer to define a number of channel regions in horizontal matrix distribution; through a selective epitaxial or deposition process, forming a semiconductor material layer in the channel region which will be used as the gate nanosheet 3 later, and through an etching process, making it suspended above the epitaxial layer; the sacrificial layer patterning precisely defines the horizontal matrix channel position, and the selective epitaxy / deposition ensures the lattice quality of the nanosheet material (which will be converted into the gate nanosheet 3 later); the suspended etching releases the channel region, creating physical space for the full-surrounding gate oxide layer wrapping, and breaking through the limitation of the planar structure.

[0038] Step three, forming a gate oxide layer 4 on the surface of the epitaxial layer and the suspended nanosheet material, and through a selective etching process, making the gate oxide layer 4 wrap around the suspended nanosheet material; the selective etching process ensures the gate oxide layer 4 to wrap around the suspended nanosheet material, and the suspended nanosheet material is converted into the gate nanosheet 3.

[0039] Step 3: A gate oxide layer 4 is grown over the entire surface of the suspended semiconductor material layer; then, conductive material of the gate nanosheet 3 is deposited to fill and encapsulate the suspended structure, and excess material is removed by an etch-back process; the gate oxide layer 4 is grown on the surface of the suspended nanosheet to achieve uniform dielectric isolation; P-type polycrystalline silicon is filled and encapsulated to form the conductive body of the gate nanosheet 3; the etch-back process precisely controls the thickness / morphology of the nanosheet, and simultaneously ensures the channel electrostatic control force and carrier mobility.

[0040] Step 4: Deposit the material of the gate capping layer 2 on the structure containing the gate nanosheet 3; pattern the gate capping layer 2 through photolithography and etching processes to ensure that the ends of the gate nanosheet 3 extend and are embedded into the patterned gate capping layer 2, forming direct electrical and physical contact with it; the deposition of titanium nitride / tungsten nitride gate capping layer 2 provides a highly conductive path; photolithography-etching patterning embeds the ends of the nanosheets into the capping layer, forming a nanoscale ohmic contact, significantly reducing the gate resistance (>30% lower than traditional interfaces), and has strong process compatibility.

[0041] Step 5: Through ion implantation and annealing processes, ohmic contact regions of source 5 and drain 1 are formed on both sides of the gate structure; ion implantation is performed using the gate structure as a mask to ensure that source 5 / drain 1 is precisely aligned with the channel; the annealing process simultaneously activates impurities and repairs damage, forming an ohmic junction with low contact resistance, and completing the electrical activation of customized doped structures such as the guard ring (11 / 1101).

[0042] Step 6: Deposit the interlayer dielectric layer and form contact holes through photolithography and etching, then deposit metal to fill the contact holes, ultimately forming the source 5, drain 1, and gate capping layer 2. Interlayer dielectric planarization avoids topological differences; photolithography of the contact holes precisely exposes the key nodes of the source / drain / gate capping layer 2; metal filling forms a low-resistance interconnect network, continuing the low-resistance advantage of the gate capping layer, ultimately achieving high-efficiency output of device performance.

[0043] Example 1

[0044] like Figure 1 As shown, according to one aspect of the present invention, a MOSFET structure with gate nanosheets is provided, comprising a plurality of parallel MOSFET cells. Each MOSFET cell includes a drain 1, a semiconductor epitaxial layer, a gate, a gate oxide layer 4, and a source 5. The semiconductor epitaxial layer includes an N-substrate layer 6, an N-drift layer 7, an N-well layer 8, a P+ layer 9, and a P-well layer 10. The gate includes a gate capping layer 2 and gate nanosheets 3. Each MOSFET cell contains a plurality of gate nanosheets 3, which are arranged in a horizontal matrix. The gate nanosheets 3 extend into and directly contact the interior of the gate capping layer 2. The gate nanosheets 3 are made of P-type polycrystalline silicon. The gate capping layer 2 is made of either titanium nitride or tungsten nitride.

[0045] Three-dimensional electrical contacts are formed by embedding titanium nitride and tungsten nitride gate capping layers 2 with horizontally matrix-distributed P-type polycrystalline silicon gate nanosheets 3. The nanosheet-encircled structure provides stronger channel electrostatic control, thereby enhancing gate control capability. Direct contact between the nanosheets and the highly conductive capping layer reduces current path impedance and thus lowers contact resistance; the horizontal matrix distribution enables higher drive current per unit area, thereby increasing integration density.

[0046] Example 2

[0047] like Figure 2 As shown, a P-type guard ring 11 is formed inside the N-drift layer 7 in a single MOS cell and directly below the gate nanosheet 3 through ion implantation; the number and position of the P-type guard ring 11 correspond one-to-one with the number and position of the gate nanosheet 3 in the middle region.

[0048] A P-type guard ring 11 is selectively implanted into the N-drift layer 7 directly beneath the central gate nanosheet to form a local charge balance region. This design suppresses electric field spikes beneath the central nanosheet, optimizes the electric field distribution, and avoids local breakdown, thus homogenizing the cell breakdown voltage and improving breakdown voltage capability. Moreover, it targets only the central nanosheet region with high electric field risk, avoiding excessive sacrifice of on-resistance.

[0049] Example 3

[0050] like Figure 3 As shown, a P-type guard ring 11 is formed by ion implantation inside the N-drift layer 7 in a single MOS cell and directly below the gate nanosheet 3; the number and position of the P-type guard ring 11 correspond one-to-one with the number and position of the gate nanosheet 3 in the middle region. The P-type guard ring 11 also includes a convex guard ring 1101; wherein, the cross-sectional profile of all convex guard ring 1101 regions in a single MOS cell is convex downward in the middle.

[0051] The P-type guard ring 11 is designed as a downwardly convex guard ring 1101, forming a three-dimensional charge compensation structure. The convex profile expands the depletion region volume, more effectively dispersing the electric field, and the curved junction depth improves the carrier extraction efficiency in the drift region to enhance carrier control. This is achieved by adjusting the ion implantation angle / energy, without the need for an additional mask.

[0052] Example 4

[0053] like Figure 4As shown, a P-type guard ring 11 is formed by ion implantation inside the N-drift layer 7 and directly below the gate nanosheet 3 in a single MOS cell. The number and position of the P-type guard rings 11 correspond one-to-one with the number and position of the gate nanosheets 3 in the middle region. The P-type guard ring 11 also includes a convex guard ring 1101; wherein, the cross-sectional profile of all convex guard ring 1101 regions in a single MOS cell is convex downward in the middle. An N+ capping layer 12 is formed by ion implantation inside the N-drift layer 7 and below the convex guard ring 1101, and the two ends of the N+ capping layer 12 are in direct contact with the P-well layer 10.

[0054] An N+ capping layer 12 is injected below the convex guard ring 1101, with its two ends connected to the P-well layer 10 to form a carrier acceleration channel. The N+ capping layer 12 provides a low-resistance path, accelerates electrons through the high-voltage drift region to achieve dynamic resistance optimization, and the P-well connection at both ends avoids the floating effect, improves switching stability to suppress parasitic effects; and this design, together with the convex guard ring, constitutes a dual mechanism of "electric field shielding-carrier conduction".

[0055] Example 5

[0056] like Figure 5 As shown, a P-type matrix region 13 is provided in a single MOS cell on both sides of the N substrate layer 6. The P-type matrix region 13 is composed of several P-type gates arranged in an array. The top of the P-type gate extends into the interior of the N drift layer 7, and the bottom of the P-type gate is in 1-ohm contact with the drain.

[0057] An array of P-type matrix regions 13 is constructed on both sides of the N substrate (6), with the top of the P-type gate extending to the N drift layer 7 and the bottom end connected to the drain 1. The P-type matrix region 13 disperses the edge electric field, eliminating the risk of terminal breakdown; and the P-type gate provides vertical current bypass, reducing the overall on-resistance and thus improving the conduction characteristics; and this array distribution avoids local heat concentration, enhancing the reliability of high current.

[0058] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A MOSFET structure with gate nanosheet, comprising a plurality of mutually juxtaposed MOS cells, a single MOS cell comprising a drain (1), a semiconductor epitaxial layer, a gate, a gate oxide layer (4) and a source (5), the semiconductor epitaxial layer comprising an N substrate layer (6), an N drift layer (7), an N well layer (8), a P+ layer (9) and a P well layer (10), characterized in that: The gate comprises a gate cover layer (2) and a gate nanosheet (3); The gate nanosheet (3) in a single MOS cell is in a horizontal matrix distribution, and extends to the inside of the gate cover layer (2) and directly contacts the gate cover layer (2).

2. The MOSFET structure with gate nanosheets of claim 1, wherein: The gate nanosheet (3) is made of P-type polysilicon.

3. The MOSFET structure with gate nanosheets of claim 1, wherein: The gate cover layer (2) is made of one of titanium nitride and tungsten nitride.

4. The MOSFET structure with gate nanosheets of claim 1, wherein: The inside of the N drift layer (7) in a single MOS cell and directly below the gate nanosheet (3) is formed with a P-type guard ring (11) through ion implantation. The number and position of the P-type guard ring (11) correspond to the number and position of the gate nanosheet (3) in the middle region one by one.

5. The MOSFET structure with gate nanosheets of claim 4, wherein: The P-type guard ring (11) further comprises a convex guard ring (1101). The cross-sectional profile of all convex guard ring (1101) regions in a single MOS cell is convex downward in the middle.

6. The MOSFET structure with gate nanosheets of claim 5, wherein: The inside of the N drift layer (7) and below the convex guard ring (1101) is formed with an N+ cover layer (12) through ion implantation, and the two ends of the N+ cover layer (12) directly contact the P-well layer (10).

7. The MOSFET structure with gate nanosheets of claim 1, wherein: Both sides of the N substrate layer (6) in a single MOS cell are provided with a P-type matrix area (13), which is composed of a plurality of P-type gates arranged in an array.

8. The MOSFET structure with gate nanosheets of claim 7, wherein: The top end of the P-type gate extends to the inside of the N drift layer (7), and the bottom end of the P-type gate is in ohmic contact with the drain (1).

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