A planar siC mosfet integrated with a reverse freewheeling diode

Abstract

The application discloses a planar SiC MOSFET integrated with a reverse freewheeling diode, and belongs to the technical field of semiconductors. The gate of the device is a split gate structure, the gate polysilicon is divided into left and right parts through source polysilicon, and an additional P-shield area is added at the bottom, and the source polysilicon is connected with the P-shield area through a through freewheeling tube oxide. The structure makes the channel diode integrated at the bottom of the planar structure oxide replace the body diode as the freewheeling diode in the device, reduces the bipolar degradation effect caused by the combination of electrons and holes in the traditional SiC MOSFET, and the opening voltage drop of the freewheeling diode is smaller than that of the body diode, thereby reducing the power consumption of the circuit system. The split gate structure of the application replaces the traditional whole gate structure, reduces the directly opposite area of the capacitor between the gate and the drain, improves the capacitor characteristics and the Miller effect of the device, and reduces the switching loss and switching time of the device.

Description

Technical Field

[0001] This invention relates to a planar SiC MOSFET with an integrated reverse freewheeling diode, belonging to the field of semiconductor technology. Background Technology

[0002] Third-generation semiconductor materials, represented by silicon carbide (SiC), have entered the market due to their superior material properties. Compared to traditional Si-based semiconductors, SiC MOSFETs have higher breakdown voltage, higher stability, higher thermal conductivity, and a wider bandgap, and are increasingly widely used today.

[0003] Compared to trench SiC MOSFETs, planar SiC MOSFETs have a more mature and simpler manufacturing process, eliminating the need for additional trench etching on the SiC crystal. The trench quality of trench-type SiC MOSFETs largely determines various device characteristics, such as breakdown voltage, switching life, gate charge, and on-resistance. This poses significant technical challenges for many companies, which is why planar SiC MOSFETs still dominate the commercial SiC MOSFET market. Furthermore, planar MOSFETs do not require consideration of high impact ionization and high electric field strength at the trench gate corners when facing high forward bias voltages, thus often exhibiting higher voltage withstand levels. Therefore, in the 3000V–4500V range, planar SiC MOSFETs are more competitive and fully capable of replacing Si IGBTs as ideal high-voltage power switching devices.

[0004] As switching devices, freewheeling diodes are often needed in circuits due to oscillations or voltage spikes to prevent device degradation. Currently, there are several methods for using freewheeling diodes: 1. Connecting the diode in parallel with the circuit. However, this increases the associated switching capacitor and gate charge degradation, increasing the overall energy loss of the circuit. 2. Integrating the freewheeling diode and MOSFET into a single package. However, this reduces chip area utilization and increases the device's reliability due to additional current leakage caused by multiple system integrations. 3. Utilizing the parasitic body diode inherent in the switching element as a freewheeling diode for reverse voltage. However, for traditional SiC MOSFETs, the use of a body diode introduces several characteristics: First, the threshold voltage of the SiC MOSFET's body diode is relatively high, approximately 3V, increasing additional energy consumption and decreasing energy utilization. Second, the conduction of the body diode can lead to bipolar degradation of the device. This is because electron-hole recombination increases defects within the SiC material, causing doped regions to drift, resulting in a permanent increase in various leakage currents of the MOSFET, ultimately leading to permanent damage and failure.

[0005] Furthermore, in traditional planar switching transistors, the high impact ionization and electric field concentration at the gate oxide-JFET interface under high forward bias voltages lead to premature breakdown of the oxide dielectric under high fields and degradation of the device's static characteristics over long-term use. Moreover, in power MOSFETs, during the process of applying charge to the gate and turning it on, the presence of the gate-drain capacitance (Miller capacitance) between the input and output results in the capacitor being charged before the device turns on. This causes a prolonged plateau voltage during the turn-on process, increasing switching energy loss and negatively impacting the device's performance. Summary of the Invention

[0006] To address the various problems arising from the use of parasitic freewheeling diodes in traditional planar SiC MOSFET structures, this invention proposes a planar SiC MOSFET with an integrated reverse freewheeling diode. The gate of this planar SiC MOSFET device is a split-gate structure, with the polysilicon connected to the gate divided into left and right parts by the polysilicon connected to the source. An additional P-shield region is added to the bottom of the freewheeling diode oxide below the polysilicon connected to the source, and the polysilicon connected to the source is connected to the P-shield region through the freewheeling diode oxide. The thickness of the freewheeling diode oxide below the polysilicon connected to the source is less than the thickness of the channel oxide below the polysilicon connected to the gate.

[0007] Optionally, the cell structure of the planar SiC MOSFET includes, from bottom to top, a drain metal 1, a first conductivity type substrate layer 2, a first conductivity type epitaxial layer 3, a JFET region 4, and a source metal 13.

[0008] The JFET region 4 is symmetrically provided with a P-base region 11, a P-plus region 10, and an N-plus region 9 above it. The JFET region 4 is provided with a P-shield region 5 in the middle above it. The left P-plus region 10 is located to the upper left of the left P-base region 11. The left N-plus region 9 is located above the left P-base region 11, and the right side and bottom of the left N-plus region 9 are wrapped by the left P-base region 11. The left side of the left N-plus region 9 is in contact with the left P-plus region 10. The right P-base region 11, the right P-plus region 10, and the right N-plus region 9 are symmetrically arranged with the left side.

[0009] The P-shield region 5 is located at the top center of the JFET region 4;

[0010] The left-side channel oxide 8 is located above the left-side N-plus region 9, the left-side P-base region 11, and the JFET region 4; the right-side channel oxide 8 is symmetrically arranged with the left-side channel oxide 8;

[0011] The left gate polysilicon 7 is located above the left channel oxide 8; the right gate polysilicon 7 is located above the right channel oxide 8;

[0012] The left and right freewheeling tube oxides 12 are located above the P-shield region 5;

[0013] The source polysilicon 6 is located above the P-shield region 5 and the freewheeling oxide 12. The bottom of the freewheeling oxide 12 is connected to the P-shield region 5, and the top of the blocking oxide 14 is connected to the source metal 13.

[0014] The blocking oxide 14 is divided into two parts, left and right, after being penetrated by the top of the source polysilicon 6. The left blocking oxide 14 is located above, to the left and to the right of the left gate polysilicon 7; the right blocking oxide is located above, to the left and to the right of the right gate polysilicon 7.

[0015] The source metal 13 is located above the P-plus region 10, the N-plus region 9, the blocking oxide 14, and the source polysilicon 6.

[0016] Optionally, the oxide below the gate polysilicon 7 is a channel oxide 8, and the oxides at other locations around it are blocking oxides 14. The thickness of the blocking oxide 14 is greater than the thickness of the channel oxide 8; the thickness of the channel oxide 8 is greater than the thickness of the freewheeling diode oxide 12.

[0017] Optionally, the thickness of the channel oxide 8 is 40 nm to 100 nm, the thickness of the freewheeling oxide 12 is 10 nm to 40 nm, and the thickness of the blocking oxide 14 is 0.5 to 5 μm.

[0018] Optionally, the contact hole length between the source metal 13 and the source polycrystalline silicon 6 is 1μm to 5μm.

[0019] Optionally, the contact hole length between the P-shield region 5 and the source polysilicon 6 is 0.4 μm to 1 μm.

[0020] Optionally, the width of the P-shield region 5 is 1μm to 2μm, and the thickness is 0.5μm to 1μm; the distance between the P-shield region 5 and the two P-base regions 11 is 1μm to 5μm.

[0021] Optionally, the width of one side of the freewheeling tube oxide 12 is 0.5 μm to 1 μm.

[0022] Optionally, the P-shield region 5 is p-type doped, the doping element is Al, and the doping concentration is 1×10⁻⁶. 17 ~1×10 19 cm -3 Furthermore, the doping concentration in the middle part is higher than that at the top and bottom ends.

[0023] This application also provides a method for fabricating a planar SiC MOSFET device with an integrated reverse freewheeling diode, the method comprising:

[0024] A substrate 2 of the first conductivity type is provided, and an epitaxial layer 3 of the first conductivity type is grown thereon.

[0025] A JFET region 4 is grown on the surface of the first conductivity type epitaxial layer 3;

[0026] Using photoresist as a mask, Al ions are implanted into the JFET region 4 to form the P-base region 11;

[0027] Using photoresist as a mask, N ions are implanted into the P-base region 11 using an ion implantation process to form the N-plus region 9;

[0028] Using photoresist as a mask, Al ions are implanted into the JFET region 4 using an ion implantation process to form a P-shield region 5;

[0029] Using photoresist as a mask, contact holes are left on the top of the MOSFET between the source polysilicon 6 and the P-shield region 5. Dielectric material is deposited on the top of the MOSFET to form the freewheeling oxide 12. Using photoresist as a mask, dielectric material is deposited on the top of the MOSFET to increase its thickness and form the channel oxide 8.

[0030] Using photoresist as a mask, gate polysilicon 7 is deposited on the surface of the channel oxide 8;

[0031] Using photoresist as a mask, source polysilicon 6 is deposited on the surface of the freewheeling tube oxide 12;

[0032] Using photoresist as a mask, a dielectric material is deposited over the N-plus region 9, P-plus region 10, gate polysilicon 7, and channel oxide 8 to form a blocking oxide 14;

[0033] Using photoresist as a mask, the blocking oxide 14 was etched;

[0034] Metal is deposited on the top of the device as source metal 13, and metal is deposited on the bottom of the device as drain metal 1.

[0035] The beneficial effects of this invention are:

[0036] This invention provides a SiC planar power MOSFET device with a special structure. The device has a split gate structure, consisting of two parts: polysilicon connected to the source and polysilicon connected to the gate. An additional P-shield region is added to the bottom of the freewheeling oxide. The source polysilicon is connected to the P-shield region through the freewheeling oxide, and the thickness of the freewheeling oxide is significantly smaller than the thickness of the channel oxides at both ends. The above structure offers several advantages. First, it allows the channel diode integrated on the bottom of the planar oxide structure to replace the body diode as a freewheeling diode in the device, reducing the bipolar degradation effect caused by electron-hole recombination in commercial SiC MOSFETs. Furthermore, the turn-on voltage drop of the freewheeling diode is lower than that of the body diode, reducing system power consumption. Second, it replaces the original monolithic gate structure with a discrete gate structure, reducing the capacitance area between the gate and drain, improving the device's capacitance characteristics and Miller effect, and reducing switching losses and switching time. Third, by adding an additional P-shield region, this structure reduces the peak electric field at high voltages and optimizes the electric field distribution of the gate under forward withstand voltage, thereby extending device lifespan. Ultimately, without a significant increase in on-resistance, the breakdown voltage of the device is greatly improved, amplifying the performance of planar SiC MOSFETs. The characteristics of MOSFETs; Fourth, the additional P-shield region weakens the impact ionization of the oxide during long-term use, reduces the number of electrons or holes injected into the oxide under high field strength, weakens the performance degradation of the device under repeated avalanche, short circuit, etc., and improves the stability of the oxide above the JFET region of this device during long-term use, so that it can still maintain a high level of operation during long-term use. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a cell structure diagram of a traditional planar SiC MOSFET device;

[0039] Figure 2 This is a cell structure diagram of a SiC planar power MOSFET device with reverse freewheeling effect proposed in this invention.

[0040] Figures 3-7 This is a flowchart of the fabrication method of the device structure of the present invention;

[0041] Figures 1-7 In the diagram, 1—drain metal; 2—substrate of the first conductivity type; 3—epitaxy of the first conductivity type; 4—JFET region; 5—P-shield region; 6—source polysilicon; 7—gate polysilicon; 8—channel oxide; 9—N-plus region; 10—P-plus region; 11—P-base region; 12—freewheeling oxide; 13—source metal; 14—blocking oxide.

[0042] Figure 8 This is a comparison of the voltage-current characteristic curves and forward breakdown characteristic curves of the conventional structure and the structure of the present invention in the on state.

[0043] Figure 9 A comparison of voltage and current simulation results between the conventional structure and the structure of this invention when the freewheeling diode is in operation.

[0044] Figure 10 For reverse current I SD =100A / cm 2 The diagram shows the longitudinal distribution of hole concentration inside the conventional structure and the structure of this invention as a function of device depth.

[0045] Figure 11 This is a comparison chart of simulation results of the gate charge characteristics of the traditional structure and the structure of this invention.

[0046] Figure 12 For reverse current I SD =100A / cm 2 At that time, the voltage condition V of the conventional structure and the structure of the present invention. DS A comparison chart of the situations.

[0047] Figure 13 The input capacitance characteristics (C) of the conventional structure and the structure of the present invention are compared. ISS ), Output capacitor characteristics (C) OSS ) and transfer capacitance characteristics (C RSS The simulation results are compared.

[0048] Figure 14 This is a concentration distribution map of the P-shield region 5.

[0049] Figure 15 For reverse current I SD =100A / cm 2 The image shows a structural simulation comparison of the hole concentration distribution inside the device with the traditional structure and the structure of the present invention.

[0050] Figure 16 The traditional structure and the structure of the present invention are compared in terms of reverse current I. SD =100A / cm 2The current flow diagram. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0052] like Figure 1 The diagram shows the cell structure of a traditional planar SiC MOSFET device (a SiC MOSFET device is composed of multiple identical cells). It can be seen that in the traditional SiC MOSFET device structure, when the device is operating under reverse bias, a large amount of current flows through the parasitic body diode of the device. The recombination of holes and electrons in the P-base region 11 and the JFET region 4 of the device will increase the number of defects inside the SiC material and cause the doped region to drift. This will lead to an increase in MOSFET leakage current, causing permanent failure damage, ultimately affecting the service life of the switching device and bringing significant safety hazards.

[0053] Furthermore, when traditional planar SiC MOSFETs operate at high forward bias voltages, the collisional ionization rate and electric field concentration of the oxide dielectric above the JFET region are very high, which may lead to premature breakdown and performance degradation of the device during long-term operation.

[0054] Therefore, this application proposes a novel SiC planar power MOSFET device, which is described in detail below:

[0055] Example 1:

[0056] This embodiment provides a planar SiC MOSFET device with an integrated reverse freewheeling diode. The gate of this device has a split gate structure. The polysilicon connected to the gate is divided into left and right parts by the polysilicon connected to the source. An additional P-shield region is added to the bottom of the freewheeling diode oxide below the polysilicon connected to the source. The polysilicon connected to the source is connected to the P-shield region through the freewheeling diode oxide. The thickness of the freewheeling diode oxide below the polysilicon connected to the source is significantly smaller than the thickness of the channel oxide below the polysilicon connected to the gate.

[0057] For details, see Figure 2 The cell structure of the planar SiC MOSFET device includes, from bottom to top, a drain metal 1, a first conductivity type substrate layer 2, a first conductivity type epitaxial layer 3, a JFET region 4, and a source metal 13.

[0058] Above the JFET region 4 are P-base region 11, P-plus region 10, N-plus region 9, and P-shield region 5;

[0059] The P-shield region 5 is located at the top center of the JFET region 4;

[0060] The P-base region 11 is located at the top two ends of the JFET region 4. The P-plus region 10 and the N-plus region 9 are located adjacent to the top two ends of the P-base region 11 on both sides. The P-plus region 9 is located on the side away from the P-shield region, and the N-plus region 9 is located on the side closer to the P-shield region 5.

[0061] The channel oxide 8, blocking oxide 14, and freewheeling oxide 12 are located above the P-shield region 5, JFET region 4, P-base region 11, N-plus region 9, and P-plus region 10.

[0062] The gate polysilicon 7 is located above the channel oxide 8, and is surrounded by blocking oxide 14 on both sides and above; the source polysilicon 6 is located above the P-shield region 5 and the freewheeling oxide 12, with blocking oxide 14 on both sides, and the bottom is connected to the P-shield region 5 through the freewheeling oxide 12.

[0063] The source metal 13 is located above the P-plus region 10, the N-plus region 9, the blocking oxide 14, and the source polysilicon, and its top is connected to the source polysilicon 6 through the blocking oxide 14.

[0064] In the SiC planar power MOSFET device with the above structure, the contact hole length between the source metal 13 and the source polysilicon 6 is 1μm to 5μm; the contact hole length between the P-shield region 5 and the source polysilicon 6 is 0.4μm to 1μm.

[0065] The doping concentration of the first conductivity type substrate layer 2 is 8 × 10⁻⁶. 15 ~1×10 20 cm -3 The depth is 0.5–10 μm.

[0066] The doping concentration of the first conductivity type epitaxial layer 3 is 1×10⁻⁶. 14 ~1×10 16 cm -3 The thickness is 5–15 μm.

[0067] The doping concentration of JFET region 4 is 1×10⁻⁶. 14 ~1×10 17 cm -3 The thickness is 1–5 μm.

[0068] The doping concentration of P-shield region 5 is 1×10⁵. 17 ~1×10 19cm -3 The doping concentration in the middle part is higher than that at the top and bottom ends, and the thickness is 0.5 to 1 μm. The distance between the P-shield region 5 and the two P-base regions 11 is 1 μm to 5 μm.

[0069] The doping concentration of P-base region 11 is 1×10⁻⁶. 16 ~1×10 18 cm -3 The thickness is 0.5–2 μm.

[0070] The doping concentration of P-plus region 10 is 1×10⁻⁶. 18 ~1×10 20 cm -3 The thickness is 0.1–0.5 μm.

[0071] The doping concentration of N-plus region 9 is 1×10⁹. 18 ~1×10 20 cm -3 The thickness is 0.1–0.5 μm.

[0072] The thickness of the channel oxide 8 is 0.5–1 μm.

[0073] The oxide 12 of the freewheeling tube has a thickness of 0.1 to 0.5 μm and a length of 0.5 to 1 μm.

[0074] The doping concentration of the source polysilicon 6 is 1×10⁶. 18 ~1×10 20 cm -3 The thickness is 1 to 2 μm.

[0075] The doping concentration of the gate polysilicon 7 is 1×10⁻⁶. 18 ~1×10 20 cm -3 The thickness is 1 to 2 μm.

[0076] The thickness of the source metal 13 is 0.5–1.5 μm.

[0077] The thickness of the blocking oxide 14 is 0.5–5 μm.

[0078] The cell width of a single device is 1–5 μm.

[0079] The SiC planar power MOSFET device with the above structure has a freewheeling diode consisting of two parts:

[0080] The first part is a heterojunction diode formed by N-type source polysilicon 6 and JFET region 4 of SiC material, thereby realizing the integration of Si / SiC heterojunction diode in N-channel SiC planar power MOSFET.

[0081] The second part is the channel diode. When the device operates under reverse voltage, a channel is formed under the freewheeling oxide 12, thereby discharging the reverse transient current.

[0082] When a reverse voltage is applied to a SiC MOSFET device, the integrated freewheeling diode inside the device turns on, causing a change in the current flow direction of the traditional SiC MOSFET device:

[0083] like Figure 16 As shown in the left figure, the current flow of a traditional SiC MOSFET device is as follows: source metal 13 → P-source region 10 → P-base region 11 → JFET region 4 → first conductivity type epitaxial layer 3 → first conductivity type substrate 2 → drain metal 1.

[0084] like Figure 16 As shown in the right figure, the current flow inside the planar SiC MOSFET device of the present invention is as follows: source metal 13 → source polysilicon 6 → channel between P-shield region 5 and freewheeling oxide 12 → JFET region 4 → first conductivity type epitaxial layer 3 → first conductivity type substrate 2 → drain metal 1.

[0085] As can be seen, the freewheeling diode formed by the heterojunction diode (6) of the N-type source polysilicon and the JFET region 4 of SiC, and the channel diode, in this application shares the current that would normally flow through the parasitic diode within the SiC MOSFET device. In other words, the freewheeling diode within the device turns on earlier than the parasitic diode, thus suppressing the conduction of the parasitic diode and avoiding the bipolar degradation effect within the device. Simultaneously, the threshold voltage of the freewheeling diode is only about 1.5V, reducing the power loss of the circuit system. Furthermore, the gate polysilicon is etched to form source polysilicon and gate polysilicon, optimizing the input capacitance, Miller capacitance, and gate charge characteristics of the SiC MOSFET. Due to the presence of the gate-drain capacitance (Miller capacitance) between the input and output, the power MOSFET device experiences a Miller plateau during turn-on, increasing the switching energy loss of the device. The SiC MOSFET device structure provided in this application reduces the overlap area between the gate and drain, converting a portion of the gate-drain capacitance into source-drain capacitance, which greatly shortens the Miller plateau time of the device, effectively improves the switching characteristics, gate charge, and capacitance characteristics of the device, and ultimately reduces the switching time and switching losses of the device.

[0086] like Figure 2As shown, the SiC planar power MOSFET device designed in this application has a forward voltage drop of approximately 1.2V for the integrated Si / SiC heterojunction diode, which is much smaller than the forward voltage drop of the SiC MOSFET's body diode (3V). This allows the freewheeling diode in the SiC MOSFET to turn on earlier than the body diode during reverse breakdown, thus suppressing the body diode's conduction and avoiding reliability issues caused by body diode degradation. Furthermore, the reverse recovery characteristics of the SiC freewheeling diode are superior to those of the SiC MOSFET's body diode, specifically exhibiting faster switching response, lower reverse recovery current, and lower reverse recovery charge, which improves the device's switching speed.

[0087] Example 2

[0088] This embodiment provides a method for fabricating a SiC planar power MOSFET device with an integrated reverse freewheeling diode, used to fabricate the planar SiC MOSFET device with the reverse freewheeling diode described in Embodiment 1. See [link to previous embodiment]. Figures 3-7 The method includes:

[0089] like Figure 3 As shown, a doping concentration of 8×10 is provided. 15 ~1×10 20 cm -3 A first-conductivity type substrate 2 with a depth of 0.5–10 μm is used to grow a first-conductivity type epitaxial layer 3, the doping concentration of the first-conductivity type epitaxial layer 3 being 1 × 10⁻⁶. 14 ~1×10 16 cm -3 The thickness is 5–15 μm.

[0090] A JFET region 4 is grown on the surface of the first conductivity type epitaxial layer 3; the doping concentration of the JFET region 4 is 1×10⁻⁶. 14 ~1×10 17 cm -3 The thickness is 1–5 μm.

[0091] In the JFET region 4, Al ions are implanted using an ion implantation process to form a P-base region 11; the doping concentration of the P-base region 11 is 1×10⁻⁶. 16 ~1×10 18 cm -3 The thickness is 0.5–2 μm.

[0092] like Figure 4 As shown, photoresist is used as a mask, and Al ions are implanted into the P-base region 11 using an ion implantation process to form the P-plus region 10; the doping concentration of the P-plus region 10 is 1×10⁻⁶. 18 ~1×1020 cm -3 The thickness is 0.1–0.5 μm.

[0093] Using photoresist as a mask, N ions are implanted into the P-base region 11 using an ion implantation process to form the N-plus region 9; the doping concentration of the N-plus region 9 is 1×10⁻⁶. 18 ~1×10 20 cm -3 The thickness is 0.1–0.5 μm.

[0094] Using photoresist as a mask, Al ions are implanted into the JFET region 4 to form a P-shield region 5. The doping concentration of the P-shield region 5 is 1×10⁻⁶. 17 ~1×10 19 cm -3 The doping concentration in the middle part is higher than that at the top and bottom ends, the width is 1μm to 2μm, and the thickness is 0.5 to 1μm.

[0095] like Figure 5 As shown, using photoresist as a mask, contact holes for the source polysilicon 6 and the P-shield region 5 are left on the top of the MOSFET, with a contact hole length of 0.4 μm to 1 μm; a dielectric material is deposited on the top of the MOSFET to form a freewheeling diode oxide 12, with a thickness of 0.1 to 0.5 μm and a length of 0.5 to 1 μm; using photoresist as a mask, a dielectric material is deposited on the top of the MOSFET to increase its thickness, forming a channel oxide 8 with a thickness of 0.5 to 1 μm;

[0096] Using photoresist as a mask, gate polysilicon 7 is deposited on the surface of the channel oxide 8. The doping concentration of the gate polysilicon 7 is 1×10⁻⁶. 18 ~1×10 20 cm -3 The thickness is 1–2 μm;

[0097] like Figure 6 As shown, a source polysilicon 6 is deposited on the surface of the freewheeling diode oxide 12 using photoresist as a mask. The doping concentration of the source polysilicon 6 is 1×10⁻⁶. 18 ~1×10 20 cm -3 The thickness is 1–2 μm;

[0098] Using photoresist as a mask, a dielectric material is deposited over the N-plus region 9, P-plus region 10, gate polysilicon 7, and channel oxide 8 to form a blocking oxide 14, the thickness of which is 0.5 to 5 μm.

[0099] Photoresist is used as a mask to etch blocking oxide 14, which serves as a contact hole between the subsequent source metal 13 and the source polysilicon 6. The contact hole length is 1μm to 5μm.

[0100] Source metal 13 and drain metal 1 are formed.

[0101] The present invention adds a P-shield region 5 to the bottom of the oxide, the main advantages of which are:

[0102] 1. Solved the high electric field problem faced by SiC heterojunction diodes;

[0103] 2. It solves the problems of high field strength and high impact ionization faced by traditional planar SiC MOSFETs during forward operation, optimizes the electric field distribution of the gate oxide, and improves the reliability of the device during long-term use;

[0104] 3. Improved device switching speed and optimized gate charge characteristics;

[0105] 4. The thinner freewheeling diode oxide 12 is protected, so that it can protect the channel oxide 8 and the freewheeling diode oxide 12 while playing the role of the freewheeling diode channel.

[0106] Furthermore, by adjusting the doping concentration of the P-shield region, a higher concentration is achieved in the middle section and a lower concentration at the top and bottom ends. The lower concentration at the top and bottom ends ensures that the freewheeling diode can turn on before the parasitic diode when the diode is operating under reverse voltage. The higher concentration in the middle ensures that the structure of this invention can operate under forward high voltage bias, improving the electric field distribution of the freewheeling diode oxide, while also providing good protection for the gate oxide, preventing premature breakdown of the oxide and performance degradation.

[0107] like Figure 8 The figure shows a comparison of the voltage-current characteristic curves and breakdown characteristic curves of the conventional structure and the structure of the present invention in the on-state. It can be seen that the on-state current and forward breakdown voltage of the device with the improved structure of this application are significantly higher than those of the conventional device, especially in the case of R... on While maintaining the original level of the conduction characteristic curve, the BV breakdown characteristic curve has been significantly improved.

[0108] Figure 9 The figure shows a comparison of the reverse voltage and current simulation results of the conventional structure and the structure of the present invention when the integrated freewheeling diode is working. It can be seen that the reverse current of the structure of the present application at -3V is much greater than that of the conventional structure, and the freewheeling diode is in a fully turned-on state.

[0109] Figure 10 For reverse current I SD =100A / cm 2The diagram shows the longitudinal distribution of hole concentration in the device with varying device depth for both the conventional structure and the structure of this invention. It can be seen that the hole concentration distribution in the drift region of the structure of this application is much smaller than that of the conventional structure, which effectively reduces recombination in the device drift region and increases the reliability of the device.

[0110] Figure 11 The figure shows a comparison of simulation results of the gate charge characteristics of the conventional structure and the structure of the present invention. It can be seen that the Miller plateau of the gate charge curve of the structure of the present application is smaller than that of the conventional structure, which can reduce the switching loss of the device, shorten the turn-on time, and improve the switching performance of the device.

[0111] Figure 12 For reverse current I SD =100A / cm 2 At that time, the voltage condition V of the conventional structure and the structure of the present invention. DS The comparison diagram shows that the reverse voltage required for the structure of this application to reach the target current is about 1.5V, which is less than the 2.8V of the traditional structure. This suppresses the conduction of the body diode of the device and reduces the energy loss of the device in reverse conduction.

[0112] Figure 13 The input capacitance characteristics (C) of the conventional structure and the structure of the present invention are compared. ISS ), Output capacitor characteristics (C) OSS ) and transfer capacitance characteristics (C RSS The simulation results are compared; it can be seen that the CV characteristics of the structure in this application are significantly better than those of the traditional structure.

[0113] Figure 14 The concentration distribution diagram of P-shield region 5 shows that the concentration distribution of the structure in this application is characterized by a higher concentration in the middle region and a lower concentration at both ends. This ensures both a low threshold voltage for the freewheeling diode and that the P-shield region 5 can optimize the electric field distribution of the oxide above the JFET region 4 when the device is off.

[0114] Figure 15 For reverse current I SD =100A / cm 2 The diagram shows a comparison of the hole concentration distribution inside the device with the conventional structure and the structure proposed in this invention (the left diagram corresponds to the conventional structure, and the right diagram corresponds to the structure proposed in this invention). It can be seen that the hole concentration in the drift region of the structure proposed in this application is less than that of the conventional structure under the target current. Therefore, it reduces the bipolar degradation effect caused by the recombination of electrons and holes in commercial planar SiC MOSFETs and avoids possible permanent damage and failure.

[0115] Figure 16 The traditional structure and the structure of the present invention are compared in terms of reverse current I. SD=100A / cm 2 The current flow diagrams (the left side shows the current flow diagram corresponding to the conventional structure, and the right side shows the current flow diagram corresponding to the structure of this invention) show that, due to the presence of the freewheeling diode, the reverse current no longer flows out through the body diode, effectively protecting the body diode area of ​​the device, improving the reliability of the device, and extending the service life of the device.

[0116] Some steps in the embodiments of the present invention can be implemented using software, and the corresponding software program can be stored in a readable storage medium, such as an optical disc or a hard disk.

[0117] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A planar SiC MOSFET device with an integrated reverse freewheeling diode, characterized in that, The gate of the planar SiC MOSFET device is a split gate structure. The polysilicon connected to the gate is divided into left and right parts by the polysilicon connected to the source. An additional P-shield region is added to the bottom of the freewheeling oxide below the polysilicon connected to the source. The polysilicon connected to the source is connected to the P-shield region through the freewheeling oxide. The thickness of the freewheeling oxide below the polysilicon connected to the source is less than the thickness of the channel oxide below the polysilicon connected to the gate. The cell structure of the planar SiC MOSFET includes a drain metal (1), a first conductivity type substrate layer (2), a first conductivity type epitaxial layer (3), a JFET region (4), and a source metal (13) stacked sequentially from bottom to top. The JFET region (4) is symmetrically provided with a P-base region (11), a P-plus region (10), and an N-plus region (9) on the left and right sides above it. The JFET region (4) is provided with a P-shield region (5) in the middle above it. The left P-plus region (10) is located above the left P-base region (11) on the left. The left N-plus region (9) is located above the left P-base region (11), and the right side and bottom of the left N-plus region (9) are wrapped by the left P-base region (11). The left side of the left N-plus region (9) is in contact with the left P-plus region (10). The right P-base region (11), the right P-plus region (10), and the right N-plus region (9) are symmetrically provided with the left side. The P-shield region (5) is located at the top center of the JFET region (4); The left channel oxide (8) is located above the left N-plus region (9), the left P-base region (11), and the JFET region (4); the right channel oxide (8) is symmetrically arranged with the left channel oxide (8); The left gate polysilicon (7) is located above the left channel oxide (8); the right gate polysilicon (7) is located above the right channel oxide (8); The oxide (12) of the left and right freewheeling tubes is located above the P-shield region (5); The source polycrystalline silicon (6) is located above the P-shield region (5) and the freewheeling oxide (12). The bottom of the freewheeling oxide (12) is connected to the P-shield region (5), and the top of the blocking oxide (14) is connected to the source metal (13). The blocking oxide (14) is divided into two parts after being penetrated by the top of the source polysilicon (6). The left blocking oxide (14) is located above, to the left and to the right of the left gate polysilicon (7); the right blocking oxide is located above, to the left and to the right of the right gate polysilicon (7). The source metal (13) is located above the P-plus region (10), the N-plus region (9), the blocking oxide (14), and the source polysilicon (6).

2. The planar SiC MOSFET device according to claim 1, characterized in that, The oxide below the gate polysilicon (7) is the channel oxide (8), and the oxides at other locations around it are the blocking oxides (14). The thickness of the blocking oxide (14) is greater than the thickness of the channel oxide (8); the thickness of the channel oxide (8) is greater than the thickness of the freewheeling oxide (12).

3. The planar SiC MOSFET device according to claim 2, characterized in that, The thickness of the channel oxide (8) is 40 nm to 100 nm, the thickness of the freewheeling oxide (12) is 10 nm to 40 nm, and the thickness of the blocking oxide (14) is 0.5 to 5 μm.

4. The planar SiC MOSFET device according to claim 3, characterized in that, The contact hole length between the source metal (13) and the source polycrystalline silicon (6) is 1μm to 5μm.

5. The planar SiC MOSFET device according to claim 4, characterized in that, The contact hole length between the P-shield region (5) and the source polycrystalline silicon (6) is 0.4 μm to 1 μm.

6. The planar SiC MOSFET device according to claim 5, characterized in that, The width of the P-shield region (5) is 1μm to 2μm and the thickness is 0.5μm to 1μm; the distance between the P-shield region (5) and the two P-base regions (11) is 1μm to 5μm.

7. The planar SiC MOSFET device according to claim 6, characterized in that, The width of one side of the freewheeling tube oxide (12) is 0.5μm to 1μm.

8. The planar SiC MOSFET device according to claim 7, characterized in that, The P-shield region (5) is doped with P-type doping, the doping element is Al, and the doping concentration is 1×10⁻⁶. 17 ~1×10 19 cm -3 Furthermore, the doping concentration in the middle part is higher than that at the top and bottom ends.

9. A method for fabricating a planar SiC MOSFET device with an integrated reverse freewheeling diode as described in any one of claims 1-8, characterized in that, The method includes: Provide a substrate of the first conductivity type (2) and grow an epitaxial layer of the first conductivity type (3); A JFET region (4) is grown on the surface of the first conductivity type epitaxial layer (3); Using photoresist as a mask, Al ions are implanted in the JFET region (4) to form a P-base region (11). Using photoresist as a mask, N ions are implanted in the P-base region (11) to form the N-plus region (9). Using photoresist as a mask, Al ions are implanted into the JFET region (4) to form a P-shield region (5) by ion implantation. Using photoresist as a mask, a contact hole is left on the top of the MOSFET between the source polysilicon (6) and the P-shield region (5). Dielectric material is deposited on the top of the MOSFET to form a freewheeling oxide (12). Using photoresist as a mask, dielectric material is deposited on the top of the MOSFET to increase its thickness and form a channel oxide (8). Using photoresist as a mask, gate polysilicon (7) is deposited on the surface of the channel oxide (8). Using photoresist as a mask, source polysilicon (6) is deposited on the surface of the freewheeling tube oxide (12). Using photoresist as a mask, dielectric material is deposited over the N-plus region (9), P-plus region (10), gate polysilicon (7), and channel oxide (8) to form a blocking oxide (14). Using photoresist as a mask, the blocking oxide was etched (14). Metal is deposited on the top of the device as the source metal (13), and metal is deposited on the bottom of the device as the drain metal (1).

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