A neural network-based method for predicting the capacitance characteristics of SiC MOSFETs

Abstract

The SiC MOSFET capacitance characteristic prediction method based on a neural network comprises the following steps: step 1: for the capacitance characteristics of a SiC MOSFET device, a C-V capacitance-voltage relationship dataset is constructed, the corresponding relationship data between voltage and capacitance is obtained by simulating and sampling the junction capacitance of the SiC MOSFET under different bias voltage conditions; step 2: the corresponding relationship data is used as the dataset of the neural network of the experiment, and the dataset of the neural network is randomly divided into a training set, a validation set and a test set; step 3: a neural network prediction model for predicting the capacitance characteristics of the SiC MOSFET is constructed; step 4: the neural network prediction model constructed above is trained using the training set and the validation set; and step 5: the V GS , V GD voltage two characteristic variable parameters of the test set are input into the trained neural network prediction model to realize the prediction of the capacitance characteristics of the SiC MOSFET. The present application has the characteristics of high prediction accuracy, low dependence on experimental data and high efficiency.

Description

Technical Field

[0001] This invention belongs to the field of SiC MOSFET capacitance characteristic prediction technology, specifically relating to a method for predicting SiC MOSFET capacitance characteristics based on neural networks. Background Technology

[0002] With the development of power electronics technology towards higher frequencies, smaller sizes, and higher power densities, SiC MOSFETs, with their high breakdown electric field, low on-resistance, and excellent switching characteristics, have become core devices in next-generation power conversion systems. In power electronic circuit design, the capacitive characteristics of SiC MOSFETs (such as input capacitance C) are crucial. ISS Output capacitor C OSS and reverse transfer capacitor C RSS Junction capacitance (JFC) is a key physical parameter that determines system switching losses, electromagnetic interference performance, and drive circuit design. Especially during high-frequency switching, the nonlinear characteristics of JFC as a function of drain-source voltage directly affect the voltage rise rate (dv / dt) and current rise rate (di / dt), which in turn affect the energy conversion efficiency and electromagnetic compatibility stability of the entire power electronic system.

[0003] Currently, the acquisition and research of the capacitance characteristics of SiC MOSFETs mainly rely on traditional experimental measurement methods and analytical models based on semiconductor physical structures. While traditional experimental measurement methods can directly obtain data, they suffer from significant efficiency and cost bottlenecks. Such experiments typically require high-precision LCR meters, high-voltage bias power supplies, and dedicated semiconductor parameter analyzers, resulting in extremely high equipment purchase and laboratory maintenance costs. Because the junction capacitance of SiC MOSFETs exhibits drastic nonlinear fluctuations across orders of magnitude with voltage, experiments must perform extremely precise voltage step scans, leading to lengthy single test cycles. Furthermore, experimental methods struggle to cover the complex operating conditions in real-world applications, and frequent repetitive experiments consume substantial human, material, and time resources for large-scale device consistency screening. In addition, analytical model prediction methods based on physical structures also face significant challenges in practical applications. The internal junction structure of SiC MOSFETs is complex, and manufacturing process parameters are often core secrets of manufacturers, making it difficult for external researchers to obtain accurate underlying physical parameters. To achieve mathematical solutions, these models often have to make a lot of physical simplifications and idealizations, ignoring the effects of parasitic inductance, interface state traps, and multi-physics coupling. This results in a large deviation between the predicted results and the actual measured values ​​in the region of drastic nonlinear changes, making it impossible to provide reliable data support for high-precision circuit simulation.

[0004] The high cost of experimental equipment and samples: Current methods for obtaining the capacitance characteristics of SiC MOSFETs primarily rely on high-precision junction capacitance testing experiments. These experiments require expensive semiconductor parameter analyzers, high-voltage bias units, and specialized instruments such as LCR meters capable of maintaining high resolution under high voltage. Furthermore, the junction capacitance of a SiC MOSFET varies with the drain-source voltage Vd. DS Gate-source voltage V GS The capacitance exhibits dramatic nonlinear changes. To obtain a complete capacitance characteristic curve, a large number of repetitive experiments are required on devices of different specifications and batches. This leads to expensive instrument depreciation costs and device sample losses, making the economic cost of obtaining capacitance data remain high.

[0005] Inefficiency and incomplete data coverage: Traditional research methods typically employ analytical models to assist experimental verification. However, the junction capacitance of SiC MOSFETs is affected by a variety of complex factors, including internal doping concentration distribution, chip structure parameters, and process variations. Analytical models based on semiconductor physics often require idealization and simplification, making it difficult to accurately reproduce the true capacitance characteristics of devices under high-voltage or high-temperature dynamic environments. In practical applications, whenever the device model is changed or the operating environment changes, tedious wiring, calibration, and point-by-point scanning tests must be performed again, resulting in an extremely inefficient data acquisition process that cannot meet the rapid screening requirements for device characteristics in large-scale power circuit designs.

[0006] The testing process is excessively time-consuming: Because junction capacitance is extremely sensitive to voltage changes, the testing process typically requires very fine voltage steps to capture nonlinear characteristics, resulting in a long single test cycle. From experimental preparation and environment setup to the cleaning and fitting analysis of massive amounts of test data, the entire process consumes a significant amount of R&D time. For modern power electronics product development, which pursues high power density and extremely short R&D cycles, this greatly slows down the progress of circuit simulation and system optimization, increases the time risk of R&D, and weakens the product's market responsiveness. Summary of the Invention

[0007] To overcome the shortcomings of the existing technology, the present invention aims to provide a method for predicting the capacitance characteristics of SiC MOSFETs based on neural networks. This method effectively improves the efficiency of SiC MOSFET dynamic characteristic research and has the characteristics of high prediction accuracy, low dependence on experimental data, and high efficiency.

[0008] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A neural network-based method for predicting the capacitance characteristics of SiC MOSFETs includes the following steps; Step 1: Construct a CV (capacitance-voltage) relationship dataset for the capacitance characteristics of SiC MOSFET devices. By simulating and sampling the junction capacitance of SiC MOSFETs under different bias voltage conditions, obtain the corresponding relationship data between voltage and capacitance. Step 2: Randomly divide the capacitance-voltage relationship dataset into a training set, a validation set, and a test set; Step 3: Construct a neural network prediction model for predicting the capacitance characteristics of SiC MOSFETs; Step 4: Train the neural network prediction model built above using the training set and validation set; Step 5: Input the test set V into the trained neural network prediction model GS V GD Using two characteristic variable parameters, voltage, to predict the capacitance characteristics of SiC MOSFETs.

[0009] In step 1, an equivalent circuit of the parasitic capacitance of the SiC MOSFET device is constructed; this includes a capacitor C located between the gate and the source. GS C located between the gate and drain GD C located between the source and drain DS By examining the parasitic capacitance C in the equivalent circuit GS C GD and C DS Simulations were performed under different voltage conditions to obtain the corresponding capacitance-voltage relationship data, which formed a sample dataset for neural network training.

[0010] The parasitic capacitance C between the gate and the source GS , by C N+ C P and C SM Three capacitors are connected in parallel to form a; the parasitic capacitance C between the gate and drain. GD It is by C OX and C GD1 It is formed by connecting the dots; Where C N+ C is the capacitance between the gate and the N+ source region. P C is the capacitance between the gate and the Pwell region. SM C is the capacitance between the gate and source metals. OX For the gate oxide capacitance, C GD1 C is the depletion layer capacitance between the gate and the drift region. DS This refers to the depletion layer capacitance of the PN junction. The capacitance values ​​of the parasitic capacitances mentioned above were obtained through device physical structure simulation, that is, by establishing a SiCMOSFET device structure model in TCAD and extracting the corresponding capacitance values ​​under different bias voltage conditions.

[0011] The equivalent circuit is constructed based on the physical structure of the SiC MOSFET device and the distribution of its parasitic capacitance; the equivalent capacitance model is derived from the device structure. It is a complete device simulation, where the SiC MOSFET structure is built in TCAD software, and the capacitance value of the device is extracted through simulation.

[0012] The capacitance-coefficient (CV) relationship was tested on the two parts, specifically the total port capacitance C. ISS C OSS C RSS With output voltage V DS The relationship between the two ports, and the relationship between the inter-port capacitance and the corresponding inter-port voltage, C GD -V GD C GS -V GS C DS -V DS The relationship is shown in the following formula: C ISS The input capacitance is equivalent to the capacitance C between the gate and the source. GS The capacitance C between the gate and drain gd The sum of; C OSS The output capacitor is equivalent to the capacitance C between the drain and source. DS The capacitance C between the gate and drain GD The sum of; C RSS The reverse transfer capacitor is equivalent to the capacitance C between the gate and drain. GD V DS V is the voltage between the drain and source. GS V is the voltage between the gate and source. GD This is the voltage between the gate and drain.

[0013] C GS C is the capacitance between the gate and drain. DS C is the capacitance between the drain and source. GS This is the capacitance between the gate and the source.

[0014] The dependence of the capacitor on the bias is obtained by scanning at different DC bias ranges; V DS The value range is from 0 to 400V, with each sampling point spaced 0.5V apart; V GS The value range is -10 to 10V, with an interval of 0.1V between each sampling point; V GD The value range is from -400 to 10V, and the interval between each sampling point is 0.5V.

[0015] V GS A total of 1001 sets of capacitance data samples were obtained through the above scan; Each set of sample data includes: Input parameters: VGS (gate-source voltage); VDS (gate-drain voltage); Output parameters: CGS (gate-source capacitance); CGD (gate-drain capacitance); CDS (drain-source capacitance). The data samples used to train the neural network are in the following form: (VGS,VDS) → (CGS,CGD,CDS); Capacitance CGS is related to voltage VGS, CDS to VDS, and CGD to VGD. In capacitance characteristic prediction, the corresponding voltage is used as the input and capacitance as the output. However, since VGD = VGS - VDS, only VGS and VDS data are needed. VGS and VDS are used as inputs, and capacitance CGS, CGD, and CDS are used as outputs to establish a strong correlation between the inputs and outputs in the dataset.

[0016] In step 2, the capacitance characteristic parameters of the SiC MOSFET devices in the training and validation sets are standardized. Standardization transforms the data into a distribution with a mean of 0 and a standard deviation of 1. The transformation function is shown in the equation: ; Normalization transforms a series of data into a fixed interval or range, typically [0, 1]. A commonly used transformation function is shown in the following equation: ; Among them, X i Here are the data to be processed, μ is the mean, σ is the variance, and X is the variance. min X is the minimum value in the data. max This represents the maximum value in the data.

[0017] In step 3, the network model used to predict the capacitance characteristics of SiC MOSFET devices includes fully connected layers and convolutional layers at the input and output ends. The input for predicting the capacitance characteristic parameters of a SiC MOSFET device is V. GS V GD Voltage is one of the two characteristic variables, and the output consists of three junction capacitances C. GS C GD C DS The input layer is used for inputting two voltage feature variable parameters; the input layer has a total of 2 input neurons. The fully connected layer expands the dimension of the input vector and reduces the dimension of the output vector. The convolutional layer further expands the feature channels; The output layer is used to output the capacitance characteristics of the SiC MOSFET device; the number of neurons in the output layer is the same as the number of capacitances in the SiC MOSFET device, that is, 3 output neurons.

[0018] In step 4, the network parameters of the neural network prediction model are iteratively updated using the backpropagation method to obtain the trained prediction model. During training, the three junction capacitances C of the SiC MOSFET devices in the training and validation sets are... GS C GD C DS The parameters are used as labels; the network weights and biases are optimized by backpropagation through the calculation of the loss function for each batch of training. The Adam optimizer is used to update the network parameters during training, and the learning rate is dynamically adjusted using an exponential decay strategy until the neural network model converges, thus obtaining the trained neural network model.

[0019] The beneficial effects of this invention are: This invention directly establishes the mapping relationship between input variables and nonlinear parasitic capacitance through a neural network model, eliminating the need for complex semiconductor physics formula derivations or deep reliance on cumbersome material parameter settings in TCAD simulation tools, thus greatly simplifying the modeling process.

[0020] Compared to traditional impedance analysis testing methods, this invention can achieve high-precision coverage of full-range capacitance characteristics using a limited number of experimental sample points, significantly reducing the time and cost of expensive testing equipment and improving the efficiency of characteristic acquisition.

[0021] When dealing with the extremely strong nonlinear capacitance unique to SiC devices, this invention utilizes the powerful nonlinear fitting capability of neural networks to effectively solve the problem of insufficient prediction accuracy of traditional analytical models in specific voltage ranges, achieving a dual improvement in speed and accuracy.

[0022] Furthermore, this invention provides power system designers with a convenient tool, enabling circuit designers without semiconductor manufacturing expertise to quickly obtain accurate device models, effectively lowering the modeling threshold in the SiC power converter development process. Simultaneously, this data-driven prediction approach offers a novel perspective for semiconductor device research. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the capacitor structure of a SiC MOSFET device.

[0024] Figure 2 This is the equivalent circuit for the parasitic capacitance of a SiC MOSFET device.

[0025] Figure 3 This is the capacitance characteristic (CV) curve of a SiC MOSFET device.

[0026] Figure 4 This is a schematic diagram of the structure of a neural network prediction model.

[0027] Figure 5 Comparison of predicted and measured capacitance characteristics of SiC MOSFET devices. (a) C ISS / C OSS / C RSS -V DS Characteristics, (b) C GS -V GS Characteristics, (c) C GD -V GD Characteristics, (d) C DS -V DS characteristic.

[0028] Figure 6 This is a schematic diagram of the verification loss during the training process of the capacitance characteristic model of a SiC MOSFET device. Detailed Implementation

[0029] The present invention will now be described in further detail with reference to the accompanying drawings.

[0030] A neural network-based method for predicting the capacitance characteristics of SiC MOSFETs includes the following steps; Step 1. To construct a complete CV (capacitance-voltage) relationship dataset, CV relationship tests were performed on the capacitance of two parts: the total port capacitance (C...). ISS C OSS C RSS ) and output voltage V DS The relationship between the two ports, and the relationship between the inter-port capacitance and the corresponding inter-port voltage (C GD -V GD C GS -V GS C DS -V DS The relationship is shown in the following formula: C ISS The input capacitance is equivalent to the capacitance C between the gate and the source. GS The capacitance C between the gate and drain GD The sum of; COSS The output capacitor is equivalent to the capacitance C between the drain and source. DS The capacitance C between the gate and drain GD The sum of; C RSS The reverse transfer capacitor is equivalent to the capacitance C between the gate and drain. GD V DS V is the voltage between the drain and source. GS V is the voltage between the gate and source. GD This is the voltage between the gate and drain.

[0031] C GD C is the capacitance between the gate and drain. DS C is the capacitance between the drain and source. GS This is the capacitance between the gate and the source.

[0032] A measurement frequency of 100kHz was selected.

[0033] The dependence of capacitance on bias is obtained by scanning within different DC bias ranges. To ensure comprehensive dataset sampling, the voltage scan ranges for these different types of CV relationships are set as shown in Table 1.

[0034] V DS The value range is from 0 to 400V, with each sampling point spaced 0.5V apart; V GS The value range is -10 to 10V, with an interval of 0.1V between each sampling point; V GD The value range is from -400 to 10V, and the interval between each sampling point is 0.5V.

[0035] Table 1. C-V Characteristic Test Sample Range CV scanning Range:(start:step:end) / V CDS-VDS VDS:0:0.5:400 CGS-VGS VGS:-10:0.1:10 CGD-VGD VGD:-400:0.5:10 Table 2: Voltage Scan Range Values A total of 1001 sets of SiC MOSFET capacitance characteristic datasets were obtained. Each set of sample data includes two parts: input variables and output variables. The input variable is the gate-source voltage V. GS and drain-source voltage V DS Due to the gate-drain voltage V GD V GD =V GS V DS The result is calculated, therefore it is not used as a separate input parameter in this experiment. The output parameters are the three junction capacitances C. GS C GD C DSThis data will serve as the foundation for subsequent neural network training and model building.

[0036] Table 3 shows a partial dataset of the capacitance characteristics of SiC MOSFETs. refer to Figure 1 This is a schematic diagram of the capacitor structure of the SiC MOSFET device used in this embodiment. Wherein C... N+ C is the capacitance between the gate and the N+ source region. P C is the capacitance between the gate and the Pwell region. SM C is the capacitance between the gate and source metals. OX For the gate oxide capacitance, C GD1 This is the depletion layer capacitance between the gate and the drift region.

[0037] Figure 1 The capacitor structure of the SiC MOSFET device shown determines the internal C of the device. GS C GD The physical source of the gate-source capacitance C GS It is mainly composed of C N+ C P and C SM Three capacitors connected in parallel form a; C GD It is by C OX and C GD1 These parasitic capacitances are connected in series. The CV relationship dataset constructed in this invention is a data set established based on the simulation results of these parasitic capacitances changing with bias voltage. By collecting capacitance values ​​under different voltage conditions, the nonlinear relationship between voltage and each parasitic capacitance can be obtained, serving as the data basis for training the neural network model.

[0038] The parameters of this SiC MOSFET device are as follows: channel length 0.35~0.6μm; JFET region width 0.8~2.0μm; drift region thickness 5~15μm; drift region doping concentration 1×10⁻⁶. 15 / cm 3 ~5×10 16 / cm 3 The gate oxide layer thickness is 42~50 nm; the uniform doping concentration of the substrate is 1×10⁻⁶. 18 / cm 3 ~1×10 20 / cm 3 .

[0039] Figure 2 This is the equivalent circuit for the parasitic capacitance of a SiC MOSFET device; it includes C located between the gate and source. GS C located between the gate and drainGD C located between the source and drain DS By examining the parasitic capacitance C in the equivalent circuit GS C GD and C DS Simulations under different voltage conditions can yield corresponding capacitance-voltage relationship data, thus forming a sample dataset for neural network training.

[0040] refer to Figure 3 , is the capacitance characteristic CV curve of the SiC MOSFET device. (a) is the capacitance characteristic CV curve of the SiC MOSFET device. ISS C OSS C RSS With V DS The capacitance characteristic curve between [the two values]. From this graph, it can be seen that C [is related to the capacitance characteristic curve]. ISS It has the largest value among the three types of capacitors, and in V DS The voltage remains essentially constant across the entire range from 0V to 400V. And C OSS and C RSS All with V DS The capacitance C decreases as the capacitance increases. Figure (b) shows the capacitance C. GS With voltage V GS The characteristics of change. Figure (c) shows C. GD With V DG The characteristics of change. We can see C GS and C GD In V DG When it is smaller, it is larger; as V increases... DG Increase, C GD It will gradually decrease. This figure illustrates the non-linear relationship between these junction capacitances and their corresponding bias voltages, adding credibility to the neural network dataset.

[0041] Step 2. Randomly divide the 1001 sets of data in the sample set into training set, validation set and test set in a ratio of 6:2:2; the test set does not participate in any training, but only participates in the calculation of the accuracy of prediction or classification, so as to truly reflect the generalization ability of the network. The capacitance characteristic parameters of the SiC MOSFET devices in the training and validation sets were standardized. Standardization transforms the data into a distribution with a mean of 0 and a standard deviation of 1. The transformation function is shown in the equation: ; Normalization transforms a series of data into a fixed interval or range, typically [0, 1]. A commonly used transformation function is shown in the following equation: ; Among them, X i Here are the data to be processed, μ is the mean, σ is the variance, and X is the variance. minX is the minimum value in the data. max This represents the maximum value in the data. Standardizing or normalizing the data is done to eliminate the influence of different features having different magnitudes.

[0042] Step 3. Construct a neural network prediction model; The network model reference used for predicting the capacitance characteristics of SiC MOSFET devices Figure 4 It includes fully connected layers and convolutional layers at the input and output ends; The input for predicting the capacitance characteristic parameters of a SiC MOSFET device is V. GS V GD Voltage is one of the two characteristic variables, and the output consists of three junction capacitances C. GS C GD C DS The input layer is used for inputting two voltage parameters; the input layer has a total of 2 input neurons. The fully connected layer can expand the dimension of the input vector, and the batch normalization between layers helps to reduce network overfitting. By correcting the nonlinearity introduced by the linear unit, the network's representation ability is improved. Fully connected layers can reduce the dimensionality of the output vector, and batch normalization between layers helps to reduce network overfitting. By correcting the nonlinearity introduced by linear units, the network's representation ability can be improved. Convolutional layers further expand the feature channels, thereby improving the network's feature extraction capabilities and enabling it to capture more complex and diverse feature patterns.

[0043] The output layer is used to output the capacitance characteristics of the SiC MOSFET device; the number of neurons in the output layer is the same as the number of capacitances in the SiC MOSFET device, that is, 3 output neurons.

[0044] The network model of this invention is built with a high average prediction accuracy as the guiding principle, and the prediction accuracy is mainly improved by adjusting the following parameters: 1. The number of neurons in each layer of the network architecture. When the validation set error is large, the expressive power of the model can be improved by increasing the number of neurons in the hidden layers. 2. The number of convolutional layers, the number of neurons in each layer, and the number of channels: When the neural network has poor feature extraction capabilities, it is necessary to increase the number of convolutional layers to improve feature extraction capabilities; 3. Normalization, activation functions, and downsampling operations between layers: When the model exhibits overfitting, regularization and other operations need to be added to improve the model's generalization ability. 4. Optimizer and learning rate: When the training process converges slowly or the loss function does not decrease significantly, the learning rate can be appropriately increased to improve the model parameter update speed.

[0045] In the network structure of this invention, BatchNorm1d (one-dimensional batch normalization) is used for normalization between layers, which helps reduce network overfitting. Nonlinearity is introduced by correcting the ReLU (Rectified Linear Unit), improving the network's representational ability. Max pooling is used for downsampling between two convolution operations. During the training of the NMOS electrical characteristic parameter prediction network, the Adam optimizer is used to update the network parameters, with a learning rate set to 0.001.

[0046] Step 4. Train the neural network prediction model using the training set and validation set, and iteratively update the network parameters of the neural network prediction model using the backpropagation method to obtain the trained prediction model. Specifically, during the training process, the three junction capacitances C of the SiC MOSFET devices in the training and validation sets are... GS C GD C DS The parameters are used as labels; the network weights and biases are optimized by backpropagation through the calculation of the loss function for each batch of training. The Adam optimizer is used to update the network parameters during training, and the learning rate is dynamically adjusted using an exponential decay strategy. The initial learning rate is set to 0.001 until the neural network model converges, and the trained neural network model is obtained.

[0047] Step 5. Input the test set V into the trained neural network prediction model. GS V GD Using the two characteristic variable parameters of voltage, the three junction capacitances C of the SiC MOSFET device in the test set are obtained. GS C GD C DS The prediction results.

[0048] refer to Figure 5 As can be seen, the neural network in this embodiment can predict the capacitance characteristics of SiC MOSFET devices very well. Figure 5 This embodiment of the invention compares the predicted capacitance characteristics of a SiC MOSFET device with measured data. (Reference) Figure 6 As can be observed from the figure, the validation loss is very low at the end of the training phase. This indicates that the trained neural network model achieves very high accuracy in fitting the experimental data and can effectively reproduce the measured capacitance characteristics in the experiment, accurately predicting the capacitance behavior under different operating conditions. The error between the prediction results and the actual experimental data is very small, verifying the effectiveness and reliability of the model.

[0049] This invention overcomes the limitations of traditional methods that rely on expensive testing equipment to measure capacitance at all voltage points. Step 1 obtains capacitance characteristic data of SiC MOSFET devices under different voltage conditions, and preprocesses and partitions this data. Step 3 constructs a neural network model to establish a nonlinear mapping relationship between voltage and capacitance, transforming complex semiconductor physical characteristic equations into a neural network mapping relationship. Step 4 trains the model and obtains a converged model. Finally, Step 5 enables rapid prediction of the capacitance characteristics of SiC MOSFETs under unknown voltage conditions, achieving a high-dimensional leap from static structural parameters to dynamic capacitance characteristics. This is the core logic of the predictive model construction in this invention.

[0050] In terms of model input design, the change in junction capacitance in SiC MOSFET devices is essentially a change in depletion layer width with bias voltage. Given that SiC material has a wide bandgap, its depletion region charge distribution exhibits significant nonlinear characteristics, leading to a strongly nonlinear capacitance-voltage relationship. Therefore, this invention uses voltage bias as the input feature of a neural network, enabling the model to learn the relationship between voltage changes and charge distribution changes. This ensures that the model is not only a mathematical fit but also has logical support at the physical level, thereby achieving accurate prediction of parasitic capacitance.

[0051] This invention constructs a customized neural network architecture specifically designed for the steep capacitance variation characteristics of SiC devices. Considering C... GD Since the parameters decrease by an order of magnitude with increasing voltage, the convolutional layer uses a combination of activation functions that can capture changes in local features to solve the problems of gradient vanishing or insufficient fitting accuracy when the capacitance changes drastically in the low-voltage region.

[0052] In step 4, during training, the error between the predicted and true values ​​is calculated by defining a loss function, and the network weight parameters are continuously updated using the backpropagation algorithm, thereby gradually reducing the prediction error and eventually converging. This process realizes the automatic learning process from simulation data to the prediction model. This enables the model to achieve extremely high prediction accuracy across the entire range, especially in the low-voltage nonlinear region where switching losses have a significant impact, significantly reducing the reliance on complex analytical models and empirical parameter derivations.

[0053] This invention aims to leverage the powerful self-learning and multi-dimensional nonlinear mapping capabilities of neural networks to construct an intelligent model capable of accurately predicting the capacitance characteristics of SiC MOSFETs across the entire voltage range through deep learning and training on a small number of representative capacitance test samples. This significantly reduces reliance on high-voltage precision testing equipment, substantially lowers experimental equipment investment and device sample consumption, skips the tedious point-by-point scanning process, significantly improves research efficiency, and shortens the data acquisition cycle, enabling efficient and low-cost acquisition of SiC MOSFET junction capacitance prediction results under different bias voltages and operating conditions.

[0054] Leveraging the advantages of neural networks in handling complex multivariate correlations, this invention comprehensively considers the coupling effects of multiple factors such as drain-source voltage, ambient temperature, and process parameter fluctuations on the junction capacitance of SiC MOSFETs, effectively overcoming the prediction bias caused by oversimplification in traditional physical analytical models. By accurately predicting dynamic capacitance changes, it provides high-precision underlying data support for optimizing switching losses and electromagnetic compatibility simulations in power converters, thereby improving the accuracy and reliability of power electronic system design, reducing the failure rate during circuit debugging, and enhancing the competitiveness and economic benefits of related semiconductor products in high-end application markets.

[0055] The present invention aims to address the problem that the research and evaluation methods for the capacitance characteristics of SiC MOSFETs (silicon carbide metal oxide semiconductor field-effect transistors) based on device simulation and experimental testing are complex and time-consuming.

[0056] This invention aims to leverage the powerful nonlinear mapping and multidimensional data processing capabilities of neural networks to construct a capacitance characteristic prediction model through deep learning training on a small number of typical experimental samples. This significantly reduces the long-term occupancy of high-voltage precision testing instruments, substantially lowers the investment in experimental equipment, reduces experimental wear and tear on device samples, and minimizes the operation time for technical personnel. This method can quickly and accurately predict the capacitance characteristics of SiC MOSFETs across the entire voltage range and under multi-physics coupling.

[0057] In summary, firstly, this invention is the first to apply a neural network model to the prediction of parasitic capacitance characteristics of SiC MOSFET devices. By constructing a nonlinear mapping relationship between voltage bias and parasitic capacitance, it achieves rapid prediction of the device's capacitance characteristics.

[0058] Second, this invention uses TCAD software to simulate the capacitance characteristics of SiC MOSFET devices and combines voltage scanning to construct a capacitance-voltage dataset, transforming the traditional capacitance characteristic method that relies on a large number of experimental measurements into a neural network prediction method, thereby significantly reducing the number of experimental tests and improving efficiency.

[0059] Third, this invention designs a neural network structure for the strong nonlinear capacitance characteristics of SiC devices. By combining convolutional layers and fully connected layers, the model's ability to extract features from changes in nonlinear capacitance is improved, thus achieving high-precision prediction even with fewer samples and a very high accuracy rate.

Claims

1. A method for predicting the capacitance characteristics of SiC MOSFETs based on neural networks, characterized in that, Includes the following steps; Step 1: Based on the capacitance characteristics of SiC MOSFET devices, construct a CV capacitance-voltage relationship dataset. By simulating and sampling the junction capacitance of SiC MOSFETs under different bias voltage conditions, obtain the corresponding relationship data between voltage and capacitance. Step 2: Randomly divide the capacitance-voltage relationship dataset into a training set, a validation set, and a test set; Step 3: Construct a neural network prediction model for predicting the capacitance characteristics of SiC MOSFETs; Step 4: Train the neural network prediction model built above using the training set and validation set; Step 5: Input the test set V into the trained neural network prediction model GS V GD Using two characteristic variable parameters, voltage, to predict the capacitance characteristics of SiC MOSFETs.

2. The method for predicting the capacitance characteristics of SiC MOSFETs based on neural networks according to claim 1, characterized in that, In step 1, an equivalent circuit of the parasitic capacitance of the SiC MOSFET device is constructed; wherein the parasitic capacitance between the gate and the source is C. GS The parasitic capacitance between the gate and drain is C. GD The parasitic capacitance between the source and drain is C. DS By examining the parasitic capacitance C in the equivalent circuit GS C GD and C DS Simulations were performed under different voltage conditions to obtain the corresponding capacitance-voltage relationship data, which formed a sample dataset for neural network training.

3. The method for predicting the capacitance characteristics of SiC MOSFETs based on neural networks according to claim 2, characterized in that, The parasitic capacitance C between the gate and the source GS , by C N+ C P and C SM Three capacitors are connected in parallel to form the parasitic capacitance C between the gate and drain. GD It is by C OX and C GD1 Composed of connected series; C DS For the depletion layer capacitance of the PN junction; where C N+ C is the capacitance between the gate and the N+ source region. P C is the capacitance between the gate and the Pwell region. SM C is the capacitance between the gate and source metals. OX For the gate oxide capacitance, C GD1 This is the depletion layer capacitance between the gate and the drift region; The capacitance values ​​of the parasitic capacitances mentioned above were obtained through device physical structure simulation, that is, by establishing a SiC MOSFET device structure model in TCAD and extracting the corresponding capacitance values ​​under different bias voltage conditions.

4. The method for predicting the capacitance characteristics of SiC MOSFETs based on neural networks according to claim 3, characterized in that, The capacitance-coefficient (CV) relationship was tested on the two parts, specifically the total port capacitance C. ISS C OSS C RSS With output voltage V DS The relationship between the two ports, and the relationship between the inter-port capacitance and the corresponding inter-port voltage, C GD -V GD C GS -V GS C DS -V DS The relationship is shown in the following formula: C ISS The input capacitance is equivalent to the capacitance C between the gate and the source. GS The capacitance C between the gate and drain GD The sum of; C OSS The output capacitor is equivalent to the capacitance C between the drain and source. DS The capacitance C between the gate and drain GD The sum of; C RSS The reverse transfer capacitor is equivalent to the capacitance C between the gate and drain. GD V DS V is the voltage between the drain and source. GS V is the voltage between the gate and the source. GD This is the voltage between the gate and drain. C GD C is the capacitance between the gate and drain. DS C is the capacitance between the drain and source. GS This is the capacitance between the gate and the source.

5. The method for predicting the capacitance characteristics of SiC MOSFETs based on neural networks according to claim 4, characterized in that, The dependence of the capacitor on the bias is obtained by scanning at different DC bias ranges; V DS The value range is from 0 to 400V, with each sampling point spaced 0.5V apart; V GS The value range is from -10 to 10V, and the interval between each sampling point is 0.1V; The input is V GS V DS Voltage is one of the two characteristic variables, and the output consists of three junction capacitances C. GS C GD C DS VDS ranges from 0 to 400V, with a voltage step size of 0.5V.

6. The method for predicting the capacitance characteristics of SiC MOSFETs based on neural networks according to claim 5, characterized in that, V GS Capacitance data samples were obtained through the above scanning process; Each set of sample data includes: Input parameters: VGS (gate-source voltage); VDS (gate-drain voltage); Output parameters: CGS (gate-source capacitance); CGD (gate-drain capacitance); CDS (drain-source capacitance). The data samples used to train the neural network are in the following format: (VGS,VDS) → (CGS,CGD,CDS); The capacitance CGS is related to the voltage VGS, CDS is related to VDS, and CGD is related to VGD. In the prediction of capacitance characteristics, the corresponding voltage is used as the input and the capacitance is used as the output; VGS and VDS are used as the input and capacitance CGS, CGD, and CDS are used as the output to establish a strong correlation between the input and output of the data.

7. The method for predicting the capacitance characteristics of SiC MOSFETs based on neural networks according to claim 6, characterized in that, In step 2, the capacitance characteristic parameters of the SiC MOSFET devices in the training and validation sets are standardized. Standardization transforms the data into a distribution with a mean of 0 and a standard deviation of 1. The transformation function is shown in the equation: ； Normalization transforms a series of data into a fixed interval or range, typically [0, 1]. A commonly used transformation function is shown in the following equation: ； Among them, X i Here are the data to be processed, μ is the mean, σ is the variance, and X is the variance. min X is the minimum value in the data. max This represents the maximum value in the data.

8. The method for predicting the capacitance characteristics of SiC MOSFETs based on neural networks according to claim 7, characterized in that, In step 3, the network model used to predict the capacitance characteristics of SiC MOSFET devices includes fully connected layers and convolutional layers at the input and output ends. The input for predicting the capacitance characteristic parameters of a SiC MOSFET device is V. GS V GD Voltage is one of the two characteristic variables, and the output consists of three junction capacitances C. GS C GD C DS The input layer is used for inputting two voltage feature variable parameters; the input layer has a total of 2 input neurons. The fully connected layer expands the dimension of the input vector and reduces the dimension of the output vector. Convolutional layers expand the feature channels; The output layer is used to output the capacitance characteristics of the SiC MOSFET device; the number of neurons in the output layer is the same as the number of capacitances in the SiC MOSFET device, that is, 3 output neurons.

9. The method for predicting the capacitance characteristics of SiC MOSFETs based on neural networks according to claim 1, characterized in that, In step 4, the network parameters of the neural network prediction model are iteratively updated using the backpropagation method to obtain the trained prediction model. During training, the three junction capacitances C of the SiC MOSFET devices in the training and validation sets are... GS C GD C DS The parameters are used as labels; the network weights and biases are optimized by backpropagation through the calculation of the loss function for each batch of training. The Adam optimizer is used to update the network parameters during training, and the learning rate is dynamically adjusted using an exponential decay strategy until the neural network model converges, thus obtaining the trained neural network model.

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