Semiconductor structure and forming method thereof

Abstract

A gate structure is formed on a substrate at the junction of a well region and a drift region, the gate structure on the drift region is doped to form a first doped region and a second doped region which are adjacent to each other, the first doped region is doped with first type ions, and the second doped region is doped with second type ions; the conduction types of the second type ions and the first type ions are different, so that the first doped region and the second doped region form a reverse biased PN junction, an electric field caused by the interconnection structure can be balanced and dispersed in the direction from the drain electrode to the source electrode, and the high voltage of the interconnection structure can be effectively isolated; besides, the first doped region and the second doped region form a reverse-biased PN junction to disperse the high potential difference between the first doped region and the second doped region, so that the electric field intensity and the potential peak value on the surface of the device are effectively reduced, the segmented voltage division effect is beneficial to optimization of electric field distribution on the surface of the device, electric field concentration is reduced, and the performance of the device is improved. Therefore, the breakdown voltage of the semiconductor structure is improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] In the development of power integrated circuits, single chip processes developed to integrate power switches and control circuits together, especially the lateral double diffusion MOS (LDMOS) process currently used to make single chip integrated circuits, are a mainstream trend. The LDMOS process is a planar diffusion performed on the surface of a semiconductor substrate to form a lateral main current path. Since the LDMOS is manufactured from a typical IC process, the control circuit and the LDMOS can be integrated on a single power IC.

[0003] Among the performance parameters of the LDMOS device, the on-resistance and the breakdown voltage are two core indicators. Specifically, the on-resistance is directly related to the current and the spacing of the device structure, and the smaller the value, the lower the power consumption of the device, and the smaller the required device area. The breakdown voltage is an important indicator of the pressure resistance of the device, and is related to the electric field strength inside the device.

[0004] The design of the semiconductor structure of the high-voltage power integrated circuit often involves the integration of high-voltage LDMOS devices and low-voltage devices, as well as the mutual transmission of control signals between high-voltage LDMOS devices and low-voltage devices, which requires the use of high-voltage interconnection (HVI) to realize signal transmission between different voltage regions on the surface of the circuit. The design and optimization of the high-voltage interconnection directly affect the performance of the semiconductor structure of the high-voltage power integrated circuit. SUMMARY

[0005] The problem solved by the embodiments of the present application is to provide a semiconductor structure and a forming method thereof, which improves the breakdown voltage of the semiconductor structure.

[0006] To solve the above problems, the embodiment of the present application further provides a semiconductor structure, comprising: a substrate; a well region and a drift region which are adjacent to each other and are located in the substrate; a gate structure which is located on the substrate at the junction of the well region and the drift region, and extends in a lateral direction perpendicular to the extending direction of the gate structure; a first doped region and a second doped region which are adjacent to each other and are located in the gate structure on the drift region, and are used for shielding, the first doped region is doped with a first type of ion, and the second doped region is doped with a second type of ion, the second type of ion and the first type of ion are different in the conduction type; a source which is located in the well region on one side of the gate structure; and a drain which is located in the drift region on one side of the gate structure.

[0007] Correspondingly, the embodiment of the present application provides a forming method of a semiconductor structure, comprising: providing a substrate; forming a well region and a drift region which are adjacent to each other in the substrate; forming a gate structure on the substrate at the junction of the well region and the drift region, and extending in a lateral direction perpendicular to the extending direction of the gate structure; doping the gate structure on the drift region to form a first doped region and a second doped region which are adjacent to each other and are used for shielding, the first doped region is doped with a first type of ion, and the second doped region is doped with a second type of ion, the second type of ion and the first type of ion are different in the conduction type; forming a source in the well region on one side of the gate structure; and forming a drain in the drift region on one side of the gate structure.

[0008] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0009] In the forming method of the semiconductor structure provided by the embodiment of the present application, an interconnection structure which crosses the gate structure will be formed subsequently, because the gate structure on the drift region is doped to form a first doped region and a second doped region which are adjacent to each other, the first doped region is doped with a first type of ion, and the second doped region is doped with a second type of ion, the second type of ion and the first type of ion are different in the conduction type, therefore, the first doped region and the second doped region constitute a reverse-biased PN junction, which helps to balance and disperse the electric field caused by the interconnection structure in the direction from the drain to the source, can effectively isolate the high voltage of the interconnection structure, and is not easy to cause hot carrier injection, thereby improving the reliability and stability of the semiconductor structure; in addition, the first doped region and the second doped region constitute a reverse-biased PN junction, which disperses the high potential difference between the first doped region and the second doped region, thereby effectively reducing the electric field intensity and potential peak value on the surface of the device, and the effect of segmented voltage division helps to optimize the electric field distribution on the surface of the device, reduces the electric field concentration, and thereby improves the breakdown voltage of the semiconductor structure.

[0010] In an optional solution, in the step of forming the gate structure, the number of the first regions and the second regions is multiple, and the first regions and the second regions are arranged alternately; in the step of doping the gate structure above the drift region, the first doped regions are formed in the first regions, and the second doped regions are formed in the second regions, and the first doped regions and the second doped regions are arranged alternately. By arranging the first doped regions and the second doped regions alternately in the lateral direction, a plurality of continuous PN junctions can be formed in the direction from the drain to the source, the high potential difference is dispersed between each pair of N-type and P-type doped regions, the electric field in the drift region is redistributed, which helps to balance and disperse the electric field caused by the interconnection structure, so that the electric field in the drift region is not easy to concentrate, the electric field intensity and the potential peak value on the surface of the drift region are effectively reduced, and the breakdown voltage of the semiconductor structure is improved.

[0011] In an optional solution, in the step of forming the drift region, the drift region comprises a third region for forming the drain; in the step of forming the gate structure, the gate structure covers the drift region between the well region and the third region; in the step of forming the drain in the drift region on one side of the gate structure, the drain is formed in the third region. Because the gate structure extends in the lateral direction in the drift region and covers the drift region between the well region and the third region, that is, the gate structure is not composed of a plurality of segmented structures, but is a whole long strip structure, when the semiconductor structure works, the concentration of the field intensity of the gate structure on the drift region can be effectively reduced, the field intensity distribution in the drift region under the gate structure is uniform, the electric field concentration is not easy to occur, the peak field intensity of the drain is reduced, and the breakdown voltage of the semiconductor structure is improved.

[0012] In an optional solution, in the step of doping the gate structure with the first type of ions, the first type of ions are also doped in the well region and the drift region, the source is formed in the well region, and the drain is formed in the drift region. Because the first doped regions, the source and the drain are formed in the same doping process, the forming step of the first doped regions is simplified, and the forming period of the semiconductor structure is shortened. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 FIG. 1 is a structural schematic diagram of a semiconductor structure;

[0014] Figures 2 to 11 FIG. 6 is a structural schematic diagram corresponding to each step in the forming method of the semiconductor structure of the embodiment of the present application. DETAILED DESCRIPTION

[0015] As known from the background, in the semiconductor structure of the high-voltage power integrated circuit formed at present, the high-voltage metal interconnection line affects the performance of the semiconductor structure. The reasons for the poor performance of the semiconductor structure will be analyzed in combination with a forming method of a semiconductor structure.

[0016] Reference Figure 1 Fig. 1 shows a structural schematic diagram of a semiconductor structure.

[0017] The semiconductor structure comprises: a substrate 10; an adjacent well region 11 and a drift region 12 located in the substrate 10; a gate structure 20 located on the substrate 10 at the junction of the well region 11 and the drift region 12; a source region 31 and a body region 33 located in the well region 11 on one side of the gate structure 20; and a drain region 32 located in the drift region 12 on the other side of the gate structure 20.

[0018] The semiconductor structure further comprises: a contact hole plug 40 located on the drain region 32; and an interconnection structure 41 electrically connected to the contact hole plug 40 on the drain region 32 and crossing the gate structure 20.

[0019] Taking an N-type lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS) as an example, when the LDMOS is working, carriers flow out of the drain region 32 and flow to the source region 31. The breakdown voltage is used to characterize the voltage resistance of the LDMOS and is related to the field strength inside the LDMOS. For the LDMOS, the maximum field strength often occurs near the drain region 32, and therefore how to optimize the electric field of the drain region 32 becomes the key to improving the breakdown voltage of the LDMOS. The interconnection structure 41 is a high-voltage interconnection (HVI) and is used to realize signal transmission between different voltage regions. When the semiconductor structure is working, the interconnection structure 41 has a high potential thereon, which generates an enhanced longitudinal vertical electric field on the surface of the LDMOS. Because the interconnection structure 41 crosses the gate structure 20, it affects the distribution of the electric field in the drift region 12, which not only increases the peak value of the electric field on the surface of the LDMOS but also reduces the voltage resistance performance of the LDMOS, easily leading to hot carrier injection and reducing the reliability and stability of the device.

[0020] To solve the technical problem, the embodiment of the present application provides a forming method of a semiconductor structure, which comprises the following steps: providing a substrate; forming an adjacent well region and a drift region in the substrate; forming a gate structure on the substrate at the junction of the well region and the drift region, the gate structure extending in a lateral direction perpendicular to the extending direction of the gate structure in the drift region; doping the gate structure on the drift region to form adjacent first and second doped regions for shielding, the first doped region being doped with first-type ions and the second doped region being doped with second-type ions, the second-type ions and the first-type ions being different in conductive type; forming a source electrode in the well region on one side of the gate structure; and forming a drain electrode in the drift region on one side of the gate structure.

[0021] The forming method of the semiconductor structure provided by the embodiment of the present application comprises the following steps: forming adjacent well regions and drift regions in a substrate; forming a gate structure on the substrate in the well regions and the drift regions, the gate structure extending in a lateral direction perpendicular to the extending direction of the gate structure; doping the gate structure on the drift region to form adjacent first doped regions and second doped regions for shielding, the first doped regions being doped with first type ions, and the second doped regions being doped with second type ions, the second type ions and the first type ions being different in the conductive type; forming a source electrode in the well region on one side of the gate structure; and forming a drain electrode in the drift region on one side of the gate structure. The subsequent forming method of the semiconductor structure further comprises forming an interconnection structure across the gate structure. Because the gate structure on the drift region is doped to form adjacent first doped regions and second doped regions, the first doped regions are doped with first type ions, and the second doped regions are doped with second type ions, the second type ions and the first type ions being different in the conductive type, therefore, the first doped regions and the second doped regions form reverse-biased PN junctions, which help to balance and disperse the electric field caused by the interconnection structure in the direction from the drain electrode to the source electrode, can effectively isolate the high voltage of the interconnection structure, and are not prone to causing hot carrier injection, thereby improving the reliability and stability of the semiconductor structure. In addition, the first doped regions and the second doped regions form reverse-biased PN junctions, which disperse the high potential difference between the first doped regions and the second doped regions, thereby effectively reducing the electric field intensity and the potential peak on the surface of the device. The segmented voltage division effect helps to optimize the electric field distribution on the surface of the device, reduces the electric field concentration, and thereby improves the breakdown voltage of the semiconductor structure.

[0022] In order to make the above-mentioned purposes, characteristics and advantages of the embodiments of the present application more obvious and easy to understand, the specific embodiments of the embodiments of the present application will be described in detail below with reference to the drawings.

[0023] Figures 2 to 11 FIG. 1 is a structure diagram corresponding to each step in the forming method of the semiconductor structure of the embodiment of the present application.

[0024] Referring to FIG. 1, Figure 2 a substrate 100 is provided.

[0025] The substrate 100 is used to provide a process platform for subsequent formation of an LDMOS.

[0026] In the embodiment, the LDMOS is a planar transistor, and the substrate 100 is a planar substrate. In other embodiments, the semiconductor structure is taken as an example of an LDMOS fin field effect transistor, and the substrate comprises a substrate and a fin portion located on the substrate.

[0027] In the embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate can also be a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, a gallium arsenide substrate, or a gallium indium substrate, or a substrate of other materials. The substrate can also be a silicon on insulator substrate or a germanium on insulator substrate, or other types of substrates.

[0028] With reference to the drawings again, Figure 2 Adjacent well region 101 and drift region 102 are formed in the substrate 100, the drift region 102 has first type ions, and the well region 101 has second type ions, the first type ions and the second type ions are of different conductivity types. Here, the first type ions and the second type ions are of different conductivity types means that when the first type is N type, the second type is P type; when the first type is P type, the second type is N type.

[0029] The well region 101 and the drift region 102 are in contact, the well region 101 serves as a lateral diffusion region to form a channel with a concentration gradient, and the drift region 102 is used to withstand a large voltage.

[0030] Specifically, in the embodiment, the semiconductor structure is used to form an NLDMOS, the first type ions are N type ions, and the N type ions include one or more of phosphorus ions, arsenic ions, and antimony ions, the second type ions are P type ions, and the P type ions include one or more of boron ions, gallium ions, and indium ions. In other embodiments, the semiconductor structure is used to form a PLDMOS, the first type ions are P type ions, and the P type ions include one or more of boron ions, gallium ions, and indium ions, the second type ions are N type ions, and the N type ions include one or more of phosphorus ions, arsenic ions, and antimony ions.

[0031] In the embodiment, the well region 101 and the drift region 102 are formed by ion implantation. Ion implantation has the characteristics of simple operation and low process cost.

[0032] It should be noted that in the step of forming the drift region 102, the drift region 102 includes a third region for forming a drain. The third region is used to form a drain in a subsequent process.

[0033] With reference to the drawings again, Figures 3 to 6 A gate structure 103 is formed on the substrate 100 at the junction of the well region 101 and the drift region 102 (as shown in FIG. 1B), which extends transversely to the extension direction of the gate structure 103. Figure 6 The gate structure 103 extends transversely in the drift region 102.

[0034] In the embodiment, the gate structure 103 is used to control the opening and closing of the LDMOS channel.

[0035] In the step of forming the gate structure 103, the distance from the end of the gate structure 103 away from the well region 101 to the substrate 100 is greater than the distance from the end of the gate structure 103 close to the well region 101 to the substrate 100. That is, the distance from the end of the gate structure 103 close to the drain to the substrate 100 is greater than the distance from the end of the gate structure 103 close to the source to the substrate 100.

[0036] The method for forming the semiconductor structure is used to form an LDMOS. In operation, the closer to the drain, the more likely to break down. The distance from the end of the gate structure 103 close to the drain to the substrate 100 is greater than the distance from the end of the gate structure 103 close to the source to the substrate 100, which is conducive to improving the breakdown voltage of the LDMOS.

[0037] Specifically, as shown in Figure 6 In the step of forming the gate structure 103, the gate structure 103 is in a stepped shape, the gate structure 103 includes a first part 103a close to the substrate 100, a second part 103c away from the substrate 100, and a transition part 103b connecting the first part 103a and the second part 103c. The first part 103a is located at the junction of the well region 101 and the drift region 102, and the second part 103c and the transition part 103b are located on the drift region 102.

[0038] The transition part 103b of the gate structure 103 is located on the drift region 102, so that more parts of the gate structure 103 are located on the drift region 102, which is conducive to providing an electric field from the drain to the gate structure 103, reducing the peak field strength of the drain, and improving the breakdown voltage of the semiconductor structure.

[0039] In the method for forming the semiconductor structure, the second part 103c of the gate structure 103 is doped to form adjacent first and second doping regions 106 and 107. In operation of the semiconductor structure, the electric field at the first and second doping regions 106 and 107 is strong. By making the second part 103c of the gate structure 103 away from the substrate 100, the probability of breakdown of the semiconductor structure at the second part 103c of the gate structure 103 is reduced, and the breakdown voltage of the semiconductor structure is improved.

[0040] In the step of forming the gate structure 103 on the substrate 100 at the junction of the well region 101 and the drift region 102, the method includes: forming a first gate dielectric layer 1031 on the drift region 102 (as shown in Figure 5The first gate dielectric layer 1031 is spaced apart from the junction of the well region 101 and the drift region 102, and is also spaced apart from the end of the drift region 102 away from the well region 101, and specifically, the first gate dielectric layer 1031 exposes a third region for forming a drain electrode; a gate layer 1032 is formed on the substrate 100 and the first gate dielectric layer 1031 (as shown in Fig. 3). Figure 6 The gate layer 1032 is formed on the substrate 100 and the first gate dielectric layer 1031 (as shown in Fig. 3).

[0041] The first gate dielectric layer 1031 is spaced apart from the junction of the well region 101 and the drift region 102, and is also spaced apart from the end of the drift region 102 away from the well region 101, and specifically, the first gate dielectric layer 1031 exposes a third region for forming a drain electrode; a gate layer 1032 is formed on the substrate 100 and the first gate dielectric layer 1031 (as shown in Fig. 3).

[0042] In the embodiment, the gate structure 103 is a poly gate, and correspondingly, the material of the first gate dielectric layer 1031 is silicon oxide, and the material of the gate layer 1032 is poly silicon.

[0043] The step of forming the first gate dielectric layer 1031 includes: forming a first gate dielectric material layer 1034 on the substrate 100 (as shown in Fig. 3) ; forming a first mask layer (not shown in the figure) on the first gate dielectric material layer 1034 of the drift region 102; etching the first gate dielectric material layer 1034 with the first mask layer as a mask to form the first gate dielectric layer 1031. Figure 4 The step of forming the first gate dielectric layer 1031 includes: forming a first gate dielectric material layer 1034 on the substrate 100 (as shown in Fig. 3) ; forming a first mask layer (not shown in the figure) on the first gate dielectric material layer 1034 of the drift region 102; etching the first gate dielectric material layer 1034 with the first mask layer as a mask to form the first gate dielectric layer 1031.

[0044] The step of forming the gate layer 1032 includes: forming a gate material layer (not shown in the figure) covering the substrate 100 and the first gate dielectric layer 1031; patterning the gate material layer to form the gate layer 1032.

[0045] It should be noted that, in the step of forming the first gate dielectric layer 1031 on the drift region 102, if the first gate dielectric layer 1031 is too thick, the possibility of weakening the capacitive effect between the gate structure 103 and the substrate 100 is increased, which affects the switching speed of the device, and the possibility of weakening the control ability of the gate structure 103 on the carriers in the drift region 102 is also increased. Subsequently, the gate structure 103 on the drift region 102 is doped to form adjacent first and second doped regions 106 and 107. When the semiconductor structure is in operation, the electric field at the first and second doped regions 106 and 107 is very strong. If the first gate dielectric layer 1031 is too thin, the first gate dielectric layer 1031 is easily broken down, resulting in a lower breakdown voltage of the semiconductor structure, and there is also a risk of leakage current. In addition, if the first gate dielectric layer 1031 is too thin, the first gate dielectric layer 1031 is prone to degradation during long-term use, resulting in a shorter service life of the semiconductor structure. In the embodiment, in the step of forming the first gate dielectric layer 1031 on the drift region 102, the thickness of the first gate dielectric layer 1031 is 300 angstroms to 500 angstroms.

[0046] It should be noted that the step of forming the gate structure 103 further includes: after forming the adjacent well region 101 and drift region 102 in the substrate 100, forming a second gate dielectric material layer 1033 (as shown in Figure 3 In the step of patterning the gate material layer, the second gate dielectric material layer 1033 is patterned to form a second gate dielectric layer 1035 (as shown in Figure 6 .

[0047] In the embodiment, the gate structure 103 on the drift region 102 includes a first region I and a second region II which are in contact in the lateral direction.

[0048] In the subsequent process, the first region I of the gate structure 103 is doped with ions of a first type to form a first doped region, and the second region II of the gate structure 103 is doped with ions of a second type to form a second doped region.

[0049] In the embodiment, in the step of forming the gate structure 103, the number of the first region I and the second region II is both multiple, and the first region I and the second region II are arranged alternately. The first region I and the second region II are arranged alternately, so that the first doped region 106 and the second doped region 107 formed by subsequently doping the gate structure 103 are arranged alternately.

[0050] It is also needed to be explained that in the step of forming the gate structure 103, the gate structure 103 covers the drift region 102 between the well region 101 and the third region. Subsequently, a drain will be formed in the drift region 102 on one side of the gate structure 103, and the drain is formed in the third region.

[0051] In the forming method of the semiconductor structure provided by the embodiment of the present application, the gate structure 103 extends along the lateral direction in the drift region 102 and covers the drift region 102 between the well region 101 and the third region, that is, the gate structure 103 is not composed of multiple segment structures but is a whole strip-shaped structure. When the semiconductor structure works, the gate structure 103 can effectively reduce the field intensity concentration on the drift region 102, so that the field intensity distribution in the drift region 102 under the gate structure 103 is uniform and the electric field concentration is not easy to occur, the peak field intensity of the drain is reduced, and the breakdown voltage of the semiconductor structure is improved.

[0052] In the embodiment, the forming method of the semiconductor structure further includes: forming a side wall (not shown in the figure) on the sidewall of the gate structure 103. In the forming process of the semiconductor structure, the side wall plays a protection role for the sidewall of the gate structure 103.

[0053] In the embodiment, the material of the side wall includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, boron nitride, boron silicon nitride and boron silicon carbon nitride.

[0054] Reference Figure 7 The gate structure 103 on the drift region 102 is doped to form adjacent first doped regions 106 and second doped regions 107 for shielding, the first doped regions 106 are doped with first type ions, the second doped regions 107 are doped with second type ions, and the second type ions and the first type ions are different in conductive type; a source 104 is formed in the well region 101 on one side of the gate structure 103; and a drain 105 is formed in the drift region 102 on one side of the gate structure 103.

[0055] In the method for forming a semiconductor structure provided by the embodiment of the present application, an interconnection structure is further formed across the gate structure 103, because the gate structure 103 on the drift region 102 is doped, the first doped region 106 and the second doped region 107 are formed in adjacency, the first doped region 106 is doped with the first type of ions, the second doped region 107 is doped with the second type of ions, the second type of ions and the first type of ions are different in conduction type, therefore, the first doped region 106 and the second doped region 107 form a reverse-biased PN junction, which helps to balance and disperse the electric field caused by the interconnection structure in the direction from the drain 105 to the source, can effectively isolate the high voltage of the interconnection structure, and is not prone to cause hot carrier injection; in addition, the first doped region 106 and the second doped region 107 form a reverse-biased PN junction, which disperses the high potential difference between the first doped region 106 and the second doped region 107, thereby effectively reducing the electric field intensity and potential peak value on the surface of the device, and the segmented voltage division effect helps to optimize the electric field distribution on the surface of the device, reduces the electric field concentration, and thereby improves the breakdown voltage of the semiconductor structure.

[0056] In the embodiment, in the step of doping the gate structure 103 on the drift region 102, the first region I is doped with the first type of ions to form the first doped region 106, and the second region II is doped with the second type of ions to form the second doped region 107.

[0057] It should be noted that, because the number of the first region I and the second region II is both multiple in the step of forming the gate structure 103, and the first region I and the second region II are arranged alternately. Correspondingly, in the step of doping the gate structure 103 on the drift region 102, the first doped region 106 is formed in the first region I, and the second doped region 107 is formed in the second region II, and the first doped region 106 and the second doped region 107 are arranged alternately.

[0058] In the embodiment of the present application, by alternately arranging the first doped region 106 and the second doped region 107 in the lateral direction, a plurality of continuous PN junctions can be formed in the direction from the drain 105 to the source, the high potential difference is dispersed between each pair of N-type and P-type doped regions, the electric field in the drift region 102 is redistributed, which helps to balance and disperse the electric field caused by the interconnection structure, so that the electric field in the drift region 102 is not prone to be too concentrated, the electric field intensity and potential peak value on the surface of the drift region 102 are effectively reduced, and the breakdown voltage of the semiconductor structure is improved.

[0059] In the step of doping the gate structure 103 with the first type of ions, the first type of ions are also doped in the well region 101 to form the source 104, and the first type of ions are also doped in the drift region 102 to form the drain 105. Since the first doped region 106 is formed in the same doping process as the source 104 and the drain 105, the forming step of the first doped region 106 is simplified, and the forming period of the semiconductor structure is shortened.

[0060] In addition, since the source 104 and the drain 105 are formed in the same step as the first doped region 106, the doping concentration of the first type of ions in the source 104 and the drain 105 is the same as the doping concentration of the first type of ions in the first doped region 106. The uneven distribution of the electric field in the semiconductor structure is reduced, the local concentration of the electric field in the device is reduced, the local peak electric field is further reduced, and the breakdown voltage of the semiconductor structure is improved.

[0061] In the step of doping the gate structure 103 with the first type of ions, the first doped region 106 is formed before the second doped region 107. In other embodiments, the first doped region can also be formed after the second doped region.

[0062] In the step of doping the gate structure 103 with the second type of ions, the second type of ions are also doped in the well region 101 to form the body region 108. Since the body region 108 and the second doped region 107 are formed in the same step, the doping concentration of the second type of ions in the body region 108 is the same as the doping concentration of the second type of ions in the second doped region 107.

[0063] The body region 108 and the well region 101 are both doped with the second type of ions, but the doping concentration of the second type of ions in the body region 108 is higher than the doping concentration of the second type of ions in the well region 101, which enhances the concentration of electron holes. When the semiconductor structure is working, the body region 108 is used to guide the holes in the well region 101 to the external circuit.

[0064] In this embodiment, the first doped region 106 and the second doped region 107 are both doped with ions by ion implantation. Ion implantation has the characteristics of simple operation and low process cost.

[0065] When the semiconductor structure is working, the drain 105 is connected to a positive voltage, and the source is connected to zero voltage. In the direction from the drain 105 to the source 104, the potential is distributed to multiple reverse-biased PN junctions, which redistributes the electric field in the drift region 102, balances and disperses the electric field caused by the interconnection structure, so that the electric field in the drift region 102 is not easily concentrated, effectively reduces the electric field strength and potential peak on the surface of the drift region 102, and improves the breakdown voltage of the semiconductor structure.

[0066] It should be noted that the gate structure 103 is a polysilicon gate, and the material of the gate layer is polysilicon material, which has a certain work function. Different types and concentrations of doping ions can be introduced into the polysilicon to adjust the threshold voltage of the gate structure 103 and improve the current performance of the drain 105. For example, polysilicon doped with N-type ions (such as phosphorus) will have a lower work function, and polysilicon doped with P-type ions (such as boron) will have a higher work function.

[0067] Reference Figure 8 The method for forming the semiconductor structure further includes: after forming the first doped region 106 and the second doped region 107, forming a silicide blocking layer 109 (as shown in FIG. 1C) on the gate structure 103, the well region 101, and the drift region 102, wherein the silicide blocking layer 109 exposes the first doped region 106 and the second doped region 107. Figure 8 The method for forming the semiconductor structure further includes: after forming the first doped region 106 and the second doped region 107, forming a silicide blocking layer 109 (as shown in FIG. 1C) on the gate structure 103, the well region 101, and the drift region 102, wherein the silicide blocking layer 109 exposes the first doped region 106 and the second doped region 107.

[0068] In the subsequent process of the method for forming the semiconductor structure, a gate contact hole plug will be formed on the first doped region 106 and the second doped region 107. In order to reduce the contact resistance between the first doped region 106 and the second doped region 107 and the gate contact hole plug, a metal silicide layer will be formed on the first doped region 106 and the second doped region 107 in the subsequent process. The silicide blocking layer 109 is used to prevent the metal silicide layer from being formed in an undesired area.

[0069] In the embodiment, in the step of forming the silicide blocking layer 109, the silicide blocking layer 109 also exposes the source 104 and the drain 105. In the subsequent process of the method for forming the semiconductor structure, a source-drain contact hole plug will be formed on the source 104 and the drain 105. In order to reduce the contact resistance between the source 104 and the drain 105 and the source-drain contact hole plug, a metal silicide layer will be formed on the source 104 and the drain 105.

[0070] In the embodiment, the material of the silicide blocking layer 109 is an ONO (oxide-nitride-oxide) structure. In other embodiments, the material of the silicide blocking layer can also include other suitable materials, such as carbon-doped silicon nitride, etc.

[0071] The step of forming the silicide blocking layer 109 on the gate structure 103, the well region 101, and the drift region 102 includes: forming a silicide blocking material layer (not shown in the figure) on the gate structure 103, the well region 101, and the drift region 102; removing the silicide blocking material layer on the first doped region 106, the second doped region 107, the source 104, and the drain 105, and the remaining silicide blocking material layer serves as the silicide blocking layer 109.

[0072] Reference Figure 9 The forming method of the semiconductor structure further includes: performing metal silicide processing on the first doped region 106, the second doped region 107, the source 104 and the drain 105 exposed by the silicide blocking layer 109 to form a metal silicide layer 110.

[0073] The metal silicide layer 110 is used to reduce the contact resistance between the first doped region 106 and the second doped region 107 and the subsequently formed gate contact hole plug, and to reduce the contact resistance between the source 104 and the drain 105 and the subsequently formed source-drain contact hole plug.

[0074] In this embodiment, the metal silicide processing is performed on the first doped region 106, the second doped region 107, the source 104 and the drain 105 exposed by the silicide blocking layer 109 by using a metal silicide process to form the metal silicide layer 110.

[0075] In this embodiment, the material of the metal silicide layer 110 includes one or more of cobalt silicide, nickel silicide and platinum silicide.

[0076] Reference Figure 10 The forming method of the semiconductor structure further includes: forming a first dielectric layer 113 on the gate structure 103 and the substrate 100; and after forming the first dielectric layer 113, forming a gate contact hole plug 114 on the first doped region 106 and the second doped region 107, the gate contact hole plug 114 being in contact with the metal silicide layer 110 on the top of the first doped region 106 and the second doped region 107.

[0077] The gate contact hole plug 114 is used to lead out the first doped region 106 and the second doped region 107.

[0078] Specifically, the gate contact hole plug 114 is electrically connected with the metal silicide layer 110 on the top of the first doped region 106 and the second doped region 107. In this embodiment, the material of the gate contact hole plug 114 includes one or more of W, Ru and Co.

[0079] The forming method of the semiconductor structure further includes: forming a source-drain contact hole plug 115 on the source 104 and the drain 105, the source-drain contact hole plug 115 being used to lead out the source 104 and the drain 105.

[0080] Specifically, the source-drain contact hole plug 115 is electrically connected with the metal silicide layer 110 on the source 104 and the drain 105. In this embodiment, the material of the source-drain contact hole plug 115 includes one or more of W, Ru and Co.

[0081] In this embodiment, the material of the first dielectric layer 113 includes silicon oxide. The gate contact hole plug 114 and the source-drain contact hole plug 115 penetrate the first dielectric layer 113.

[0082] The method for forming the semiconductor structure further includes: forming a first metal layer 116 on the first dielectric layer 113, the first metal layer 116 being in contact with both the source-drain contact hole plug 115 on the drain 105 and the gate contact hole plug 114 on the second doped region 107.

[0083] The first metal layer 116 connects the source-drain contact hole plug 115 on the drain 105 and the gate contact hole plug 114 on the second doped region 107. When the off-state breakdown voltage test is performed, the second doped region 107 of the gate structure 103 is connected to the high voltage of the drain 105, and the first doped region 106 of the gate structure 103 is connected to the 0 volt of the source 104, which forms a potential pressure drop on the gate structure 103, and the potential of each point on the gate structure 103 is smaller than the potential of the drain 105 in the drift region 102, which not only adjusts the distribution of the electric field of the drift region 102, but also helps to reduce the lateral electric field of the drift region 102, and the pressure drop from the drain 105 to the gate structure 103 across the third gate dielectric layer 1033 is also smaller, which is beneficial to protect the first gate dielectric layer 1031 and the second gate dielectric layer 1035, reduce the damage of the electric field to the first gate dielectric layer 1031 and the second gate dielectric layer 1035, and reduce the influence of hot carrier injection.

[0084] It should be noted that the first metal layer 116 is also connected to the source-drain contact hole plug 115 on the source 104, for connecting the source 104 to the external circuit; and the first metal layer 116 is also connected to the gate contact hole plug 114 on the first doped region 106, for connecting the first doped region 106 to the external circuit.

[0085] In this embodiment, the material of the first metal layer 116 includes one or more of Cu, W and Co.

[0086] Reference Figure 11 The method for forming the semiconductor structure further includes: forming an interconnection contact hole plug 118 on the drain 105; and forming an interconnection structure 119 across the gate structure 103, the interconnection structure 119 being connected to the interconnection contact hole plug 118.

[0087] Specifically, a second dielectric layer 117 covering the first dielectric layer 113 and the first metal layer 116 is formed; an interconnection contact hole plug 118 penetrating the first dielectric layer 113 and the second dielectric layer 117 and connected to the drain 105 is formed; and an interconnection structure 119 connected to the interconnection contact hole plug 118 is formed on the second dielectric layer 117, the interconnection structure 119 being across the gate structure 103.

[0088] In the embodiment, the gate structure 103 comprises at least the first doped region 106 and the second doped region 107. When the semiconductor structure is in operation, the first doped region 106 and the second doped region 107 form a shielding electric field, which can offset the electric field generated by the interconnection structure 119, and reduce the influence of the interconnection structure 119 on the electron flow in the drift region 102.

[0089] The second dielectric layer 117 is used for electrical isolation. In the embodiment, the material of the second dielectric layer 117 comprises silicon oxide.

[0090] The interconnection via plug 118 and the interconnection structure 119 are used for leading out the drain 105. In the embodiment, the material of the interconnection structure 119 comprises one or more of Cu, W and Co, and the material of the interconnection via plug 118 comprises one or more of Cu, W and Co.

[0091] Reference Figure 11 The embodiment of the present application also provides a semiconductor structure.

[0092] The semiconductor structure comprises: a substrate 100; a well region 101 and a drift region 102 located in the substrate 100; a gate structure 103 located on the substrate 100 at the junction of the well region 101 and the drift region 102, and extending in a lateral direction perpendicular to the extension direction of the gate structure 103; a first doped region 106 and a second doped region 107 located in the gate structure 103 on the drift region 102, and adjacent to each other, and used for shielding, the first doped region 106 is doped with first-type ions, and the second doped region 107 is doped with second-type ions, and the second-type ions and the first-type ions are different in conduction type; a source 104 located in the well region 101 on one side of the gate structure 103; and a drain 105 located in the drift region 102 on one side of the gate structure 103.

[0093] The semiconductor structure provided by the embodiment of the present application is characterized in that the first doped region 106 is doped with first type ions, and the second doped region 107 is doped with second type ions, the second type ions and the first type ions are of different conductive types, thus the first doped region 106 and the second doped region 107 form a reverse-biased PN junction, which helps to balance and disperse the electric field caused by the interconnection structure in the direction from the drain 105 to the source 104, effectively isolates the high voltage of the interconnection structure, and is less likely to cause hot carrier injection, thus improving the reliability and stability of the semiconductor structure; in addition, the first doped region 106 and the second doped region 107 form a reverse-biased PN junction, which disperses the high potential difference between the first doped region 106 and the second doped region 107, thus effectively reducing the electric field intensity and potential peak value on the surface of the device, and the segmented voltage division effect helps to optimize the electric field distribution on the surface of the device, reduces the electric field concentration, and thus improves the breakdown voltage of the semiconductor structure.

[0094] The substrate 100 is used to provide a process platform for the LDMOS.

[0095] In the embodiment, the LDMOS is a planar transistor, and the substrate 100 is a planar substrate. In other embodiments, the semiconductor structure is taken as an example of an LDMOS fin field effect transistor, and the substrate includes a substrate and a fin portion located on the substrate.

[0096] In the embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate can also be a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, a gallium arsenide substrate, or a gallium indium substrate, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0097] In the embodiment, the drift region 102 has first type ions, and the well region 101 has second type ions, the first type ions and the second type ions are of different conductive types.

[0098] The well region 101 and the drift region 102 are in contact, the well region 101 serves as a lateral diffusion region to form a channel with a concentration gradient, and the drift region 102 is used to withstand a large voltage division.

[0099] Specifically, in the embodiment, the semiconductor structure is used to form an NLDMOS, the first type of ion is an N-type ion, the N-type ion includes one or more of phosphorus ion, arsenic ion and antimony ion, the second type of ion is a P-type ion, the P-type ion includes one or more of boron ion, gallium ion and indium ion. In other embodiments, the semiconductor structure is used to form a PLDMOS, the first type of ion is a P-type ion, the P-type ion includes one or more of boron ion, gallium ion and indium ion, the second type of ion is an N-type ion, the N-type ion includes one or more of phosphorus ion, arsenic ion and antimony ion.

[0100] It should be noted that in the step of forming the drift region 102, the drift region 102 includes a third region (not labeled in the figure) for forming the drain 105, and the drain 105 is formed in the third region.

[0101] In the embodiment, the gate structure 103 is used to control the opening and closing of the LDMOS channel.

[0102] In the embodiment, in the gate structure 103, the distance from the end of the gate structure 103 away from the well region 101 to the substrate 100 is greater than the distance from the end of the gate structure 103 close to the well region 101 to the substrate 100. That is, in the gate structure 103, the distance from the end of the gate structure 103 close to the drain 105 to the substrate 100 is greater than the distance from the end of the gate structure 103 close to the source to the substrate 100.

[0103] The method for forming the semiconductor structure of the application is used to form an LDMOS, and in operation, the closer to the drain 105, the more likely to occur breakdown in the LDMOS, and the distance from the end of the gate structure 103 close to the drain 105 to the substrate 100 is greater than the distance from the end of the gate structure 103 close to the source to the substrate 100, which is conducive to improving the breakdown voltage of the LDMOS.

[0104] Specifically, the gate structure 103 is in a stepped shape, and the gate structure 103 includes a first part close to the substrate 100, a second part away from the substrate 100, and a transition part connecting the first part and the second part, the first part is located at the junction of the well region 101 and the drift region 102, and the second part and the transition part are located on the drift region 102.

[0105] The transition part 103b of the gate structure 103 is located on the drift region 102, which allows more parts of the gate structure 103 to be located on the drift region 102, which is more conducive to providing an electric field from the drain 105 to the gate structure 103, reducing the peak field strength of the drain 105, and improving the breakdown voltage of the semiconductor structure.

[0106] The semiconductor structure provided by the embodiment of the present application has the second part of the gate structure 103 with the first doped region 106 and the second doped region 107 adjacent to each other, and the electric field at the first doped region 106 and the second doped region 107 is strong when the semiconductor structure works. By making the second part of the gate structure 103 away from the substrate 100, the probability of breakdown of the semiconductor structure at the second part of the gate structure 103 is reduced, and the breakdown voltage of the semiconductor structure is improved.

[0107] In the embodiment, the gate structure 103 includes: a first gate dielectric layer 1031 located in the drift region 102, and the first gate dielectric layer 1031 is spaced apart from the junction of the well region 101 and the drift region 102 and is also spaced apart from the end of the drift region 102 away from the well region 101, and specifically, the first gate dielectric layer 1031 exposes the third region for forming the drain electrode; and a gate layer 1032 located on the substrate of the well region 101 and the drift region 102 and the first gate dielectric layer 1031.

[0108] In the embodiment, the first gate dielectric layer 1031 is spaced apart from the junction of the well region 101 and the drift region 102 and is also spaced apart from the end of the drift region 102 away from the well region 101, that is, the first gate dielectric layer 1031 is located at the position close to the center of the drift region 102, so that the second part and the transition part of the gate structure 103 are formed in the drift region 102.

[0109] In the embodiment, the gate structure 103 is a poly gate, and correspondingly, the material of the first gate dielectric layer 1031 is silicon oxide, and the material of the gate layer 1032 is polysilicon.

[0110] It should be noted that if the first gate dielectric layer 1031 is too thick, the capacitance effect between the gate structure 103 and the substrate 100 is weakened, the switching speed of the device is affected, and the control ability of the gate structure 103 on the carriers of the drift region 102 is weakened. When the semiconductor structure works, the electric field at the first doped region 106 and the second doped region 107 is strong, and if the first gate dielectric layer 1031 is too thin, the first gate dielectric layer 1031 is easily broken down, resulting in a low breakdown voltage of the semiconductor structure, and there is also a risk of leakage current. In addition, the first gate dielectric layer 1031 is too thin and is prone to degradation during long-term use, resulting in a shorter service life of the semiconductor structure. In the embodiment, the thickness of the first gate dielectric layer 1031 is 300 angstroms to 500 angstroms.

[0111] It should be noted that the gate structure 103 further includes a second gate dielectric layer 1035 between the first gate dielectric layer 1031 and the substrate 100, and between the gate layer 1032 and the substrate 100.

[0112] In this embodiment, the gate structure 103 on the drift region 102 includes a first region I and a second region II which are laterally contacted.

[0113] The first doped region 106 is located in the first region I of the gate structure 103, and the second doped region 107 is located in the second region II of the gate structure 103.

[0114] Specifically, the number of the first region I and the second region II in the gate structure 103 is multiple, and the first region I and the second region II are alternately arranged. The first region I and the second region II are alternately arranged, so that the first doped region 106 and the second doped region 107 formed after subsequent doping of the gate structure 103 are alternately arranged.

[0115] It should be further noted that the gate structure 103 covers the drift region 102 between the well region 101 and the drain 105.

[0116] In the semiconductor structure provided by the embodiment of the present application, the gate structure 103 extends in the drift region 102 along the lateral direction and covers the drift region 102 between the well region 101 and the drain 105, that is, the gate structure 103 is not composed of multiple segment structures, but is an integral long strip structure. When the semiconductor structure works, the gate structure 103 on the drift region 102 can effectively reduce the field strength concentration, so that the field strength distribution in the drift region 102 under the gate structure 103 is uniform, and the electric field concentration is not easy to occur, the peak field strength of the drain 105 is reduced, and the breakdown voltage of the semiconductor structure is improved.

[0117] In this embodiment, the semiconductor structure further includes a side wall on the sidewall of the gate structure 103 (not shown in the figure). In the forming process of the semiconductor structure, the side wall plays a protective role for the sidewall of the gate structure 103.

[0118] In this embodiment, the material of the side wall includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, boron nitride, boron silicon nitride and boron silicon carbon nitride.

[0119] In this embodiment, the source 104 and the drain 105 have first-type ions.

[0120] When the semiconductor structure is in operation, the electric field lines are directed from the drain 105 to the source 104 and also to the first doped region 106 and the second doped region 107 in the gate structure 103, the electric field on the gate structure 103 is redistributed, so that the electric field in the drift region 102 is not too concentrated, the peak electric field of the drain 105 is reduced, and the breakdown voltage of the semiconductor structure is improved. Moreover, because the first doped region 106 is formed in the same doping process as the source 104 and the drain 105, the forming process of the first doped region 106 is simplified, and the forming period of the semiconductor structure is shortened.

[0121] It should be noted that the doping concentration of the first type of ions in the source 104 and the drain 105 is the same as the doping concentration of the first type of ions in the first doped region 106, which can reduce the uneven distribution of the electric field in the semiconductor structure, help to reduce the local concentration of the electric field, thereby reducing the local peak electric field, and is conducive to improving the breakdown voltage of the device.

[0122] The semiconductor structure further comprises a body region 108 in the well region 101, the body region 108 having the second type of ions therein. The body region 108 and the well region 101 are both doped with the second type of ions, and the body region 108 is used to direct the holes in the well region 101 to an external circuit.

[0123] In this embodiment, the body region 108 is a high-concentration doped region of the second type of ions, which enhances the concentration of the holes.

[0124] In this embodiment, the body region 108 and the second doped region 107 are formed simultaneously, and the doping concentration of the second type of ions in the body region 108 is the same as the doping concentration of the second type of ions in the second doped region 107.

[0125] It should be further noted that the gate structure 103 is a polysilicon gate, and the material of the gate layer is polysilicon material, which has a certain work function. By introducing different types and concentrations of doping ions in the polysilicon, the threshold voltage of the gate structure 103 can be adjusted, and the current performance of the drain 105 can be improved. For example, polysilicon doped with N-type ions (such as phosphorus) will have a lower work function, and polysilicon doped with P-type ions (such as boron) will have a higher work function.

[0126] The semiconductor structure further comprises a silicide blocking layer 109 covering the gate structure 103 and the substrate 100, and exposing the first doped region 106 and the second doped region 107; a metal silicide layer 110 on top of the first doped region 106 and the second doped region 107; and a gate contact hole plug 114 on the metal silicide layer 110 on top of the first doped region 106 and the second doped region 107.

[0127] In the formation of the semiconductor structure, the silicide barrier layer 109 defines the formation position of the metal silicide layer 110, which is used to reduce the contact resistance between the first doped region 106 and the second doped region 107 and the gate contact hole plug 114, which is used to lead out the first doped region and the second doped region.

[0128] In the embodiment, the material of the silicide barrier layer 109 is an ONO (oxide-nitride-oxide) structure. In other embodiments, the material of the silicide barrier layer can also include other suitable materials, such as carbon-doped silicon nitride, etc.

[0129] In the embodiment, the material of the metal silicide layer 110 includes one or more of cobalt silicide, nickel silicide, and platinum silicide.

[0130] Specifically, the gate contact hole plug 114 is electrically connected to the metal silicide layer 110 on the first doped region 106 and the second doped region 107. In the embodiment, the material of the gate contact hole plug 114 includes one or more of Cu, W, and Co.

[0131] In the embodiment, the silicide barrier layer 109 also exposes the source 104 and the drain 105, and the metal silicide layer 110 is also formed on the source 104 and the drain 105. The semiconductor structure further includes a source-drain contact hole plug 115 located on the metal silicide layer 110 on the source 104 and the drain 105.

[0132] The semiconductor structure further includes a first dielectric layer 113 located on the gate structure 103 and the substrate 100, and the gate contact hole plug 114 and the source-drain contact hole plug 115 penetrate the first dielectric layer 113.

[0133] In the embodiment, the material of the first dielectric layer 113 includes silicon oxide.

[0134] The semiconductor structure further includes a first metal layer 116 located on the first dielectric layer 113, which simultaneously contacts the source-drain contact hole plug 115 on the source 103 and the gate contact hole plug 114 on the first doped region 106, and simultaneously contacts the source-drain contact hole plug 115 on the drain 105 and the gate contact hole plug 114 on the second doped region 107.

[0135] The first metal layer 116 connects the source-drain contact hole plug 115 on the source 103 with the gate contact hole plug 114 on the first doped region 106, and connects the source-drain contact hole plug 115 on the drain 105 with the gate contact hole plug 114 on the second doped region 107. When the off-state breakdown voltage test is performed, the second doped region 107 of the gate structure 103 is connected to the high voltage of the drain 105, and the first doped region 106 of the gate structure 103 is connected to the 0 volt of the source 104, which forms a potential pressure drop on the gate structure 103, and the potential of each point on the gate structure 103 is smaller than the difference between the potential of the drain 105 and the potential of the drift region 102, which not only adjusts the distribution of the electric field of the drift region 102, but also reduces the lateral electric field of the drift region 102, and the pressure drop from the drain 105 to the gate structure 103 across the gate dielectric layer 1031 is also smaller, which is beneficial to protect the gate dielectric layer 1031, reduce the damage of the electric field to the gate dielectric layer 1031, and reduce the influence of hot carrier injection.

[0136] In the embodiment, the material of the first metal layer 116 includes one or more of Cu, W and Co.

[0137] The semiconductor structure further includes: an interconnection contact hole plug 118 located on the drain 105; and an interconnection structure 119 crossing the gate structure 103 and connected with the interconnection contact hole plug 118.

[0138] Specifically, the semiconductor structure further includes: a second dielectric layer 117 located on the first dielectric layer 113 and the first metal layer 116; the interconnection contact hole plug 118 penetrating the first dielectric layer 113 and the second dielectric layer 117 and connected with the drain 105; and the interconnection structure 119 located on the second dielectric layer 117 and connected with the interconnection contact hole plug 118, and the interconnection structure 119 crosses the gate structure 103.

[0139] In the embodiment, the gate structure 103 at least includes the first doped region 106 and the second doped region 107, and the first doped region 106 and the second doped region 107 form a shielding electric field when the semiconductor structure works, which can offset the electric field generated by the interconnection structure 119 and reduce the influence of the interconnection structure 119 on the electron flow in the drift region 102.

[0140] In the embodiment, the material of the second dielectric layer 117 includes silicon oxide.

[0141] In the embodiment, the material of the interconnection structure 119 includes one or more of Cu, W and Co.

[0142] In the embodiment, the material of the interconnection contact hole plug 118 includes one or more of Cu, W and Co.

[0143] The semiconductor structure can be formed by the forming method of the foregoing embodiments or other forming methods. For the specific description of the semiconductor structure of the present embodiment, reference can be made to the corresponding description in the foregoing embodiments, which will not be repeated here.

[0144] Although the embodiments of the present application have been disclosed as above, they are not limited to the above. Any person skilled in the art, without departing from the spirit and scope of the embodiments of the present application, can make various changes and modifications, and therefore the scope of protection of the embodiments of the present application should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that substrate; The adjacent well region and drift region are located in the substrate; a gate structure located on the substrate at the junction of the well region and the drift region, with the gate structure extending in the drift region in a lateral direction perpendicular to the extension direction of the gate structure; a first doping region and a second doping region, located in the gate structure on the drift region, and adjacent to each other, for shielding, wherein the first doping region is doped with a first type of ions, and the second doping region is doped with a second type of ions, and the second type of ions and the first type of ions have different conductivity types; a source electrode, located in the well region on one side of the gate structure; A drain is located in the drift region on one side of the gate structure.

2. The semiconductor structure according to claim 1, wherein The gate structure on the drift region includes a first region and a second region that are laterally contacted; The first doping region is located in the first area, and the second doping region is located in the second area.

3. The semiconductor structure according to claim 2, wherein: There are multiple first and second regions in the gate structure, and the first and second regions are arranged alternately; the first doped region is located in the first region, the second doped region is located in the second region, and the first doped region and the second doped region are arranged alternately.

4. The semiconductor structure according to claim 2, wherein: The source and drain contain the first type ions, and the doping concentration of the first type ions in the source and drain is the same as the doping concentration of the first type ions in the first doping region; The semiconductor structure further includes a body region located in the well region, wherein the body region contains second-type ions, and the doping concentration of the second-type ions in the body region is the same as the doping concentration of the second-type ions in the second doping region.

5. The semiconductor structure according to claim 1, wherein The drift region includes a third region for forming a drain, and the drain is formed in the third region; The gate structure covers the drift region between the well region and the drain.

6. The semiconductor structure according to claim 1, wherein In the gate structure, a distance from an end away from the well region in a lateral direction to the substrate is greater than a distance from an end close to the well region in a lateral direction to the substrate.

7. The semiconductor structure according to claim 1 or 6, wherein: The gate structure is stepped and includes a first portion close to the substrate, a second portion away from the substrate, and a transition portion connecting the first portion and the second portion. The first portion is located at the junction of the well region and the drift region, and the second portion and the transition portion are located on the drift region.

8. The semiconductor structure according to claim 1, wherein: The gate structure includes: A first gate dielectric layer is located in the drift region, and the first gate dielectric layer is spaced apart from the junction of the well region and the drift region, and is also spaced apart from one end of the drift region away from the well region; a gate layer is located on the substrate of the well region and the drift region, and on the first gate dielectric layer.

9. The semiconductor structure according to claim 8, wherein: The thickness of the first gate dielectric layer is 300 angstroms to 500 angstroms.

10. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: an interconnection contact hole plug, located on the drain; An interconnection structure spans the gate structure and is connected to the interconnection contact hole plug.

11. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming adjacent well and drift regions in the substrate; forming a gate structure on the substrate at the junction of the well region and the drift region, with the gate structure extending in the drift region in a lateral direction perpendicular to the extension direction of the gate structure; doping the gate structure on the drift region to form adjacent first doping regions and second doping regions for shielding, wherein the first doping region is doped with first-type ions and the second doping region is doped with second-type ions, wherein the second-type ions and the first-type ions have different conductivity types; forming a source electrode in the well region on one side of the gate structure; A drain is formed in the drift region on one side of the gate structure.

12. The method for forming a semiconductor structure according to claim 11, wherein: In the step of forming a gate structure on the substrate of the well region and the drift region, the gate structure on the drift region includes a first region and a second region that are laterally contacted; In the step of doping the gate structure on the drift region, the first region is doped with first-type ions to form the first doping region, and the second region is doped with second-type ions to form the second doping region.

13. The method for forming a semiconductor structure according to claim 12, wherein: In the step of forming the gate structure, the number of the first region and the number of the second region are both plural, and the first regions and the second regions are alternately arranged; In the step of doping the gate structure above the drift region, the first doping region is formed in the first region, and the second doping region is formed in the second region, and the first doping region and the second doping region are alternately arranged.

14. The method for forming a semiconductor structure according to claim 11, wherein: In the step of doping the gate structure with first-type ions, the first-type ions are also doped in the well region to form the source, and the first-type ions are also doped in the drift region to form the drain, and the doping concentration of the first-type ions in the source and drain is the same as the doping concentration of the first-type ions in the first doping region; In the step of doping the gate structure with second-type ions, the second-type ions are also doped in the well region to form a body region, and the doping concentration of the second-type ions in the body region is the same as the doping concentration of the second-type ions in the second doping region.

15. The method for forming a semiconductor structure according to claim 11, wherein: In the step of forming the drift region, the drift region includes a third region for forming a drain; In the step of forming the gate structure, the gate structure covers the drift region between the well region and the third region; In the step of forming a drain in the drift region on one side of the gate structure, the drain is formed in the third region.

16. The method for forming a semiconductor structure according to claim 11, wherein: In the step of forming the gate structure, a distance from an end portion away from the well region in a lateral direction to the substrate is greater than a distance from an end portion close to the well region in a lateral direction to the substrate.

17. The method for forming a semiconductor structure according to claim 11 or 16, wherein: In the step of forming the gate structure, the gate structure is stepped, and the gate structure includes a first part close to the substrate, a second part away from the substrate, and a transition part connecting the first part and the second part. The first part is located at the junction of the well region and the drift region, and the second part and the transition part are located on the drift region.

18. The method for forming a semiconductor structure according to claim 11, wherein: The step of forming a gate structure on the substrate at the junction of the well region and the drift region includes: A first gate dielectric layer is formed in the drift region, and the first gate dielectric layer is spaced apart from the junction of the well region and the drift region, and is also spaced apart from one end of the drift region away from the well region; a gate layer is formed on the substrate of the well region and the drift region and the first gate dielectric layer.

19. The method for forming a semiconductor structure according to claim 18, wherein: In the step of forming a first gate dielectric layer in the drift region, the thickness of the first gate dielectric layer is 300 angstroms to 500 angstroms.

20. The method for forming a semiconductor structure according to claim 11, wherein: The method for forming the semiconductor structure further includes: forming an interconnection contact hole plug on the drain; An interconnection structure is formed across the gate structure, wherein the interconnection structure is connected to the interconnection contact plug.

Images