A method for generating a circuit topology based on a transfer function

Abstract

The application discloses a method for generating a circuit topology based on a transfer function, and relates to the technical field of circuit design, and solves the technical problem that it is difficult to combine artificial intelligence methods to improve the efficiency and reliability of analog circuit design in circuit design. The method comprises the following steps: based on graph theory, a connected graph G is established under the structure and element parameters of a given RLC circuit; the relationship between the transfer function and the impedance or admittance of the network nodes of the connected graph G is derived based on the RLC circuit; a tree and a secondary tree required for searching and calculating the transfer function are searched and calculated to obtain the final expression of the transfer function; the order and structure of the transfer function are analyzed, and circuit design rules are obtained in combination with specification constraints and design specifications of the circuit design; and the topology and parameters of the RLC circuit are searched through genetic programming to obtain the optimal topology structure and the optimal element admittance value. The application significantly improves the efficiency and reliability of circuit synthesis design by analyzing a set of hard constraint rules to guide the automatic search of genetic programming.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit design, and in particular to a method for generating a circuit topology based on a transfer function. BACKGROUND

[0002] The topology design of a circuit is a complex and time-consuming process, and although there are Electronic design automation (EDA) tools, designers still need to have a deep understanding of circuit parameterization and topology changes to create high-quality designs.

[0003] In recent years, various types of artificial intelligence algorithms, such as evolutionary algorithms, machine learning, and reinforcement learning, have been able to effectively learn and optimize circuits by employing human-like learning and reasoning capabilities, thereby finding the best circuit parameters that meet the given specifications. Such algorithms typically require a target (fitness) function that describes the performance or quality of the circuit, and can include certain constraints of the circuit design. The fitness evaluation process can be divided into two categories: an equation-based evaluation process that applies mathematical equations to describe the behavior of the circuit; and a simulation-based evaluation process that requires Spice simulation software to analyze the circuit. However, the latter is usually more difficult to implement and can consume more time due to the interaction between the algorithm compiler and the simulation platform. Although most machine learning-based methods have excellent performance in optimizing analog circuits, they usually require intensive computation and are less flexible than traditional optimization methods. In addition, they often lack explainability for the optimization process, making it difficult for users to understand how the circuit is optimized and how design choices are made for each optimization step.

[0004] A transfer function refers to the ratio of the Laplace transform (or z-transform) of the response (i.e., output) quantity to the Laplace transform of the excitation (i.e., input) quantity under zero initial conditions, and is an important mathematical model for describing the relationship between the input and output of a circuit. In circuit design, the transfer function can be used to analyze the stability, frequency response, and other characteristics of a circuit. For specific circuits, such as filter circuits, the transfer function can be used to calculate specific parameters such as cutoff frequency, passband attenuation, and stopband attenuation during the design process. The transfer function can also be used to characterize the performance and partial functions of a circuit. In actual chip design, due to the limitation of chip area, the corresponding module circuit area is also limited. The limitation of area is represented as constraints on the size and number of components at the schematic level. Under the constraints of component number and size, it is necessary to search for circuit topology and component parameters based on artificial intelligence algorithms using transfer functions to improve the efficiency of analog circuit design. SUMMARY

[0005] The purpose of the present application is to provide a method for generating circuit topology based on transfer function, so as to solve the technical problem that it is difficult to combine artificial intelligence method to improve the efficiency and reliability of analog circuit design in the prior art. The preferred technical solutions in the many technical solutions provided by the present application can produce many technical effects, which are described in detail below.

[0006] To achieve the above-mentioned purpose, the present application provides the following technical solutions:

[0007] The method for generating circuit topology based on transfer function provided by the present application comprises the following steps: S100: based on graph theory, establishing a connected graph G based on circuit topology under the given structure and element parameters of RLC circuit; S200: deriving the relationship between the transfer function and the impedance or admittance of the network nodes of the connected graph G based on the RLC circuit; S300: searching for the tree and the secondary tree required for calculating the transfer function, and calculating the final expression of the transfer function of the RLC circuit; S400: analyzing the order and structure of the transfer function based on the transfer function expression, combining the specification constraints and design specifications of circuit design, obtaining the pre-requisites and constraints of designing heterogeneous circuits as circuit design rules; S500: taking the circuit design rules as a set of hard constraint rules for searching topology and parameters, searching the topology and parameters of the RLC circuit through genetic programming, and obtaining the optimal topology structure and the optimal element admittance value.

[0008] Preferably, the method further comprises the following steps: S600: outputting the optimal topology structure and the optimal element admittance value, and comparing them with the Bode diagram of the target response H_target of the transfer function to verify the performance.

[0009] Preferably, in the S100 step, the RLC circuit is a two-port network comprising port 1 and port 2, forming five element branches of first branch, second branch, third branch, fourth branch and fifth branch; in the RLC circuit, the edges in the circuit are taken as the edges of the connected graph G, the nodes in the circuit are taken as the nodes of the connected graph G, and the sum of the admittances of all elements on each edge is the value of the edge in the connected graph G.

[0010] Preferably, in the S200 step,

[0011] The first expression of the transfer function H corresponding to the circuit based on the parameter matrix Z is obtained:

[0012] ,

[0013] The parameter matrix Z is defined as:

[0014] ,

[0015] Among them, Vp1 and Vp2 represent the port voltage of port 1 and port 2 respectively, and Ip1 and Ip2 represent the port current of port 1 and port 2 respectively; Zin1 represents the input impedance of port 1; Z12 represents the first mutual impedance of port 1 and port 2, and represents the influence of the current of port 2 on the voltage of port 1; Z21 represents the second mutual impedance of port 1 and port 2, and represents the influence of the current of port 1 on the voltage of port 2; Zin2 represents the input impedance of port 2;

[0016] Based on the open circuit of port 2, the second expression of transfer function H is obtained as follows:

[0017] .

[0018] Preferably, the S300 step comprises: analyzing the tree and the secondary tree involved in the node admittance based on the second expression of transfer function H, and obtaining the third expression of transfer function H based on the topological formula of the two-port network:

[0019] ,

[0020] The topological formula of the two-port network is:

[0021]

[0022] wherein represents the sum of the admittance products of all secondary trees in which a and b are not together in the connected graph G, represents the sum of the admittance of all secondary trees in which ab and cd are respectively two groups and ab and cd are not together in the connected graph G, is the sum of the branch admittance products of all trees; the sum of the admittance products of the required tree and the secondary tree is calculated, and the admittance after Laplace transform based on the resistance R, the capacitance C and the inductance L is respectively The final expression of the transfer function is as follows, wherein s is a complex frequency variable:

[0023] .

[0024] Preferably, in the S400 step, the order of the transfer function is the order of the highest order term in the final expression of the transfer function, which corresponds to the number of energy storage elements.

[0025] ​Preferably, in the step S400, the preconditions and constraints for designing the heterogeneous circuit include: under high frequency AC condition, if the transfer function H(∞) = 0, the circuit cannot have only resistance, if the transfer function H(∞) ≠ 0, the circuit cannot contain series inductance in the main signal path or parallel capacitance to ground; under DC condition, if the transfer function H(0) = 0, the circuit is not a pure resistance network, nor a structure that allows DC to pass, if the transfer function H(0) ≠ 0, the circuit cannot contain series capacitance in the main signal path or parallel inductance to ground.

[0026] Preferably, in the step S500, the searching of the topology and parameters of the RLC circuit by genetic programming includes: S510: taking the basic building blocks of the RLC circuit as the terminal set of the genetic programming; S520: defining the objective function of the genetic programming Minimize Cost = Error(H_actual, H_target) + Penalty, wherein Error represents the root mean square error between the actual response H_actual and the target response H_target of the transfer function calculated at multiple frequency points, and Penalty represents the penalty term for the features that are not expected to appear; S530: initializing the genetic population of the genetic programming, randomly generating a batch of circuit individuals, each of which is a tree structure including a function set and a terminal set, and removing the circuit individuals that violate the hard constraint rule set; S540: performing a fast local optimization search on the element admittance values in the topology structure of each circuit individual, finding the admittance value combination that minimizes the root mean square error Error, and calculating the fitness Cost value thereof; S550: generating new circuit individuals through crossover or mutation, and immediately verifying them with the hard constraint rule set, discarding the new circuit individuals that violate the hard constraint rule set; S560: replacing the circuit individuals in the population before the step S550 with the new generated compliant offspring to form a new generation population, and returning to the step S540 to repeat the whole process until a preset number of generations of genetic programming is reached, or the Cost value converges within a preset threshold.

[0027] Preferably, the step S550 includes: S551: according to the objective function Cost value, selecting the elite circuit individuals with the lowest Cost value into the next generation through roulette selection or tournament selection; S552: performing breeding operation on the selected elite circuit individuals to generate new offspring circuits; S553: exchanging the sub-trees of two parent circuits to generate new circuit structures; S554: randomly changing a part of a circuit individual, or adding a new parallel branch at a node.

[0028] Preferably, the S600 step specifically comprises: S610: outputting a circuit individual with the lowest Cost value as a target circuit individual, including a complete topology and optimal element admittance value; and S620: simulating the target circuit individual in circuit simulation software, drawing a Bode plot, and comparing the Bode plot with a Bode plot of a target response H_target of the transfer function to verify performance.

[0029] Implementing one of the above technical solutions of the present application has the following advantages or beneficial effects:

[0030] In this embodiment, a connected graph model of the circuit is established by graph theory, and a general relationship between the circuit transfer function and the network node impedance / admittance is derived based on this, thereby constructing a forward mapping from the circuit topology to a mathematical expression. Subsequently, the transfer function is analyzed in depth, its order and structure are extracted, and circuit design rules are formed in combination with specification constraints and design specifications of the circuit design. Based on the circuit design rules, the genetic programming algorithm is guided to perform effective search in the search space, thereby avoiding blind exploration of the algorithm in physically infeasible or performance-unrelated regions. The algorithm optimizes the structure (topology) and parameters (element values) of the circuit in coordination, obtains the optimal topology structure and optimal element admittance value, and obtains a complete circuit design scheme including the topology structure and accurate element values. This embodiment guides the automated search of the genetic programming by analyzing the hard constraint rule set, significantly improves the efficiency and reliability of the circuit synthesis design, and realizes the automated design of analog circuits. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained according to these drawings without creative labor for those skilled in the art. In the drawings:

[0032] Figure 1 is a flowchart of a method for generating a circuit topology based on a transfer function according to an embodiment of the present application;

[0033] Figure 2 is a flowchart of the S500 step of the method for generating a circuit topology based on a transfer function according to an embodiment of the present application;

[0034] Figure 3 is a flowchart of the S550 step of the method for generating a circuit topology based on a transfer function according to an embodiment of the present application;

[0035] Figure 4 is a flowchart of the S600 step of the method for generating a circuit topology based on a transfer function according to an embodiment of the present application;

[0036] Figure 5 is an RLC circuit diagram in a method for generating a circuit topology based on a transfer function according to an embodiment of the present application;

[0037] Figure 6 is a connected graph G corresponding to an RLC circuit in a method for generating a circuit topology based on a transfer function according to an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the objects, technical solutions, and advantages of the present application clearer, the various exemplary embodiments to be described below will be described with reference to the corresponding drawings, which form a part of the exemplary embodiments, and in which various exemplary embodiments that can be used to implement the present application are described. Identical numbers in different drawings represent identical or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present disclosure. It should be understood that they are merely examples of procedures, methods, and apparatuses, etc. consistent with some aspects of the present disclosure as detailed in the appended claims, and other implementations can be used, or modifications can be made to the implementations listed herein, without departing from the scope and spirit of the present application.

[0039] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", and the like indicate the orientation or positional relationship based on the drawings shown, and are merely for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the elements referred to must have a particular orientation, be constructed and operated in a particular orientation. The terms "first", "second", and the like are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. The term "a plurality of" means two or more. The terms "connected", "connected" should be broadly understood, for example, it can be fixed connection, detachable connection, integral connection, mechanical connection, electrical connection, communication connection, direct connection, indirect connection through intermediate medium, it can be the internal communication of two elements or the interaction relationship of two elements. The term "and / or" includes any and all combinations of one or more related listed items. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0040] In order to illustrate the technical solutions described in the present application, the following will be described by specific embodiments, only showing the parts related to the embodiments of the present application.

[0041] Embodiment:

[0042] As Figure 1As shown, the present application provides a method for generating circuit topology based on transfer function, comprising the following steps: S100: based on graph theory, establishing a connected graph G based on circuit topology under the given structure and element parameters of RLC circuit, any two points in the connected graph G are connected, which intuitively represents the connection relationship between edges and nodes in the RLC circuit; the graph in graph theory is a graph composed of a plurality of given points and lines connecting two points, which is usually used to describe a certain specific relationship between certain things, and the point represents the thing, and the line connecting two points indicates that the corresponding two things have such a relationship. S200: deriving the relationship between the transfer function and the impedance or admittance of the network nodes of the connected graph G based on the RLC circuit; S300: searching for the tree and the secondary tree required for calculating the transfer function, and calculating the final expression of the transfer function of the RLC circuit; S400: based on the transfer function (the transfer function is usually represented by H(s), which essentially describes the ratio between the Laplace transform of the output signal and the Laplace transform of the input signal, embodies the close relationship between the input signal and the output signal, and can more clearly understand the dynamic characteristics of the circuit; through the transfer function, the response of the circuit under different input signals can be predicted and optimized) expression, analyzing the order and structure of the transfer function, combining the specification constraints and design specifications of the circuit design, obtaining the pre-requisites and constraints for designing the heterogeneous circuit, and taking the circuit design rules; S500: taking the circuit design rules as a hard constraint rule set for searching for topology and parameters, in the embodiment, the hard constraint rule set is as follows: ① the circuit must contain at least three energy storage elements; ② the circuit must have a structure that can make the transfer function H(0)=0 (such as a main road series capacitor or a ground parallel inductor); ③ the circuit is prohibited from any structure that can make the transfer function H(∞)=0 (such as a ground parallel capacitor or a main road series inductor); ④ the circuit is prohibited from any form of LC trap structure; ⑤ since it is the minimum phase, the ladder network topology is preferred; then searching for the topology and parameters of the circuit through genetic programming, obtaining the optimal topology structure and the optimal element admittance value, i.e. obtaining the complete circuit design scheme.

[0043] In this embodiment, a connected graph model of the circuit is established by graph theory, and a general relationship between the circuit transfer function and the network node impedance / admittance is derived based on this, thereby constructing a forward mapping from the circuit topology to the mathematical expression. Subsequently, the transfer function is analyzed in depth, its order and structure are extracted, and the circuit design rules are formed in combination with the specification constraints and design specifications of the circuit design. Based on the circuit design rules, the genetic programming algorithm is guided to perform effective search in the search space, avoiding blind exploration of the algorithm in the region that is physically infeasible or irrelevant to performance. The algorithm optimizes the structure (topology) and parameters (element values) of the circuit in coordination, obtains the optimal topology structure and the optimal element admittance value, and obtains the complete circuit design scheme including the topology structure and the accurate element values. The embodiment guides the automatic search of the genetic programming by analyzing the hard constraint rule set, significantly improves the efficiency and reliability of the circuit synthesis design, and realizes the automatic design of the analog circuit.

[0044] As an optional implementation, the following steps are further included: S600: output the optimal topology structure and the optimal element admittance value (the admittance value is the inverse of the impedance, which is used to characterize the conduction ability of the circuit to the current, and the element admittance value at this time is the combination of the admittance values of the resistor, the inductor, and the capacitor), and compare it with the Bode plot of the target response H_target of the transfer function to verify the performance, so that the frequency response is verified to be highly consistent with the target transfer function through simulation, and the Bode plot is an important tool for analyzing the frequency response of a linear time-invariant system. By depicting how the gain (amplitude) and phase of the transfer function change with frequency, engineers can evaluate system stability. As shown in Figure 4 As shown in

[0045] As an optional implementation, as shown in Figure 5 、 Figure 6 In the step S100, the RLC circuit is a two-port network including a port 1 (terminal 1-1') and a port 2 (terminal 2-2'), forming a first branch (branch 1 in Figure 6 ), a second branch (branch 2 in Figure 6 ), a third branch (branch 3 in Figure 6 ), a fourth branch (branch 4 in Figure 6 ), and a fifth branch (branch 5 in Figure 6The middle branch 5) five meta-branches; in the RLC circuit, taking the edges in the circuit as the edges of the connected graph G, and the nodes in the circuit as the nodes of the connected graph G, and the sum of the admittance of all elements on each edge as the value of the edge in the connected graph G. Specifically, as shown in Figure 5

[0046] As an optional implementation, in the S200 step, the first expression of the transfer function H corresponding to the circuit is obtained based on the parameter matrix Z:

[0047]

[0048] The parameter matrix Z is defined as:

[0049]

[0050] wherein, V1 and V2 represent the port voltage of port 1 and port 2 respectively, and I1 and I2 represent the port current of port 1 and port 2 respectively; Z1 represents the input impedance of port 1; Z12 represents the first mutual impedance of port 1 and port 2, and represents the influence of the current of port 2 on the voltage of port 1; Z21 represents the second mutual impedance of port 1 and port 2, and represents the influence of the current of port 1 on the voltage of port 2; Z2 represents the input impedance of port 2; based on the open circuit of port 2, Z2 = Z21 = 0, and the second expression of the transfer function H is obtained as:

[0051] .

[0052] As an optional implementation, the S300 step includes:

[0053] ​​​​​​​​​​Based on the second expression of the transfer function H, the tree and second-order tree involved in the node admittance analysis are determined. The tree of the connected graph G corresponds to a subgraph of the connected graph G, and satisfies the conditions of connectivity, containing all nodes but not cycles. Removing any arbitrary edge from the tree of the connected graph G yields the second-order tree. Based on the topology formula of the two-port network, the third expression of the transfer function H is obtained:

[0054] ,

[0055] The topology formula for a two-port network is:

[0056]

[0057] in (a represents 1, b represents 1',) (The expression is for convenience) represents the sum of the admittance products of all second-order trees in a connected graph G where points a and b are not together. In a connected graph G, ab and cd represent 12, 12' and 1'2, respectively. The expression is the sum of the admittances of all second-order trees that each form two groups and whose ab and cd are not together. It is the sum of the derivative products of all tree branches;

[0058] The specific calculation process for calculating the sum of the admittance products of the required tree and the second-level tree, and the tree and second-level tree required for the transfer function, is as follows:

[0059] like Figure 6 As shown, The corresponding tree has the following branches: branch 1-2, branch 2-3, branch 3-4, branch 4-5, branch 1-4, branch 1-5, branch 2-5, and branch 3-5. Therefore, we can deduce:

[0060] in The admittance after the Laplace transform on branch a;

[0061] The corresponding tree has the following branches: branch 1-2, branch 2-3, branch 1-5, and branch 2-5. Therefore:

[0062]

[0063] There is no corresponding tree, therefore

[0064]

[0065] Therefore, we get:

[0066] ,

[0067] The admittance based on the Laplace transform of the resistance R, the capacitance C and the inductance L is The final expression of the transfer function is as follows, where s is a complex frequency variable:

[0068] .

[0069] As an optional implementation, in the step S400, a new passive two-port network is designed based on the final expression of the transfer function, and the new passive two-port network has the same transfer function as the initial circuit network. The order of the transfer function is the order of the highest order term in the final expression of the transfer function, which corresponds to the number of energy storage elements. Specifically, based on the analysis of the given transfer function, the corresponding constraints are formulated: the poles of the transfer function are analyzed, and the existing numerical method is used for the analysis, and the order is taken from the order of the highest order term in the final expression of the transfer function; the order of the transfer function corresponds to the number of energy storage elements (capacitors and inductors), and the specific correspondence is shown in Table 1, wherein the cascade is a circuit structure formed by connecting a plurality of (two cascades are two, three cascades are three, and multiple cascades are multiple) completely identical resistance-capacitance (RC) low-pass filter units in series.

[0070] Table 1 Number of capacitors and inductors corresponding to the order of the transfer function

[0071]

[0072] In addition, the poles of the circuit denominator are realized by the resonance circuit formed by the series inductance and capacitance, and it should be ensured that the configuration of these elements is consistent with the denominator polynomial of the transfer function. Each pole is configured with an RLC branch, the resistance is used to adjust the damping, and the inductance and the capacitance are used to adjust the resonance frequency together. The zero point can be realized by a specific LC network. If the numerator of the transfer function is a high-order polynomial, multiple parallel or series LC networks are required to match the zero point position to the numerator coefficient of the transfer function. The realization of each zero point should comply with the symmetry and simplification rules of the circuit to reduce the number of elements.

[0073] As an optional implementation, in the step S400, the preconditions and constraints for designing the heterogeneous circuit include: under the condition of high-frequency alternating current that the complex frequency variable s tends to infinity, in the RLC circuit, the complex frequency variable s is a core mathematical tool for describing the dynamic characteristics of the system, defined as s = σ + jω (σ is the attenuation coefficient, ω is the angular frequency, j is the imaginary unit, σ is the real part, and ω is the imaginary part), used for converting the time-domain differential equation into the algebraic equation in the complex frequency domain, and simplifying the circuit response analysis; if the transfer function H(∞) = 0, that is, the value corresponding to the final expression of the transfer function is 0, then the circuit cannot only have a resistor; if the transfer function H(∞) ≠ 0, that is, the value corresponding to the final expression of the transfer function is not 0, then the circuit does not contain a series inductance (high-frequency open circuit) on the main signal path or a parallel capacitor (high-frequency short circuit) to ground; under the condition of direct current, at this time the complex frequency variable s tends to 0, if the transfer function H(0) = 0, then the circuit is not a pure resistance network, nor a structure that allows direct current to pass through, if the transfer function H(0) ≠ 0, then the circuit cannot contain a series capacitor on the main signal path or a parallel inductor to ground. In this embodiment, if the transfer function H(∞) ≈ 1, that is, the value corresponding to the final expression of the transfer function is approximately equal to 1, then the circuit cannot have a parallel capacitor to ground and a series inductance on the main signal path; the transfer function H(0) = 0, the circuit cannot be a pure resistance network, nor a structure that allows direct current to pass through (such as a series inductance on the main path or a parallel capacitor to ground), and at the same time it also implies that there is a series capacitor or a parallel inductor in the circuit to block the direct current signal.

[0074] As an optional implementation, as Figure 2As shown, in the S500 step, the genetic programming search circuit topology and parameters include: S510: Take the basic building blocks of the RLC circuit as the terminal set of genetic programming, thereby defining the basic elements of genetic programming, the terminal set is a set of basic elements that constitute the program tree structure in genetic programming, as the leaf nodes of the program tree, used to provide the original input, limit the solution space range; In this embodiment, the basic building blocks of the RLC circuit include: resistance R, inductance L, capacitance C (each element has a to-be-determined continuous admittance value); Input / output ports Vin, Vout and GND; Function set (non-terminal symbol in genetic programming, used to define the operation mode or combination mode in the circuit structure) and connector (connector is a specific member in the function set, such as Series(A, B) represents connecting element A and element B in series, Parallel(A, B) represents connecting element A and element B in parallel, Shunt(A) represents connecting A to ground, Bridge(A, B) represents creating a bridge connection) of combining elements. S520: Define the objective function of genetic programming (objective function, i.e. fitness function, used to quantitatively evaluate the pros and cons of the program tree or expression generated by genetic programming, drive the evolution direction of genetic programming) Minimize Cost=Error(H_actual, H_target)+Penalty, where Error represents the root mean square error between the actual response H_actual and the target response H_target of the transfer function calculated at multiple frequency points, Penalty represents a penalty term for features that are not expected to appear (such as too many elements), which can be set by the user according to actual needs, therefore, minimizing the value of the right side expression Error(H_actual, H_target)+Penalty is the driving direction of genetic programming. S530: Initialize the genetic population of genetic programming, randomly generate a batch of circuit individuals, i.e. produce multiple RLC circuits, each circuit individual is a tree structure including a function set (non-leaf node of the genetic programming tree structure) and a terminal set (leaf node of the genetic programming tree structure), and remove circuit individuals that violate the hard constraint rule set, to ensure that the remaining circuit individuals meet the hardware constraint rule requirements, thereby improving the accuracy and efficiency of genetic programming search. For example, if a circuit with a parallel capacitor is generated, it violates the second item of the hard constraint rule set, so it is discarded and regenerated until a compliant circuit individual is obtained, ensuring that genetic programming search starts from a valid starting point. S540: Evaluate the fitness of each circuit individual in the population.S550: The population of circuit individuals is evolved, new circuit individuals are generated by crossover or mutation, and are immediately verified by the hard constraint rule set. The new circuit individuals that violate the hard constraint rule set are discarded. Any offspring that violates the hard constraint rule set will be discarded, preventing invalid solutions from polluting the population. S560: The circuit individuals in the population in the previous step S550 are replaced by the newly generated, compliant offspring to form a new generation of population, and the process is repeated until a preset number of generations of evolution is reached, or the Cost value converges to within a preset threshold. The preset number of generations of evolution and the preset threshold can be set as needed.

[0075] As an optional embodiment, as shown in Figure 3 S550 includes: S551: According to the target function Cost value, the elite circuit individual with the lowest Cost value is selected into the next generation by roulette selection (probability is allocated according to the fitness ratio, similar to the random hitting of an individual by the rotation of a roulette) or tournament selection (two or more individuals are randomly selected, and only the one with the highest fitness is retained); S552: The selected elite circuit individual is subjected to a breeding operation to generate a new offspring circuit; S553: The sub-trees of two parent circuits are exchanged, that is, the crossover operation in genetic programming, to generate a new circuit structure; S554: A certain part of a circuit individual is randomly changed, such as changing a resistor R to an inductor L, or a new parallel branch is added at a node, that is, the mutation operation in genetic programming.

[0076] The embodiment is only a specific example, and does not indicate that the present application is in this way.

[0077] The above is only the preferred embodiment of the present application, and those skilled in the art know that various changes or equivalent replacements can be made to the features and embodiments without departing from the spirit and scope of the present application. In addition, the features and embodiments can be modified to adapt to specific conditions and materials under the guidance of the present application without departing from the spirit and scope of the present application. Therefore, the present application is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of the present application are within the scope of protection of the present application.

Claims

1. A method for generating circuit topologies based on transfer functions, characterized in that, Includes the following steps: S100: Based on graph theory, construct a connected graph G based on the circuit topology given the structure and component parameters of an RLC circuit; S200: Derive the relationship between the transfer function and the impedance or admittance of network nodes in the connected graph G based on RLC circuits; S300: Searches for the tree and second-order tree required to calculate the transfer function, and calculates the final expression of the transfer function of the RLC circuit; S400: Based on the analysis of the transfer function expression, the order and structure of the transfer function are determined. Combined with the specifications and design rules of the circuit design, the prerequisites and constraints for designing heterogeneous circuits are obtained, which serve as circuit design rules. S500: The circuit design rules are used as a set of hard constraints for the algorithm to search for topology and parameters. The topology and parameters of the RLC circuit are searched through genetic programming to obtain the optimal topology and the optimal component admittance value.

2. The method for generating circuit topology based on transfer function according to claim 1, characterized in that, It also includes the following steps: S600: Outputs the optimal topology and optimal component admittance values, and compares them with the Bode plot of the target response H_target of the transfer function to verify performance.

3. The method for generating circuit topology based on transfer function according to claim 1, characterized in that, In step S100, the RLC circuit is a two-port network including port 1 and port 2, forming five element branches: the first branch, the second branch, the third branch, the fourth branch, and the fifth branch. In the RLC circuit, the edges in the circuit are used as edges of the connected graph G, and the nodes in the circuit are used as nodes of the connected graph G. The sum of the admittances of all elements on each edge is the value of that edge in the connected graph G.

4. The method for generating circuit topology based on transfer function according to claim 3, characterized in that, In step S200 The first expression for the transfer function H of the circuit is obtained based on the parameter matrix Z: ， The parameter matrix Z is defined as follows: ， in, These represent the port voltages of port 1 and port 2, and the port currents of port 1 and port 2, respectively. This indicates the input impedance of port 1; Let be the first mutual impedance between port 1 and port 2, representing the effect of the current at port 2 on the voltage at port 1; The second mutual impedance of port 1 and port 2 represents the effect of the current in port 1 on the voltage in port 2. This indicates the input impedance of port 2; Based on port 2 being open This yields the second expression for the transfer function H: 。 5. The method for generating circuit topology based on transfer function according to claim 4, characterized in that, The S300 step includes: Based on the second expression of the transfer function H, the tree and second-order tree involved in the node admittance are analyzed. Based on the topology formula of the two-port network, the third expression of the transfer function H is obtained: ， The topology formula for the two-port network is: in Let G represent the sum of the admittance products of all second-order trees in a connected graph G where points a and b are not together. Let G represent the sum of the admittances of all second-order trees in a connected graph G where ab and cd each form two groups and ab and cd are not in the same group. It is the sum of the derivative products of all tree branches; Calculate the sum of the admittance products of the required tree and the second-level tree, and based on the admittances after the Laplace transform of the resistor R, capacitor C, and inductor L, respectively... The final expression for the transfer function is obtained as follows, where s is the complex frequency variable: 。 6. The method for generating circuit topology based on transfer function according to claim 1, characterized in that, In step S400, the order of the transfer function is the order of the highest-order term in the final expression of the transfer function, corresponding to the number of energy storage elements.

7. The method for generating circuit topology based on transfer function according to claim 1, characterized in that, In step S400, the prerequisites and constraints for designing heterogeneous circuits include: under high-frequency AC conditions where the complex frequency variable s tends to infinity, if the transfer function H(∞) = 0, the circuit cannot contain only resistors; if the transfer function H(∞) ≠ 0, the circuit does not contain series inductors or parallel capacitors to ground on the main signal path. Under DC conditions, if the transfer function H(0) = 0, the circuit is not a pure resistive network, nor is it a structure that allows DC to pass through; if the transfer function H(0) ≠ 0, the circuit cannot contain series capacitors or parallel inductors to ground on the main signal path.

8. The method for generating circuit topology based on transfer function according to claim 1, characterized in that, In step S500, the search for the topology and parameters of the RLC circuit via genetic programming includes: S510: Uses the basic building blocks of RLC circuits as the terminal set for genetic programming; S520: Define the objective function of genetic programming as Minimize Cost = Error(H_actual, H_target) + Penalty, where Error represents the root mean square error between the actual response H_actual and the target response H_target of the transfer function calculated at multiple frequency points, and Penalty represents the penalty term for unwanted features. S530: Initialize the genetic population for genetic programming, randomly generate a batch of circuit individuals, each circuit individual is a tree structure including a function set and a terminal set, and remove circuit individuals that violate the set of hard constraint rules; S540: Perform a fast local optimization search on the component admittance values ​​in the topology of each individual circuit to find the combination of admittance values ​​that minimizes the root mean square error (RMSE) and calculate its fitness (Cost) value. S550: Generate new circuit individuals through crossover or mutation, and immediately verify them with a set of hard constraint rules, discarding new circuit individuals that violate the set of hard constraint rules; S560: Replace the circuit individuals in the population from the previous step S550 with newly generated, compliant offspring to form a new generation population, and return to step S540 to repeat the entire process until the preset number of generations is reached, or the Cost value converges to within the preset threshold.

9. The method for generating circuit topology based on transfer function according to claim 8, characterized in that, The S550 step includes: S551: Based on the objective function Cost value, select the elite circuit individual with the lowest Cost value to enter the next generation through roulette wheel selection or tournament selection; S552: Perform a breeding operation on the selected elite circuit individuals to generate new offspring circuits; S553: ​​Swap the subtrees of two parent circuits to generate a new circuit structure; S554: Randomly change a part of a circuit or add a new parallel branch at a node.

10. A method for generating circuit topology based on transfer function according to claim 2, characterized in that, The S600 step specifically includes: S610: The circuit with the lowest output cost is taken as the target circuit, including the complete topology and the optimal component admittance value; S620: Simulate the target circuit in circuit simulation software, plot the Bode plot, and compare it with the Bode plot of the target response H_target of the transfer function to verify the performance.

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