Memory testing methods, electronic devices and storage media

Abstract

This application discloses a memory testing method, electronic device, and storage medium, relating to the field of storage technology. It can flexibly run stress test threads and latency test threads under different load levels according to user-specified test parameters. This not only simultaneously and accurately reflects the memory latency and bandwidth on specific non-uniform memory access memory nodes or central processing units, but also comprehensively evaluates memory performance by iteratively traversing different load levels through test control. Thus, it can more realistically simulate actual load scenarios, avoiding measurement interference caused by the inaccurate binding of stress threads to a certain extent, and improving the accuracy of memory latency.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a memory testing method, electronic device, and storage medium. Background Technology

[0002] With the increasing complexity of computer system architectures, especially the widespread adoption of multi-core processors and NUMA (Non-Uniform Memory Access) architectures, the performance of the memory subsystem has a more significant impact on overall system performance. Memory latency is one of the key metrics for measuring memory performance, directly affecting application response time and system throughput. Therefore, accurate measurement of memory latency is of great importance for system performance tuning, hardware selection, and system design.

[0003] However, in real-world production environments, the memory subsystem is often under load. Traditional memory latency measurement tools, such as MLC (Memory Latency Checker) or the lat_mem_rd tool in the open-source lmbench, typically perform measurements under no-load conditions. This measurement method fails to reflect the system's memory latency characteristics under actual load conditions, leading to discrepancies between the measurement results and the actual situation. Summary of the Invention

[0004] This application provides a memory testing method, electronic device, and storage medium to at least solve the problem in related technologies that the memory latency characteristics of the system under real load conditions cannot be reflected, resulting in deviations between the measurement results and the actual situation.

[0005] This application provides a memory testing method, comprising: responding to test parameters; determining, based on the test parameters, a mapping relationship between a target non-uniform memory access memory node, at least one stress thread identifier corresponding to the current load level, and a first CPU identifier, and a second CPU identifier for binding latency test threads; binding at least one stress thread to the corresponding first CPU for execution based on the at least one stress thread identifier corresponding to the current load level and the mapping relationship, and controlling the first CPU to access the corresponding first memory buffer based on the stress thread to measure the bandwidth of the at least one stress thread, and determining the target bandwidth corresponding to the current load level based on the bandwidth of the at least one stress thread, wherein the stress threads correspond one-to-one with the first CPU and the first memory buffer; when the target bandwidth is within a preset bandwidth range, binding the latency test thread to the second CPU for execution based on the second CPU identifier, and controlling the second CPU to access the second memory buffer based on the latency test thread to measure the access latency time of the target non-uniform memory access memory node corresponding to the current load level; wherein both the first memory buffer and the second memory buffer are located at the target non-uniform memory access memory node.

[0006] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the aforementioned memory testing method.

[0007] This application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the aforementioned memory testing method.

[0008] This application also provides a computer program product, including a computer program / instructions, which, when executed by a processor, implement the memory testing method as described above.

[0009] The memory testing method described in this application can flexibly run stress test threads and latency test threads under different load levels according to user-specified test parameters. This not only simultaneously and accurately reflects the memory latency and bandwidth on specific non-uniform memory access memory nodes or CPUs, but also comprehensively evaluates memory performance by iteratively traversing different load levels through test control. This more realistically simulates actual load scenarios, avoiding measurement interference caused by the inability to accurately bind stress threads, and improving the accuracy of memory latency. Attached Figure Description

[0010] Figure 1 This is a flowchart of a memory testing method according to some embodiments of this application;

[0011] Figure 2This is a flowchart of a memory testing method according to other embodiments of this application;

[0012] Figure 3 This is a schematic diagram illustrating delay test results according to some embodiments of this application;

[0013] Figure 4 This is a schematic diagram illustrating delay test results according to other embodiments of this application;

[0014] Figure 5 This is a schematic diagram of delay test results according to some embodiments of this application;

[0015] Figure 6 This is a schematic diagram illustrating the delay test results according to some embodiments of this application;

[0016] Figure 7 This is a block diagram of an electronic device according to some embodiments of this application. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0018] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., used in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0019] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] The specific application environment architecture or specific hardware architecture on which the execution of the memory testing method depends is described here.

[0021] The embodiments of this application provide a memory testing method, and the method is described in detail in conjunction with the execution flow of the memory testing method.

[0022] In some embodiments, tools exist to measure memory bandwidth and latency, but these are typically measured separately. For example, lat_mem_rd from the lmbench toolset is used to measure memory read latency, and bw_mem is used to measure memory bandwidth. However, these tools lack the ability to simultaneously measure latency under simulated real-world load conditions. MLC tools generate memory bandwidth load by running a stress thread on a specified CPU (Central Processing Unit) and a latency test thread on another. However, MLC tools only support binding to a continuous range of CPUs, not a discrete list, preventing users from simulating specific combinations of load scenarios. Therefore, to simulate load, additional stress threads are usually required, but these stress threads often lack precise control over CPU affinity and NUMA node binding, and cannot apply controllable stress to specific CPUs or NUMA nodes, resulting in distorted measurement results that fail to accurately reflect memory latency on a specific NUMA node or CPU.

[0023] Based on this, this application proposes a memory testing method that can flexibly run stress test threads and latency test threads under different load levels according to user-specified test parameters. This method can not only simultaneously and accurately reflect the memory latency and bandwidth on specific non-uniform memory access memory nodes or central processing units, but also comprehensively evaluate memory performance by iteratively traversing different load levels through iterative test control.

[0024] Figure 1 This is a flowchart of a memory testing method according to some embodiments of this application. (Refer to...) Figure 1 The memory testing method in this application embodiment may include the following steps:

[0025] S110, respond to test parameters, and determine the target non-uniform memory access memory node, at least one stress thread identifier corresponding to the current load level, the mapping relationship between at least one stress thread identifier and the first CPU identifier, and the second CPU identifier used to bind the latency test thread based on the test parameters.

[0026] Specifically, when starting a memory test, the user can set test parameters, such as setting the second CPU identifier for running the latency test thread, the list of first CPU identifiers for running the stress thread, and the target non-uniform memory access memory node.

[0027] After the user sets the list of first CPU identifiers for running stress threads, multiple load levels can be automatically generated based on the length of the first CPU identifier list. The number of load levels generated can be set by the user. For example, assuming the user sets the number of load levels to 5, the length of the first CPU list is 5 (i.e., there are 5 first CPUs that can run stress threads). Specifically, a first load level, a second load level, a third load level, a fourth load level, and a fifth load level can be set. Each load level corresponds to a corresponding number of stress threads. For example, the first load level corresponds to 1 stress thread, the second load level corresponds to 2 stress threads, the third load level corresponds to 3 stress threads, the fourth load level corresponds to 4 stress threads, and the fifth load level corresponds to 5 stress threads. The first CPU bound to the stress threads of each load level is pre-set. For example, assuming the first CPU list includes CPU A, CPU B, CPU C, CPU D, and CPU E, when the load level is the first load level, one stress thread corresponding to the first load level can be randomly bound to any one of CPU A, CPU B, CPU C, CPU D, and CPU E. When the load level is the second load level, two stress threads corresponding to the second load level can be randomly bound to any two of CPU A, CPU B, CPU C, CPU D, and CPU E. And so on, the stress thread identifier corresponding to each load level can be determined, as well as the mapping relationship between the stress thread identifier corresponding to each load level and the first CPU identifier.

[0028] In other words, during iterative test control, in response to user-defined test parameters, the system sequentially traverses the load levels (e.g., from the fifth load level to the first load level) and determines the stress thread identifier corresponding to the current load level. For example, if the current load level is the fifth load level, five stress thread identifiers are determined; if the current load level is the first load level, one stress thread identifier is determined. Then, based on the stress thread identifier corresponding to the current load level and the mapping relationship between the stress thread identifier and the first CPU identifier, the stress thread corresponding to the current load level is bound to the corresponding first CPU to measure the target bandwidth corresponding to the current load level. Once the stress thread is running stably, the latency test thread is bound to the second CPU to measure the access latency corresponding to the current load level. This process is repeated sequentially from the fifth load level to the first load level to determine the target bandwidth and access latency for each load level.

[0029] It should be noted that if the user does not specify a target non-uniform memory access memory node, the non-uniform memory access memory node to which the thread belongs will be automatically determined by querying the operating system information based on the second CPU identifier corresponding to the latency test thread. If the query fails, the thread will be bound to a preset non-uniform memory access memory node by default. The preset non-uniform memory access memory node can be marked according to the actual situation, and no specific restrictions are made here.

[0030] S120: Based on the identifier and mapping relationship of at least one stress thread corresponding to the current load level, bind at least one stress thread to the corresponding first central processing unit (CPU) for execution, and control the first CPU to access the corresponding first memory buffer based on the stress thread in order to measure the bandwidth of at least one stress thread, and determine the target bandwidth corresponding to the current load level based on the bandwidth of at least one stress thread, wherein the stress thread corresponds one-to-one with the first CPU and the first memory buffer respectively.

[0031] The following description uses the second load level as an example, but this is not intended to limit the scope of this application.

[0032] Specifically, when the current load level is the second load level, the pressure threads corresponding to the current load level can be identified as pressure thread A and pressure thread B. Based on the mapping relationship between the pressure thread identifier and the first CPU identifier at the second load level, pressure thread A and pressure thread B are bound to the first CPU A and the first CPU B, respectively. At the same time, the first memory buffer A and the first memory buffer B are allocated to the first CPU A and the first CPU B, respectively. Both the first memory buffer A and the first memory buffer B are located within the target non-uniform memory access memory node.

[0033] When measuring the target bandwidth corresponding to the current load level, the first central processing unit A is controlled to access the corresponding first memory buffer A based on the pressure thread A, and the first central processing unit B is controlled to access the corresponding first memory buffer B based on the pressure thread B, so as to apply load pressure to the target non-uniform memory access memory node, and measure the bandwidth corresponding to the pressure thread A and the bandwidth corresponding to the pressure thread B, and determine the target bandwidth corresponding to the second load level based on the bandwidth corresponding to the pressure thread A and the bandwidth corresponding to the pressure thread B. For example, the bandwidth corresponding to the pressure thread A and the bandwidth corresponding to the pressure thread B are input into a preset formula to output the target bandwidth corresponding to the second load level.

[0034] S130, when the target bandwidth is within the preset bandwidth range, the latency test thread is bound to the second central processor based on the second central processor identifier and runs on it. The second central processor is controlled to access the second memory buffer based on the latency test thread to measure the access latency time of the target non-uniform memory access memory node corresponding to the current load level. The first memory buffer and the second memory buffer are both located in the target non-uniform memory access memory node.

[0035] Specifically, the main thread continuously monitors the instantaneous target bandwidth reported by all stress threads through shared memory. If the target bandwidth fluctuation is relatively small within a continuous preset time (e.g., 500 ms), such as target bandwidth fluctuation <5%, it is determined that the stress thread is running stably; otherwise, it continues to wait, with the longest waiting time not exceeding the preset duration (e.g., 10 s). If the timeout occurs, an error is reported and the thread exits.

[0036] After the stress thread is confirmed to be running stably, the latency test thread is bound to the second CPU based on the second CPU identifier. At the same time, a corresponding second memory buffer is allocated to the second CPU. The second CPU is controlled to access the corresponding second memory buffer based on the latency test thread in order to measure the access latency time of the target non-uniform memory access memory node corresponding to the current load level. Both the second memory buffer and the first memory buffer are located within the target non-uniform memory access memory node.

[0037] The memory testing method described in this application can flexibly run stress test threads and latency test threads under different load levels according to user-specified test parameters. This not only simultaneously and accurately reflects the memory latency and bandwidth on specific non-uniform memory access memory nodes or CPUs, but also comprehensively evaluates memory performance by iteratively traversing different load levels through test control. This more realistically simulates actual load scenarios, avoiding measurement interference caused by the inability to accurately bind stress threads, and improving the accuracy of memory latency.

[0038] In some embodiments, measuring the access latency of a target non-uniform memory access memory node corresponding to the current load level includes: dividing the second memory buffer into multiple second memory buffer nodes based on the cache line size of the second memory buffer; generating a random index value sequence using a first preset algorithm, and sorting the multiple second memory buffer nodes based on a preset physical address offset and the random index value sequence; determining the access address of the multiple second memory buffer nodes based on the index values ​​of the multiple second memory buffer nodes; sequentially accessing the multiple second memory buffer nodes based on the access addresses of the multiple second memory buffer nodes, and recording the access start time and access end time of each of the multiple second memory buffer nodes; determining the target access duration based on the access start time and access end time of the multiple second memory buffer nodes; and determining the access latency of the target non-uniform memory access memory node corresponding to the current load level based on the target access duration.

[0039] Specifically, the size of the second memory buffer can be 2GB, and the cache line size of the second memory buffer can be 64 bytes. Therefore, based on the cache line size of the second memory buffer, it can be divided into M second memory buffer nodes, and each second memory buffer node is numbered, for example, sequentially numbered as second memory buffer node 0, second memory buffer node 1, ..., second memory buffer node M-1, where M = 2 × 1024 × 1024 × 1024 / 64 = 33554432. In this embodiment, the second memory buffer is divided into 3 second memory buffer nodes, specifically second memory buffer node 0, second memory buffer node 1, and second memory buffer node 2, as an example for illustration, but this is not intended to limit this application.

[0040] Furthermore, a random index value sequence is generated using a first preset algorithm, such as the Fisher-Yates shuffle algorithm, and multiple second memory buffer nodes are sorted based on this random index value sequence. For example, if the partitioned second memory buffer node sequence is [second memory buffer node 0, second memory buffer node 1, second memory buffer node 2], and the random index value sequence generated by the Fisher-Yates shuffle algorithm is [1, 2, 0], then the second memory buffer node sequence obtained by re-sorting the multiple second memory buffer nodes based on the random index value sequence is [second memory buffer node 1, second memory buffer node 2, second memory buffer node 0]. Since the second central processing unit has a prefetch mechanism when accessing the second memory buffer nodes, in order to avoid the impact of the prefetch mechanism on memory latency measurement to a certain extent, the address offsets of adjacent second memory buffer nodes after scrambling can be fixed to a preset physical address offset. For example, the physical address of second memory buffer node 1 differs from the physical address of second memory buffer node 2 by a preset physical address offset, and the physical address of second memory buffer node 2 differs from the physical address of second memory buffer node 0 by a preset physical address offset. The preset physical address offset can be determined based on the prefetcher window of the second central processing unit. For example, if the size of the prefetcher window of the second central processing unit is 256 bytes, then the preset physical address offset can be 256 bytes.

[0041] After sorting multiple second memory buffer nodes, the access address of each second memory buffer node can be determined based on its index value. For example, if the sorted index value sequence of the second memory buffer nodes is [1, 2, 0], then index values ​​1, 2, and 0 can be input into the access address calculation formula to calculate the access addresses of second memory buffer node 1, second memory buffer node 2, and second memory buffer node 0, respectively.

[0042] Furthermore, after determining the access address of each second memory buffer node, the second central processing unit sequentially accesses the second memory buffer nodes based on their access addresses, and records the access start time and access end time of each second memory buffer node. For example, first, second memory buffer node 1 is accessed, and its access start time and access end time are recorded; then, second memory buffer node 2 is accessed, and its access start time and access end time are recorded; finally, second memory buffer node 0 is accessed, and its access start time and access end time are recorded.

[0043] After determining the access start time and access end time of each second memory buffer node, the access duration of each second memory buffer node is calculated based on its access start time and access end time. This access duration is then input into a preset formula to determine the target access duration. Once the target access duration is determined, it can be input into the preset formula to calculate the access latency of the target non-uniform memory access memory node corresponding to the current load level.

[0044] This application divides the second memory buffer into multiple nodes and sorts these nodes based on a random index value sequence, thereby breaking the sequential nature of access. Furthermore, by setting a preset physical address offset, it mitigates the impact of the prefetch mechanism on latency measurement to some extent, further ensuring the randomness and independence of access. This allows the measurement results to more accurately reflect the actual latency characteristics of the memory. Thus, it not only improves the accuracy of latency measurement but also more realistically simulates memory access patterns in real-world applications.

[0045] In some embodiments, determining the target access duration based on the access start time and access end time of a plurality of second memory buffer nodes includes: determining the access duration of a plurality of second memory buffer nodes based on the difference between the access end time and the corresponding access start time of the plurality of second memory buffer nodes; and determining the target access duration based on the average of the access durations of the plurality of second memory buffer nodes.

[0046] For example, firstly, the second memory buffer node 1 is accessed, and the difference between the access end time and the access start time of the second memory buffer node 1 is calculated. This difference is determined as the access duration of the second memory buffer node 1. Then, the second memory buffer node 2 is accessed, and the difference between the access end time and the access start time of the second memory buffer node 2 is calculated. This difference is determined as the access duration of the second memory buffer node 2. The difference between the access end time and the access start time of the second memory buffer node 0 is calculated, and this difference is determined as the access duration of the second memory buffer node 0. Further, the average of the access durations of the second memory buffer node 1, the second memory buffer node 2, and the second memory buffer node 0 is calculated, and this average is determined as the target access duration.

[0047] In this way, by calculating the average access time of multiple nodes to determine the target access time, the access latency of the target non-uniform memory access memory node under the current load level can be accurately evaluated. This not only improves the accuracy of latency measurement, but also enables a comprehensive evaluation of memory performance.

[0048] In some embodiments, determining the access latency of the target non-uniform memory access memory node corresponding to the current load level based on the target access duration includes: obtaining the base frequency of the second central processing unit; and determining the access latency of the target non-uniform memory access memory node corresponding to the current load level based on the ratio between the target access duration and the base frequency of the second central processing unit.

[0049] Specifically, hardware monitoring tools, such as HWMonitor, can be used to collect the base frequency of the second CPU and calculate the ratio between the target access duration and the base frequency of the second CPU to determine the access latency of the target non-uniform memory access memory node corresponding to the current load level.

[0050] In some embodiments, determining the access address of a plurality of second memory buffer nodes based on the index values ​​of the plurality of second memory buffer nodes includes: determining a plurality of corresponding first access address offsets based on the index values ​​of the plurality of second memory buffer nodes; and determining the access address of the plurality of second memory buffer nodes according to the sum of the plurality of first access address offsets and the base address of the second memory buffer, respectively.

[0051] In some embodiments, determining multiple corresponding first access address offsets based on the index values ​​of multiple second memory buffer nodes includes: determining the corresponding first access address offsets of multiple second memory buffer nodes based on the product of the index values ​​of multiple second memory buffer nodes, the cache line size of the second memory buffer, and a first preset value. The first preset value can be determined according to the prefetcher window size of the second central processing unit. For example, if the prefetcher window of the second central processing unit is 256 bytes and the cache line size of the second memory buffer is 64 bytes, the first preset value can be determined to be 8.

[0052] Specifically, after sorting the multiple second memory buffer nodes, the first access address offset of each second memory buffer node can be determined based on the index value of each second memory buffer node.

[0053] For example, assuming the sorted index sequence of the second memory buffer nodes is [1, 2, 0], then input index 1, index 2, and index 0 into the following access address calculation formula to calculate the first access address offset of each second memory buffer node:

[0054] First access address offset = (index value × cache line size × first preset value);

[0055] In other words, the first access address offset of the second memory buffer node 1 is 1×64×8=512 bytes, the first access address offset of the second memory buffer node 2 is 2×64×8=1024 bytes, and the first access address offset of the second memory buffer node 0 is 0×64×8=0 bytes.

[0056] Furthermore, the second central processing unit obtains the base address of the second memory buffer through its operating system tools, and sequentially calculates the sum of the first access address offset of the second memory buffer node 1, the first access address offset of the second memory buffer node 2, the first access address offset of the second memory buffer node 0, and the base address of the second memory buffer to determine the access address of the second memory buffer node 1, the access address of the second memory buffer node 2, and the access address of the second memory buffer node 0.

[0057] After determining the access address of each second memory buffer node, the second central processing unit accesses second memory buffer node 1, second memory buffer node 2 and second memory buffer node 0 in sequence based on the access address of each second memory buffer node.

[0058] In some embodiments, measuring the bandwidth of at least one stressed thread includes: obtaining the actual access duration of the at least one stressed thread accessing a preset number of times; and determining the bandwidth of the at least one stressed thread based on the actual access duration. The preset number of accesses can be determined according to actual conditions; for example, the preset number of accesses could be 10,000, and no specific limitation is made here.

[0059] Specifically, when measuring the bandwidth of a stress thread, the user can pre-set a preset number of accesses for the stress thread, and then randomly generate a target access address for each access. The stress thread accesses the corresponding first memory buffer based on the target access address until the preset number of accesses is reached, thus obtaining the actual access time of the stress thread for that preset number of accesses. After determining the actual access time of the stress thread for the preset number of accesses, the actual access time can be input into a preset calculation formula to determine the bandwidth of the stress thread.

[0060] This application determines the bandwidth of a stressed thread by measuring its actual access time under a preset number of accesses. This accurately reflects the memory's performance under specific load conditions, ensuring the accuracy and reliability of bandwidth measurement.

[0061] In some embodiments, obtaining the actual access duration of at least one stressed thread accessing a preset number of times includes: generating multiple pseudo-random access addresses based on a second preset algorithm, wherein the number of pseudo-random access addresses is the same as the preset number of accesses; generating a target access address based on the pseudo-random access address, the base address of the first memory buffer, the cache line size of the first memory buffer, and the size of the first memory buffer; accessing the corresponding first memory buffer based on the target access address, and recording the access start time and access end time of the stressed thread accessing the preset number of times; and determining the actual access duration based on the difference between the access end time and the access start time of the stressed thread accessing the preset number of times.

[0062] Specifically, when the current load level is the second load level, the pressure threads corresponding to the current load level can be identified as pressure thread A and pressure thread B. Pressure thread A and pressure thread B are bound to the first CPU A and the first CPU B, respectively. At the same time, the first CPU A and the first CPU B are allocated corresponding first memory buffers A and B. Both the first memory buffers A and B are located within the target non-uniform memory access memory node.

[0063] In the following description, the example of binding stress thread A to a first central processing unit A and controlling the first central processing unit A to access the corresponding first memory buffer A based on stress thread A is used, but this is not intended to limit the application.

[0064] Specifically, the user can pre-set a preset number of accesses for stress thread A. Then, based on a second preset algorithm, such as a linear congruential generator algorithm, multiple pseudo-random access addresses are generated for the first memory buffer A. The number of pseudo-random access addresses is the same as the preset number of accesses. The pseudo-random access addresses, the base address of the first memory buffer, the cache line size of the first memory buffer, and the size of the first memory buffer are then input into a preset formula to calculate the target access address for each access to the first memory buffer A by stress thread A. The user then accesses the first memory buffer A based on the target access address, while simultaneously recording the start and end times of the access. The difference between the end and start times of the access is calculated to determine the actual access time of stress thread A for the preset number of accesses. Similarly, the actual access time of stress thread B for the preset number of accesses can be obtained using the same method.

[0065] This application ensures the randomness and independence of access by randomly generating the target access address for each access, which can avoid measurement deviations caused by the regularity of access patterns to a certain extent. This allows for accurate measurement of the actual access duration of the stressed thread under a preset number of accesses.

[0066] In some embodiments, generating a target access address based on a pseudo-random access address, a base address of a first memory buffer, a cache line size of the first memory buffer, and a size of the first memory buffer includes: determining a second access address offset corresponding to the pseudo-random access address based on the pseudo-random access address, the cache line size of the first memory buffer, and the size of the first memory buffer; and determining the target access address based on the sum of the base address of the first memory buffer and the second access address offset corresponding to the pseudo-random access address.

[0067] In some embodiments, determining the second access address offset corresponding to the pseudo-random access address based on the pseudo-random access address, the cache line size of the first memory buffer, and the size of the first memory buffer includes: performing a modulo operation on the pseudo-random access address and the cache line size of the first memory buffer to determine an initial second access address offset; and determining the second access address offset corresponding to the pseudo-random access address based on the product of the initial second access address offset and the cache line size of the first memory buffer.

[0068] For example, the pseudo-random access address, the cache line size of the first memory buffer, and the size of the first memory buffer can be input into the following formula to determine the second access address offset corresponding to the pseudo-random access address:

[0069] ;

[0070] Where offset represents the offset of the second access address corresponding to the pseudo-random access address; R_next represents the pseudo-random access address; buffer_size represents the size of the first memory buffer; cache_line_size represents the cache line size of the first memory buffer; mod() represents the modulo operation.

[0071] Furthermore, the second access address offset corresponding to the pseudo-random access address and the base address of the first memory buffer are input into the following formula to calculate the target access address:

[0072] Goal_addr=base_addr + offset;

[0073] Where Goal_addr represents the target access address; base_addr represents the base address of the first memory buffer; and offset represents the offset of the second access address corresponding to the pseudo-random access address.

[0074] Thus, the target access address for each access is determined using the formula described above.

[0075] In some embodiments, determining the bandwidth of at least one stressed thread based on the actual access duration includes: determining the number of bytes accessed by at least one stressed thread based on the product of a preset number of accesses and the cache line size of a first memory buffer; and determining the bandwidth of at least one stressed thread based on the ratio between the number of bytes accessed and the actual access duration.

[0076] Specifically, when the current load level is the second load level, the pressure threads corresponding to the current load level can be identified as pressure thread A and pressure thread B. Pressure thread A and pressure thread B are bound to the first CPU A and the first CPU B, respectively. At the same time, the first CPU A and the first CPU B are allocated corresponding first memory buffers A and B. Both the first memory buffers A and B are located within the target non-uniform memory access memory node.

[0077] In the following description, the example of binding stress thread A to a first central processing unit A and controlling the first central processing unit A to access the corresponding first memory buffer A based on stress thread A is used, but this is not intended to limit the application.

[0078] Specifically, after the first central processing unit A accesses the corresponding first memory buffer A a preset number of times based on the pressure thread A, it can calculate the product between the preset number of accesses and the cache line size of the first memory buffer to determine the number of bytes accessed by the pressure thread A; then, it calculates the ratio between the number of bytes accessed by the pressure thread A and the actual access time of the pressure thread A accessing the preset number of times to determine the bandwidth corresponding to the pressure thread A. Similarly, the bandwidth corresponding to the pressure thread B can be calculated using the above method.

[0079] In some embodiments, determining the target bandwidth corresponding to the current load level based on the bandwidth of at least one stress thread includes: when there is only one stress thread, determining the bandwidth of the stress thread as the target bandwidth; when there are multiple stress threads, determining the sum of the bandwidths of the multiple stress threads as the target bandwidth.

[0080] For example, when the current load level is the second load level, the sum of the bandwidth corresponding to stress thread A and the bandwidth corresponding to stress thread B is calculated to determine the target bandwidth corresponding to the second load level; when the current load level is the first load level, the stress thread corresponding to the current load level can be determined as stress thread A, stress thread A is bound to the first central processing unit A, and a corresponding first memory buffer A is allocated to the first central processing unit A. The bandwidth corresponding to stress thread A can be calculated using the above method, and the bandwidth corresponding to stress thread A is the target bandwidth corresponding to the first load level.

[0081] As a concrete example, refer to Figure 2 The memory testing method in this application embodiment may further include the following steps:

[0082] S201, Begin.

[0083] S202 responds to and parses the test parameters.

[0084] S203, Determine the target NUMA node.

[0085] Test parameters may include the second CPU identifier for running the latency test thread, a list of first CPU identifiers for running the stress thread, and the target non-uniform memory access memory node.

[0086] S204, Generate a stress thread sequence.

[0087] Based on the length of the first CPU list of running stress threads, a stress thread count sequence is generated in each iteration, for example, a ladder sequence starting from the maximum thread count and decreasing to 0 in configurable steps, and each stress thread count sequence corresponds to a load level.

[0088] For example, assuming the length of the first CPU list is 5 (i.e., there are 5 first CPUs that can run stress threads), there can also be 5 corresponding load levels, specifically a first load level, a second load level, a third load level, a fourth load level, and a fifth load level. Each load level corresponds to a certain number of stress threads; for example, the first load level corresponds to 1 stress thread, the second load level corresponds to 2 stress threads, the third load level corresponds to 3 stress threads, the fourth load level corresponds to 4 stress threads, and the fifth load level corresponds to 5 stress threads.

[0089] S205, determine if the number of stress threads is 0. If yes, proceed to S209; otherwise, proceed to S206.

[0090] S206, apply load pressure to the target NUMA node.

[0091] Taking the current load level as the second load level as an example, when the current load level is the second load level, the pressure threads corresponding to the current load level can be determined as pressure thread A and pressure thread B. Pressure thread A and pressure thread B are bound to the first CPU A and the first CPU B respectively. At the same time, the first memory buffer A and the first memory buffer B are allocated to the first CPU A and the first CPU B respectively. The first memory buffer A and the first memory buffer B are both located in the target non-uniform memory access memory node.

[0092] When measuring the target bandwidth corresponding to the current load level, the first central processing unit A is controlled to access the corresponding first memory buffer A based on the pressure thread A, and the first central processing unit B is controlled to access the corresponding first memory buffer B based on the pressure thread B, so as to apply load pressure to the target non-uniform memory access memory node, and measure the bandwidth corresponding to the pressure thread A and the bandwidth corresponding to the pressure thread B, and determine the target bandwidth corresponding to the second load level based on the bandwidth corresponding to the pressure thread A and the bandwidth corresponding to the pressure thread B.

[0093] S207, Measure the access latency of the target NUMA node corresponding to the current load level.

[0094] When the pressure thread is running stably based on the target bandwidth, and the access latency of the target non-uniform memory access memory node corresponding to the current load level is measured, the second central processing unit is controlled to access the corresponding second memory buffer based on the latency test thread in order to measure the access latency of the target non-uniform memory access memory node corresponding to the current load level.

[0095] S208, Results Collection and Cleanup.

[0096] Record the memory access latency value corresponding to the current load level and the memory bandwidth value generated by the memory pressure thread, and wait for a preset time to ensure the load stabilizes (e.g., 5 seconds). After completing the current load level test, terminate the pressure thread and clean up related resources.

[0097] S209, Output result.

[0098] Output the memory access latency value and the memory bandwidth value generated by the memory pressure thread for each load level.

[0099] As another concrete example, on the x86 platform, the latency test results obtained using the method of this application under seven different load levels are as follows: Figure 3 As shown, the first column represents different load levels, the second column represents the corresponding latency data under different load levels, and the third column represents the target bandwidth at this time. The latency test results using the MLC tool are as follows: Figure 4 As shown, the first column represents different load levels, the second column represents the corresponding latency data under different load levels, and the third column represents the bandwidth at that time. A comparison of latency test results between this application and the MLC tool under the same hardware and load configuration shows that the average relative error between the latency values ​​measured by this application at seven different load levels and the MLC results is only 1%, with the maximum relative error also controlled within 1%. This result demonstrates that this application can measure memory latency with extremely high accuracy under the same applied memory bandwidth load conditions, and is highly consistent with the results of the MLC tool. This high-precision measurement capability makes this application highly reliable and accurate in practical applications.

[0100] As another concrete example, on the ARM platform, the latency test results of the FTS5000C device under seven different load levels, measured using the method of this application, are as follows: Figure 5 As shown, the first column represents different load levels, the second column represents the corresponding latency data under different load levels, and the third column represents the target bandwidth at this time. This indicates that this application is applicable to load latency testing on the ARM platform. On the ARM platform, the same high load level (number of stressed threads = 56) was tested four times repeatedly, and the latency test results are as follows. Figure 6 As shown, the first column represents different load levels, the second column represents the corresponding latency data under different load levels, and the third column represents the bandwidth at this time. The standard deviation of the measured memory latency results is 0.4ns, indicating that this application has high repeatability and stability.

[0101] In summary, through verification on both x86 and ARM platforms, this application demonstrates excellent performance in terms of accuracy, stability, and cross-platform compatibility. On the x86 platform, comparative testing with the MLC tool shows that when binding discrete values ​​(e.g., 0, 2, 4), the average relative error across seven load levels does not exceed 1%, and the maximum error is also controlled within 1%, exceeding the 2% error requirement of similar industry tools, while the MLC tool does not support discrete binding. On the ARM platform, the standard deviation of latency measurement under high load scenarios (56 stressed threads) is as low as 0.4 ns, demonstrating significant data consistency. Regarding stability, comparative testing on the x86 platform with the MLC tool indirectly verifies the stability of this application, with the error range strictly controlled within an average of 1%. On the ARM platform, through four repeated tests, the standard deviation is only 0.4 ns, proving the high repeatability of this application under load and latency scenarios. Regarding cross-platform compatibility, this application has achieved effective resource isolation and control on both the x86 platform (relying on the rdtsc and cpuid instructions) and the ARM platform (relying on the cntvct_el0 and dsb ish instructions), verifying its cross-architecture compatibility.

[0102] Through the above description of the embodiments, those skilled in the art can clearly understand that the application according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0103] Embodiments of this application also provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the aforementioned memory testing method.

[0104] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0105] Embodiments of this application also provide an electronic device. (Refer to...) Figure 7 The electronic device 300 of this application includes a memory 310, a processor 320, and a computer program stored in the memory 310 and executable on the processor 320. When the processor 320 executes the computer program, it implements the aforementioned memory testing method.

[0106] Embodiments of this application also provide a computer program product, including a computer program / instructions, which, when executed by a processor, implement the aforementioned memory testing method.

[0107] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described memory testing method embodiments.

[0108] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0109] The foregoing has provided a detailed description of a memory testing method, electronic device, and storage medium provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its underlying concepts. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A memory testing method, characterized in that, The method includes: In response to test parameters, based on the test parameters, determine the target non-uniform memory access memory node, at least one stress thread identifier corresponding to the current load level, the mapping relationship between at least one stress thread identifier and the first CPU identifier, and the second CPU identifier used to bind the latency test thread. Based on the at least one stress thread identifier corresponding to the current load level and the mapping relationship, at least one stress thread is bound to the corresponding first central processing unit (CPU) for execution, and the first CPU is controlled to access the corresponding first memory buffer based on the stress thread to measure the bandwidth of at least one stress thread, and to determine the target bandwidth corresponding to the current load level based on the bandwidth of at least one stress thread, wherein the stress thread corresponds one-to-one with the first CPU and the first memory buffer respectively. When the target bandwidth is within a preset bandwidth range, the latency test thread is bound to the second central processing unit (CPU) based on the second CPU identifier and runs on the second CPU. The second CPU is then controlled to access the second memory buffer based on the latency test thread to measure the access latency of the target non-uniform memory access memory node corresponding to the current load level. Both the first memory buffer and the second memory buffer are located in the target non-uniform memory access memory node.

2. The memory testing method according to claim 1, characterized in that, Measuring the access latency of the target non-uniform memory access memory node corresponding to the current load level includes: The second memory buffer is divided into multiple second memory buffer nodes based on the cache line size of the second memory buffer; A random index value sequence is generated by a first preset algorithm, and multiple second memory buffer nodes are sorted based on a preset physical address offset and the random index value sequence. The access addresses of multiple second memory buffer nodes are determined based on the index values ​​of multiple second memory buffer nodes; Based on the access addresses of multiple second memory buffer nodes, access multiple second memory buffer nodes sequentially, and record the access start time and access end time of multiple second memory buffer nodes respectively; The target access duration is determined based on the access start time and access end time of multiple second memory buffer nodes; The access latency of the target non-uniform memory access memory node corresponding to the current load level is determined based on the target access duration.

3. The memory testing method according to claim 2, characterized in that, The target access duration is determined based on the access start time and access end time of multiple second memory buffer nodes, including: The access duration of the multiple second memory buffer nodes is determined based on the difference between the access end time and the corresponding access start time of the multiple second memory buffer nodes. The target access duration is determined based on the average access duration of multiple second memory buffer nodes.

4. The memory testing method according to claim 2, characterized in that, Determining the access latency of the target non-uniform memory access memory node corresponding to the current load level based on the target access duration includes: Obtain the reference frequency of the second central processing unit; Based on the ratio between the target access duration and the base frequency of the second central processing unit, the access latency of the target non-uniform memory access memory node corresponding to the current load level is determined.

5. The memory testing method according to claim 2, characterized in that, The access addresses of multiple second memory buffer nodes are determined based on their index values, including: Multiple corresponding first access address offsets are determined based on the index values ​​of multiple second memory buffer nodes; The access addresses of multiple second memory buffer nodes are determined by summing the offsets of multiple first access addresses with the base address of the second memory buffer.

6. The memory testing method according to claim 5, characterized in that, Multiple corresponding first access address offsets are determined based on the index values ​​of multiple second memory buffer nodes, including: The first access address offset of the multiple second memory buffer nodes is determined based on the product of the index values ​​of the multiple second memory buffer nodes, the cache line size of the second memory buffer, and the first preset value.

7. The memory testing method according to claim 1, characterized in that, Measuring the bandwidth of at least one of the stressed threads includes: Obtain the actual access duration of at least one of the pressure threads accessing the preset number of accesses; The bandwidth of at least one of the stressed threads is determined based on the actual access duration.

8. The memory testing method according to claim 7, characterized in that, Obtaining the actual access duration of at least one of the pressure threads for a preset number of accesses includes: Multiple pseudo-random access addresses are generated based on a second preset algorithm, wherein the number of pseudo-random access addresses is the same as the preset number of accesses; The target access address is generated based on the pseudo-random access address, the base address of the first memory buffer, the cache line size of the first memory buffer, and the size of the first memory buffer. Access the corresponding first memory buffer based on the target access address, and record the access start time and access end time of the pressure thread for a preset number of accesses; The actual access duration is determined based on the difference between the access end time of the preset number of accesses by the pressure thread and the access start time of the preset number of accesses by the pressure thread.

9. The memory testing method according to claim 8, characterized in that, Based on the pseudo-random access address, the base address of the first memory buffer, the cache line size of the first memory buffer, and the size of the first memory buffer, a target access address is generated, including: The second access address offset corresponding to the pseudo-random access address is determined based on the pseudo-random access address, the cache line size of the first memory buffer, and the size of the first memory buffer; The target access address is determined based on the sum of the base address of the first memory buffer and the offset of the second access address corresponding to the pseudo-random access address.

10. The memory testing method according to claim 9, characterized in that, Determining the second access address offset corresponding to the pseudo-random access address based on the pseudo-random access address, the cache line size of the first memory buffer, and the size of the first memory buffer includes: The initial second access address offset is determined by performing a modulo operation between the pseudo-random access address and the cache line size of the first memory buffer. The second access address offset corresponding to the pseudo-random access address is determined based on the product of the initial second access address offset and the cache line size of the first memory buffer.

11. The memory testing method according to claim 7, characterized in that, Determining the bandwidth of at least one of the stressed threads based on the actual access duration includes: The number of bytes accessed by at least one of the stressed threads is determined based on the product of the preset number of accesses and the cache line size of the first memory buffer; The bandwidth of at least one of the stressed threads is determined based on the ratio between the number of bytes accessed and the actual access duration.

12. The memory testing method according to claim 1, characterized in that, Determining the target bandwidth corresponding to the current load level based on the bandwidth of at least one of the stress threads includes: When there is at least one stress thread, the bandwidth of the stress thread is determined as the target bandwidth; In the case where there are multiple stress threads, the sum of the bandwidths of the multiple stress threads is determined as the target bandwidth.

13. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a processor, implements the memory testing method according to any one of claims 1-12.

14. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, it implements the memory testing method according to any one of claims 1-12.

15. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by the processor, they implement the memory testing method as described in any one of claims 1-12.

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