Flash memory controller and access method of flash memory

Abstract

The invention discloses a flash memory controller and a flash memory access method. The flash memory controller includes a decoder that performs a decoding operation based on received information obtained by the flash memory and a parity check matrix of a quasi-cyclic low-density parity check code. The decoder comprises a variable node module, a V2C shift module and a check node module which are coupled in series. The decoder further comprises a state data shifting module which is used for circularly shifting the state data of the check node module and then feeding back the state data to the check node module, and the state data shifting module is coupled with the check node module in parallel. The serial coupling only has three stages, so that the decoding iteration convergence speed is improved, and the flash memory access efficiency is further improved.

Description

Technical Field

[0001] The present application relates to a storage device, and more particularly to a flash memory controller and a flash memory access method using a quasi-cyclic low-density parity-check code. Background Art

[0002] Low-density parity-check codes (LDPC) are one of many forward error correction (FEC) codes, with theoretical coding gains approaching the Shannon limit. The parity-check matrix of a typical LDPC code exhibits irregular values, making hardware implementation of large parity-check matrices challenging. Quasi-cyclic low-density parity-check codes (QC-LDPC codes) are an important branch of structured LDPC codes. Their M×N parity-check matrix H has a specific structure—M and N are the number of rows and columns of the matrix, respectively—and can be divided into multiple K×K submatrices of equal size, where K is a positive integer. Each submatrix is ​​a cyclic shift of the identity matrix or an all-zero matrix. Figure 1A This is an example where M = 10, N = 20, and K = 5. The structural regularity reduces the encoding and decoding complexity of LDPC codes, and thus they are widely used in flash memory systems and many digital communication systems.

[0003] Since each sub-matrix in the QC-LDPC code parity check matrix is ​​a cyclic shift of the K×K identity matrix or an all-zero matrix, the M×N parity check matrix H can be equivalently represented by an X×Y base matrix W, where X=M / K, Y=N / K. The value of the base matrix W is the cyclic shift of the corresponding sub-matrix in the parity check matrix H, and "Z" indicates that the sub-matrix is ​​an all-zero matrix. Figure 1A For example, M = 10, N = 20, K = 5, X = 2, Y = 4, the corresponding basic matrix W is as follows:

[0004]

[0005] The parity check matrix H can be graphically represented as a Tanner graph. Figure 1B To correspond to Figure 1A Tanner graph 200 of quasi-cyclic low-density parity-check code, variable nodes 201, v0~v 19, corresponding to the columns of parity check matrix H, and check nodes 202, c0~c9, corresponding to the rows of parity check matrix H. Each "1" in parity check matrix H represents a connection between a variable node 201 and a check node 202, and "0" represents no connection. A message passing algorithm is the core of LDPC decoding, which iteratively passes Q information - information passed from a variable node to a check node, and R information - information passed from a check node to a variable node, between variable nodes and check nodes, to iteratively calculate the probability of each variable node being 0 or 1, and to estimate a codeword. When the estimated codeword multiplied by the parity check matrix is 0, the decoding result is obtained.

[0006] However, when the number of variable nodes 201 is high, it poses a challenge to hardware area and decoding convergence speed, so many QC-LDPC code decoders adopt a layered algorithm architecture, which groups variable nodes 201, and processes one group at a time. Taking each K variable nodes as a group for example, all variable nodes are divided into Y groups, and under the layered algorithm architecture, at iteration i, the message passing algorithm for the gth group (g∈{0,…,Y-1}) - i.e. variable nodes v n ,n=gK,…,(g+1)K-1, is calculated as follows:

[0007] Based on the R information of the previous iteration i-1, the Q information to be passed to check node c n is updated according to equation (2) in this iteration i. m The information to be passed to check node c

[0008]

[0009] where P n is the log-likelihood ratio (LLR) of the nth channel information received from the flash memory, and M(n) is all check nodes connected to variable node v n . The values of the Q information connected to variable nodes not belonging to the gth group remain unchanged. The output of the decoding result (not shown in the figure) is based on equation (4) Figure 2

[0010]

[0011] The estimated codeword based on the sign is the decoding result.

[0012] Each check node c m is updated according to equation (6) in this iteration i based on the Q information.​m The information to be passed to the g-th group of variable nodes v n is called R information

[0013]

[0014] where N(m) is the number of all variable nodes connected to check node c m The values of R information not belonging to the g-th group of variable nodes remain unchanged.

[0015] Figure 2 Fig. 3 is a system block diagram of a QC-LDPC decoder 300 using a layered algorithm according to the prior art, which comprises a variable node module 301, a Q memory 302, a V2C shift module 303 (V2C is an abbreviation of variable node to check node), a check node module 304, a C2V shift module 305 (C2V is an abbreviation of check node to variable node), an R memory 306, a channel memory 307, and a shift parameter unit 309. Every K variable nodes are taken as a group for processing in groups. The variable node module 301 updates the Q information based on the R memory 306 according to equation (2). All the Q information is stored in the Q memory 302. Under the layered architecture of the QC-LDPC decoder 300, the Q information is arranged in the order of the check nodes by the V2C shift module 303 according to the shift parameters 309a output by the shift parameter unit 309. The check node module 304 receives the output result of the V2C shift module 303 and updates the R information according to equation (6). The R information output by the check node module 304 is stored in the R memory 306 after being restored to the arrangement order by the C2V shift module 305 according to the shift parameters 309b output by the shift parameter unit 309.

[0016] Figure 3 Fig. 4 is a detailed structure of the shift parameter unit 309, which comprises a read-only memory 320 and a pipeline register 321, which comprises registers d1-d YEach register can store X values. The read-only memory stores XxY base matrix values, and each column value of the base matrix is sequentially output to the pipeline registers 321 in a loop manner every clock cycle. According to the characteristics of the QC-LDPC code, the values of the base matrix are the shift parameters required by the V2C shift module 303 and the C2V shift module 305, but the cyclic shift direction of the C2V shift module 305 is opposite to that of the V2C shift module 303. Since the operation of each functional block of the QC-LDPC decoder 300 requires one or more clock cycles, the base matrix values need to be delayed for a specific clock cycle to match the operation time points of the V2C shift module 303 and the C2V shift module 305. The shift parameters 309a and 309b output by the shift parameter unit 309 come from two register values in the pipeline registers 321, Figure 3 For example.

[0017] From Figure 2 It can be seen that the variable node module 301, the V2C shift module 303, the check node module 304, and the C2V shift module 305 are coupled in series. One decoding cycle process passes through the variable node module 301, the V2C shift module 303, the check node module 304, the C2V shift module 305, and returns to the variable node module 301, a total of four modules. Each module operation requires one or more clock cycles. The more the total number of clock cycles accumulated in one decoding cycle, the slower the convergence speed of the decoder. Therefore, how to reduce the total number of clock cycles in a single decoding cycle is an important issue to improve the throughput of the QC-LDPC decoder and thus improve the flash memory access performance. SUMMARY

[0018] To improve the flash memory access performance, the present application provides a flash memory controller and a flash memory access method. By adjusting the decoder structure and improving the convergence speed of iterative operation, the decoding throughput is increased, thereby improving the flash memory access performance.

[0019] In a first aspect, a flash memory controller for accessing a flash memory is provided. The flash memory controller includes a read-only memory, a microprocessor, and a decoder. The read-only memory is configured to store a program code. The microprocessor is configured to execute the program code to control access to the flash memory. The decoder is configured to perform a decoding operation of a quasi-cyclic low-density parity-check code. The decoder includes a shift parameter unit configured to output a first shift parameter and a second shift parameter based on an X×Y base matrix of the quasi-cyclic low-density parity-check code; a Q memory configured to store Q information; an R memory configured to store R information; a variable node module configured to update Q information based on channel information obtained from the flash memory and R information; a V2C shift module configured to cyclically shift the Q information according to the first shift parameter to output Q' information; a check node module configured to update R information based on the Q' information and state data S, and output state data S, each state data S including a minimum value, a second minimum value, an index value of the minimum value, and a sign value; and a second shift module configured to cyclically shift the state data S according to the second shift parameter to output state data S' to the check node module.

[0020] In some embodiments, the check node module includes a submodule, the second shift module includes a shift unit, the second shift parameter includes a sub-parameter, the state data S includes first state data S to Kth state data S, K is an integer, the state data S' includes first state data S' to Kth state data S', the Q' information includes first Q' information to Kth Q' information, and the R information includes first R information to Kth R information, wherein: the shift unit of the second shift module is configured to receive the first state data S to the Kth state data S, cyclically shift the first state data S' to the Kth state data S' according to the sub-parameter of the second shift parameter, and output the first state data S' to the Kth state data S'; and the submodule of the check node module includes first check node unit to Kth check node unit, wherein the kth check node unit receives the kth Q' information and the kth state data S', updates the kth R information, and outputs the kth state data S, k is an integer from 1 to K.

[0021] In some embodiments, the check node module includes X submodules, each submodule of the check node module includes K check node units, the second shift module includes X shift units, the second shift parameter includes X sub-parameters, the state data S includes X·K state data S, the state data S' includes X·K state data S', the Q' information includes X·K Q' information, and the R information includes X·K R information.

[0022] In some embodiments, the shift parameter unit comprises: a read-only memory for storing the ZxY base matrix; a pipeline register comprising a number of registers less than or equal to Y, each register capable of storing X values; wherein each time a clock cycle, each column of the base matrix is sequentially output to the pipeline register; the first shift parameter output by the shift parameter unit is the difference between a first register and a second register in the pipeline register; the second shift parameter output by the shift parameter unit is the difference between a third register and a fourth register in the pipeline register; wherein the first register and the second register are adjacent, and the third register and the fourth register are adjacent.

[0023] In a second aspect, the present application also provides a method for accessing a flash memory, applied to a flash memory controller, the method comprising: obtaining a channel information from a flash memory; performing a decoding operation on the channel information based on a decoding operation of a parity check matrix of a quasi-cyclic low-density parity check code.

[0024] In some embodiments, the decoding operation method comprises: calculating a first shift parameter and a second shift parameter based on a shift parameter matrix; performing a Q information update operation to update Q information based on the channel information and R information; performing a cyclic shift on the Q information based on the first shift parameter to output Q' information; performing an R information update operation based on the Q' information and state data S' to update R information, and outputting the state data S.

[0025] In some embodiments, the initial value of the shift parameter matrix is a base matrix corresponding to the parity check matrix, each column of the shift parameter matrix is cyclically shifted by one row each time an iteration operation, the first shift parameter is the difference between a specific first column and a specific second column of the matrix, and the second shift parameter is the difference between a specific third column and a specific fourth column of the shift parameter matrix.

[0026] Compared with the prior art, the present application provides a flash memory controller and a method for accessing a flash memory, adjusts the quasi-cyclic low-density parity check code decoder architecture, and the modules connected in series in the decoding process are only the variable node module, the V2C shift module, and the check node module, the number of which is reduced to 3, so that the convergence speed of the decoding iteration is improved, and the flash memory access performance is improved. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1A An example of a parity check matrix of a quasi-cyclic low-density parity check code is shown;

[0028] Figure 1B A Tanner graph corresponding to Figure 1A is shown;

[0029] Figure 2A prior art QC-LDPC decoder block diagram is shown.

[0030] Figure 3 A prior art shift parameter unit block diagram is shown.

[0031] Figure 4 A block diagram of a storage device according to an embodiment of the present application

[0032] Figure 5 A QC-LDPC decoder block diagram according to an embodiment of the present application

[0033] Figure 6 A shift parameter unit block diagram according to an embodiment of the present application

[0034] Figure 7 A check node module and state data shift module block diagram according to an embodiment of the present application

[0035] Figure 8 A flowchart of a flash memory access method according to an embodiment of the present application. DETAILED DESCRIPTION

[0036] Example embodiments of the present application will now be described more fully with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the examples set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art, and the present application will only be defined by the claims. The accompanying drawings are included to provide a further understanding of the application and are incorporated into and constitute a part of this specification. The drawings illustrate examples of the present application and, together with the description, serve to explain the principles of the present application. In the drawings:

[0037] Referring to Figure 4 , a block diagram of a storage device 10 according to an embodiment of the present application is shown. The storage device 10 includes a flash memory controller 100 and a flash memory 190. The flash memory controller 100 is used to control the operation of the storage device 10 and the flash memory 190. The storage device 10 can include, but is not limited to, a solid state drive and various types of embedded storage devices, such as an embedded storage device conforming to the Peripheral Component Interconnect Express (PCIe) standard, etc.

[0038] As Figure 4As shown, the flash memory controller 100 can include a control logic circuit 110, an interface circuit 120, a microprocessor 130, a buffer 140, and a read-only memory 150. The flash memory controller 100 is coupled to the flash memory 190 through the control logic circuit 110 to transmit commands and access data. The flash memory controller 100 can be connected to an external host device through the interface circuit 120. The microprocessor 130 is electrically coupled to the control logic circuit 110, the interface circuit 120, the buffer 140, and the read-only memory 150. Examples of the buffer 140 include a dynamic random access memory (DRAM), a static random access memory (SRAM), or other volatile memory, without limitation. The read-only memory 150 is used to store a program code 151.

[0039] Optionally, the host device can include a processor and a power supply circuit coupled to each other. The processor can be used to control the operation of the host device, and the power supply circuit can be used to provide power to the processor and the memory device 10, and output one or more drive voltages to the memory device 10. The memory device 10 can be used to provide storage space for the host device, and obtain one or more drive voltages from the host device as a power source of the memory device 10. The host device mentioned herein can include, but is not limited to, a mobile device, a wearable device, a tablet computer, and a personal computer such as a desktop computer and a laptop computer.

[0040] Optionally, the interface circuit 120 of the flash memory controller 100 can comply with a specific communication standard, including but not limited to, a Serial Advanced Technology Attachment (Serial ATA or SATA) standard, a Peripheral Component Interconnect (PCI) standard, a PCIe standard, a Universal Flash Storage (UFS) standard, and the like, and can communicate according to the specific communication standard.

[0041] The flash memory controller 100, which executes program code 151 via a microprocessor 130, can utilize its internal components to perform various control operations, such as controlling access to the flash memory 190 using the control logic circuit 110, communicating with a host device using the interface circuit 120, and performing required buffering using the buffer 140. For example, the host device can transmit a host command and a corresponding logical address to the flash memory controller 100. The microprocessor 130 of the flash memory controller 100 receives the host command and the logical address via the interface circuit 120, converts the host command into a storage operation command, and further uses the control logic circuit 110 to perform operations such as reading and / or writing to a storage cell (e.g., a data page) at a corresponding physical address in the flash memory 190, where the physical address corresponds to the logical address.

[0042] like Figure 4 As shown, the control logic circuit 110 may include an encoder 111 and a decoder 112. The encoder 111 is used to encode data written to the flash memory 190, while the decoder 112 is used to decode data received from the flash memory 190. When the host device issues a read command, the microprocessor 130 can convert / decode the host device's read command (including a logical address) into a corresponding internal control signal (including the physical address of the flash memory 190). Based on the internal control signal, the control logic circuit 110 can address / control the flash memory 190 to read the original codewords in the flash memory 190. The decoder 112 of the control logic circuit 110 can perform LDPC code decoding operations to decode the read information obtained from the flash memory, thereby decoding the original codewords into data and temporarily storing the decoded data in the buffer 140. The microprocessor 130 can then return the data temporarily stored in the buffer 140 to the host device.

[0043] Please refer to Figure 5FIG. 5 shows a block diagram of a decoder 112 according to an embodiment of the present application. The decoder 112 comprises a variable node module 501, a Q memory 502, a V2C shift module 503, a check node module 504, a state data shift module 505, an R memory 506, a channel memory 507, and a shift parameter unit 509. The decoder 112 is designed with a layered algorithm architecture, and iteratively processes in layers of K variable nodes. The data read from the flash memory 190 is referred to as channel messages by the decoder, and is stored in the channel memory 507. A brief description of an iteration of the decoding operation is as follows. The variable node module 501 updates Q information based on the R memory 506 and the channel memory 507. All of the Q information is stored in the Q memory 502. The Q information is cyclically shifted (or rotated) by the V2C shift module 503 according to shift parameters 509a output by the shift parameter unit 509 to arrange the Q information in a particular order, resulting in Q' information 503a. The state data of the check node module 504 is cyclically shifted by the state data shift module 505 according to shift parameters 509b output by the shift parameter unit 509 to arrange the state data in a particular order, and is fed back to itself along with the received Q' information 503a, to update the output R information 504a. All of the R information is stored in the R memory 506. The above process forms one iteration of the decoding operation.

[0044] Please refer to Figure 6 FIG. 5 shows a block diagram of a decoder 112 according to an embodiment of the present application. The decoder 112 comprises a variable node module 501, a Q memory 502, a V2C shift module 503, a check node module 504, a state data shift module 505, an R memory 506, a channel memory 507, and a shift parameter unit 509. The decoder 112 is designed with a layered algorithm architecture, and iteratively processes in layers of K variable nodes. The data read from the flash memory 190 is referred to as channel messages by the decoder, and is stored in the channel memory 507. A brief description of an iteration of the decoding operation is as follows. The variable node module 501 updates Q information based on the R memory 506 and the channel memory 507. All of the Q information is stored in the Q memory 502. The Q information is cyclically shifted (or rotated) by the V2C shift module 503 according to shift parameters 509a output by the shift parameter unit 509 to arrange the Q information in a particular order, resulting in Q' information 503a. The state data of the check node module 504 is cyclically shifted by the state data shift module 505 according to shift parameters 509b output by the shift parameter unit 509 to arrange the state data in a particular order, and is fed back to itself along with the received Q' information 503a, to update the output R information 504a. All of the R information is stored in the R memory 506. The above process forms one iteration of the decoding operation. YEach register can store X values. The read-only memory 520 stores the values of the XxY base matrix W. Each column of the base matrix W (an Xxl matrix) is output sequentially to the pipeline registers 521 in a circular manner, one column per clock cycle. Therefore, the number of registers is at most Y. The effect is equivalent to circularly shifting each column of the base matrix W. According to the present application, the shift parameter is the difference between two specific adjacent registers in the pipeline registers 521. The subtracter 523 provides the difference between the register dl and the register d2 as the shift parameter 509b to the state data shift module 505. Since it takes one clock cycle for the check node module 504 to operate and store the output to the R memory 506, for the variable node module 501 to operate and store the output to the Q memory 506, and for the V2C shift module 503 to operate, the negative of the difference between the register d4 and the register d5 three clock cycles later is the shift parameter to be provided to the V2C shift module 503. That is, the subtracter 522 provides the difference between the register d5 and the register d4 as the shift parameter 509a to the V2C shift module 503. It can be understood that when Y = 4, the value of the register d5 is actually the same as the value of the register dl. Therefore, the number of registers is only four, and the shift parameter 509a can be obtained by subtracting the register d4 from the register dl. The shift parameter according to the present application is the difference between two specific adjacent registers in the pipeline registers 521, which will be further described below.

[0045] Please refer to Figure 7 The block diagram of the check node module 504 and the state data shift module 505 according to an embodiment of the present application is shown in FIG. 4. The state data shift module 505 includes X state data shift units 515(x), x = 0,..., X-l. The shift parameter 509b from the shift parameter unit 509 is an Xxl matrix, which includes X shift parameters 509b(x), x = 0,..., X-l, respectively provided to the state data shift units 515(x). The check node module 504 includes X check node sub-modules 514(x), x = 0,..., X-l, each of which includes K check node units (CNUs) 516(x, k), k = 0,..., K-l. Therefore, there are a total of M check node units 516(x, k), corresponding to the check nodes c m , m = x x K + k. The Q' information 503a output by the V2C shift module 503 is an Mxl matrix, which includes {Q' information 503a(x, k) | x = 0,..., X; k = 0,..., K-l} and is input to the corresponding check node units 516(x, k).

[0046] For each check node unit 516(x, k), based on the minimum-sum (min-sum) decoding algorithm, the processing of equation (6) for the i-th iteration and the g-th group of variable nodes can be rewritten as follows:

[0047]

[0048] Where α is a fixed compensation parameter of the minimum-sum decoding algorithm, and the function of min12(·) is to extract the minimum value of the listed input parameters (min1 m ), the next minimum value (min2 m ), and the index value corresponding to the minimum value (index)(min1_index m ), is a total positive and negative value, This is the Q′ information 503a(x, k) received by the check node unit 516(x, k). Considering the iterative operation, it can be further rewritten as the following equation:

[0049]

[0050]

[0051] in for The value before being updated by the check node module 504, the check node module will and The values ​​are stored for use in the above operations. Define the i-th iteration of the check node unit 516 (x, k) The state data is shown in the following equation:

[0052]

[0053] From the above equations, it can be concluded that for the i-th iteration, the check node unit 516 (x, k) can be based on the received Information and status data from the previous iteration You can calculate According to the present invention, each check node unit 516(x,k) in the check node submodule 514(x) calculates the status data The state data shift unit 515(x) shifts the state data according to the shift parameter 509b(x). After cyclic shift, another state data S is generated x ′, is fed back to the check node submodule 514(x) and becomes the operation status data of the next iteration of each check node unit 516(x,k). The R information output by each check node unit 516(x,k) The output R information result 504a of the check node module 504 is integrated, and the output is stored in the R storage 306.

[0054] To arrange the R information output by the check node according to the order of the variable node, the present application adopts a different method from the prior art, thereby reducing the total number of clock cycles in a decoding cycle, and improving the overall performance. This is a feature of the present application. Figure 2 In the prior art, the check node module 304 also has XxK (i.e. M) check node units, which correspond to the check nodes in the Tanner graph in sequence, and the R information output by the check node units is arranged in the order of the check nodes. The arrangement order of the R information is also the order of the check nodes. After the cyclic shift of the C2V shift module 305, the R information is rearranged in the order of the variable nodes, i.e. and then stored in the R storage 306.

[0055] From the perspective of signal order, the input signal of the V2C shift module 503 The order of the input signal of the V2C shift module 503 is the order of the variable node index n'. It can be understood that if a signal order is cyclically shifted by a shift parameter w, and then cyclically shifted by the opposite number -w of the shift parameter (the negative sign means reverse), the signal will return to the original order. Therefore, in the present application, the shift parameter received by the V2C shift module 503 and the shift parameter received by the state data shift module 505 are opposite numbers, but since the check node module 504 and the state data shift module 505 both have at least one clock cycle of operation time, the shift parameter received by the V2C shift module 503 and the shift parameter received by the state data shift module 505 will have a clock cycle difference. Through the state data shift module 505, the state data of each check node unit 516 is cyclically shifted and transferred to the next clock cycle of each check node unit 516, which is like cyclically shifting the physical check node unit 516. Since the shift parameter is the opposite number of the shift parameter of the V2C shift module 503, the order of the signal output by the check node module 504 will be the same as the order of the input signal of the V2C shift module 503, so the present application does not need the C2V shift module 305 in the prior art.

[0056] Since each check node unit 516 in the present application is equivalent to also performing cyclic shift, the shift parameters of the V2C shift module 503 must be adjusted accordingly, and thus are different from the shift parameters of the V2C shift module 303 in the prior art. It can be observed that each check node unit 516 is equivalent to having a cyclic shift, and for the next operation period, the order of the input information of the V2C shift module 503 will be aligned with the order of each check node unit 516 as long as the shift difference, i.e., the difference between the shift parameters corresponding to the previous and next operation periods, is supplemented. Therefore, the shift parameters input to the V2C shift module 503 in the present application will be the difference between two adjacent column values of the base matrix, which corresponds to Figure 6 The shift parameter unit 509 is the difference between two adjacent registers. Which two registers are related to the number of clock cycles required for the operation of each module. The shift parameter of the state data shift module 505 is the opposite of the shift parameter of the V2C shift module 503, and thus will also be Figure 6 The shift parameter unit 509 is the difference between two adjacent registers. Which two registers are related to the number of clock cycles required for the operation of each module.

[0057] It should be understood that the variable node module 501, the Q storage 502, the R storage 506, the channel storage 507, the min12(·) function, and how to output the decoding result (not shown in the figure) based on the variable node operation result of equation (4) in the decoder 112 can be various implementation methods, all of which can be applied to the decoder architecture proposed in the present application, and thus the implementation details of these parts are not described here. The V2C shift module 503 and the state data shift module 505 can use various circular shifters or barrel shifters, all of which can be applied to the present application, and thus the implementation details of these parts are not described here. The above-mentioned respective storage blocks are schematic diagrams, and do not necessarily mean physically independent storage. Depending on the implementation plan, it can be a block in the overall system physical storage.

[0058] The present application also provides a flash memory access method applied to a flash memory controller. The flash memory controller is coupled to the flash memory to transmit commands and access data. The specific structure and function of the flash memory controller and the flash memory are as described above, and are not described here.

[0059] Please refer to Figure 8 , which shows a flowchart of a flash memory access method according to an embodiment of the present application. The flash memory access method at least includes the following steps.

[0060] In step S81, a channel information is obtained from a flash memory.

[0061] In step S82, the channel information is decoded based on a parity check matrix of a quasi-cyclic low density parity check code. Step S82 includes the following steps:

[0062] In step S821, a shift parameter matrix is formed by cyclically shifting each column of the shift parameter matrix by one row for each iteration based on a base matrix corresponding to the parity check matrix, and a first shift parameter and a second shift parameter are calculated based on the shift parameter matrix, wherein the first shift parameter is a difference between a particular first column and a particular second column of the shift parameter matrix, and the second shift parameter is a difference between a particular third column and a particular fourth column of the shift parameter matrix, wherein the particular first column and the particular second column are adjacent columns, and the particular third column and the particular fourth column are adjacent columns. The particular first column and the particular second column are determined based on the number of clock cycles required for each module to operate.

[0063] In step S822, Q information updating operations as shown in equation (2) are performed to update the Q information based on the channel information and the R information.

[0064] In step S823, the Q information is cyclically shifted based on the first shift parameter to generate Q' information.

[0065] In step S824, R information updating operations as shown in equations (18) to (27) are performed to update the R information based on the Q' information and the state data S', and the state data S is outputted, wherein the state data S is a state data during the R information updating operation, and includes a minimum value, a minimum value index, and a sign value.

[0066] In step S825, the state data S is cyclically shifted based on the second shift parameter to generate state data S ′ The step S824 is fed back to the step S824.

[0067] In step S826, a decoding result is determined based on the channel information, the R information, and the parity check matrix. The decoding result is obtained when a code word estimated based on equation (4) multiplied by the parity check matrix is 0.

[0068] The above is an iteration operation process, and the R information updated in step S824 is used in step S822, and the operation loop is continuously executed.

[0069] It is understood that the steps in the method of the present application are examples for convenience of explanation, and the order is not necessarily as described. For example, step S825 and step S824 can be performed in parallel, and step S821 can also be performed in parallel with other steps, and thus there is no order.

[0070] The above description is an example of using the variable nodes as a group of K to perform hierarchical algorithm decoding operations. It should be understood that using the variable nodes as a group of zK (z is an integer) to perform hierarchical algorithm decoding operations can also be applied to the present application.

[0071] From the decoder architecture, the modules connected in series in the decoding process of the prior art decoder include the variable node module, the V2C shift module, the check node module, and the C2V shift module, for a total of four. The modules connected in series in the decoding process of the decoder of the present application include only the variable node module, the V2C shift module, and the check node module, for a total of three. Therefore, the decoding iteration convergence speed is improved, and the flash memory access performance is improved.

[0072] The above is merely specific embodiments of the present application, and the protection scope of the present application is not limited thereto. Those skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, and all should be encompassed within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A flash memory controller for accessing a flash memory, characterized in that: The flash memory controller contains: a first storage for storing a program code; a microprocessor for executing the program code to control access to the flash memory; as well as A decoder is configured to perform a decoding operation of a quasi-cyclic low-density parity-check code based on a channel information obtained from the flash memory, wherein the operation data of the decoder includes: a plurality of Q information and a plurality of R information. The decoder includes: a shift parameter unit for outputting a first shift parameter and a second shift parameter based on an X×Y basic matrix of the quasi-cyclic low-density parity-check code; a second storage device for storing the plurality of Q information; a third storage device for storing the plurality of R information; a variable node module for updating the plurality of Q information based on the channel information obtained from the flash memory and the plurality of R information; a first shift module, configured to output a plurality of Q′ information based on the plurality of Q information and the first shift parameter; a second shift module for generating a plurality of state data S'; and a check node module configured to update the plurality of R information based on the plurality of Q′ information and the plurality of state data S′, and output a plurality of state data S, wherein the state data S includes a minimum value, a minimum value, an index value of the minimum value, and a total sign value; The second shift module receives the plurality of state data S, performs cyclic shift according to the second shift parameter, and generates the plurality of state data S′.

2. The flash controller of claim 1, wherein, The check node module includes a submodule, the second shift module includes a shift unit, the second shift parameter includes a subparameter, the plurality of state data S includes first state data S to K-th state data S, K is an integer, the plurality of state data S′ includes first state data S′ to K-th state data S′, the plurality of Q′ information includes first Q′ information to K-th Q′ information, and the plurality of R information includes first R information to K-th R information, wherein: The shift unit of the second shift module is used to receive the first state data S to the K-th state data S, perform cyclic shift according to the sub-parameter of the second shift parameter, and generate the first state data S′ to the K-th state data S′; and The submodule of the check node module includes the first check node unit to the Kth check node unit, wherein the kth check node unit receives the kth Q′ information and the kth state data S′, updates the kth R information, and outputs the kth state data S, where k is an integer from 1 to K.

3. The flash controller of claim 2, wherein, The check node module includes X submodules, each submodule of the check node module includes K check node units, the second shift module includes X shift units, the second shift parameter includes X subparameters, the multiple state data S includes X·K state data S, the multiple state data S′ includes X·K state data S′, the multiple Q′ information includes X·K Q′ information, and the multiple R information includes X·K R information.

4. The flash controller of claim 1, wherein, The shift parameter unit includes: a fourth storage for storing the X×Y basic matrix; A pipeline register, which includes multiple registers, each of which can store X values; The base matrix is sequentially output to the pipeline register by each clock cycle. The first shift parameter output by the shift parameter unit is the difference between the first register and the second register in the pipeline register. The second shift parameter output by the shift parameter unit is the difference between the third register and the fourth register in the pipeline register. The first register is adjacent to the second register, and the third register is adjacent to the fourth register.

5. The flash controller of claim 4, wherein, The number of registers in the pipeline register is less than or equal to Y.

6. The flash controller of claim 1, wherein, The first shift module and the second shift module are barrel shifters.

7. An access method of a flash memory, applied to a memory controller, characterized in that, The method comprises: Obtaining a channel information from a flash memory; and Performing a decoding iteration operation on the channel information based on a parity check matrix of a quasi-cyclic low-density parity-check code, which comprises: Calculating a first shift parameter based on a shift parameter matrix, the first shift parameter being the difference between a specific first column and a specific second column of the matrix; Performing a Q information update operation based on the channel information and a plurality of R information to update a plurality of Q information; and Cyclically shifting the plurality of Q information based on the first shift parameter to output a plurality of Q' information; The specific first column and the specific second column are adjacent, and the initial value of the shift parameter matrix is a base matrix corresponding to the parity check matrix. Each time the iteration operation is performed, each column of the shift parameter matrix is cyclically shifted by one row.

8. The method of accessing flash memory of claim 7, wherein, The decoding iteration operation further comprises the following method: Calculating a second shift parameter based on the shift parameter matrix, the second shift parameter being the difference between a specific third column and a specific fourth column of the shift parameter matrix; Cyclically shifting a plurality of state data S based on the second shift parameter to output a plurality of state data S'; Performing an R information update operation based on the plurality of Q' information and the plurality of state data S' to update the plurality of R information, and outputting the plurality of state data S to; The plurality of state data S is a state data in the R information update operation process.

9. The method of accessing flash memory of claim 8, wherein, Each state data S includes a minimum value, a small value, an index value of the minimum value, and a sign value.

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