Simulation method, device, system and equipment of digital circuit and medium

Abstract

The invention relates to a simulation method, device, system and equipment of a digital circuit and a medium. Comprising the steps that description information for the same digital circuit is obtained, and the description information comprises at least one of register transfer level description and gate level description; generating a primary circuit model based on the description information; the primary circuit model is converted into a middle layer circuit model connected with a preset basic logic unit, the basic logic unit is single-bit or multi-bit, each basic logic unit is provided with a corresponding model level attribute and a bit width attribute, and the model level attribute is a register transmission level or a gate level; and calling a simulation algorithm based on the intermediate layer circuit model to carry out circuit simulation to obtain a simulation result. By adopting the method, the simulation efficiency can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of digital circuit simulation, in particular to a simulation method, device, system, equipment and medium for digital circuit. BACKGROUND

[0002] With the rapid development of electronic technology, digital circuit design is becoming more and more complex, and the requirement for simulation technology is also getting higher and higher. Digital circuit simulation is mainly used to verify the correctness and performance of circuit design, and to ensure that potential problems can be found and solved before actual manufacturing. In the prior art, digital circuit simulation can be classified from two dimensions: simulation mode (including dynamic simulation and static simulation) and simulation level (including RTL (Register Transfer Level Simulation) simulation and Gate-Level Simulation).

[0003] In practical applications, users often need to select appropriate simulation mode and level according to specific requirements. However, the existing circuit simulation tools mainly have the following problems: 1. High maintenance cost; 2. There may be data structure compatibility problems between different circuit models used for circuit simulation, which cannot be simulated under a unified circuit model. The above problems will result in low simulation efficiency.

[0004] At present, there is no effective solution to the problem of low efficiency of digital circuit simulation in the prior art. SUMMARY

[0005] Therefore, it is necessary to provide a simulation method, device, system, equipment and medium for digital circuit to solve the above technical problems.

[0006] In a first aspect, the present application provides a simulation method for digital circuit. The method comprises:

[0007] Obtaining description information for the same digital circuit, the description information including at least one of register transfer level description and gate level description;

[0008] Generating a primary circuit model based on the description information;

[0009] Converting the primary circuit model into an intermediate layer circuit model connected by preset basic logic units, each basic logic unit being provided with a corresponding model level attribute, the model level attribute being register transfer level or gate level;

[0010] Calling a simulation algorithm based on the intermediate layer circuit model to perform circuit simulation and obtain a simulation result.

[0011] In one of the embodiments, converting the primary circuit model into the intermediate layer circuit model connected by the preset basic logic units comprises:

[0012] When the primary circuit model is the register transfer level circuit model, mapping the primary circuit model in the register transfer level circuit model into the basic logic units in the intermediate layer circuit model; the basic logic units comprise preset intermediate layer circuit units; wherein,

[0013] In the intermediate layer circuit model, the basic logic units are provided with register transfer level attributes, wherein the register transfer level attributes are used to represent that the basic logic units come from the register transfer level circuit model.

[0014] In one of the embodiments, converting the primary circuit model into the intermediate layer circuit model connected by the preset basic logic units comprises:

[0015] When the primary circuit model is the gate level circuit model, mapping each unit in the gate level circuit model into the basic logic units in the intermediate layer circuit model; the basic logic units comprise basic units of a standard unit library; wherein,

[0016] In the intermediate layer circuit model, the basic logic units are provided with gate level attributes, wherein the gate level attributes are used to represent that the basic logic units come from the gate level circuit model.

[0017] In one of the embodiments, calling a simulation algorithm based on the intermediate layer circuit model to perform circuit simulation to obtain a simulation result comprises:

[0018] Obtaining a switching instruction through a preset simulation configuration interface;

[0019] In response to the switching instruction, performing corresponding static simulation processing or dynamic simulation processing.

[0020] In one of the embodiments, the basic logic units comprise timing logic units; performing corresponding static simulation processing comprises:

[0021] When performing static simulation processing based on the intermediate layer circuit model, establishing a static simulation queue composed of the timing logic units in the intermediate layer circuit model;

[0022] Setting a preset target logic unit in the timing logic units at a preset target position in the static simulation queue, and obtaining a static simulation result based on the static simulation queue.

[0023] In one of the embodiments, after establishing the static simulation queue composed of the timing logic units in the intermediate layer circuit model when performing static simulation processing based on the intermediate layer circuit model, further comprising:

[0024] In the determining timing logic unit, the target logic unit changing the output state based on the specific trigger condition, the output of the target logic unit under the specific trigger condition is set as an undetermined state.

[0025] In one of the embodiments, the performing the corresponding dynamic simulation processing includes:

[0026] In the dynamic simulation processing based on the intermediate layer circuit model, an event queue is established based on the output signals in the intermediate layer circuit model, and each event in the event queue is updated based on the output signals of the events in the event queue and in combination with the preset dynamic simulation rule, so as to obtain the dynamic simulation result.

[0027] In one of the embodiments, the updating the event queue based on the output signals of the events in the event queue and in combination with the preset dynamic simulation rule to obtain the dynamic simulation result includes:

[0028] The updating step: the event simulation is performed based on the default priority in the event queue in sequence and is dequeued in a loop, wherein, each time an event is dequeued, the output signals generated by the event simulation are traversed to iterate the subordinate events related to the event, and the subordinate events are put into the event queue for updating;

[0029] If it is detected that there is an unprocessed output signal in the event queue, the next round of simulation is performed, and the updating step is repeated until the preset simulation end condition is met, so as to obtain the dynamic simulation result.

[0030] In a second aspect, the application further provides a simulation device of a digital circuit. The device includes:

[0031] A description information acquisition unit is configured to acquire description information for the same digital circuit, and the description information includes at least one of register transfer level description and gate level description;

[0032] A primary circuit model generation unit is configured to generate a primary circuit model based on the description information;

[0033] An intermediate layer circuit model conversion unit is configured to convert the primary circuit model into an intermediate layer circuit model connected by preset basic logic units, and the intermediate layer circuit unit includes the basic logic units, each of which is provided with a corresponding model level attribute, and the model level attribute is a register transfer level or a gate level;

[0034] A simulation unit is configured to call a simulation algorithm to perform circuit simulation based on the intermediate layer circuit model, so as to obtain a simulation result.

[0035] In a third aspect, the application further provides a simulation system of a digital circuit, which includes a modeling module, a simulation manager and a simulation queue calculation engine, wherein the simulation manager is connected with the modeling module and the simulation queue calculation engine respectively.

[0036] The modeling module is configured to acquire description information of the same digital circuit, generate a primary circuit model based on the description information, and convert the primary circuit model into an intermediate layer circuit model connected by preset basic logic units; the description information comprises at least one of register transfer level description and gate level description, the intermediate layer circuit unit comprises a basic logic unit, each basic logic unit is provided with a corresponding model level attribute, and the model level attribute is register transfer level or gate level;

[0037] The simulation manager is configured to manage and schedule the simulation queue calculation engine.

[0038] The simulation queue calculation engine is configured to perform circuit simulation by calling a simulation algorithm based on the intermediate layer circuit model, and obtain a simulation result.

[0039] In a fourth aspect, the present application further provides a computer device. The computer device comprises a memory and a processor, the memory stores a computer program, and the processor implements the following steps when executing the computer program:

[0040] Acquire description information of the same digital circuit, and the description information comprises at least one of register transfer level description and gate level description.

[0041] Generate a primary circuit model based on the description information.

[0042] Convert the primary circuit model into an intermediate layer circuit model connected by preset basic logic units, each basic logic unit is provided with a corresponding model level attribute, and the model level attribute is register transfer level or gate level.

[0043] Call a simulation algorithm based on the intermediate layer circuit model to perform circuit simulation, and obtain a simulation result.

[0044] In a fifth aspect, the present application further provides a computer readable storage medium. The computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the following steps:

[0045] Acquire description information of the same digital circuit, and the description information comprises at least one of register transfer level description and gate level description.

[0046] Generate a primary circuit model based on the description information.

[0047] Convert the primary circuit model into an intermediate layer circuit model connected by preset basic logic units, each basic logic unit is provided with a corresponding model level attribute, and the model level attribute is register transfer level or gate level.

[0048] Call a simulation algorithm based on the intermediate layer circuit model to perform circuit simulation, and obtain a simulation result.

[0049] The simulation method, device, system, equipment and medium of the digital circuit can generate a primary circuit model based on the description information of the same digital circuit, convert the primary circuit model into an intermediate layer circuit model connected by preset basic logic units, each basic logic unit is provided with a corresponding model level attribute, and the model level attribute is a register transfer level or a gate level; and finally, a simulation algorithm is called based on the intermediate layer circuit model to perform circuit simulation to obtain a simulation result. Through the present application, the register transfer level circuit model and the gate level circuit model can be uniformly converted into a unified intermediate layer circuit model, avoiding the data structure compatibility problem and improving the simulation efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0050] Figure 1 An application environment diagram of the simulation method in an embodiment;

[0051] Figure 2 A flowchart of the simulation method in an embodiment;

[0052] Figure 3 A full adder structure diagram in an embodiment;

[0053] Figure 4 A mapping result diagram of the full adder structure in the intermediate layer circuit model;

[0054] Figure 5 A mapping result diagram of a 2-bit adder in the intermediate layer circuit model;

[0055] Figure 6 A structural block diagram of the simulation device in an embodiment;

[0056] Figure 7 A structural block diagram of the simulation system in an embodiment;

[0057] Figure 8 An internal structure diagram of the computer equipment in an embodiment. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0059] The simulation method of the digital circuit provided by the embodiments of the present application can be applied to, for example Figure 1The application environment is shown. Among them, the terminal 102 communicates with the server 104 through the network. The data storage system can store the data required by the server 104 to process. The data storage system can be integrated on the server 104, or placed on the cloud or other network servers. The method comprises: obtaining description information for a digital circuit, the description information comprising at least one of register transfer level description and gate level description; then generating a primary circuit model based on the description information; converting the primary circuit model into an intermediate layer circuit model connected by preset basic logic units, the intermediate layer circuit model comprising basic logic units, each basic logic unit being provided with a corresponding model level attribute, the model level attribute being a register transfer level or a gate level; calling a simulation algorithm based on the intermediate layer circuit model to perform circuit simulation, and obtaining a simulation result. Among them, the terminal 102 can be, but is not limited to, various personal computers, notebook computers, smart phones, tablet computers, Internet of Things devices, etc., can obtain instructions (such as simulation mode or simulation level switching instructions) issued by the user through the terminal 102, can also obtain the required data through the terminal 102, such as the description information of the specified digital circuit, and display the simulation result through the terminal 102, etc. The server 104 can be implemented by an independent server or a server cluster composed of multiple servers.

[0060] In one embodiment, as shown in Figure 2 , a simulation method of a digital circuit is provided. The method is applied to the server in Figure 1 for example, comprising the following steps:

[0061] Step S210, obtaining description information for a digital circuit, the description information comprising at least one of register transfer level description and gate level description.

[0062] Specifically, the above-mentioned description information for a digital circuit at least comprises register transfer level description or gate level description, the register transfer level description refers to RTL (Register Transfer Level) level description, and the gate level description refers to Gate-Level level description, wherein the register transfer level description is a higher abstract level circuit representation, mainly focusing on the data flow between registers and the function of combinational logic, containing the function definition of combinational logic, such as addition, comparison, selection and other operations; the gate level description is a circuit description composed of basic logic gates and flip-flops. In actual application, the description information obtained for the same digital circuit sometimes includes part of the register transfer level description and part of the gate level description.

[0063] Step S220, generating a primary circuit model based on the description information.

[0064] Specifically, the description information is parsed by the parser to generate a corresponding basic circuit model. If the description information is a register transfer level description, a register transfer level circuit model is generated accordingly. Similarly, if the description information is a gate level description, a gate level circuit model is generated accordingly. In actual application, if the description information is a register transfer level description and a gate level description, a register circuit model can be modeled, that is, the scheme in the application is applicable to register transfer level circuit description, gate level circuit description, and mixed register transfer level and gate level circuit description. In actual application, generating a register transfer level circuit model based on a register transfer level description includes pre-synthesizing RTL code into a netlist composed of basic types, which can cover all RTL syntax, such as AND, OR, NOT, DFF, MUX, EQ, and dozens of basic types. Gates instantiated from these basic types are connected to each other to form a register transfer level circuit model. The pre-synthesizing function described above can be integrated in the parser or provided by the parser. The basic types are defined by different manufacturers. Generating a gate level circuit model based on a gate level description includes parsing a gate level netlist into a gate level structure, which is also composed of gates, but the types are determined by cells (standard cells used in logic synthesis) instantiated in the description information, and the cells are defined by a pre-existing standard cell library. The gates are connected to each other to form the gate level circuit model described above.

[0065] In step S230, the primary circuit model is converted into an intermediate layer circuit model connected by preset basic logic units, each of which is provided with a corresponding model level attribute, which is a register transfer level or a gate level.

[0066] Specifically, the primary circuit model is converted into an intermediate layer circuit model composed of basic logic units, each of which is provided with a corresponding model level attribute. The model level attribute indicates whether the basic logic unit is a register transfer level or a gate level. If the model level attribute is a register transfer level, it means that the basic logic unit is converted from a register transfer level circuit model. If the model level attribute is a gate level, it means that the basic logic unit is converted from a gate level circuit model. By setting the model level attribute of the basic logic unit, it is convenient for subsequent error tracing and debugging. In the simulation process, different simulation algorithms are called without sensing the specific circuit level, only focusing on the corresponding basic logic unit for circuit logic processing, which simplifies the simulation process.

[0067] The basic logic unit in the intermediate layer circuit model can be a combinational logic unit or a sequential logic unit, and can be a single bit or a multi-bit. Each basic logic unit can be provided with a corresponding bit width attribute, which indicates whether the basic logic unit is a single bit or a multi-bit. The basic logic unit in the present application supports multi-bit width configuration. Through the multi-bit basic logic unit, the intermediate layer circuit model allows to handle more complex logic structures in simulation, such as multi-bit adders or multi-bit multipliers, rather than single-bit logic gates. Handling multi-bit operations can reduce the number of logic gates that need to be simulated, thereby improving simulation efficiency.

[0068] In addition, the intermediate layer circuit model retains the hierarchical information (RTL or Gate-Level) of the primary circuit model, that is, the module is composed of basic logic unit gates, and the entire digital circuit is designed hierarchically by modules.

[0069] In step S240, a simulation algorithm is called based on the intermediate layer circuit model to perform circuit simulation, and a simulation result is obtained.

[0070] Specifically, based on the intermediate layer circuit model, a corresponding simulation algorithm is called to perform circuit simulation according to actual needs, and a corresponding simulation result is obtained, wherein the circuit simulation at least includes at least one of dynamic simulation and static simulation.

[0071] Specifically, according to the model level attribute of the basic logic unit, if the model level attribute of the basic logic unit is a register transfer level, an RTL model simulation method is called to perform simulation; if the model level attribute of the basic logic unit is a gate level, a gate level model simulation method is called to perform simulation. The RTL model simulation method and the gate level model simulation method can refer to conventional technologies, which are not limited herein.

[0072] Generally, there are RTL parsers and Gate-Level parsers on the market, but due to different implementation standards, in some cases, for a digital circuit composed of sub-circuit A and sub-circuit B, we need to use the RTL parsing function of the RTL parser to parse sub-circuit A and the Gate-Level parsing function of the Gate-Level parser to parse sub-circuit B. However, there can be data structure compatibility problems between different parsers, and mixed simulation cannot be performed under a unified circuit model.

[0073] By the step S210 to the step S240, the application supports the simulation of the register transfer level circuit and the simulation of the gate level circuit simultaneously, and the generated register transfer level circuit model or the gate level circuit model is converted into the intermediate layer circuit model. Since the unified intermediate layer circuit model is introduced, the intermediate modeling method compatible with the modeling results of the register transfer level description and the gate level description is provided, the application range is wider, and the support for the mixed simulation is provided. Therefore, even if the different parsers are used to generate the register transfer level circuit model or the gate level circuit model, the intermediate layer circuit model can be converted respectively, so that the simulation is performed under the unified circuit model, and the data structure compatibility problem does not occur, so that in the actual application, the efficiency of the model simulation can be effectively improved.

[0074] In one of the embodiments, the primary circuit model is converted into the intermediate layer circuit model connected by the preset basic logic unit, and the method comprises the following steps of:

[0075] When the primary circuit model is the register transfer level circuit model, the primary circuit model in the register transfer level circuit model is mapped into the basic logic unit in the intermediate layer circuit model; the basic logic unit comprises the preset intermediate layer circuit unit; wherein,

[0076] The intermediate layer circuit model is provided with the register transfer level attribute, and the basic logic unit can also be provided with the bit width attribute, wherein the register transfer level attribute is used to represent that the basic logic unit comes from the register transfer level circuit model, and the bit width attribute is used to represent the bit width value of the basic logic unit, and the bit width value is greater than or equal to 1.

[0077] Specifically, when the primary circuit model is the register transfer level circuit model, the initial circuit model is mapped into the basic logic unit in the intermediate layer circuit model. For the register transfer level circuit model, the basic logic unit comprises the preset intermediate layer circuit unit. In the embodiment, the mapping relationship between the register transfer level circuit model and the intermediate layer circuit model can be established by the relevant technical personnel based on the actual needs. Exemplarily, the types of the preset intermediate layer circuit unit include but are not limited to:

[0078] AND (AND) / OR (OR) / NOT (NOT) / XOR (XOR) / XNOR (XNOR) / NAND (NAND);

[0079] LogicAND / LogicOR / LogicNOT (all are derived logic gates, standard logic unit implementations defined in specific tool libraries);

[0080] RecudeAND / ReduceOR / ReduceXOR (all are reduction logic gates, which reduce multi-bit vectors to single bits);

[0081] ADD (adder) / SUB (subtractor) / MUL (multiplier) / DIV (divider);

[0082] EQ (equal) / NE (not equal) / GT (greater than) / GE (greater than or equal) / LT (less than) / LE (less than or equal);

[0083] MUX (general multiplexer) / PMUX (priority multiplexer) / SHL (logical left shift) / SHR (logical right shift) / SHIFTX (shift with sign extension).

[0084] DFF (D flip-flop) / LATCH (latch) / ADFF (asynchronous reset D flip-flop).

[0085] For example, there is generally a full adder (FA) in the register transfer level circuit model, but there is no existing full adder unit in the intermediate layer circuit model, at which time the relevant technical personnel need to establish a corresponding mapping relationship, Figure 3 is a schematic diagram of a full adder in the register transfer level model in an embodiment, and correspondingly, the function of the full adder can be realized by combining the three units of AND (AND gate), OR (OR gate) and XOR (XOR gate) in the intermediate layer circuit model, as Figure 4 indicated, Figure 4 which includes two AND gates, two XOR gates and one OR gate. In summary, a mapping relationship can be established for the full adder in the register transfer level circuit model and the structure in Figure 4 in the intermediate layer circuit model, and the full adder in the above register transfer level model is single-bit, and the mapped result in the intermediate layer circuit model is also single-bit. In the figure, interfaces A and B represent two input bits of the full adder, C represents the carry output of the full adder, and Ci represents the carry input of the full adder, which is used to receive the carry signal from the low bit.

[0086] In another example, the register transfer level circuit can have a 2-bit adder, but there is no existing 2-bit adder unit in the intermediate layer circuit model, at which time the 2-bit adder unit can be composed of two full adders (the full adder unit in the intermediate layer circuit model can be composed of the structure in Figure 4 , Figure 5 is a schematic diagram of a 2-bit adder composed of two full adders. In summary, a mapping relationship can be established for the 2-bit adder in the register transfer level circuit model and the structure in Figure 5 in the intermediate layer circuit model, and the 2-bit adder in the above register transfer level circuit model is 2-bit, and the mapped result in the intermediate layer circuit model is also 2-bit, Figure 5In the middle, A[1:0] represents the two-bit binary input of the first addend, where A[1] is the high bit and A[0] is the low bit; B[1:0] represents the two-bit binary input of the second addend, where B[1] is the high bit and B[0] is the low bit; C[2:0] represents the output of the carry signal and the related sum, C[2] represents the highest bit carry output, C[1] represents the intermediate carry, and C[0] represents the lowest bit carry input.

[0087] In summary, the above gives two mapping relationships, in actual application, the mapping relationship can be configured by the related technical personnel according to the actual need.

[0088] Further, in the intermediate layer circuit model, the basic logic unit is provided with a register transfer level attribute, wherein the gate converted from the register transfer level circuit model can carry the "Hdlop=true" attribute, i.e. the above-mentioned register transfer level attribute, which indicates that the basic logic unit comes from the register transfer level circuit model. Further, the basic logic unit can also be provided with a bit width attribute, since there are some gates with multiple bit widths in the register transfer level circuit, for example, a 4-bit AND gate, in the intermediate layer circuit model in this embodiment, it is only converted into one gate device, and an attribute of "bit width=4" is added, i.e. the above-mentioned bit width attribute, which can represent the bit width value of the basic logic unit.

[0089] In one embodiment, the primary circuit model is converted into an intermediate layer circuit model connected by preset basic logic units, comprising:

[0090] When the primary circuit model is a gate level circuit model, each unit in the gate level circuit model is mapped to a basic logic unit in the intermediate layer circuit model; the basic logic unit includes a basic unit of a standard cell library; in some embodiments, each unit in the gate level circuit model corresponds to a basic unit of the standard cell library one-to-one, and each unit in the gate level circuit model can be "translated" (i.e. copied) to a basic logic unit in the intermediate layer circuit model according to the above correspondence, wherein,

[0091] In the intermediate layer circuit model, the basic logic unit is provided with a gate level attribute, and optionally, the basic logic unit can also be provided with a bit width attribute, wherein the gate level attribute is used to represent that the basic logic unit comes from the gate level circuit model, and the bit width value of the basic logic unit from the gate level circuit model is equal to 1.

[0092] Specifically, when the primary circuit model is a gate-level circuit model, each unit in the gate-level circuit model is mapped to a basic logic unit in the intermediate-layer circuit model. Different from the mapping of the register transfer level circuit model, in this embodiment, each unit in the gate-level circuit model can be one-to-one mapped to a basic logic unit in the intermediate-layer circuit model based on a preset standard cell library, where the basic logic unit includes a basic cell in the standard cell library. In summary, when the gate-level circuit model is mapped to the intermediate-layer circuit model, the mapping relationship between the gate and the combinational logic cell in the original gate-level circuit model can be preserved, and the intermediate-layer circuit model similar to the original gate-level circuit model can be established.

[0093] Further, in the intermediate-layer circuit model converted from the gate-level circuit model, the basic logic unit is provided with a gate-level attribute, where the gate-level attribute can be set as "Hdlop=false", and the gate-level attribute is used to represent that the unit comes from the gate-level circuit model. Further, the basic logic unit can also be provided with a bit width attribute, and the bit width of the basic logic unit from the gate-level circuit model is 1, that is, the basic logic unit from the gate-level circuit model is a single bit.

[0094] In one of the embodiments, a simulation algorithm is called based on the intermediate-layer circuit model to perform circuit simulation, and a simulation result is obtained, which includes:

[0095] The switching instruction is obtained through a preset simulation configuration interface;

[0096] In response to the switching instruction, a corresponding static simulation process or a dynamic simulation process is performed.

[0097] Specifically, the present application supports static simulation and dynamic simulation, and a switching instruction can be received through a preset switch (i.e., the simulation configuration interface). In actual application, if the switching instruction is dynamicSimulation=true, it means that dynamic simulation needs to be switched to; if the switching instruction is dynamicSimulation=default, it means that static simulation needs to be switched to. Through this embodiment, dynamic simulation and static simulation modes can be flexibly switched.

[0098] In one of the embodiments, the basic logic unit includes a sequential logic unit; and the corresponding static simulation process includes:

[0099] When the static simulation process is performed based on the intermediate-layer circuit model, a static simulation queue composed of the sequential logic unit in the intermediate-layer circuit model is established;

[0100] A preset target logic unit in the sequential logic unit is set at a preset target position in the static simulation queue, and a static simulation result is obtained based on the static simulation queue.

[0101] Specifically, the embodiment provides a method for static simulation processing. The static simulation refers to analysis based on the logic structure of a circuit and static rules without simulating the change of signals over time. Generally, all primary inputs (PI) in the circuit are put into a static simulation queue, and corresponding events are executed in sequence.

[0102] In the present application, after the static simulation queue is established by the timing logic units in the intermediate circuit model, the preset target logic unit in the timing logic unit is set at the preset target position in the static simulation queue, and then events in the static simulation queue are executed in sequence. The preset target logic unit includes specific units that do not need to perceive the change of clock edges, such as flip-flops. The preset target position is generally the tail position. Further, taking a flip-flop as an example, it is known that the flip-flop outputs the latched signal at a non-trigger edge. However, in static simulation, only the signal reaching the flip-flop is concerned, and the output of the flip-flop is not concerned. Therefore, the output of the flip-flop is generally used in the next round of simulation, and the target logic unit similar to the flip-flop can be set at the tail position (equivalent to the flip-flop as an initial unit in the next round of execution) as an input signal for the static simulation queue, so as to significantly reduce the computational complexity and improve the performance of static simulation.

[0103] In one embodiment, generally, in some scenarios, the clock edge change of the timing logic unit is not needed in the static simulation process. After the static simulation queue is established by the timing logic units in the intermediate circuit model, the method further includes:

[0104] Determining a target logic unit in the timing logic unit that changes the output state based on a specific trigger condition, and setting the output of the target logic unit under the specific trigger condition as an undetermined state.

[0105] Specifically, the target logic unit is a unit that changes the output state based on a specific trigger condition. The specific trigger condition can be a non-trigger moment of a trigger edge. Since the change of the clock edge is not needed in some scenarios, the output of the target logic unit at the non-trigger moment can be set as an undetermined state X. It can be understood that in other embodiments, the specific trigger condition can also be related to the input signal, the clock signal, the reset signal and the enable signal of the target logic unit, for example, the state in which the output of the target logic unit is unstable or the reset signal is activated as the specific trigger condition.

[0106] In summary, since the output of the target logic unit under certain trigger condition is directly set to the indeterminate state X, the uncertain, undefined or non-affecting output of the target logic unit does not need to be processed, thereby effectively reducing redundant calculation in the static simulation process and improving the performance of the static simulation.

[0107] In one of the embodiments, performing the corresponding dynamic true processing includes:

[0108] In the dynamic simulation processing based on the intermediate layer circuit model, an event queue is established based on the output signals in the intermediate layer circuit model, and each event in the event queue is updated based on the output signals of the events in the event queue and in combination with the preset dynamic simulation rule to obtain the dynamic simulation result.

[0109] Specifically, the embodiment provides a dynamic simulation method. In the dynamic simulation, first, an event queue for dynamic simulation is established based on all the output signals in the intermediate layer circuit model, and the output signals are taken as events to be processed.

[0110] Then, each event in the event queue is updated based on the output signals of the events in the event queue and in combination with the preset dynamic simulation rule to obtain the dynamic simulation result, wherein the dynamic simulation rule is preset by the relevant technical personnel according to actual needs.

[0111] In one of the embodiments, the event queue is updated based on the output signals of the events in the event queue and in combination with the preset dynamic simulation rule to obtain the dynamic simulation result, including:

[0112] The updating step: the event simulation is executed based on the default priority in the event queue and is cycled out of the queue, wherein each time an event is dequeued, the output signals generated by the event simulation are traversed to iterate the subordinate events related to the event, and the subordinate events are put into the event queue for updating;

[0113] If it is detected that there is an unprocessed output signal in the event queue, the next round of simulation is performed, and the updating step is repeated until the preset simulation end condition is met to obtain the dynamic simulation result.

[0114] Specifically, the updating step includes that the event simulation is executed based on the default priority in the event queue and is cycled out of the queue, wherein the specific setting of the priority can be set by the relevant technical personnel according to actual needs, such as being set to be sorted according to the event trigger time or the pin priority.

[0115] Whenever an event is dequeued (i.e. an output pin is taken from the head of the queue as the current processing object), the events associated with the lower-level events of the event are traversed, which are the input pins associated with the dequeued event, which can be the driving source or controlled object of the current output pin, etc. The lower-level events of the output pin can be determined at least according to the connection relationship of the circuit and the signal type, which refers to the type of the output pin, for example, the output pin can be a timing logic processing analog flip-flop (FF), or a combinational logic processing analog combinational logic circuit (such as a gate circuit, a multiplexer, etc.).

[0116] For example, the following gives a method for determining the lower-level event: if the input pin has a simulation constraint (such as a user forced assignment or a test vector), the constraint value is directly obtained, and the dynamic calculation is skipped; if the input pin is marked as a loopCutPoint (break point) and enableLoopCut is true, return X (unknown state); if the input pin has no driving pin, check if there is a constant value, if there is a constant value, return the value, otherwise return the undriven signal value; if the input pin has a driving pin, and the driving pin has a constraint, return the constraint value; if the driving pin of the input pin is marked as a break point, return the unknown state (X); if the driving pin of the input pin has been updated, return the value according to the timing logic and / or combinational logic of the driving pin, etc.

[0117] If it is detected that there is an unprocessed output signal in the event queue, the next round of simulation is performed, and the above updating steps are repeated until the preset simulation end condition is met, and the dynamic simulation result is obtained, wherein the simulation end condition can be set by a person skilled in the art according to actual needs, for example, it can be set as a fixed number of cycles (such as 100 clock cycles), or it can be set as a simulation time, etc.

[0118] In summary, through the embodiment, the existing multi-queue algorithm can be simplified to a single-queue algorithm, and dynamic simulation can be completed through an event queue for dynamic simulation, thereby effectively improving the simulation efficiency.

[0119] The embodiment also provides a preferred embodiment of a simulation method of a digital circuit.

[0120] First, the description information of a preset digital circuit is determined, which can only include register transfer level description information, or only include gate level description information, or include part of the register transfer level description and part of the gate level description;

[0121] Based on the description information, a primary circuit model is generated. If the description information is register transfer level description information, the corresponding primary circuit model is a register transfer level circuit model. If the description information is gate level description information, the corresponding primary circuit model is a gate level circuit model. The method for generating the register transfer level circuit model includes parsing the description information through a parser to generate a basic circuit model. The parser can map the rtl code to a default cell type, which can cover all rtl syntax. The method for generating the gate level circuit model includes parsing the gate level description information through a parser to generate a basic circuit model, and generating a mapping between the basic circuit model and a basic cell in a preset standard database to obtain the gate level circuit model.

[0122] Then, the primary circuit model is converted into an intermediate layer circuit model, i.e., the gate level circuit model, the register transfer level circuit model or the mixed circuit model is converted into the intermediate layer circuit model. In the intermediate layer circuit model, each basic logic cell is provided with a corresponding level attribute. The level attribute represents the type of the basic logic cell from the primary circuit model. Further, the basic logic cell can be provided with a bit width attribute. The bit width attribute represents the bit width setting of the basic logic cell. The basic logic cell in the intermediate layer circuit model supports at least 1-bit bit width.

[0123] Based on the intermediate layer circuit model, static simulation or dynamic simulation is performed. A switching instruction indicating whether the static simulation or the dynamic simulation needs to be performed can be obtained through a preset simulator configuration interface, so that the corresponding simulation processing is performed according to the switching instruction.

[0124] It should be understood that, although each step in the flowchart involved in each embodiment as described above is displayed in sequence according to the arrow, these steps are not necessarily executed in sequence according to the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, at least part of the steps in the flowchart involved in each embodiment as described above can include multiple steps or stages, which are not necessarily executed at the same time, but can be executed at different times. The execution sequence of these steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or stages in other steps.

[0125] Based on the same inventive concept, the embodiments of the present application also provide a simulation device for implementing the simulation method as described above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme described in the above method, and therefore the specific limitations in one or more simulation device embodiments provided below can refer to the limitations of the simulation method described above, which will not be described here again.

[0126] In one embodiment, as shown in Figure 6 An emulation device is provided, comprising: a description information acquisition unit 31, a primary circuit model generation unit 32, an intermediate layer circuit model conversion unit 33, and an emulation unit 34, wherein:

[0127] The description information acquisition unit 31 is configured to acquire description information for the same digital circuit, the description information comprising at least one of a register transfer level description and a gate level description;

[0128] The primary circuit model generation unit 32 is configured to generate a primary circuit model based on the description information;

[0129] The intermediate layer circuit model conversion unit 33 is configured to convert the primary circuit model into an intermediate layer circuit model connected by preset basic logic units, the intermediate layer circuit unit comprising the basic logic units, each of the basic logic units being provided with a corresponding model level attribute, the model level attribute being a register transfer level or a gate level;

[0130] The emulation unit 34 is configured to invoke an emulation algorithm based on the intermediate layer circuit model to perform circuit emulation, and obtain an emulation result.

[0131] The above-mentioned modules in the emulation device can be realized by software, hardware, and combinations thereof, in whole or in part. The above-mentioned modules can be embedded in or independent of a processor in a computer device in hardware form, or can be stored in a memory in a computer device in software form, so as to be called and executed by a processor to perform the operations corresponding to the above-mentioned modules.

[0132] In one embodiment, as shown in Figure 7 An emulation system for a digital circuit is provided, comprising a modeling module, an emulation manager, and an emulation queue calculation engine, wherein the emulation manager is connected to the modeling module and the emulation queue calculation engine:

[0133] The modeling module is configured to acquire description information for the same digital circuit, generate a primary circuit model based on the description information, and convert the primary circuit model into an intermediate layer circuit model connected by preset basic logic units. The description information comprises at least one of a register transfer level description and a gate level description. The intermediate layer circuit unit comprises the basic logic units, the basic logic units being single-bit or multi-bit. Each of the basic logic units is provided with a corresponding model level attribute and a bit width attribute, the model level attribute being a register transfer level or a gate level.

[0134] The emulation manager is configured to manage and dispatch the emulation queue calculation engine;

[0135] The emulation queue calculation engine is configured to perform an emulation algorithm based on the intermediate layer circuit model to perform circuit emulation, and obtain an emulation result.

[0136] Specifically, the modeling module is configured to establish a primary circuit model and convert the primary circuit model into an intermediate layer circuit model. The simulation manager is configured to manage a plurality of simulator instances, each of which is an execution unit independently running in the simulation system and having complete simulation capability, and each of which is configured to call a simulation queue calculation engine when simulating each event, and the simulation queue calculation engine is configured to implement event queue-based circuit simulation based on a simulation algorithm.

[0137] In one embodiment, a computer device, which can be a server, has an internal structure diagram as shown in Figure 8 The computer device includes a processor, a memory, and a network interface connected by a system bus. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for running the operating system and the computer program in the non-volatile storage medium. The database of the computer device is configured to store simulation-related data of a digital circuit. The network interface of the computer device is configured to communicate with an external terminal through a network connection. The computer program is executed by the processor to implement a simulation method.

[0138] Those skilled in the art can understand that Figure 8 The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. Specifically, the computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0139] In one embodiment, a computer readable storage medium is provided, which stores a computer program. The computer program is executed by a processor to implement the following steps:

[0140] Obtain description information for the same digital circuit, the description information including at least one of register transfer level description and gate level description;

[0141] Generate a primary circuit model based on the description information;

[0142] Convert the primary circuit model into an intermediate layer circuit model connected by preset basic logic units, the basic logic units being single-bit or multi-bit, each basic logic unit being provided with a corresponding model level attribute and a bit width attribute, the model level attribute being a register transfer level or a gate level;

[0143] Call a simulation algorithm based on the intermediate layer circuit model to perform circuit simulation and obtain a simulation result.

[0144] It should be noted that the user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or authorized by all parties.

[0145] It can be understood by those skilled in the art that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiments. Any reference to memory, database or other medium used in the embodiments provided by the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration but not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The database involved in the embodiments provided by the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided by the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., without being limited thereto.

[0146] The technical features of the above embodiments can be combined in any way. To make the description concise, not all possible combinations of the technical features in the above embodiments are described, but as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present disclosure.

[0147] The above-described embodiments are merely illustrative of several embodiments of the present application, and the description is relatively specific and detailed, but should not be understood as a limitation on the scope of the patent. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the scope of the present application. Therefore, the scope of protection of the present application should be subject to the appended claims.

Claims

1. A simulation method of a digital circuit, characterized by, The method comprises: acquiring description information for a digital circuit, the description information comprising at least one of a register transfer level description and a gate level description; generating a primary circuit model based on the description information; converting the primary circuit model into an intermediate layer circuit model connected by preset basic logic units, each of the basic logic units being provided with a corresponding model level attribute, the model level attribute being a register transfer level or a gate level; calling a simulation algorithm based on the intermediate layer circuit model to perform circuit simulation and obtain a simulation result.

2. The method of claim 1, wherein, The conversion of the primary circuit model into the intermediate layer circuit model connected by the preset basic logic units comprises: when the primary circuit model is a register transfer level circuit model, mapping the primary circuit model into the basic logic units in the intermediate layer circuit model; the basic logic units comprise preset intermediate layer circuit units; wherein in the intermediate layer circuit model, the basic logic units are provided with a register transfer level attribute, wherein the register transfer level attribute is used to represent that the basic logic units come from the register transfer level circuit model.

3. The method of claim 1, wherein, The conversion of the primary circuit model into the intermediate layer circuit model connected by the preset basic logic units comprises: when the primary circuit model is a gate level circuit model, mapping each unit in the gate level circuit model into a basic logic unit in the intermediate layer circuit model; the basic logic units comprise basic units of a standard cell library; wherein in the intermediate layer circuit model, the basic logic units are provided with a gate level attribute, wherein the gate level attribute is used to represent that the basic logic units come from the gate level circuit model.

4. The method of claim 1, wherein, The calling of the simulation algorithm based on the intermediate layer circuit model to perform circuit simulation and obtain a simulation result comprises: acquiring a switching instruction through a preset simulation configuration interface; in response to the switching instruction, performing corresponding static simulation processing or dynamic simulation processing.

5. The method of claim 4, wherein, The basic logic units comprise timing logic units; the performance of the corresponding static simulation processing comprises: when performing static simulation processing based on the intermediate layer circuit model, establishing a static simulation queue composed of timing logic units in the intermediate layer circuit model; setting a preset target logic unit in the timing logic units at a preset target position in the static simulation queue, and obtaining a static simulation result based on the static simulation queue.

6. The method of claim 5, wherein, After the establishment of the static simulation queue composed of the timing logic units in the intermediate layer circuit model, the method further comprises: determining a target logic unit in the timing logic units that changes an output state based on a specific trigger condition, and setting the output of the target logic unit under the specific trigger condition to an undetermined state.

7. The method of claim 4, wherein, The performance of the corresponding dynamic simulation processing comprises: when performing dynamic simulation processing based on the intermediate layer circuit model, establishing an event queue based on output signals in the intermediate layer circuit model, and updating each event in the event queue based on output signals of the events and in combination with a preset dynamic simulation rule to obtain a dynamic simulation result.

8. The method of claim 7, wherein, The event queue is updated based on output signals of each event in the event queue in combination with preset dynamic simulation rules to obtain a dynamic simulation result, including: An updating step: events in the event queue are executed in turn based on a default priority and dequeued in a loop, wherein, each time an event is dequeued, output signals generated by the event simulation are traversed to iterate through lower-level events related to the event, and the lower-level events are put into the event queue for updating; If it is detected that there are unprocessed output signals in the event queue, the next round of simulation is performed, and the updating step is repeated until a preset simulation end condition is met to obtain a dynamic simulation result.

9. A simulation apparatus of a digital circuit, characterized by comprising: The device comprises: A description information acquisition unit configured to acquire description information for a same digital circuit, the description information comprising at least one of register transfer level description and gate level description; A primary circuit model generation unit configured to generate a primary circuit model based on the description information; An intermediate layer circuit model conversion unit configured to convert the primary circuit model into an intermediate layer circuit model connected by preset basic logic units, each of the basic logic units being provided with a corresponding model level attribute, the model level attribute being register transfer level or gate level; A simulation unit configured to perform circuit simulation based on the intermediate layer circuit model by calling a simulation algorithm to obtain a simulation result.

10. A simulation system of a digital circuit, characterized by, The simulation system comprises a modeling module, a simulation manager and a simulation queue calculation engine, wherein the simulation manager is connected to the modeling module and the simulation queue calculation engine respectively: The modeling module is configured to acquire description information for a same digital circuit, generate a primary circuit model based on the description information, and convert the primary circuit model into an intermediate layer circuit model connected by preset basic logic units; the description information comprises at least one of register transfer level description and gate level description, and each of the basic logic units is provided with a corresponding model level attribute, the model level attribute being register transfer level or gate level; The simulation manager is configured to manage and dispatch the simulation queue calculation engine; The simulation queue calculation engine is configured to perform circuit simulation based on the intermediate layer circuit model by calling the simulation algorithm to obtain a simulation result. 11.A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the computer device is configured to perform the method according to any one of claims 1-10. The processor executes the computer program to implement the steps of the method of any one of claims 1 to 8.

12. A storage medium comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to run the computer program to execute the simulation method of the digital circuit of any one of claims 1 to 8.

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