Electronic probe computer

Abstract

The invention relates to an electronic probe computer. The electronic probe computer adopts a three-stage heterogeneous architecture, wherein a control layer realizes the transcoding and data verification of a graph coloring problem through an upper computer debugging system; the optical routing layer realizes high-speed transmission through an optical interface; the probe calculation layer comprises a plurality of probe calculation cards, each card is integrated with n probe units, parallel tasks are dynamically distributed through a bus, and nine types of probe operators including deletion points, rhombus, color changing points, shrinkage points, edge adding, tree type, odd circle and K4 are achieved. And customizing a transmission protocol of probe data frames (including WAKE, COMMAND, CONFIG, MATRIX, TASK) and a data driving control flow, and operating the probe unit by using the transmission protocol of the probe data frames (including WAKE, COMMAND, CONFIG, MATRIX, TASK) and the data driving control flow. The complexity bottleneck of a traditional algorithm is broken through through layered hardware acceleration, operator parallelization design and optimization design of an edge adding and shrinking unit, the system can process multiple types of calculation tasks in parallel on the same hardware platform, and the real-time and diversified requirements of large-scale complex graph calculation are flexibly met.

Description

Technical Field

[0001] This invention relates to an electronic probe computer, belonging to the field of computer science and technology. Background Technology

[0002] Calculation tools are considered one of the main factors driving the development of human civilization, evolving gradually along with its progress. Human development can be divided into five stages according to technological milestones: the Stone Age, the Iron Age, the Steam Age, the Electric Age, and the Information Age. Therefore, calculation tools have undergone a long evolutionary process from simple to complex, appearing successively in the form of knotted ropes (for simple calculations), abacuses, slide rules, mechanical calculators, and electronic calculators, each playing an indispensable role in its historical period.

[0003] A computer is conceptually a general-purpose device based on a computational model, made of specific materials that can be used to implement a particular computational model. For example, today's electronic computers are conceptualized from the Turing Machine (TM), which consists of electronic components. The TM was introduced by Alan Turing to solve the problem of whether a given Diophantine equation with integer coefficients has integer solutions. This problem was one of Hilbert's 23 mathematical problems presented at the International Congress of Mathematicians in 1900. The TM consists of three parts: a finite controller, an infinite magnetic tape, and a read / write head.

[0004] In 1945, John von Neumann established the architecture of the electronic computer using the TM (Transformer-Temperature) model and semiconductors as the implementation material. The following year, the first electronic computer based on the von Neumann architecture was successfully developed. To date, the development of electronic computers has gone through four main stages: vacuum tube computers, transistor computers, integrated circuit computers, and large-scale integrated circuit computers.

[0005] While the phenomenal growth of TM-based computing devices (such as electronic computers) follows Moore's Law, scientists have been searching for new computing models to build even more powerful computers for the past half-century. In 2011, on the 100th anniversary of Turing's birth, he publicly solicited new computing models that surpassed TM. The motivations behind the pursuit of new computing models are twofold: 1) semiconductor manufacturing technology would reach its limits within the next decade, as Kaku predicted in 2012; and 2) due to the limitations of TM, today's electronic computers cannot solve large-scale NP-complete problems.

[0006] At its root, the serial computation mode and one-dimensional data representation of Turing machines severely limit their ability to process complex problems in parallel. Although the academic community has proposed new models such as biomimetic computing, optical computing, quantum computing, and biological computing to break through the bottleneck, most models are still equivalent to Turing machines in terms of computability, only improving efficiency in specific scenarios and failing to fundamentally solve the exponential explosion challenge of NP-complete problems.

[0007] In 2016, Professor Xu Jin and his team proposed a low-level fully parallel computing model called the "Probe Machine". This model theoretically surpasses the traditional Turing machine model for the first time, aiming to solve NP-complete problems that current electronic computers cannot efficiently process, such as the Hamiltonian problem and the vertex coloring problem of graphs.

[0008] Based on this, the present invention adopts a three-level heterogeneous architecture and nine types of probe operators to specifically implement the probe computer, further optimizes the "probe machine", and customizes the probe data frame and probe transmission protocol, providing an efficient solution platform for complex optimization problems, which is applicable to graph coloring, combinatorial optimization and cryptography. Summary of the Invention

[0009] Solving NP-complete problems is one of the major challenges facing society today, requiring breakthroughs in the limitations of the Turing model. The probe computer developed in this invention, taking the graph coloring problem with a chromatic number of 3 as an example, is described below:

[0010] 1. An electronic probe computer, comprising a three-layer heterogeneous architecture, nine probe operators, a probe data frame format, and a transmission protocol.

[0011] 2. An electronic probe computer, with the following overall architecture: Figure 1 As shown, a three-tier heterogeneous architecture is adopted, including:

[0012] The control layer, primarily composed of a high-performance host computer and a monitor, is also commonly referred to as the "host computer." It includes a host computer debugging system and a host computer display system. The host computer's functions include data transcoding, format conversion, and distribution. The host computer debugging system comprises a transcoding system, data verification, and data distribution. The transcoding system converts the problem to be solved into a graph coloring problem and then converts the solution of the graph coloring problem back to the solution of the original problem. The host computer display system showcases applications such as graph coloring, trajectory planning, and large number factorization.

[0013] The optical routing layer connects the control layer and the probe computing layer, enabling high-speed data transmission through an optical interface. The optical routing layer mainly consists of several optical routing cards, each of which can communicate with several probe computing cards in the probe computing layer, greatly satisfying the probe computers' requirements for high-performance data transmission.

[0014] The probe computing layer comprises multiple probe computing cards operating in parallel, each card integrating n probe units. These probe computing cards implement the following nine probe operators via FPGA: deletion probe operator. Rhombus probe operator Color-changing point probe operator Shrinking probe operator Edge probe operator Tree probe operator Odd-cycle probe operator , probe operator K4 probe operator It is used to solve graph coloring problems.

[0015] 3. Optical routing layer architecture as follows Figure 2 As shown, the optical routing layer mainly consists of several optical routing cards. The advantage of optical routing cards compared to other FPGA cards lies in the larger number of optical port resources they provide. One optical routing card can provide five QSFP+ optical interfaces, meaning that one optical routing card can communicate with five probe computing cards in the probe computing layer. This greatly satisfies the high-performance data transmission requirements of electronic probe computers. In addition, each optical routing card also provides a network interface card, enabling it to transmit UDP protocol data with the control layer.

[0016] 4. Probe computing layer architecture as follows Figure 3 As shown, this includes multiple probe computing cards operating in parallel. Each probe computing card comprises a data distribution master device and n probe operator slave devices, which communicate via an AXI bus. In addition, a memory access module (DMA) and random access memory (RAM) are mounted on the AXI bus to implement memory access functions. A single probe computing card communicates with other probe computing cards via an AXI adapter bridge and an optical port driver module. The functions implemented by the probe computing cards include: parallel computation of probe operators through FPGA hardware acceleration; and dynamic allocation of probe operator processing tasks based on the adjacency matrix.

[0017] 5. The probe computation layer contains multiple probe operators. A general diagram of the probe operators is shown below. Figure 4 As shown. Nine probe operators were used in the specific implementation, including:

[0018] Deletion probe operator In parallel, all vertices with degrees of 0, 1, and 2 are deleted from the graph to simplify the graph structure, and the connection relationships of the remaining vertices are dynamically updated through the adjacency matrix.

[0019] Rhombus probe operator The algorithm detects rhombus subgraphs (quadrilaterals containing only one diagonal), shrinks the unconnected diagonals of the rhombuses, and processes all non-intersecting rhombus subgraphs in parallel.

[0020] Color-changing point probe operator The color of the pseudo-edge endpoints can be directly changed to help resolve conflicts.

[0021] Shrink probe operator The non-adjacent vertex pairs are shrunk to inherit the connection relationship.

[0022] Edge probe operator Add edges between non-adjacent vertices to construct a rhombus or K4 structure.

[0023] Tree probe operator The false edges are eliminated through the following process: an initial 3-coloring scheme is randomly generated, the false edges are located and their corresponding 2-color trees are determined, the Kempe transformation is performed along the 2-color trees to swap colors, and the coloring scheme is iteratively updated until all false edges are eliminated.

[0024] Odd Cycle Probe Operator False edges on the 23-odd cycle are eliminated by color substitution and Kempe.

[0025] probe operator It is specifically designed for processing sparse graphs.

[0026] K4 probe operator Regardless of the stage, if K4 exists in the graph, it means that the graph has no solution.

[0027] 6. The probe protocol is a one-way control protocol used to drive the probe unit, including the following data: probe unit wake-up data (WAKE), probe unit command data (COMMAND), probe unit setting data (CONFIG), matrix data (MATRIX), and task data (TASK). The designed probe data frame format is as follows: Figure 5 As shown.

[0028] The probe unit wake-up data (WAKE) consists of a 128-bit all-1 binary sequence, used to trigger the probe unit to enter the command receiving state. This data is considered successfully triggered after being sent and successfully received n times. Furthermore, when the probe unit is operating, it will also re-enter the command receiving state if the triggering condition is met. The value of n is derived from the following formula:

[0029]

[0030] Where n is the number of times the probe unit sends wake-up data (WAKE), and M is the maximum matrix size that the probe unit can process;

[0031] The probe unit command data (COMMAND) is a 128-bit data set used to indicate the next operation to be performed by the probe unit. Its field assignments are as follows:

[0032] Bits 128 to 97: Identifier field for command data. The probe unit will process the data according to the command data only when this field is the same as the set identifier field. This field can be user-defined and the default value is 0xFFFF.

[0033] Bits 96 to 65: The address field of the command data, indicating the specific hardware on which the command applies. If a piece of hardware receives a command that is not valid for that hardware, it will not execute the command. However, if that hardware has slave devices, it will send the command to all valid slave devices. The specific hardware and its corresponding address can be defined by the user. By default, the address 0x0001 cannot be customized; it represents that the command applies to all hardware that passes through it.

[0034] Bits 64 to 33: The specific command field of the command data. This field indicates the specific operation that the hardware should perform next. The specific value of this field and its corresponding command include:

[0035] 0x0001: Perform a reset operation;

[0036] 0x0002: Enter the receive probe unit setting data (CONFIG) process and start the normal calculation process;

[0037] The probe unit configuration data (CONFIG) is 128 bits, and its field assignments are as follows:

[0038] Bits 112 through 97: Indicate the number of points in the coloring problem;

[0039] Bits 63 to 32: Identifier matrix ID;

[0040] The matrix data (MATRIX) is 128 bits used to store the elements of a single row of the adjacency matrix. Elements are encoded in 1-bit form, from least significant bit to most significant bit. If the order of the adjacency matrix is ​​less than 128, the most significant bits are padded with 0s until the matrix reaches 128 bits. If the order of the adjacency matrix is ​​greater than 128, it is stored contiguously using multiple sets of 128-bit data.

[0041] The task data (TASK) is 128 bits long and is used to specify the adjacency matrix region to be verified. Its field assignments are as follows:

[0042] 95th to 81st positions: Identifier of point 1 to be verified;

[0043] Bits 80 to 64: Identifier of point 2 to be verified;

[0044] 63rd to 32nd positions: The matrix ID to which the point pair to be verified belongs;

[0045] The result data is 128 bits long, and its field assignments are as follows:

[0046] Bits 95 to 81: Identifier of verified point 1;

[0047] Bits 80 to 64: Identifier of verified point 2;

[0048] Bits 31 to 0: Encoding of the probe operator processing result, specifically including:

[0049] 0x0000: No operation performed; current state cannot be determined.

[0050] 0x0001: Points 1 and 2 can execute the edge probe operator;

[0051] 0x0002: Points 1 and 2 can execute the shrinking probe operator;

[0052] 0x0003: An empty graph is generated after the edge probe operator is executed at points 1 and 2;

[0053] 0x0004: An empty graph is generated after the point shrinking probe operator is executed at points 1 and 2;

[0054] 0x0005: Error, the current image is a four-color image, and probe operation cannot be performed.

[0055] Based on the aforementioned probe data frame format, this invention further designs a corresponding transmission protocol. First, the probe unit is triggered to enter the command receiving state by sending n all-F commands via the WAKE command. Then, the COMMAND command stage begins. When bits 64 to 33 of this command are 0x0001, the system performs a reset operation, then returns to the WAKE command to resend the data; if the field is 0x0002, the system enters the receive probe unit setting data (CONFIG) process, followed by the MATRIX and TASK command processes in sequence.

[0056] 7. The electronic probe computer contains multiple probe operators. When solving graph problems, the multiple probe operators operate in parallel. The specific workflow is as follows: Figure 6 As shown:

[0057] S1 Upper computer preprocessing: Step S101 performs rhombus reduction on the input image G and deletes 0, 1, and 2 degree points to obtain a new preprocessed image G; Step S102 determines whether the input image G in step S4 is a sparse image. If so, selects the pixel a1 with the smallest degree, performs point reduction on any two pixels in its neighborhood, and returns to step S101; if not, performs batch update and returns to step S101.

[0058] S2 FPGA lower-level machine calculation: Write the matrix data and point pair data of the new graph G obtained in step S101 into the main storage, backup storage and task FIFO respectively. The FPGA determines the current state of the pixel based on the matrix data and point pair data. The current state of the pixel is one of unknown (0), edge can be added (1), point can be shrunk (2), empty graph after adding edge (3) or empty graph after shrunk (4), and returns the judgment result to the upper-level machine.

[0059] S3 Four-color determination: Based on the determination result returned by step S2, determine whether four-coloring has been calculated. If not, continue to step S4. If yes, report to the host computer.

[0060] S4 Empty graph determination: If an empty graph is calculated, continue to step S5; otherwise, jump to step S102.

[0061] S5. Upper Computer Image Update and Coloring: Based on all the judgment results in step S4, update the image and determine whether to add edges and shrink points. If yes, add edges to pixels that can be added and shrink points to pixels that can be shrunken in sequence to generate the updated image G, and output the new image to the upper computer, repeating steps S1-S5. If no, color the image according to the original image and the order in which points disappear, and the process ends. Attached Figure Description

[0062] Figure 1 This is a diagram of a three-tier heterogeneous architecture for a probe computer.

[0063] Figure 2 This is a diagram of the optical routing layer architecture;

[0064] Figure 3 This is a diagram of the probe computing layer architecture;

[0065] Figure 4 A schematic diagram of the nine probe operators;

[0066] Figure 5 Diagram of probe data frame format;

[0067] Figure 6 A flowchart of the probe computer's workflow;

[0068] Figure 7 This is a pseudocode diagram of the probe operator; Detailed Implementation

[0069] The application background of this embodiment is to solve the problem of finding the optimal solution for graph coloring.

[0070] The electronic probe computer consists of four parts: a conversion system, an input system, a calculation system, and an output system. The conversion system converts the problem to be solved into a graph coloring problem, and vice versa. The input system takes the graph coloring problem obtained from the conversion system and inputs it into the calculation system, which then distributes the task to the various probe calculation cards within the calculation system. The calculation system calculates a color for the graph to be solved. The output system first outputs the solution to the graph coloring problem to the conversion system, which then converts it into a solution to the problem to be solved.

[0071] The electronic probe computer implements nine probe operators, which enable efficient graph computation.

[0072] Tree probe operator This is an important probe operator used in the electronic probe computer for processing 3-color images. Its core idea is to eliminate false edges through the Kempe transform (K-transform), thereby finding an effective 3-coloring scheme. The basic steps include random coloring, false edge detection, K-transform, and iterative processing.

[0073] 1. Random Coloring: First, generate a random 3-coloring scheme for the given 3-color graph. This coloring scheme may contain pseudo-edges, where adjacent vertices are assigned the same color.

[0074] 2. Detecting false edges: If false edges exist in the current coloring scheme, and one endpoint of the false edge is located on a 2-color tree, the false edge can be eliminated by K-transformation.

[0075] 3. K-Transformation: K-transformation is a color-swapping technique that eliminates false edges by swapping colors along a 2-color tree. Specifically, assuming one endpoint of a false edge is located on a 12-tree, the false edge can be eliminated by swapping colors 1 and 2.

[0076] 4. Iterative processing: If pseudo-edges still exist after the K-transformation, continue to apply the tree probe operator until all pseudo-edges are eliminated, resulting in an effective 3-coloring scheme.

[0077] This algorithm initializes a random 3-coloring scheme and then iteratively detects and eliminates false edges (edges where adjacent vertices are assigned the same color) in the graph, ultimately obtaining an effective 3-coloring scheme. The algorithm primarily utilizes the structure of a 2-color tree and the K-transform to adjust vertex colors to eliminate color conflicts. The advantage of the tree probe operator lies in its parallelism, allowing it to process multiple false edges simultaneously, thus accelerating the solution process. The pseudocode description of this operator is as follows: Figure 7 .

[0078] Odd Cycle Probe Operator This is a probe operator used in the electronic probe computer to process odd-cycle structures in 3-color graphs. An odd cycle is a loop in a graph containing an odd number of vertices; the presence of odd cycles can complicate the 3-coloring problem. The main basic steps of the odd-cycle probe operator are as follows:

[0079] 1. Random Coloring: First, generate a random 3-coloring scheme for the given 3-color image. This coloring scheme may contain false edges, especially those located on odd cycles.

[0080] 2. Detecting odd cycles: If there are false edges in the current coloring scheme, and the false edge is located on a 23-odd cycle, the false edge can be eliminated by the odd cycle probe operator.

[0081] 3. Color Replacement: Select a vertex on the odd cycle that lies on both the inside and outside of the odd cycle in a 12-tree. Replace the color of this vertex with color 1 using a K-transform, and then perform a K-transform along both trees to eliminate false edges.

[0082] 4. Iterative processing: If pseudo-edges still exist after processing with the odd-cycle probe operator, continue to apply the operator until all pseudo-edges are eliminated, resulting in an effective 3-coloring scheme.

[0083] The advantage of the odd-cycle probe operator lies in its ability to effectively handle complex odd-cycle structures, especially in sparse graphs, where it can significantly improve solution efficiency. The odd-cycle probe operator begins by checking for pseudo-edges in graph G. Pseudo-edges are edges connecting vertices of the same color; their presence indicates that the current 3-coloring scheme is invalid. Then, for each pseudo-edge, if it lies on an odd-length 23-odd cycle with alternating colors of 2 and 3, a vertex w within the 12-tree (with alternating colors of 1 and 2) inside or outside the cycle is selected. The color of w is set to 1 using a K-transform, and then a K-transform is performed along the relevant 12-tree to eliminate the pseudo-edge, thus updating the coloring scheme of graph G. This process is repeated until no more pseudo-edges remain in graph G, finally outputting a valid 3-coloring scheme. The pseudocode description of this operator is as follows: Figure 7 .

[0084] Color-changing point probe operator This is a simple and effective probe operator used in the electronic probe computer to process pseudo-edges in sparse graphs. Its core idea is to eliminate pseudo-edges by directly changing the color of their endpoints. The specific steps are as follows:

[0085] 1. Random Coloring: First, generate a random 3-coloring scheme for the given 3-color graph. This coloring scheme may contain pseudo-edges, especially pseudo-edges located in sparse graphs.

[0086] 2. Detecting false edges: If there are 23 false edges in the current coloring scheme, they can be eliminated by using the color-changing point probe operator.

[0087] 3. Color Replacement: Select one endpoint of the pseudo-edge and directly replace its color with color 1. Then, depending on the specific situation, apply the tree probe operator or the odd cycle probe operator to further eliminate the pseudo-edge.

[0088] 4. Iterative processing: If pseudo-edges still exist after processing by the color-changing point probe operator, the operator is applied again until all pseudo-edges are eliminated, resulting in an effective 3-coloring scheme.

[0089] The color-changing vertex probe operator first randomly assigns a color to each vertex of graph G, constructing an initial 3-coloring scheme. Then, it checks graph G; if a false edge connecting vertices of the same color is found, the current scheme is invalid. For each false edge, if it is a 2^3 false edge formed by endpoints of colors 2 and 3, it randomly selects either endpoint u or v and sets the color of the selected endpoint to 1. Then, depending on the actual situation, it flexibly uses a tree probe operator or an odd-cycle probe operator to further eliminate false edges. After completing the above operations, it updates the coloring scheme of graph G. This process is repeated until no false edges exist in graph G, at which point the valid 3-coloring scheme of graph G can be output. The advantage of the color-changing vertex probe operator lies in its simplicity and efficiency, especially in sparse graphs, where it can quickly eliminate false edges, thus accelerating the solution speed. The pseudocode description of this operator is as follows: Figure 7 .

[0090] δ operator This is an operator designed to handle sparse graphs, where a sparse graph refers to a graph with many vertices but few edges. The delta operator handles such sparse graphs by first finding the vertex with the minimum degree in the graph. If... Figure 4If all the points shown are minimum-degree points (all with a degree of 4), then directly shrink the two non-adjacent points; otherwise, shrink any two points connected to the minimum-degree points. This effectively handles situations where operations are not possible with sparse graphs.

[0091] Shrink probe operator It inherits the connection relationships between any non-adjacent pairs of points. In other words, it inherits all the connection relationships of one point to another point and then deletes that point, simplifying the original topology. For example... Figure 4 The diagram shows how to shrink point 3 to point 1. The adjacency matrix represents the connections between points; for example, a 1 in row 0 and column 1 indicates a connection between point 0 and point 1, and vice versa. Shrinking points 1 and 3 from their original structure first requires extracting the corresponding columns of points 1 and 3, performing a bitwise OR operation, and then assigning the resulting columns to the rows and columns of point 1. This is equivalent to inheriting the connection relationships of point 3 to point 1. Then, all the connection relationships of point 3 are deleted, meaning the rows and columns of point 3 are set to zero. The final result is the shrunken graph.

[0092] Edge probe operator It allows you to connect specified pairs of unconnected points. For example... Figure 4 The diagram shows the addition of edges to points 0 and 2. Adding edges does not affect the final coloring of the graph. The purpose of adding edges is to construct a rhombus. Here, a rhombus does not refer to a mathematical rhombus, but rather a quadrilateral formed by connecting two diagonals. If both diagonals of the quadrilateral are connected, the graph structure is called a K4 structure. After adding edges to points 0 and 2 in the original structure, the resulting 0-1-2-3 is a rhombus.

[0093] Deletion probe operator After each graph update and the generation of a new graph, first- and second-degree nodes are deleted. These nodes do not affect the coloring of their neighbors in a ternarily colored graph, thus simplifying the graph through deletion. The process is as follows: Figure 4 As shown.

[0094] Rhombus probe operator This step, performed before simplifying the graph by shrinking the points, checks for pairs of points suitable for the shrinking operation. As mentioned in the edge probe operator, the rhombus referred to here is not a mathematical rhombus, but rather a quadrilateral connected by only one diagonal. The purpose of finding the rhombus is to shrink its unconnected diagonals for the next step. For example... Figure 4 As shown, taking finding a rhombus with sides 0-2 as an example, we take the columns corresponding to points 0 and 2 and perform a bitwise AND operation. The resulting vector represents the connection relationship with points 0 and 2. This connection relationship can be used to determine whether a rhombus has been found.

[0095] K4 probe operator Regardless of the stage, the presence of K4 in the graph indicates that the graph has no solution. Based on the above diamond-shaped search, if points 1 and 3 are found to be connected, then 0-1-2-3 forms a K4 structure. Finding K4 indicates that the graph has no solution. In this case, simply iterate through the next pair of points. The process is as follows... Figure 4 As shown.

[0096] The probe protocol is a data-driven control flow used to drive the operation of the probe unit. Its data includes the following types: probe unit wake-up data (WAKE), probe unit command data (COMMAND), probe unit configuration data (CONFIG), matrix data (MATRIX), and task data (TASK). The designed probe data frame format is as follows: Figure 5 As shown.

[0097] The probe unit wake-up data (WAKE) consists of a 128-bit all-1 binary sequence, used to trigger the probe unit to enter the command receiving state. This data is considered successfully triggered after being sent and successfully received n times. Furthermore, when the probe unit is operating, it will also re-enter the command receiving state if the triggering condition is met. The value of n is derived from the following formula:

[0098]

[0099] Where n is the number of times the probe unit sends wake-up data (WAKE), and M is the maximum matrix size that the probe unit can process;

[0100] The probe unit command data (COMMAND) is a 128-bit data set used to indicate the next operation to be performed by the probe unit. Its field assignments are as follows:

[0101] Bits 128 to 97: Identifier field for command data. The probe unit will process the data according to the command data only when this field is the same as the set identifier field. This field can be user-defined and the default value is 0xFFFF.

[0102] Bits 96 to 65: The address field of the command data, indicating the specific hardware on which the command applies. If a piece of hardware receives a command that is not valid for that hardware, it will not execute the command. However, if that hardware has slave devices, it will send the command to all valid slave devices. The specific hardware and its corresponding address can be defined by the user. By default, the address 0x0001 cannot be customized; it represents that the command applies to all hardware that passes through it.

[0103] Bits 64 to 33: The specific command field of the command data. This field indicates the specific operation that the hardware should perform next. The specific value of this field and its corresponding command include:

[0104] 0x0001: Perform a reset operation;

[0105] 0x0002: Enter the receive probe unit setting data (CONFIG) process and start the normal calculation process;

[0106] The probe unit configuration data (CONFIG) is 128 bits, and its field assignments are as follows:

[0107] Bits 112 through 97: Indicate the number of points in the coloring problem;

[0108] Bits 63 to 32: Identifier matrix ID;

[0109] The matrix data (MATRIX) is 128 bits used to store the elements of a single row of the adjacency matrix. Elements are encoded in 1-bit form, from least significant bit to most significant bit. If the order of the adjacency matrix is ​​less than 128, the most significant bits are padded with 0s until the matrix reaches 128 bits. If the order of the adjacency matrix is ​​greater than 128, it is stored contiguously using multiple sets of 128-bit data.

[0110] The task data (TASK) is 128 bits long and is used to specify the adjacency matrix region to be verified. Its field assignments are as follows:

[0111] 95th to 81st positions: Identifier of point 1 to be verified;

[0112] Bits 80 to 64: Identifier of point 2 to be verified;

[0113] 63rd to 32nd positions: The matrix ID to which the point pair to be verified belongs;

[0114] The result data is 128 bits long, and its field assignments are as follows:

[0115] Bits 95 to 81: Identifier of verified point 1;

[0116] Bits 80 to 64: Identifier of verified point 2;

[0117] Bits 31 to 0: Encoding of the probe operator processing result, specifically including:

[0118] 0x0000: No operation performed; current state cannot be determined.

[0119] 0x0001: Points 1 and 2 can execute the edge probe operator;

[0120] 0x0002: Points 1 and 2 can execute the shrinking probe operator;

[0121] 0x0003: An empty graph is generated after the edge probe operator is executed at points 1 and 2;

[0122] 0x0004: An empty graph is generated after the point shrinking probe operator is executed at points 1 and 2;

[0123] 0x0005: Error, the current image is a four-color image, and probe operation cannot be performed.

[0124] Based on the aforementioned probe data frame format, this invention further designs a corresponding transmission protocol. Taking an adjacency matrix width of 2048 bits as an example: First, a 128-bit all-F instruction is sent in 16 separate WAKE commands to trigger the probe unit to enter the command receiving state. Then, the COMMAND instruction stage begins. When bits 64 to 33 of this instruction are 0x0001, the system performs a reset operation, then returns to the WAKE instruction and retransmits the data; if the field is 0x0002, the system enters the receive probe unit setting data (CONFIG) process, followed by the MATRIX and TASK instruction processes in sequence.

[0125] The electronic probe computer adopts a three-level heterogeneous architecture, such as... Figure 1 As shown, the system consists of a control layer, an optical routing layer, and a probe computation layer. The control layer, also known as the "host computer," mainly comprises a high-performance host (9950X CPU) and a display. The host computer's function is to encode, convert, and distribute data. The specific steps are as follows: First, the host computer transforms the actual problem into a computational graph model using a encoding system; then, it converts different computational graph data into the corresponding data frame format according to the designed probe data frame format; finally, it sends the data via UDP protocol through the RJ45 interface to the optical routing layer of the 12 optical routing cards. In addition, the control layer also uses soft probe operators to identify and perform calculations on the computation results fed back from the optical routing layer.

[0126] The optical routing layer mainly consists of several optical routing cards, such as Figure 2 As shown. Since the data sent from the host computer is in UDP protocol, the optical routing layer first needs to connect an RJ45 interface module. This module is specifically designed to receive UDP protocol network interface data. Because this design uses the AXI-STREAM bus for data transmission, a UDP-to-AXI-STREAM protocol adapter bridge is required. The purpose is to convert the externally input UDP protocol network interface data into AXI-STREAM protocol data, and to convert the internally calculated AXI-STREAM protocol data back into UDP protocol data before transmitting it back to the host computer.

[0127] The data distribution module is used to distribute matrix data and task data separately. According to the probe transmission protocol described above, after the wake-up data is received, there is an indication data entry. The data distribution module can identify this indication data to determine how many matrix data entries and how many task data entries are contained within it. Based on the obtained information, it reads and sends the data. The data routing module can aggregate or transmit the received data in a many-to-one or one-to-many manner, playing a data routing and distribution role in the overall optical routing layer. The receive / transmit buffer module is used to buffer data to prevent data loss during transmission due to differences in processing latency between modules.

[0128] An optical routing card in the optical routing layer provides five optical module interfaces, requiring five optical interface modules internally to communicate with the physical optical interfaces. The data flow in the optical routing layer is shown by the arrows in the diagram. First, the host computer in the control layer transmits data to the RJ45 module via the network port, and then the data format is converted by the UDP-AXIS adapter bridge module. The converted data is then buffered and identified and distributed by the data distribution module. Finally, the distributed data is transmitted from the optical communication module to the probe computing layer. Conversely, data received from the probe computing layer by the optical communication module is transmitted to the host computer in the opposite direction; this will not be elaborated further.

[0129] The probe computing layer consists of several probe computing cards, such as... Figure 3 As shown in the diagram, probe computing cards, with their superior hardware performance and ample programmable resources, are widely used as massively parallel computing accelerators in heterogeneous computing scenarios. The probe computing layer in this invention relies on the high parallelism, high performance, and low power consumption characteristics of probe computing cards, implementing five types of frequently invoked hard probe operators within the probe computing card. The data flow of the probe computing layer can be clearly seen in the diagram. First, data from the optical routing layer enters through the optical port of the probe computing layer. After passing through a first-level cache, the incoming data is distributed by the data distribution module. Since the resources of each probe computing card in the probe computing layer are limited, we configured 16 probe units in each card during the design. This design not only meets the massively parallel computing requirements of the electronic probe computer but also maximizes the utilization of the probe computing card's internal resources. The calculated data is aggregated by the data routing module and then transmitted back to the optical routing layer, and finally to the host computer of the control layer.

[0130] Finally, to make the overall process visible, we also equipped each of the four racks with an OLED touchscreen so that operators could monitor the computation progress of the graph coloring problem in real time.

[0131] The overall workflow of the probe computer is as follows: Figure 6 As shown:

[0132] S1 Upper computer preprocessing: Step S101 performs rhombus reduction on the input image G and deletes 0, 1, and 2 degree points to obtain a new preprocessed image G; Step S102 determines whether the input image G in step S4 is a sparse image. If so, selects the pixel a1 with the smallest degree, performs point reduction on any two pixels in its neighborhood, and returns to step S101; if not, performs batch update and returns to step S101.

[0133] S2 FPGA lower-level machine calculation: Write the matrix data and point pair data of the new graph G obtained in step S101 into the main storage (Main_bram), backup storage (bak_bram) and task FIFO (Task_fifo) respectively. The FPGA determines the current state of the pixel based on the matrix data and point pair data, which is one of the following: unknown (0), edge can be added (1), point can be shrunk (2), empty graph after adding edge (3) or empty graph after shrunk (4), and returns the judgment result to the upper-level machine.

[0134] S3 Four-color determination: Based on the determination result returned by step S2, determine whether four-coloring has been calculated. If not, continue to step S4. If yes, report to the host computer.

[0135] S4 Empty graph determination: If an empty graph is calculated, continue to step S5; otherwise, jump to step S102.

[0136] S5. Upper Computer Image Update and Coloring: Based on all the judgment results in step S4, update the image and determine whether to add edges and shrink points. If yes, add edges to pixels that can be added and shrink points to pixels that can be shrunken in sequence to generate the updated image G, and output the new image to the upper computer, repeating steps S1-S5. If no, color the image according to the original image and the order in which points disappear, and the process ends.

[0137] The host computer first obtains the problem to be solved through the input unit, and then runs the transcoding system to transform the target problem into a 3-coloring graph problem. Next, it organizes the graph data of the problem and distributes it to the probe computation layer. After the probe computation layer completes the solution to the graph problem, the host computer receives the solution and, based on the transcoding process, reverses the process to reconstruct the solution to the original problem. Finally, it displays the execution results through the output unit.

[0138] After the host computer finishes preprocessing, it transmits the data to the slave computer for calculation. The slave computer is in an idle state by default and will only be activated when it detects valid data input. At this point, it enters the data receiving state and stores the two target points to be verified, the adjacency matrix, and other necessary data into the main memory. After data reception is complete, the slave computer copies the data from the main memory to the secondary memory and initializes other associated registers. Then, it branches based on whether a hypothetical point shrinking operation has been performed: if not, it enters the point shrinking test process and merges the two points to be verified; if it has been performed, it enters the edge addition test process and adds a virtual connection between the two points.

[0139] In point shrinking or edge adding operations, the initial processing must target the original two points to be verified. Subsequent operations are performed based on the marked points in the record table. After completing the basic operations, the module enters the common-edge triangle search state: traversing the adjacency matrix to find a third point that connects both target points. If at least two such points are found, a K4 structure detection is triggered; otherwise, the search continues or the module enters the low-degree point cleanup state, deleting nodes with a connection number less than or equal to 2. After cleaning up low-degree nodes, if the adjacency matrix is ​​completely cleared, the result is considered valid; if there is still residual data, the module returns to the copy state for cyclic processing. Ultimately, six types of conclusions may be generated, including determining that a K4 or rhombus has been found, confirming the need for four-coloring, or marking that the current operation cannot reach a conclusion.

[0140] After all processes are completed, the module enters a waiting state and caches the calculation results. When the external FIFO buffer sends a ready signal, the result data is sent to the FIFO for subsequent communication. After completion, it automatically resets to an idle state to wait for new tasks. The entire process is controlled by a state machine, realizing the automated processing of graph structure analysis and coloring problems. The lower-level machine processing is now complete.

[0141] After processing the data, the lower-level machine will send the results back to the upper-level machine. The upper-level machine will then update the graph based on the results from the lower-level machine. Before updating, it needs to determine whether to add edges or shrink points. If not, it will color the graph according to the order in which the points disappeared in the original graph; otherwise, it will add edges or shrink points to obtain a new graph, which will then be sent to the lower-level machine for further calculation.

Claims

1. An electronic probe computer, characterized in that, It includes a three-layer heterogeneous architecture, nine probe operators, probe data frame format, and transmission protocol. The three-layer heterogeneous architecture includes a control layer, an optical routing layer, and a probe computing layer; The nine probe operators include the deletion probe operator. Rhombus probe operator Color-changing point probe operator Shrinking probe operator Edge probe operator Tree probe operator Odd-cycle probe operator , probe operator K4 probe operator ; The probe data frame includes probe unit wake-up data, probe unit command data, probe unit setting data, matrix data, and task data; The transmission protocol is a data-driven control flow used to drive the operation of the probe unit.

2. The electronic probe computer according to claim 1, characterized in that, The three-layer heterogeneous architecture includes: The control layer comprises a host computer debugging system and a host computer display system. The host computer debugging system includes a conversion system, data verification, and data distribution. The conversion system converts the problem to be solved into a graph coloring problem and then converts the solution of the graph coloring problem back into the solution of the original problem. The host computer display system demonstrates applications such as graph coloring, trajectory planning, and large number factorization. The optical routing layer connects the control layer and the probe computing layer, enabling high-speed data transmission through an optical interface. The probe computing layer comprises multiple probe computing cards operating in parallel, each integrating n probe units. These probe computing cards implement the following nine probe operators via FPGA: deletion probe operator. Rhombus probe operator Color-changing point probe operator Shrinking probe operator Edge probe operator Tree probe operator Odd-cycle probe operator , probe operator K4 probe operator It is used to solve graph coloring problems.

3. The electronic probe computer according to claim 1, characterized in that, The optical routing layer architecture includes: The network communication interface module is used to receive external protocol data and perform preliminary verification. The adapter bridge module converts protocol data into a standardized data format adapted to the internal bus and reverses the calculation results into a protocol to be transmitted back to the host computer. The data distribution module dynamically allocates data to designated processing units based on the target identifier field in the protocol. The receive / transmit buffer module is used to buffer data to avoid data loss due to transmission delay; The optical interface module provides n optical communication interfaces to enable optical physical link interconnection between the optical routing card and the probe computing layer; The data flow of the optical routing card is as follows: the host computer data is input through the network communication interface module, converted into probe protocol data through the adapter bridge module, cached, identified and distributed to the optical interface module by the data distribution module, and finally transmitted to the probe computing layer through the optical link; the reverse data is transmitted back along the opposite path.

4. The electronic probe computer according to claim 1, characterized in that, The probe computing card includes: The system consists of one data distribution master device and n probe operator slave devices, which communicate via a bus. In addition, the bus is equipped with a Direct Memory Access (DMA) module and Random Access Memory (RAM) for memory access. Individual probe computing cards communicate with other probe computing cards via an adapter bridge and an optical port driver module. The probe computing card's functions include: parallel computation of probe operators through FPGA hardware acceleration; and dynamic allocation of probe operator processing tasks based on the adjacency matrix.

5. The electronic probe computer according to claim 1, characterized in that, The functions of the nine probe operators include: Deletion probe operator In parallel, all vertices with degrees of 0, 1, and 2 are deleted from the graph to simplify the graph structure, and the connection relationships of the remaining vertices are dynamically updated through the adjacency matrix. Rhombus probe operator The algorithm detects rhombus subgraphs (quadrilaterals containing only one diagonal), shrinks the unconnected diagonals of the rhombuses, and processes all non-intersecting rhombus subgraphs in parallel. Color-changing point probe operator The color of the pseudo-edge endpoints can be directly changed to help resolve conflicts. Shrink probe operator The non-adjacent vertex pairs are shrunk to inherit the connection relationship. Edge probe operator Add edges between non-adjacent vertices to construct a rhombus or K4 structure. Tree probe operator The false edges are eliminated through the following process: an initial 3-coloring scheme is randomly generated, the false edges are located and their corresponding 2-color trees are determined, the Kempe transformation is performed along the 2-color trees to swap colors, and the coloring scheme is iteratively updated until all false edges are eliminated. Odd Cycle Probe Operator False edges on the 23-odd cycle are eliminated by color substitution and Kempe. probe operator It is specifically designed for processing sparse graphs. K4 probe operator Regardless of the stage, if K4 exists in the graph, it means that the graph has no solution.

6. The electronic probe computer according to claim 1, characterized in that, The system includes a probe protocol module, which is a data-driven control flow used to drive the operation of the probe unit. The probe data frame includes the following data types: The probe unit wake-up data consists of a 128-bit all-1 binary sequence, used to trigger the probe unit to enter the operation preparation state; The probe unit command data is 128 bits long and is used to indicate the next operation to be performed by the probe unit. Its field allocation is as follows: Bits 128 to 97: Identification fields for command data; Bits 96 to 65: The address field of the command data, which indicates the specific hardware on which the command takes effect; Bits 64 to 33: The specific command field of the command data. This field indicates the specific operation that the hardware should perform next. The specific value of this field and its corresponding command include: 0x0001: Perform a reset operation; 0x0002: Enter the receive probe unit setting data (CONFIG) process and start the normal calculation process; The probe unit configuration data (CONFIG) is 128 bits, and its field assignments are as follows: Bits 112 through 97: Indicate the number of points in the coloring problem; Bits 63 to 32: Identifier matrix ID; The matrix data is 128 bits, used to store the elements of a single row of the adjacency matrix. Elements are encoded in 1-bit form, from least significant bit to most significant bit. If the order of the adjacency matrix is ​​less than 128, the most significant bits are padded with 0s to reach 128 bits. If the order of the adjacency matrix is ​​greater than 128, it is stored contiguously using multiple sets of 128-bit data. The task data is 128 bits, used to specify the adjacency matrix region to be verified, and its field allocation is as follows: 95th to 81st positions: Identifier of point 1 to be verified; Bits 80 to 64: Identifier of point 2 to be verified; 63rd to 32nd positions: The matrix ID to which the point pair to be verified belongs; The result data is 128 bits long, and its field assignments are as follows: Bits 95 to 81: Identifier of verified point 1; Bits 80 to 64: Identifier of verified point 2; Bits 31 to 0: Encoding of the probe operator processing result, specifically including: 0x0000: No operation performed; current state cannot be determined. 0x0001: Points 1 and 2 can execute the edge probe operator; 0x0002: Points 1 and 2 can execute the shrinking probe operator; 0x0003: An empty graph is generated after the edge probe operator is executed at points 1 and 2; 0x0004: An empty graph is generated after the point shrinking probe operator is executed at points 1 and 2; 0x0005: Error, the current image is a four-color image, and probe operation cannot be performed.

7. The electronic probe computer according to claim 1, characterized in that, The transmission protocol is as follows: First, the probe unit is triggered to enter the command receiving state by sending all F commands n times via the WAKE command. Then, the COMMAND command stage begins. When bits 64 to 33 of this command are 0x0001, the system performs a reset operation, then returns to the WAKE command to resend data; if the value of this field is 0x0002, the system enters the receive probe unit setting data (CONFIG) process, followed by the MATRIX and TASK command processes in sequence.

8. The electronic probe computer according to claim 1, characterized in that, The working process of the probe computer: S1 Upper computer preprocessing: Step S101 performs rhombus reduction on the input image G and deletes 0, 1, and 2 degree points to obtain a new preprocessed image G; Step S102 determines whether the input image G in step S4 is a sparse image. If so, selects the pixel a1 with the smallest degree, performs point reduction on any two pixels in its neighborhood, and returns to step S101; if not, performs batch update and returns to step S101. S2 FPGA lower-level machine calculation: Write the matrix data and point pair data of the new graph G obtained in step S101 into the main storage, backup storage and task FIFO respectively. The FPGA determines the current state of the pixel based on the matrix data and point pair data. The current state of the pixel is one of unknown (0), edge can be added (1), point can be shrunk (2), empty graph after adding edge (3) or empty graph after shrunk (4), and returns the judgment result to the upper-level machine. S3 Four-color determination: Based on the determination result returned by step S2, determine whether four-coloring has been calculated. If not, continue to step S4. If yes, report to the host computer. S4 Empty graph determination: If an empty graph is calculated, continue to step S5; Otherwise, proceed to step S102; S5. Upper Computer Image Update and Coloring: Based on all the judgment results in step S4, update the image and determine whether to add edges and shrink points. If yes, add edges to pixels that can be added and shrink points to pixels that can be shrunken in sequence to generate the updated image G, and output the new image to the upper computer, repeating steps S1-S5. If no, color the image according to the original image and the order in which points disappear, and the process ends.

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