Digital circuit matrix peak point detection method with low resource occupation
By creating a 3x3 data comparison matrix and a register shifting method, the problem of high resource consumption in traditional matrix peak point search algorithms is solved, realizing low-resource-consumption digital circuit matrix peak point detection, and reducing chip area and cost.
Patent Information
- Application Number
- CN202511009379.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-22
- Publication Date
- 2025-10-28
AI Technical Summary
Traditional matrix peak finding algorithms consume a lot of hardware resources in digital circuits, resulting in increased chip area and high manufacturing costs.
A 3x3 data comparison matrix is used to determine the peak point by comparing the size of the data at the center point and the data at the periphery. The matrix position is moved to traverse and make judgments. Data is reused by using register shifting method to avoid caching the entire row of matrix data and multiplexer data.
It greatly saves on the resource consumption of digital circuits, reduces chip area and manufacturing costs, and yields significant benefits, especially in large-scale matrix applications.
Smart Images
Figure CN120848955A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computer science and technology, and in particular to a method for detecting peak points in a digital circuit matrix with low resource consumption. Background Technology
[0002] Traditional matrix peak point lookup algorithms determine peak points by indexing cached data, which requires caching matrix data with multiple rows and columns and selecting the corresponding data through a multiplexer. However, in digital circuits, caching and multiplexers consume a lot of hardware resources, increase chip area, and have high manufacturing costs. Summary of the Invention
[0003] The main objective of this invention is to provide a low-resource-consumption method for detecting peak points in digital circuit matrices. This method aims to solve the problem that traditional matrix peak point search algorithms consume a lot of hardware resources in digital circuits, such as caching and multiplexers, increasing chip area and manufacturing costs.
[0004] To achieve the above objectives, this invention proposes a method for detecting peak points in a low-resource-consumption digital circuit matrix, the method comprising: Create a 3x3 data comparison matrix; The peak point is determined by comparing the data at the center point of the 3*3 data comparison matrix with the data on the periphery in turn. Move the position of the 3*3 data comparison matrix and iterate through the original 3*3 data comparison matrix to determine whether each data point is a peak point.
[0005] In one embodiment, the movement of the 3*3 data comparison matrix is performed using a register shifting method, following a left-to-right and top-to-bottom shifting rule to obtain overlapping matrix data.
[0006] In one embodiment, the specific steps for determining the peak point by sequentially comparing the size of the center point data and the peripheral data of the 3*3 data comparison matrix are as follows: Assign a register name to each matrix data, namely D0, D1, D2, D3, D5, D6, D7, and D8; If the center point data D4 is greater than all the peripheral data, then the center point data of the current 3*3 data comparison matrix is determined to be the peak point, and the coordinates of the center point data D4 are written out and saved in the storage data; otherwise, the peak point writing and storage stage is skipped.
[0007] In one embodiment, the specific steps of moving the position of the 3*3 data comparison matrix include: When determining the boundary peak point, special processing of the boundary situation is required based on the coordinates of the center point.
[0008] In one embodiment, the specific steps for performing special processing on the boundary condition based on the center point coordinates when determining the peak value of the boundary point are as follows: If it is the top edge, then skip the reading stage of data D1 and D2; If it is the bottom edge, then skip the reading stage of data D7 and D8; If it is the left edge, then skip the reading stage of data D3 and D6; If it is the right edge, then jump to the next line and reread the data D1, D4, D7, D2, D5, D8.
[0009] The technical solution of this invention first creates a 3*3 data comparison matrix; then, it compares the size of the data at the center point of the 3*3 data comparison matrix with the data on the periphery in turn to determine the peak point; then, it moves the position of the 3*3 data comparison matrix and iterates through and judges whether each data in the original 3*3 data comparison matrix is a peak point. This method greatly saves the resource occupation of the digital circuit in the chip implementation of the algorithm, without caching the entire row of matrix data, and without consuming the hardware resources of the multiplexer. The ratio of the digital circuit cache area to the traditional index caching data method is 3 / C (C is the number of matrix columns), that is, the more matrix columns, the greater the resource benefit. Attached Figure Description
[0010] Figure 1 This is a flowchart illustrating the low-resource-consumption digital circuit matrix peak point detection method of the present invention; Figure 2 This is a schematic diagram of the 3*3 data comparison matrix movement in the low-resource-consumption digital circuit matrix peak point detection method of the present invention; Figure 3 This is a schematic diagram illustrating the data value reading of the low-resource-consumption digital circuit matrix peak point detection method of the present invention; Figure 4 This is a schematic diagram of boundary point data reading for the low-resource-consumption digital circuit matrix peak point detection method of the present invention. Detailed Implementation
[0011] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0012] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.
[0013] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0014] In the description of this invention, it should be understood that the terms "upper," "lower," "inner," "outer," "left," "right," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use, or the orientation or positional relationship commonly understood by those skilled in the art. They are only used to facilitate the description of this invention and to simplify the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.
[0015] Furthermore, the terms "first," "second," etc., are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.
[0016] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, terms such as "set" and "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0017] Traditional matrix peak point lookup algorithms determine peak points by indexing cached data, which requires caching matrix data with multiple rows and columns and selecting the corresponding data through a multiplexer. However, in digital circuits, caching and multiplexers consume a lot of hardware resources, increase chip area, and have high manufacturing costs.
[0018] To address the aforementioned problems, this invention proposes a method for detecting peak points in a digital circuit matrix with low resource consumption. The specific implementation of this invention will be described in detail below with reference to the accompanying drawings.
[0019] like Figure 1-4 As shown, the peak point detection method for a low-resource-consumption digital circuit matrix includes the following steps: Create a 3x3 data comparison matrix; The peak point is determined by comparing the data at the center point of the 3*3 data comparison matrix with the data on the periphery in turn. Move the position of the 3*3 data comparison matrix and iterate through the original 3*3 data comparison matrix to determine whether each data point is a peak point.
[0020] In one embodiment, the movement of the 3*3 data comparison matrix is performed using a register shifting method, following a left-to-right and top-to-bottom shifting rule to obtain overlapping matrix data.
[0021] In one embodiment, the specific steps for determining the peak point by sequentially comparing the size of the center point data and the peripheral data of the 3*3 data comparison matrix are as follows: Assign a register name to each matrix data, namely D0, D1, D2, D3, D5, D6, D7, and D8; If the center point data D4 is greater than all the peripheral data, then the center point data of the current 3*3 data comparison matrix is determined to be the peak point, and the coordinates of the center point data D4 are written out and saved in the storage data; otherwise, the peak point writing and storage stage is skipped.
[0022] In one embodiment, the specific steps of moving the position of the 3*3 data comparison matrix include: When determining the boundary peak point, special processing of the boundary situation is required based on the coordinates of the center point.
[0023] In one embodiment, the specific steps for performing special processing on the boundary condition based on the center point coordinates when determining the peak value of the boundary point are as follows: If it is the top edge, then skip the reading stage of data D1 and D2; If it is the bottom edge, then skip the reading stage of data D7 and D8; If it is the left edge, then skip the reading stage of data D3 and D6; If it is the right edge, then jump to the next line and reread the data D1, D4, D7, D2, D5, D8.
[0024] In this embodiment, a 3x3 data comparison matrix is created, and each matrix data is assigned a register name (D0-D8), such as... Figure 2 As shown, the peak value is determined by comparing the data at the center point D4 of the 3*3 matrix with the values of the eight peripheral data points D0, D1, D2, D3, D5, D6, D7, and D8.
[0025] Understandably, the process begins by initializing the 3x3 data comparison matrix by reading elements from the SRAM (Static Random Access Memory) storage device. Assuming the original data matrix is stored sequentially in the storage device, the data storage address of D4 is set to A, where A can be obtained from the row and column numbers of the center point of the current 3x3 matrix. Thus, the address of D0 is AC-1, the address of D1 is AC, the address of D2 is A-C+1, the address of D3 is A-1, the address of D5 is A+1, the address of D6 is A+C-1, the address of D7 is A+C, and the address of D8 is A+C+1. The data comparison matrix is then read sequentially through the storage addresses, and the elements of the 3x3 data comparison matrix are written into the corresponding registers according to the memory timing. After the 3*3 data comparison matrix is initialized, the value of the center point D4 is compared with the values of the eight outer data points in turn. If D4 is greater than all the outer data points, the center point of the current 3*3 data comparison matrix is determined to be the peak value, and the coordinates of the current center point D4 are written out to the storage data. If the peak value condition is not met, the peak value writing and storage stage is skipped.
[0026] In this embodiment, after the current peak point is determined, the 3x3 data comparison matrix is moved according to the rules of moving from left to right and from top to bottom, such as... Figure 2 As shown. In this example, matrix elements can be reused in different positions. Overlapping matrix data is directly obtained using register shifting, avoiding repeated data retrieval from storage devices. Understandably, after the peak point determination of the previous 3x3 matrix is completed, the values of registers D1, D4, and D7 are written to D0, D3, and D6 respectively using shifting. Simultaneously, the values of registers D2, D5, and D8 are written to D1, D4, and D7 respectively using shifting registers. The data values of D2, D5, and D8 are still read sequentially from SRAM through storage addresses, as shown... Figure 3 As shown; after the data is read, the peak value of the center point of the current 3*3 data comparison matrix is determined.
[0027] This embodiment moves the 3x3 data comparison matrix using the method described above, traversing and determining whether each element in the original matrix is a peak point. During the shifting of the 3x3 data comparison matrix, if it is necessary to determine the peak value of boundary points, special processing of the boundary conditions is required based on the current center point coordinates, such as... Figure 4 As shown, specifically: if it is the top edge (row number 0), skip the stage of reading data D1 and D2; if it is the bottom edge (row number L-1 of the total number of rows), skip the stage of reading data D7 and D8; if it is the left edge (column number 0), skip the stage of reading data D3 and D6; if it is the right edge (column number C-1 of the total number of columns), you need to jump to the next row and reread data D1, D4, D7, D2, D5, and D8.
[0028] This invention provides a low-resource-consumption digital circuit matrix peak point detection method. First, a 3x3 data comparison matrix is created. Then, the values of the data at the center point and the data on the periphery of the 3x3 data comparison matrix are compared sequentially to determine peak points. Next, the position of the 3x3 data comparison matrix is moved, and each data point in the original 3x3 data comparison matrix is iterated to determine if it is a peak point. This method significantly reduces the resource consumption of the digital circuit in the chip implementation, eliminating the need to cache entire rows of matrix data or consume the hardware resources of a multiplexer. Compared to the traditional index-based data caching method, the digital circuit cache area ratio is 3 / C (where C is the number of matrix columns). That is, the more matrix columns, the greater the resource benefit, thus reducing manufacturing costs.
[0029] In summary, the low-resource-consumption digital circuit matrix peak point detection method of this invention replaces the traditional cache row and column data indexing method with the creation of a 3*3 data comparison matrix to reduce resource consumption; it improves detection efficiency by reusing adjacent cross matrix data values through shift registers; it detects peak points in real time by sequentially moving the center point of the 3*3 data comparison matrix; and it facilitates handling boundary conditions by controlling the matrix data to be obtained from the storage device through a state machine.
[0030] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A method for peak point detection in a digital circuit matrix with low resource consumption, characterized in that, The method for detecting peak points in a low-resource-consumption digital circuit matrix includes the following steps: Create a 3x3 data comparison matrix; The peak point is determined by comparing the data at the center point of the 3*3 data comparison matrix with the data on the periphery in turn. Move the position of the 3*3 data comparison matrix and iterate through the original 3*3 data comparison matrix to determine whether each data point is a peak point.
2. The method for detecting peak points in a low-resource-consumption digital circuit matrix according to claim 1, characterized in that, The position of the 3*3 data comparison matrix is moved using a register shifting method, following the shifting rules from left to right and from top to bottom to obtain overlapping matrix data.
3. The method for detecting peak points in a low-resource-consumption digital circuit matrix according to claim 1, characterized in that, The specific steps for comparing the center point data and the peripheral data of the 3*3 data comparison matrix in sequence to determine the peak point are as follows: Assign a register name to each matrix data, namely D0, D1, D2, D3, D5, D6, D7, and D8; If the center point data D4 is greater than all the peripheral data, then the center point data of the current 3*3 data comparison matrix is determined to be the peak point, and the coordinates of the center point data D4 are written out and saved in the storage data; otherwise, the peak point writing and storage stage is skipped.
4. The method for detecting peak points in a low-resource-consumption digital circuit matrix according to claim 3, characterized in that, The specific steps for moving the 3x3 data comparison matrix are as follows: When determining the boundary peak point, special processing of the boundary situation is required based on the coordinates of the center point.
5. The method for detecting peak points in a low-resource-consumption digital circuit matrix according to claim 4, characterized in that, The specific steps for special handling of the boundary situation based on the center point coordinates when determining the peak value of the boundary point are as follows: If it is the top edge, then skip the reading stage of data D1 and D2; If it is the bottom edge, then skip the reading stage of data D7 and D8; If it is the left edge, then skip the reading stage of data D3 and D6; If it is the right edge, then jump to the next line and reread the data D1, D4, D7, D2, D5, D8.