Power amplifier

Abstract

The invention discloses a power amplifier, relates to the technical field of base stations, and aims to solve the problem of low efficiency of a traditional power amplifier in an output power backoff region in the prior art. The power amplifier comprises a driving amplifier, a power divider and an inversion Doherty amplifier, the inversion Doherty amplifier comprises a carrier amplifier and a peak amplifier, the driving amplifier receives radio frequency signals and is connected with the power divider, a first output end of the power divider is connected with the carrier amplifier, a second output end of the power divider is connected with the peak amplifier, and a third output end of the power divider is connected with the peak amplifier. The first output end of the power divider is connected with the carrier amplifier, the second output end of the power divider is connected with the peak amplifier, the carrier amplifier comprises a first transistor amplification module, the peak amplifier comprises a second transistor amplification module, and the ratio of the number of transistors of the first transistor amplification module to the number of transistors of the second transistor amplification module is a preset ratio. The preset ratio is less than 1.

Description

Technical Field

[0001] This invention relates to the field of base station technology, and more particularly to power amplifiers. Background Technology

[0002] With the development of 5G technology in wireless mobile communication, complex modulation techniques (such as OFDM modulation) are used for signal transmission to improve the utilization of limited spectrum, resulting in a high peak-to-average power ratio (PAPR). A high PAPR requires the radio frequency system to maintain high efficiency within a certain output range.

[0003] Traditional power amplifiers exhibit low efficiency in the fallback region due to the small output voltage swing at low power. Three solutions exist: envelope tracking and envelope cancellation / recovery techniques; out-of-phase power amplifier technology; and Doherty technology, which applies a larger load to the amplifier at lower output power levels to maintain full-scale output voltage swing. The first two techniques require additional hardware circuitry, introducing external problems. Doherty technology, however, requires no external hardware, is easy to implement, and delivers excellent results. Therefore, Doherty technology is the mainstream efficiency improvement technology for wireless communication systems, leading to its widespread application in base station RF components.

[0004] There is an urgent need in this field to improve the efficiency of base station power amplifiers when operating in the fallback zone. Summary of the Invention

[0005] The purpose of this invention is to provide a power amplifier for improving the efficiency of the power amplifier when operating in the back-off region.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A power amplifier includes: a driver amplifier, a power divider, and an inverted Doherty amplifier; the inverted Doherty amplifier includes a carrier amplifier and a peak amplifier;

[0008] The driver amplifier receives radio frequency signals; the driver amplifier is connected to the power divider; the first output terminal of the power divider is connected to the carrier amplifier, and the second output terminal of the power divider is connected to the peak amplifier.

[0009] The carrier amplifier includes a first transistor amplification module; the peak amplifier includes a second transistor amplification module; the ratio of the number of transistors in the first transistor amplification module to the number of transistors in the second transistor amplification module is a preset ratio; the preset ratio is less than 1.

[0010] Compared with existing technologies, the power amplifier provided by this invention includes a driver amplifier, a power divider, and an inverted Doherty amplifier. The inverted Doherty amplifier includes a carrier amplifier and a peak amplifier. The driver amplifier receives radio frequency (RF) signals. The driver amplifier is connected to the power divider, the first output terminal of the power divider is connected to the carrier amplifier, and the second output terminal of the power divider is connected to the peak amplifier. The carrier amplifier includes a first transistor amplification module, and the peak amplifier includes a second transistor amplification module. The ratio of the number of transistors in the first transistor amplification module to the number of transistors in the second transistor amplification module is a preset ratio, which is less than 1. In this invention, the driver amplifier amplifies the RF signal for the first time. The power divider divides the RF signal after the first amplification into two sub-RF signals, which are then fed into the carrier amplifier and the peak amplifier, respectively. After the RF signal is amplified by the two amplifiers with a transistor ratio less than 1, the efficiency of the final output RF signal in the back-off region is improved compared to the efficiency of traditional power amplifier structures operating in the back-off region. Attached Figure Description

[0011] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0012] Figure 1 A schematic diagram of the structure of a power amplifier provided for one embodiment of the present invention;

[0013] Figure 2 A schematic diagram of the structure of a carrier amplifier provided for one embodiment of the present invention;

[0014] Figure 3 A schematic diagram of the structure of a peak amplifier provided for one embodiment of the present invention;

[0015] Figure 4 A schematic diagram of a power divider provided in one embodiment of the present invention;

[0016] Figure 5 A schematic diagram of the structure of a drive amplifier provided in one embodiment of the present invention;

[0017] Figure 6 The power-added efficiency versus output saturation power curve of the power amplifier provided in a specific embodiment of the present invention;

[0018] Figure 7 The output saturation power versus input power curve of the power amplifier provided in a specific embodiment of the present invention;

[0019] Figure 8 The gain-output saturation power relationship curve of the power amplifier provided for a specific embodiment of the present invention;

[0020] Figure label:

[0021] 10 - Power Amplifier; 100 - Driver Amplifier; 200 - Power Divider; 300 - Inverted Doherty Amplifier; 400 - Carrier Amplifier; 500 - Peak Amplifier; 101 - Fifth Voltage Source; 102 - Sixth Power Supply; 410 - First Transistor Amplifier Module; 420 - First Input Matching Network; 421 - Second Voltage Source; 430 - First Output Matching Network; 431 - First Voltage Source; 510 - Second Transistor Amplifier Module; 520 - Second Input Matching Network; 521 - Third Voltage Source; 530 - Second Output Matching Network; 531 - Fourth Voltage Source;

[0022] C1-C24: Capacitors 1 to 24; L1-L16: Inductors 1 to 16;

[0023] R1-R6: Resistors 1 to 6; M1-M7: Transistors 1 to 7. Detailed Implementation

[0024] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0025] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0026] In this invention, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between the associated objects, indicating that three relationships can exist.

[0027] like Figure 1As shown, this embodiment of the invention provides a power amplifier 10, which can be applied to small base stations. The power amplifier 10 includes: a driver amplifier 100, a power divider 200, and an inverse Doherty amplifier 300; the inverse Doherty amplifier 300 includes a carrier amplifier 400 and a peak amplifier 500.

[0028] The driver amplifier 100 receives the radio frequency signal RFin; the driver amplifier 100 is connected to the power divider 200; the first output terminal of the power divider 200 is connected to the carrier amplifier 400, and the second output terminal of the power divider 200 is connected to the peak amplifier 500.

[0029] like Figure 2 As shown, the carrier amplifier 400 may include a first transistor amplification module 410; as Figure 3 As shown, the peak amplifier 500 may include a second transistor amplifier module 510; the ratio of the number of transistors in the first transistor amplifier module 410 to the number of transistors in the second transistor amplifier module 510 is a preset ratio; the preset ratio is less than 1, for example, the preset ratio may be 1:2, and the output terminal of the power amplifier 10 (the junction of the carrier amplifier 400 and the peak amplifier 500) outputs the radio frequency signal Rfout.

[0030] Specifically, the power divider 200 is an unequal power divider. In the inverted Doherty amplifier 300 stage, the RF signal is unequally distributed by the power divider 200 and then input to the carrier amplifier 400 and the peak amplifier 500 respectively. After passing through the two amplifiers, the signals are then combined and sent to the output port of the power amplifier 10. Unlike the traditional Doherty amplifier structure, the inverted Doherty amplifier 300 adopts an inverted structure, interchanges the peak amplifier 500 and the carrier amplifier 400 in the traditional Doherty amplifier, and integrates the open transmission line into the function of the λ / 4 inverter, thereby reducing the amount of inverter used.

[0031] Optionally, such as Figure 2 As shown, the first transistor amplification module 410 may include a first transistor M1 and a second transistor M2; the carrier amplifier 400 may also include a first input matching network 420 and a first output matching network 430; the first output matching network 430 is used to make the impedance of the output terminal of the power amplifier 10 reach a preset impedance value.

[0032] The gates of the first transistor M1 and the second transistor M2 are both connected to the output of the first input matching network 420.

[0033] The source of the first transistor M1 and the source of the second transistor M2 are both grounded;

[0034] The drains of both the first transistor M1 and the second transistor M2 are connected to the input of the first output matching network 430.

[0035] Optionally, such as Figure 2 As shown, the first output matching network 430 may include a first capacitor C1, a second capacitor C2, a first inductor L1, and a first voltage source 431;

[0036] The first terminal of the first capacitor C1 and the first terminal of the first inductor L1 are both connected to the input terminal of the first output network.

[0037] The second terminal of the first inductor L1 is connected to the positive terminal of the first voltage source 431; the negative terminal of the first voltage source 431 is grounded.

[0038] The first terminal of the first capacitor C1 and the first terminal of the second capacitor C2 are connected by a microstrip line of a first length; the first terminal of the second capacitor C2 is also connected to the output terminal of the first output matching network 430; the second terminal of the second capacitor C2 is grounded.

[0039] 5G base stations are mainly divided into macro base stations and small base stations. Macro base stations are primarily used for outdoor coverage, and are large in size with a wide coverage area. However, due to the high-frequency operation of 5G, the signal range that a macro base station can cover is limited, requiring a large number of small base stations to work in conjunction with macro base stations for continuous coverage and shallow indoor coverage. Small base stations have lower transmission power and can be divided into micro base stations, pico base stations, and femto base stations based on their coverage area. They are widely used in various indoor scenarios, and their portability and compactness have become important indicators for evaluating base station quality. Reducing the size of the power amplifier is one of the key issues in improving portability. Therefore, improving the compactness of the power amplifier and improving its performance indicators are equally important.

[0040] In related technologies, the output matching network of the carrier amplifier is connected to at least one impedance adjustment circuit containing multiple capacitors and inductors to make the output impedance of the power amplifier reach the target impedance value, such as 50 ohms (Ω). This is not only inefficient but also has a cumbersome circuit structure. In this embodiment, the first output matching network 430 in the carrier amplifier 400 replaces the traditional output matching network and subsequent impedance adjustment circuit of the carrier amplifier. Firstly, an asymmetric inverse Doherty structure is used, eliminating the quarter-wavelength impedance inverter line after the carrier amplifier, reducing circuit area, and increasing the overall backoff of the Doherty amplifier, further improving the impedance at the combiner port (output of the power amplifier). By adjusting the parameters of the first capacitor, the second capacitor, and the first inductor in the first output matching network 430, the output impedance of the first output matching network 430 can reach a preset impedance value of 100Ω. Therefore, after the two amplifiers are connected in parallel at the combiner port, a 50Ω impedance output can be directly obtained, thus eliminating the need for a matching network structure that transforms the impedance from 25Ω to 50Ω at the combiner port, reducing circuit complexity and the overall circuit area of ​​the power amplifier. Simultaneously, the introduction of impedance matrix transformation technology ensures that the first output matching network of the carrier amplifier maintains high efficiency at both the backoff point and saturation point, improving the power amplifier's operating efficiency and performance, reducing its size, and enhancing portability.

[0041] Optionally, such as Figure 2 As shown, the first input matching network 420 may include a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, a second inductor L2, a third inductor L3, a fourth inductor L4, a first resistor R1, and a second voltage source 421.

[0042] The first terminal of the third capacitor C3 and the first terminal of the second inductor L2 are both connected to the input terminal of the first input matching network 420; the second terminal of the third capacitor C3 is grounded.

[0043] The first terminal of the fourth capacitor C4 and the first terminal of the fifth capacitor C5 are both connected to the second terminal of the second inductor L2; the second terminal of the fourth capacitor C4 is grounded.

[0044] The first terminal of the sixth capacitor C6 and the first terminal of the third inductor L3 are both connected to the second terminal of the fifth capacitor C5; the second terminal of the sixth capacitor C6 is grounded.

[0045] The second terminal of the third inductor L3 is connected to the first terminal of the fourth inductor L4; the second terminal of the third inductor L3 is also connected to the output terminal of the first input matching network 420.

[0046] The first terminal of the first resistor R1 and the first terminal of the seventh capacitor C7 are both connected to the second terminal of the fourth inductor L4.

[0047] The second terminal of the first resistor R1 is connected to the positive terminal of the second voltage source 421; the second terminal of the seventh capacitor C7 is connected to the negative terminal of the second voltage source 421; and the negative terminal of the second voltage source 421 is grounded.

[0048] pass Figure 2 As can be seen, in this embodiment, the carrier amplifier 400 adopts a bandpass T-type (CLC) topology input match network (IMN) structure and a traditional RCL bias structure.

[0049] In related technologies, traditional Doherty amplifiers use a quarter-wavelength line as an impedance transformer at the 400° output port of the carrier amplifier. However, when using a quarter-wavelength line as an impedance transformer, the expected impedance transformation can only be achieved at the design frequency. Outside the design frequency, although the real part transformation is small, the imaginary part deviates significantly from zero, causing a mismatch between the carrier power amplifier and the peak power amplifier, affecting the overall output power and drain efficiency of the Doherty circuit. Secondly, it occupies a large area, making it unsuitable for small-area applications in base stations.

[0050] This embodiment proposes using a lumped element network instead of a traditional microstrip line structure, reducing circuit area and lowering frequency limitations, while also allowing for convenient phase adjustment. Using lumped elements in circuit design offers several advantages: the lumped element circuit structure is more compact, the chip size is relatively small, and it is convenient to use at lower frequencies. Therefore, the input matching network adopts an LC-microstrip-C structure, with L as part of the bias. Both the first input matching network and the first output matching network employ maximum power conjugate matching. Substituting the port impedances at back-off and saturation, the S-parameters and phase shift parameters of the first output matching network are determined using a dual impedance matching method, thereby determining the component parameters of the carrier power amplifier's output matching network. The specific implementation steps are as follows: Based on the dynamic load modulation transformation law, the relationship between the input and output impedances of the first output matching network in the carrier amplifier at the back-off point and the saturation point can be obtained, i.e., the transmission matrix Z. The matrix contains four parameters: the optimal network input impedance and the optimal network output impedance at the back-off point, and the optimal network input impedance and the optimal network output impedance at the saturation point. After substituting specific values, through the mutual conversion between the Z matrix and the S matrix, the transmission network can be expressed as a matrix S that is only related to S11, thus obtaining an output network S parameter value that best satisfies the two working states. Adjusting the output matching network to satisfy the S parameter will achieve the optimal output.

[0051] like Figure 3As shown, the peak amplifier 500 also includes a second input matching network 520 and a second output matching network 530; optionally, the second transistor amplification module 510 may include a third transistor M3, a fourth transistor M4, a fifth transistor M5 and a sixth transistor M6;

[0052] The gates of the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are all connected to the output of the second input matching network 520.

[0053] The source of the third transistor M3 is connected to the source of the fourth transistor M4 and both are grounded; the source of the fifth transistor M5 is connected to the source of the sixth transistor M6 and both are grounded; the drains of the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are all connected to the input of the second output matching network 530.

[0054] Optionally, such as Figure 3 As shown, the second input matching network 520 may also include an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, a fifth inductor L5, a sixth inductor L6, a second resistor R2, and a third voltage source 521.

[0055] The first terminal of the eighth capacitor C8 is connected to the input terminal of the second input matching network 520; the first terminal of the ninth capacitor C9 and the first terminal of the fifth inductor L5 are both connected to the second terminal of the eighth capacitor C8; the second terminal of the ninth capacitor C9 is grounded.

[0056] The second terminal of the fifth inductor L5 is connected to the first terminal of the sixth inductor L6; the second terminal of the fifth inductor L5 is also connected to the output terminal of the second input matching network 520.

[0057] The first terminal of the second resistor R2 and the first terminal of the tenth capacitor C10 are both connected to the second terminal of the sixth inductor L6; the second terminal of the second resistor R2 is connected to the positive terminal of the third voltage source 521; the second terminal of the tenth capacitor C10 is connected to the negative terminal of the third power source; the negative terminal of the third voltage source 521 is grounded.

[0058] The second input matching network 520 also includes an eleventh capacitor C11, a twelfth capacitor C12, a thirteenth capacitor C13, a seventh inductor L7, an eighth inductor L8, and a third resistor R3.

[0059] The first terminal of the eleventh capacitor C11 is connected to the input terminal of the second input matching network 520; the first terminal of the twelfth capacitor C12 and the first terminal of the seventh inductor L7 are both connected to the second terminal of the eleventh capacitor C11; the second terminal of the twelfth capacitor C12 is grounded.

[0060] The second terminal of the seventh inductor L7 is connected to the first terminal of the eighth inductor L8; the second terminal of the seventh inductor L7 is also connected to the output terminal of the second input matching network 520.

[0061] The first terminal of the thirteenth capacitor C13 and the first terminal of the third resistor R3 are both connected to the second terminal of the eighth inductor L8.

[0062] The second terminal of the thirteenth capacitor C13 is connected to the second terminal of the third resistor R3; the second terminal of the thirteenth capacitor C13 is also grounded.

[0063] Optionally, such as Figure 3 As shown, the second output matching network 530 may include a fourteenth capacitor C14, a fifteenth capacitor C15, a sixteenth capacitor C16, a ninth inductor L9, and a fourth voltage source 531;

[0064] The first terminal of the fourteenth capacitor C14 and the first terminal of the ninth inductor L9 are both connected to the input terminal of the second output matching network 530; the second terminal of the ninth inductor L9 is connected to the positive terminal of the fourth voltage source 531; the negative terminal of the fourth voltage source 531 is grounded.

[0065] The second terminal of the fourteenth capacitor C14 is connected to the first terminal of the fifteenth capacitor C15 via a microstrip line of the second length; the first terminal of the fifteenth capacitor C15 is also connected to the first terminal of the sixteenth capacitor C16 via a microstrip line of the third length; the second terminal of the fifteenth capacitor C15 is grounded; the first terminal of the sixteenth capacitor C16 is also connected to the output terminal of the second output matching network 530; the second terminal of the sixteenth capacitor C16 is grounded.

[0066] In this embodiment, the peak amplifier 500 adopts a bandpass T-type (CLC) topology IMN structure and a traditional RCL bias structure. The second output matching network adopts an LC-microstrip line-C structure, with L as part of the bias. An open-circuit compensation line needs to be connected after the matching structure of the peak amplifier 500 to achieve a complete short circuit in the pinch-off state. For the peak amplifier 500, its turn-on point is mainly determined by the gate voltage. In an inverted Doherty amplifier, the turn-on threshold of the peak amplifier 500 needs to be confirmed in conjunction with the saturation point of the carrier amplifier 400 in the back-off region. First, the input power of the carrier amplifier 400 in the back-off saturation state is obtained. Based on the ratio of this input power to the output of the power divider 200, the turn-on threshold power of the peak amplifier 500 can be obtained. After determining the turn-on point, the low-pass Π-type phase network is adjusted to achieve the function of an open-circuit compensation line. The inductor is replaced by a microstrip line. Both the second input matching network and the second output matching network adopt maximum power conjugate matching. By substituting the port impedance value of the power amplifier output terminal when saturated, the component parameters of the second output matching network of the peak power amplifier are determined.

[0067] After the design of the carrier amplifier 400 and peak amplifier 500 is completed, the phases of the carrier amplifier 400 and peak amplifier 500 are coordinated by adding a low-pass Π-type structure before the carrier amplifier 400 to compensate for the phase. At this point, both the carrier amplifier 400 and peak amplifier 500 should reach their optimal output power and power-added gain. Adjusting the power divider 200 to make the power distribution more reasonable will ensure that both the carrier amplifier 400 and peak amplifier 500 meet their optimal output.

[0068] Optionally, such as Figure 4 As shown, the power divider 200 may include a seventeenth capacitor C17, an eighteenth capacitor C18, a nineteenth capacitor C19, a tenth inductor L10, an eleventh inductor L11, and a fourth resistor R4.

[0069] The first terminal of the seventeenth capacitor C17, the first terminal of the tenth inductor L10, and the first terminal of the eleventh inductor L11 are all connected to the input terminal of the power divider 200; the second terminal of the seventeenth capacitor C17 is grounded.

[0070] The first terminal of the fourth resistor R4, the first terminal of the eighteenth capacitor C18, and the first output terminal of the power divider 200 are all connected to the second terminal of the tenth inductor L10; the second terminal of the eighteenth capacitor C18 is grounded.

[0071] The second terminal of the fourth resistor R4, the first terminal of the nineteenth capacitor C19, and the second output terminal of the power divider 200 are all connected to the second terminal of the eleventh inductor L11; the second terminal of the nineteenth capacitor C19 is grounded.

[0072] In this embodiment, the power divider 200 is designed with a Wilkinson power divider structure. Considering that the carrier amplifier 400 and the peak amplifier 500 are non-uniformly sized amplifiers and that the two amplifiers operate in different states, a non-uniform Wilkinson power divider 200 is used. Adjusting the power divider 200 makes the power distribution more reasonable and can meet the optimal output of both amplifiers. Ultimately, the power distribution between the carrier amplifier and the peak amplifier is approximately a preset ratio, such as 1.74:1.

[0073] Optionally, such as Figure 5As shown, the driver amplifier 100 receives the radio frequency signal RFin. The driver amplifier 100 may include the twelfth inductor L12, the thirteenth inductor L13, the fourteenth inductor L14, the fifteenth inductor L15, the sixteenth inductor L16, the twentieth capacitor C20, the twenty-first capacitor C21, the twenty-second capacitor C22, the twenty-third capacitor C23, the twenty-fourth capacitor C24, the fifth resistor R5, the sixth resistor R6, the sixth voltage source 102, the seventh voltage source, and the seventh transistor M7.

[0074] The first terminal of the twelfth inductor L12 and the first terminal of the twentieth capacitor C20 are both connected to the input terminal of the driver amplifier 100; the second terminal of the twelfth inductor L12 is grounded.

[0075] The first terminal of the twenty-first capacitor C21 and the first terminal of the thirteenth inductor L13 are both connected to the second terminal of the twenty-second capacitor C20; the second terminal of the twenty-first capacitor C21 is grounded; the second terminal of the thirteenth inductor L13 is connected to the first terminal of the fifth resistor R5.

[0076] The first terminal of the fourteenth inductor L14 and the gate of the seventh transistor M7 are both connected to the second terminal of the fifth resistor R5.

[0077] The first terminal of the twenty-second capacitor C22 and the first terminal of the sixth resistor R6 are both connected to the second terminal of the fourteenth inductor L14; the second terminal of the sixth resistor R6 is connected to the positive terminal of the fifth voltage source 101; the second terminal of the twenty-second capacitor C22 is connected to the negative terminal of the fifth voltage source 101; the negative terminal of the fifth voltage source 101 is grounded.

[0078] The first terminal of the fifteenth inductor L15 and the first terminal of the sixteenth inductor L16 are both connected to the drain of the seventh transistor M7; the second terminal of the fifteenth inductor L15 is connected to the positive terminal of the sixth voltage source 102; the negative terminal of the sixth voltage source 102 is grounded; the source of the seventh transistor M7 is grounded.

[0079] The first terminal of the twenty-third capacitor C23 and the first terminal of the twenty-fourth capacitor C24 are both connected to the second terminal of the sixteenth inductor L16; the second terminal of the twenty-third capacitor C23 is grounded; and the second terminal of the twenty-fourth capacitor C24 is connected to the output terminal of the driver amplifier 100.

[0080] In this embodiment, the driver amplifier circuit adopts an internal matching structure, directly integrated onto the substrate using surface-mount devices (SMDs). The third input matching network of the driver amplifier employs maximum power conjugate transmission, and the impedance transformation section uses an LC-CL structure to extend the bandwidth. An RC parallel stabilizing circuit is added after the input matching network to stabilize the entire circuit and prevent oscillations. The bias section uses a traditional RCL bias structure, and the third output matching network of the driver amplifier employs maximum gain conjugate matching, using an LC structure to extend the bandwidth. The bias inductor also participates in output matching to reduce overall losses. A DC blocking capacitor is added afterward to isolate DC.

[0081] After the circuit structure of the driver amplifier 100, power divider 200, carrier amplifier 400, and peak amplifier 500 is selected, the RF signal is first input to the driver amplifier 100. The driver amplifier 100 provides the initial gain and drives the subsequent amplifiers, while ensuring the stability of the overall circuit. Next, the RF signal, after passing through the initial gain, is unevenly transmitted to the carrier amplifier 400 and peak amplifier 500 in the inverted Doherty amplifier 300 via the power divider 200. The carrier amplifier and peak amplifier work together to form the structure of the inverted Doherty amplifier 300, achieving load modulation of the carrier amplifier to compensate for the efficiency drop after the RF signal reaches saturation. The carrier amplifier 400 starts working first. After the RF signal output reaches saturation, the peak amplifier 500 starts working, changing the load impedance of the carrier amplifier through output current transformation, so that the output impedance of both the carrier amplifier 400 and peak amplifier 500 is half of the target impedance. Finally, the currents of the carrier amplifier 400 and peak amplifier 500 are combined for output.

[0082] like Figures 6-8 In Specific Implementation Method 1, after the circuit structures of the driver amplifier 100, power divider 200, carrier amplifier 400, and peak amplifier 500 are selected, the transistors can use GaN HEMT technology, the IPD section can use GaAs technology, and the on-board integrated section can use SMD surface-mount components. A 48V bias voltage is ultimately used, and the overall power amplifier operates in the 4.8-5.0GHz frequency band. The circuit area of ​​the inverted Doherty amplifier is less than 5*9.5mm, within the operating frequency range of 4.8GHz-5.0GHz. The following is a joint electromagnetic simulation of the layout schematic of the power amplifier circuit in Specific Implementation Method 1, yielding the following results:

[0083] In the first specific implementation method, such as Figure 6 As shown ( Figure 6The diagram shows the relationship between power-added efficiency and output saturation power at three frequencies: 4.8GHz, 4.9GHz, and 5.0GHz. The backoff point is the output power corresponding to the first peak point of power-added efficiency. One of the backoff points corresponds to an output power of 39.93dBm, and the saturation point is the second peak point at 47.6dBm. Subtracting the output power at the saturation point from the backoff point yields a backoff of 7.7dB. Traditional Doherty structures can only achieve a backoff of 6dB. This embodiment features an increased backoff.

[0084] Figure 7 The curves showing the relationship between output saturation power and input power at three frequencies: 4.8GHz, 4.9GHz, and 5.0GHz are presented.

[0085] In existing architectures, the efficiency of high-power output power amplifiers is often only high at the saturation point. However, as... Figure 6 As shown, in the circuit design of this invention, impedance matrix transformation technology is used to maintain high output efficiency at both the backoff point and the saturation point.

[0086] like Figure 8 ( Figure 8 The curves showing the relationship between gain and output saturation power at three frequencies (4.8GHz, 4.9GHz, and 5.0GHz) are illustrated. The gain range of 23-29dB refers to the overall gain of the power amplifier within its operating range. Existing structures using a single-stage amplifier can only achieve a gain of around 10dB, while this design uses a two-stage amplifier to achieve an overall output gain of over 23dB.

[0087] As can be seen from the above specific implementation method, the power amplifier provided by the present invention improves the efficiency and back-off of power amplifiers for 5G band applications, effectively expanding the high efficiency range of the saturated power output of traditional Doherty amplifiers to 7-7dB, while ensuring that the efficiency is greater than 35%. This achieves performance improvement of power amplifiers applied to base stations. While ensuring that the output power and gain meet the requirements of base station applications, it effectively improves the efficiency reduction problem caused by the high PAPR of complex modulation signals, and has high engineering application value.

[0088] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other device can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0089] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A power amplifier, characterized in that, include: Driver amplifiers, power dividers, and inverted Doherty amplifiers; The inverse Doherty amplifier includes a carrier amplifier and a peak amplifier; The driver amplifier receives radio frequency signals; the driver amplifier is connected to the power divider; the first output terminal of the power divider is connected to the carrier amplifier, and the second output terminal of the power divider is connected to the peak amplifier. The carrier amplifier includes a first transistor amplification module; the peak amplifier includes a second transistor amplification module; the ratio of the number of transistors in the first transistor amplification module to the number of transistors in the second transistor amplification module is a preset ratio; the preset ratio is less than 1.

2. The power amplifier according to claim 1, characterized in that, The first transistor amplification module includes a first transistor and a second transistor; the carrier amplifier further includes a first input matching network and a first output matching network; the first output matching network is used to make the impedance at the output terminal of the power amplifier reach a preset impedance value; The gates of the first transistor and the second transistor are both connected to the output of the first input matching network. The source of the first transistor and the source of the second transistor are both grounded; The drains of both the first transistor and the second transistor are connected to the input of the first output matching network.

3. The power amplifier according to claim 2, characterized in that, The first output matching network includes a first capacitor, a second capacitor, a first inductor, and a first voltage source; The first terminal of the first capacitor and the first terminal of the first inductor are both connected to the input terminal of the first output network. The second terminal of the first inductor is connected to the positive terminal of the first voltage source; the negative terminal of the first voltage source is grounded. The first terminal of the first capacitor and the first terminal of the second capacitor are connected by a microstrip line of a first length; the first terminal of the second capacitor is also connected to the output terminal of the first output matching network; the second terminal of the second capacitor is grounded.

4. The power amplifier according to claim 3, characterized in that, The first input matching network includes a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, a second inductor, a third inductor, a fourth inductor, a first resistor, and a second voltage source; The first terminal of the third capacitor and the first terminal of the second inductor are both connected to the input terminal of the first input matching network; the second terminal of the third capacitor is grounded. The first terminal of the fourth capacitor and the first terminal of the fifth capacitor are both connected to the second terminal of the second inductor; the second terminal of the fourth capacitor is grounded. The first terminal of the sixth capacitor and the first terminal of the third inductor are both connected to the second terminal of the fifth capacitor; the second terminal of the sixth capacitor is grounded. The second end of the third inductor is connected to the first end of the fourth inductor; the second end of the third inductor is also connected to the output end of the first input matching network. The first terminal of the first resistor and the first terminal of the seventh capacitor are both connected to the second terminal of the fourth inductor; The second end of the first resistor is connected to the positive terminal of the second voltage source; the second end of the seventh capacitor is connected to the negative terminal of the second voltage source; and the negative terminals of the second voltage source are all grounded.

5. The power amplifier according to claim 1, characterized in that, The peak amplifier further includes a second input matching network and a second output matching network; the second transistor amplification module includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; The gates of the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are all connected to the output of the second input matching network. The source of the third transistor is connected to the source of the fourth transistor; the source of the fifth transistor is connected to the source of the sixth transistor; the drains of the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are all connected to the input of the second output matching network.

6. The power amplifier according to claim 5, characterized in that, The second input matching network includes an eighth capacitor, a ninth capacitor, a tenth capacitor, a fifth inductor, a sixth inductor, a second resistor, and a third voltage source; The first terminal of the eighth capacitor is connected to the input terminal of the second input matching network; the first terminal of the ninth capacitor and the first terminal of the fifth inductor are both connected to the second terminal of the eighth capacitor; the second terminal of the ninth capacitor is grounded. The second terminal of the fifth inductor is connected to the first terminal of the sixth inductor; the second terminal of the fifth inductor is also connected to the output terminal of the second input matching network. The first terminal of the second resistor and the first terminal of the tenth capacitor are both connected to the second terminal of the sixth inductor; the second terminal of the second resistor is connected to the positive terminal of the third voltage source; the second terminal of the tenth capacitor is connected to the negative terminal of the third power source; the negative terminal of the third voltage source is grounded. The second input matching network also includes an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, a seventh inductor, an eighth inductor, and a third resistor; The first terminal of the eleventh capacitor is connected to the input terminal of the second input matching network; the first terminal of the twelfth capacitor and the first terminal of the seventh inductor are both connected to the second terminal of the eleventh capacitor; the second terminal of the twelfth capacitor is grounded. The second terminal of the seventh inductor is connected to the first terminal of the eighth inductor; the second terminal of the seventh inductor is also connected to the output terminal of the second input matching network. The first terminal of the thirteenth capacitor and the first terminal of the third resistor are both connected to the second terminal of the eighth inductor. The second terminal of the thirteenth capacitor is connected to the second terminal of the third resistor; the second terminal of the thirteenth capacitor is also grounded.

7. The power amplifier according to claim 6, characterized in that, The second output matching network includes a fourteenth capacitor, a fifteenth capacitor, a sixteenth capacitor, a ninth inductor, and a fourth voltage source; The first terminal of the fourteenth capacitor and the first terminal of the ninth inductor are both connected to the input terminal of the second output matching network; the second terminal of the ninth inductor is connected to the positive terminal of the fourth voltage source; the negative terminal of the fourth voltage source is grounded. The second terminal of the fourteenth capacitor is connected to the first terminal of the fifteenth capacitor via a microstrip line of a second length; the first terminal of the fifteenth capacitor is also connected to the first terminal of the sixteenth capacitor via a microstrip line of a third length; the second terminal of the fifteenth capacitor is grounded; the first terminal of the sixteenth capacitor is also connected to the output terminal of the second output matching network; the second terminal of the sixteenth capacitor is grounded.

8. The power amplifier according to claim 1, characterized in that, The power divider includes a seventeenth capacitor, an eighteenth capacitor, a nineteenth capacitor, a tenth inductor, an eleventh inductor, and a fourth resistor; The first terminal of the seventeenth capacitor, the first terminal of the tenth inductor, and the first terminal of the eleventh inductor are all connected to the input terminal of the power divider; the second terminal of the seventeenth capacitor is grounded. The first terminal of the fourth resistor, the first terminal of the eighteenth capacitor, and the first output terminal of the power divider are all connected to the second terminal of the tenth inductor; the second terminal of the eighteenth capacitor is grounded. The second terminal of the fourth resistor, the first terminal of the nineteenth capacitor, and the second output terminal of the power divider are all connected to the second terminal of the eleventh inductor; the second terminal of the nineteenth capacitor is grounded.

9. The power amplifier according to claim 1, characterized in that, The drive amplifier includes a twelfth inductor, a thirteenth inductor, a fourteenth inductor, a fifteenth inductor, a sixteenth inductor, a twentieth capacitor, a twenty-first capacitor, a twenty-second capacitor, a twenty-third capacitor, a twenty-fourth capacitor, a fifth resistor, a sixth resistor, a sixth voltage source, a seventh voltage source, and a seventh transistor; The first terminal of the twelfth inductor and the first terminal of the twentieth capacitor are both connected to the input terminal of the drive amplifier; the second terminal of the twelfth inductor is grounded. The first terminal of the 21st capacitor and the first terminal of the 13th inductor are both connected to the second terminal of the 20th capacitor; the second terminal of the 21st capacitor is grounded; the second terminal of the 13th inductor is connected to the first terminal of the fifth resistor. The first terminal of the fourteenth inductor and the gate of the seventh transistor are both connected to the second terminal of the fifth resistor. The first terminal of the 22nd capacitor and the first terminal of the 6th resistor are both connected to the second terminal of the 14th inductor; the second terminal of the 6th resistor is connected to the positive terminal of the 5th voltage source; the second terminal of the 22nd capacitor is connected to the negative terminal of the 5th voltage source; the negative terminal of the 5th voltage source is grounded. The first terminal of the fifteenth inductor and the first terminal of the sixteenth inductor are both connected to the drain of the seventh transistor; the second terminal of the fifteenth inductor is connected to the positive terminal of the sixth voltage source; the negative terminal of the sixth voltage source is grounded; the source of the seventh transistor is grounded. The first terminal of the 23rd capacitor and the first terminal of the 24th capacitor are both connected to the second terminal of the 16th inductor; the second terminal of the 23rd capacitor is grounded; and the second terminal of the 24th capacitor is connected to the output terminal of the driver amplifier.

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