Amplifier MMIC with grid temperature compensation bias network and design method

Abstract

The invention discloses an amplifier MMIC with a grid temperature compensation bias network and a design method, and belongs to the technical field of microwave integrated circuits. The circuit comprises a grid bias module and an amplifier module. Wherein the grid bias module changes the magnitude of voltage output to the amplifier module through temperature characteristics of a resistor and a field effect transistor, the amplifier module compensates and realizes the change of quiescent current along with temperature through the temperature compensation characteristic of a main amplifier FET along with the voltage, and the function that the quiescent current of the amplifier is greatly reduced along with temperature fluctuation is realized. The grid temperature compensation biasing circuit suitable for the E technology can compensate the phenomenon that quiescent current fluctuation of an amplifier is too large along with temperature.

Description

Technical Field

[0001] This invention relates to the field of microwave integrated circuit technology, and in particular to an amplifier MMIC with a gate temperature compensated bias network and its design method. Background Technology

[0002] Designing amplifiers using gallium arsenide enhancement-mode (E-process) technology presents numerous challenges. For instance, in traditional designs, the gate bias circuit typically relies on a resistor divider. Since this divider provides a relatively constant voltage, the turn-on voltage changes with temperature fluctuations, leading to significant fluctuations in the quiescent current. This, in turn, causes variations in gain and power performance. In practical applications, it's desirable for the amplifier's quiescent current to remain stable within a defined range. Therefore, integrating the gate temperature compensation network and the amplifier itself can be a viable solution to address these issues. Summary of the Invention

[0003] The purpose of this invention is to overcome one or more shortcomings of existing amplifiers and provide an amplifier MMIC with a gate temperature compensated bias network and its design method.

[0004] The objective of this invention is achieved through the following technical solution:

[0005] An amplifier MMIC with a gate temperature-compensated bias network is disclosed. The amplifier MMIC includes a temperature-compensated bias circuit module and an amplifier circuit module. The temperature-compensated bias circuit module includes a first resistor, a second resistor, a third resistor, and a fourth resistor, a first field-effect transistor (FET), a second field-effect transistor (FET), and a third field-effect transistor (FET). The amplifier circuit module includes an E-process FET and a fourth FET, a first inductor, a second inductor, and a first capacitor. The gate of the first FET is connected to the third resistor, the drain of the first FET is connected to a DC power supply through the first resistor, and the source is grounded. The gate of the second FET is connected to its own source and to the drain of the first FET. The drain of the second FET is connected to a DC power supply through the second resistor, and the source of the second FET is connected to the first FET. The gates of the three field-effect transistors are connected together; the gate of the third field-effect transistor is connected to the source of the second field-effect transistor, and the source of the third field-effect transistor is connected to the gate of the fourth field-effect transistor in the amplifier circuit module through a fourth resistor to provide a bias voltage. The drain of the third field-effect transistor is connected to the DC power supply through a second resistor; one end of the first resistor is connected to the source of the first field-effect transistor, and the other end of the first resistor is connected to the DC power supply; one end of the second resistor is connected to the drains of the second and third field-effect transistors, and the other end of the second resistor is connected to the DC power supply; one end of the third resistor is connected to the gate of the first field-effect transistor, and the other end of the third resistor is connected to the drain of the first field-effect transistor; one end of the fourth resistor is connected to the source of the third field-effect transistor, and the other end of the fourth resistor is connected to the first inductor of the amplifier circuit module.

[0006] Furthermore, the gate of the fourth field-effect transistor is connected to the RF input terminal and also to the first inductor, the source is grounded, and the drain is connected to the RF output terminal and also to the second inductor; one end of the first inductor is connected to the fourth resistor of the temperature compensation bias circuit module, and the other end of the first inductor is connected to the gate of the fourth field-effect transistor; one end of the second inductor is connected to the DC power supply and also to the first capacitor, and the other end of the second inductor is connected to the drain of the fourth field-effect transistor; one end of the first capacitor is connected to the DC power supply, and the other end of the first capacitor is grounded.

[0007] Furthermore, the source of the third field-effect transistor in the temperature compensation bias circuit module is connected to the gate of the fourth field-effect transistor in the amplifier circuit module through the first inductor.

[0008] Furthermore, the DC power supply VDC is +5V.

[0009] Furthermore, the amplifier module uses a common-source topology as its basic structure. It achieves signal amplification by grounding the source of the fourth field-effect transistor, connecting its gate to the RF input port, and connecting its drain to the output port. It also achieves temperature-dependent regulation of the static operating current by connecting the gate of the fourth field-effect transistor through a temperature compensation network.

[0010] An amplifier MMIC design method with gate temperature compensation bias network is proposed, which introduces an active bias compensation network module into the gate bias circuit of the amplifier to compensate for the quiescent current of the circuit.

[0011] The beneficial effects of the present invention are:

[0012] (1) By using temperature-sensitive resistors and field-effect transistor voltage divider networks, the amplifier gate voltage is dynamically adjusted to counteract the effect of temperature on the threshold voltage of the field-effect transistor, significantly reducing the amplitude of static operating current fluctuation with temperature and improving the reliability of the circuit in a wide temperature environment.

[0013] (2) Based on a stable static operating point and optimized RF signal path design, it effectively suppresses gain drift caused by temperature changes, reduces system calibration requirements, and is suitable for microwave integrated circuit application scenarios with high gain stability requirements.

[0014] (3) The problem of large fluctuation range of the static operating point with temperature change during the design of amplifier using enhanced process is solved on a single chip, reducing the temperature sensitivity of the amplifier and maintaining the static operating current. Attached Figure Description

[0015] Figure 1 This embodiment provides a schematic diagram of a gate temperature compensated bias circuit amplifier MMIC and its design method.

[0016] Figure 2 The graph shows the linear gain effect as a function of frequency at various temperatures under traditional bias conditions.

[0017] Figure 3 The graph shows the linear gain effect of the MMIC and design method for the gate temperature compensated bias circuit amplifier proposed in this embodiment as a function of frequency at various temperatures.

[0018] Figure 1 In the diagram, there are: first resistor R1, second resistor R2, third resistor R3, fourth resistor R4, first field-effect transistor FET1, second field-effect transistor FET2, third field-effect transistor FET3, fourth field-effect transistor FET4, first inductor L1, second inductor L2, and first capacitor C1. Detailed Implementation

[0019] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] This embodiment discloses a gate temperature-compensated bias amplifier (MMIC) and its design method. The amplifier includes a temperature-compensated bias circuit module and an amplification module. The temperature-compensated bias circuit module controls the gate voltage of the amplification module according to temperature. The amplification module is connected between the RF input and RF output ports to realize the circuit's amplification function.

[0021] Example 1

[0022] See Figure 1 The temperature-compensated gate bias circuit module includes a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4, and three field-effect transistors (FETs) of process E: FET1, FET2, and FET3. The gate of FET1 is connected to the third resistor R3, and the drain of FET1 is connected to a DC power supply through the first resistor R1. The source of FET1 is grounded. The gate of FET2 is connected to its own source and to the drain of FET1. The drain of FET2 is connected to a DC power supply through the second resistor R2, and the source of FET2 is connected to the gate of FET3. The gate of FET3 is connected to the source of FET2. The source of FET3 provides a bias voltage, which is also provided by the fourth resistor R4. The gate of the fourth field-effect transistor FET4 in the amplifier circuit is connected to the DC power supply through the second resistor R2; one end of the first resistor R1 is connected to the source of FEF1, and the other end of the first resistor R1 is connected to the DC power supply; one end of the second resistor R2 is connected to the drain of FEF2 and the third field-effect transistor FET3, and the other end of the second resistor R2 is connected to the DC power supply; one end of the third resistor R3 is connected to the gate of the first field-effect transistor FET1, and the other end of the third resistor R3 is connected to the drain of the first field-effect transistor FET1; one end of the fourth resistor R4 is connected to the source of the third field-effect transistor FET3, and the other end of the fourth resistor R4 is connected to the first inductor L1 of the amplifier circuit module.

[0023] The temperature compensation module controls the gate voltage of the FET in the amplifier module by dividing the voltage of the temperature-sensitive resistor and the field-effect transistor, thereby changing the FET's quiescent operating current according to different temperatures.

[0024] The amplifier module includes an E-process fourth field-effect transistor (FET4), a first inductor L1, a second inductor L2, and a first capacitor C1. The gate of the fourth field-effect transistor FET4 is connected to the RF input terminal and also to the first inductor L1. The source of the fourth field-effect transistor FET4 is grounded. The drain of the fourth field-effect transistor FET4 is connected to the RF output terminal and also to the second inductor L2. One end of the first inductor L1 is connected to the source of the fourth resistor R4 in the temperature compensation bias circuit module, and the other end of the first inductor L1 is connected to the gate of the fourth field-effect transistor FET4. One end of the second inductor L2 is connected to the DC power supply and also to the first capacitor C1. The other end of the second inductor L2 is connected to the drain of the fourth field-effect transistor FET4. One end of the first capacitor C1 is connected to the DC power supply, and the other end of the first capacitor C1 is grounded.

[0025] The amplifier module includes field-effect transistors (FETs), choke inductors, and filter capacitors. The gate and drain of the FETs form the main amplifier path between the RF input and output ports, with the source grounded. Both the gate and drain of the FETs are connected to choke inductors to prevent RF signals from leaking to the power supply port, and the drain is connected to a ground capacitor to improve the power supply filtering effect of the circuit. The gate of the FET in the amplifier module is connected to the output of the temperature compensation module's bias network.

[0026] The bias amplifier with gate temperature compensation proposed in this embodiment is designed based on gallium arsenide process.

[0027] The DC power supply VDC is +5V.

[0028] The gate temperature compensated bias amplifier MMIC described in this embodiment operates at a frequency of 8-12 GHz, has a bandwidth of 4 GHz, a center point of 10 GHz, a relative bandwidth of 40%, a compensation range of -55℃ to 125℃, and a relative compensation of ≥10% for the static current. As shown in Table 1, the static operating current fluctuation range under the conventional bias network is 42-58 mA, while the static operating current fluctuation range under the temperature compensated bias network is 47-52 mA, which meets the characteristic that the static operating current can achieve temperature compensation.

[0029] Table 1. Comparison of quiescent operating currents at various temperatures for amplifiers with gate temperature compensation and those with conventional bias circuits under the same conditions.

[0030]

[0031] according to Figure 2 and Figure 3 The comparison shows that the gain fluctuation range of the amplifier under traditional bias conditions is ±0.65dB under high temperature, low temperature and normal temperature conditions, while the gain fluctuation range of the amplifier under high temperature and low temperature conditions with gate temperature compensation bias network is ±0.45dB, which meets the design requirements of temperature compensation.

[0032] Example 2

[0033] Resistors R1 and R2: Thin-film resistors with a temperature coefficient of ±100ppm / ℃, with a resistance range of 1kΩ to 10kΩ (specific values ​​need to be calculated based on the FET threshold voltage and target quiescent current). Resistor R3: Used to adjust the operating point of the first field-effect transistor FET1, with a recommended resistance value of 500Ω to 2kΩ. R4: Output bias resistor, with a resistance value determined based on the gate voltage requirements of the fourth field-effect transistor FET4 (e.g., 1kΩ to 5kΩ). Field-effect transistor (FET) parameters: First field-effect transistor FET1 to third field-effect transistor FET3: Gallium arsenide E-type process, threshold voltage Vth≈0.5V, transconductance gm≈200mS / mm. Fourth field-effect transistor FET4: Amplifier transistor, with dimensions designed according to target gain and power (e.g., gate width 100μm to 500μm). Inductors and capacitors: First inductor L1 and second inductor L2: RF choke inductors, with values ​​of 1nH to 10nH, using planar spiral inductors. First capacitor C1: Power supply filter capacitor, value 10pF~100pF, using MIM capacitor.

[0034] Temperature-compensated bias network design steps:

[0035] Utilizing the temperature characteristics of FETs, the threshold voltage Vth decreases with increasing temperature (approximately 2 mV / ℃), and the mobility μ decreases with increasing temperature (leading to a decrease in gm).

[0036] The resistor divider network design uses a combination of the first resistor R1, the second resistor R2, the third resistor R3, and the first field-effect transistors FET1 to FET3 to make the output voltage Vg change with temperature in the opposite direction to the change of Vth of the fourth field-effect transistor FET4, thereby offsetting the static current fluctuation.

[0037] Simulation optimization: Use ADS or Cadence software to build a circuit model and set the temperature scan range (-55℃~125℃); adjust the resistance values ​​of the first resistor R1~R4 so that the quiescent current of the fourth field-effect transistor FET4 fluctuates within ≤±5% within the target temperature range. Optimize the values ​​of the first inductor L1 and the second inductor L2 to ensure RF signal isolation, while the first capacitor C1 needs to be large enough to filter out power supply noise.

[0038] Typical performance parameters of the amplifier module (tested at 10 GHz) are shown in Table 2.

[0039] Table 2 Comparison of Traditional Bias Circuit and Temperature Compensated Bias Circuit Provided in the Embodiments

[0040]

[0041] Temperature compensation effect verification: At 55℃, the quiescent current decreased from 58mA to 52mA, and the gain fluctuation decreased by 30%. At +125℃, the quiescent current increased from 42mA to 47mA, and the gain fluctuation decreased by 30%.

[0042] Fabrication employs a 0.15μm GaAs pHEMT process, supporting high electron mobility and low noise characteristics. The metal layers consist of three layers (M1M3), with M3 used for the spiral inductor and interconnects.

[0043] Shorten the connection path between the gate of the fourth field-effect transistor (FET4) and the compensation network to reduce parasitic capacitance. The first power supply filter capacitor, C1, should be placed close to the drain of FET4 to reduce power supply noise coupling. The first spiral inductor, L1, and the second spiral inductor, L2, should be kept away from sensitive signal paths to avoid electromagnetic interference.

[0044] Implementation variations and improvements:

[0045] Variant 1: Source compensation combined with gate compensation: A negative temperature coefficient resistor (such as a thermistor) is connected in series with the source of the fourth field-effect transistor (FET4) to further suppress the effect of temperature on transconductance. The bias network parameters need to be re-optimized to balance the gate and source compensation effects.

[0046] Variant 2: Dynamic Temperature Compensation: Introduces a temperature sensor (such as a thermocouple) to monitor the ambient temperature in real time and adjusts the bias voltage through digital control. Suitable for high-precision applications, but increases circuit complexity and cost.

[0047] In this embodiment, the first field-effect transistor FET1 and the third resistor R3 form a negative feedback loop to stabilize the gate voltage of the second field-effect transistor FET2. The second and third field-effect transistors FET2 and FET3 act as current mirrors, converting temperature-sensitive current into voltage output to the gate of the fourth field-effect transistor FET4. When the temperature rises, the Vth of the fourth field-effect transistor FET4 decreases, and the compensation network increases the gate voltage through R4 to maintain quiescent current stability. The common-source structure offers advantages such as high input impedance and low output impedance, making it suitable for cascaded amplification. The drain choke inductor, the second inductor L2, improves output matching and reduces power loss.

[0048] By supplementing component parameters, design steps, experimental data, and process details, this embodiment further clarifies the implementation method and advantages of the temperature-compensated bias network. Through a temperature-sensitive resistor and MOSFET voltage divider network, the amplifier gate voltage is dynamically adjusted to counteract the effect of temperature on the MOSFET threshold voltage, significantly reducing the amplitude of quiescent current fluctuations with temperature and improving circuit reliability in a wide temperature range. Based on a stable quiescent operating point and optimized RF signal path design, it effectively suppresses gain drift caused by temperature changes, reduces system calibration requirements, and is suitable for microwave integrated circuit applications with high gain stability requirements.

[0049] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. An amplifier MMIC with a gate temperature compensated bias network, characterized in that, The amplifier MMIC includes a temperature-compensated bias circuit module and an amplifier circuit module. The temperature-compensated bias circuit module includes a first resistor, a second resistor, a third resistor, and a fourth resistor, a first field-effect transistor (FET), a second field-effect transistor (FET), and a third field-effect transistor (FET). The amplifier circuit module includes an E-process FET and a fourth FET, a first inductor, a second inductor, and a first capacitor. The gate of the first FET is connected to the third resistor, the drain of the first FET is connected to a DC power supply through the first resistor, and the source is grounded. The gate of the second FET is connected to its own source and to the drain of the first FET. The drain of the second FET is connected to a DC power supply through the second resistor, and the source of the second FET is connected to the gate of the third FET. The gate of the third field-effect transistor is connected to the source of the second field-effect transistor. The source of the third field-effect transistor is connected to the gate of the fourth field-effect transistor in the amplifier circuit module through a fourth resistor to provide a bias voltage. The drain of the third field-effect transistor is connected to the DC power supply through a second resistor. One end of the first resistor is connected to the source of the first field-effect transistor, and the other end of the first resistor is connected to the DC power supply. One end of the second resistor is connected to the drain of the second and third field-effect transistors, and the other end of the second resistor is connected to the DC power supply. One end of the third resistor is connected to the gate of the first field-effect transistor, and the other end of the third resistor is connected to the drain of the first field-effect transistor; one end of the fourth resistor is connected to the source of the third field-effect transistor, and the other end of the fourth resistor is connected to the first inductor of the amplifier circuit module.

2. The amplifier MMIC with gate temperature compensated bias network according to claim 1, characterized in that, The gate of the fourth field-effect transistor is connected to the RF input terminal and also to the first inductor. Its source is grounded, and its drain is connected to the RF output terminal and also to the second inductor. One end of the first inductor is connected to the fourth resistor of the temperature compensation bias circuit module, and the other end of the first inductor is connected to the gate of the fourth field-effect transistor. One end of the second inductor is connected to the DC power supply and also to the first capacitor, and the other end of the second inductor is connected to the drain of the fourth field-effect transistor. One end of the first capacitor is connected to the DC power supply, and the other end of the first capacitor is grounded.

3. An amplifier MMIC with a gate temperature compensated bias network according to claim 1 or 2, characterized in that, The source of the third field-effect transistor in the temperature compensation bias circuit module is connected to the gate of the fourth field-effect transistor in the amplifier circuit module through the first inductor.

4. The amplifier MMIC with gate temperature compensated bias network according to claim 1, characterized in that, The DC power supply VDC is +5V.

5. An amplifier MMIC with a gate temperature compensated bias network according to claim 1 or 2, characterized in that, The amplifier module uses a common-source topology as its basic structure. It achieves signal amplification by grounding the source of a fourth field-effect transistor, connecting the gate to the RF input port, and connecting the drain to the output port.

6. A method for designing an amplifier MMIC with a gate temperature compensated bias network, characterized in that, An active bias compensation network module is introduced into the gate bias circuit of the amplifier to compensate for the quiescent current of the circuit.

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