Method for improving height difference between NMOS and PMOS, semiconductor structure and device

Abstract

The invention belongs to the technical field of semiconductors, and particularly relates to a method for improving the height difference of an NMOS (N-channel Metal Oxide Semiconductor) and a PMOS (P-channel Metal Oxide Semiconductor), a semiconductor structure and a device, which comprises the following steps of: providing an intermediate product which comprises a PMOS region and an NMOS region, and forming a polycrystalline silicon gate structure and a first oxide layer covering the polycrystalline silicon gate structure on each of the PMOS region and the NMOS region, the polycrystalline silicon gate structure comprises a gate polycrystalline silicon layer, a hard mask layer, a silicon oxide layer and a silicon nitride layer which are sequentially formed from inside to outside; grinding the first oxide layer to enable the surface of the first oxide layer to be flush; thinning the remaining first oxide layer to expose the top of the silicon nitride layer; etching to remove the top of the silicon nitride layer and a part of the side wall so as to expose the top of the silicon oxide layer; and thinning the remaining first oxide layer, and removing the silicon oxide layer and the top of the hard mask layer until the top surface of the gate polycrystalline silicon layer is reached. According to the invention, the height difference between the NMOS region and the PMOS region is effectively reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and specifically to a method for improving the height difference between NMOS and PMOS, a semiconductor structure, and a device. Background Technology

[0002] In modern semiconductor manufacturing processes, especially in the fabrication of high-performance complementary metal-oxide-semiconductor (CMOS) devices, precise control of material removal and deposition at each process step is crucial. Among these, EPI (epitaxy growth) dry etching technology is widely used to define key transistor features, such as the gate structure. However, this technology also faces a series of challenges in its implementation.

[0003] Specifically, during EPI dry etching, specific regions typically need to be selectively covered or exposed depending on the device type (NMOS (N-type metal-oxide-semiconductor) or PMOS (P-type metal-oxide-semiconductor)). For example, in the N-cover, P-open (covering the N-type region with a protective layer while processing the P-type region) process step, the aim is to protect the NMOS region while etching the PMOS region. However, this process may result in partial loss of oxide in the PMOS region due to non-ideal factors during etching, such as improper etching rate control, mask alignment errors, or uneven etching depth.

[0004] The loss of the first oxide layer introduces a height difference between the PMOS and NMOS regions (e.g., a height difference exists between the silicon oxide layers 3 in the two polysilicon gate structures, see [reference]). Figure 1 This height difference has a significant impact on the subsequent ILD0 (first interlayer dielectric) CMP (chemical mechanical polishing) step. ILD0 CMP aims to planarize the wafer surface, providing a uniform substrate for subsequent multilayer metallization and interconnect structures. However, due to the inconsistency in oxide height between the NMOS and PMOS regions, this height difference causes different N / P loading in ILD0 CMP, resulting in PMOS inheriting a lower height than NMOS. During ILD0 CMP, if the bottom film height is inconsistent, the etching rate differs during polishing. When the loading effect during CMP is significant, it not only affects surface uniformity but also leads to differences in gate height between NMOS and PMOS. This height difference directly affects the transistor's electrical performance, such as threshold voltage, leakage current, and transconductance, thus adversely impacting the overall performance and reliability of the CMOS device.

[0005] Therefore, it is necessary to develop a new method, semiconductor structure, and device to improve the height difference between NMOS and PMOS. Summary of the Invention

[0006] The purpose of this invention is to provide a method, semiconductor structure, and device for improving the height difference between NMOS and PMOS regions, so as to reduce the height difference between the NMOS and PMOS regions.

[0007] In a first aspect, the method for improving the height difference between NMOS and PMOS according to the present invention includes the following steps: Step 1. Provide an intermediate product, the intermediate product including at least a PMOS region and an NMOS region, a polysilicon gate structure and a first oxide layer covering the polysilicon gate structure are formed on the PMOS region and the NMOS region, the polysilicon gate structure including a gate polysilicon layer, a hard mask layer, a silicon oxide layer and a silicon nitride layer formed sequentially from the inside to the outside; Step 2. Perform a grinding process to grind the first oxide layer until the surface of the first oxide layer is flush; Step 3. Perform an etching process to thin the remaining first oxide layer to expose the top of the silicon nitride layer; Step 4. Perform an etching process to remove a portion of the top and sidewalls of the silicon nitride layer to expose the top of the silicon oxide layer; Step 5. Perform a polishing process to thin the remaining first oxide layer and remove the top of the silicon oxide layer and the hard mask layer until the top surface of the gate polysilicon layer is reached.

[0008] Optionally, the hard mask layer covers the outside of the gate polysilicon layer, the silicon oxide layer covers the outside of the hard mask layer, and the silicon nitride layer covers the outside of the silicon oxide layer.

[0009] Secondly, the semiconductor structure of the present invention includes an intermediate product, which is manufactured using the method for improving the height difference between NMOS and PMOS as described in the present invention.

[0010] Thirdly, the semiconductor device described in this invention employs the semiconductor structure described in this invention.

[0011] Fourthly, the method for improving the height difference between NMOS and PMOS according to the present invention includes the following steps: Step 1. Provide an intermediate product, the intermediate product including at least a PMOS region and an NMOS region, a polysilicon gate structure and a first oxide layer covering the polysilicon gate structure are formed on the PMOS region and the NMOS region, the polysilicon gate structure including a gate polysilicon layer, a hard mask layer, a silicon oxide layer and a silicon nitride layer formed sequentially from the inside to the outside; Step 2. Perform a grinding process to grind the first oxide layer until the surface of the first oxide layer is flush; Step 3. Perform an etching process to thin the remaining first oxide layer to expose the top of the silicon nitride layer; Step 4. Perform an etching process to remove a portion of the top and sidewalls of the silicon nitride layer to expose the top of the silicon oxide layer; Step 5. Perform a polishing process to thin the remaining first oxide layer and remove the top of the silicon oxide layer to expose the hard mask layer; Step 6. Perform an etching process to remove the top of the hard mask layer and remove part of the sidewalls of the silicon nitride layer, silicon oxide layer and hard mask layer to expose the top surface of the gate polysilicon layer; Step 7. Perform a polishing process to thin the remaining first oxide layer until the top surface of the gate polysilicon layer is reached.

[0012] This method makes the polishing results more controllable, which helps to obtain a more uniform and flat surface when polishing to the top of the gate polysilicon layer. In addition, due to the greater precision in removing each layer, the risk of damage to the gate polysilicon layer caused by over-polishing or etching is reduced, thereby improving product reliability.

[0013] Optionally, in step 7, a second oxide layer is deposited on top of the gate polysilicon layer before performing the polishing process. After step 6 is completed, this method adds a crucial step: depositing a thin second oxide layer. This oxide deposition does not need to be too thick; its main purpose is to facilitate subsequent polishing operations. Considering that the first oxide layer may be damaged during the previous dry etching step, resulting in insufficient retention, direct polishing might increase control difficulty and affect process accuracy. Therefore, by depositing this thin second oxide layer, the difficulty of the polishing process can be effectively alleviated, making planarization easier to achieve, thereby ensuring the stability and controllability of the entire process flow.

[0014] Optionally, the second oxide layer is made of the same material as the first oxide layer. Using the same material helps reduce CMP loading.

[0015] Optionally, the hard mask layer covers the outside of the gate polysilicon layer, the silicon oxide layer covers the outside of the hard mask layer, and the silicon nitride layer covers the outside of the silicon oxide layer.

[0016] Fifthly, the semiconductor structure of the present invention includes an intermediate product, which is manufactured using the method for improving the height difference between NMOS and PMOS as described in the present invention.

[0017] Sixthly, the semiconductor device of the present invention employs the semiconductor structure described in the present invention.

[0018] The unexpected beneficial effects of this invention are as follows: (1) No need to modify the layout of integrated semiconductors, effectively adjusting the height difference between NMOS and PMOS: This method, through a combination of chemical mechanical polishing (CMP) and dry etching, can precisely adjust the height difference between NMOS and PMOS regions without altering the existing layout. This technology not only simplifies the manufacturing process but also avoids the design complexity and cost increases that can result from modifying the semiconductor layout, thereby significantly improving production efficiency and product yield.

[0019] (2) Reduce graphics load and optimize ILD0 CMP process: This invention effectively reduces the impact of pattern load on the ILD0 (first dielectric layer) CMP process by optimizing the process and employing advanced CMP technology. This not only reduces non-uniformity and scratches during CMP, but also improves the flatness and consistency of the ILD0 layer, providing a more reliable foundation for subsequent transistor manufacturing and interconnection.

[0020] (3) Simplify the process and reduce the cost of photomasks and processes: This invention eliminates the traditional PREB (pre-exposure baking) process, thereby reducing the number of photomasks and process steps. This change not only simplifies the production process but also significantly reduces manufacturing and time costs. Furthermore, by avoiding the errors and uncertainties that may be introduced by the PREB process, product quality and reliability are further improved.

[0021] (4) Eliminate the height difference between NMOS and PMOS to improve the uniformity of CMP grinding: By employing two CMP processes and a high-selectivity OX / SIN (silicon oxide / nitride) dry etching technique, the multilayer structure at the top of the gate is completely removed, thereby eliminating the height difference between NMOS and PMOS caused by the EPI (epitaxy) process. This technology not only improves transistor performance and consistency but also further reduces the loading effect during the CMP process by unifying the CMP polishing layer, thus improving the uniformity and precision of the polishing process.

[0022] In summary, this invention achieves multiple technical benefits without altering the layout by combining CMP with dry etching, optimizing the CMP process, simplifying process steps, and improving grinding uniformity. These benefits include precisely adjusting the height difference between NMOS and PMOS, reducing pattern load, optimizing the ILD0 CMP process, reducing manufacturing and time costs, and improving product quality and reliability. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a semiconductor structure in the prior art where there is a height difference between NMOS and PMOS; Figure 2 This is a flowchart of the method for improving the height difference between NMOS and PMOS as described in Example 1; Figure 3 This is a schematic diagram of the structure of the intermediate product described in the embodiments of this application; Figure 4 These are schematic diagrams of the structures after step 2 has been performed in Examples 1 to 3; Figure 5 These are schematic diagrams of the structures after step 3 is completed in Examples 1 to 3; Figure 6 This is a schematic diagram of the structure after step 4 is performed in Examples 1 to 3; Figure 7 These are schematic diagrams showing the structures after step 5 in Example 1, and after step 7 in Examples 2 and 3. Figure 8 This is a flowchart of the method for improving the height difference between NMOS and PMOS as described in Example 2; Figure 9 This is a schematic diagram of the structure after step 5 is performed in Examples 2 and 3; Figure 10 This is a schematic diagram of the structure after step 6 is completed in Examples 2 and 3; Figure 11 This is a flowchart of the method for improving the height difference between NMOS and PMOS as described in Example 3; Figure 12 This is a schematic diagram of the structure after an oxide layer is deposited in step 7 of Example 3; In the figure: 1-first oxide layer, 2-silicon nitride layer, 3-silicon oxide layer, 4-hard mask layer, 5-gate polysilicon layer, 6-second oxide layer. Detailed Implementation

[0024] The embodiments of the present invention will be described below with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention and not for limiting the scope of protection of the present invention.

[0025] Example 1 like Figure 2 As shown, a method for improving the height difference between NMOS and PMOS transistors achieves height adjustment without altering the existing layout, simplifying the manufacturing process and improving production efficiency and product yield. The method includes the following steps: Step 1. Provide an intermediate product (i.e., from wafer preparation to polysilicon gate structure formation, at which point the gate of the transistor device is not yet fully formed). The intermediate product includes at least a PMOS region and an NMOS region. A polysilicon gate structure and a first oxide layer 1 covering the polysilicon gate structure are formed on both the PMOS and NMOS regions. The polysilicon gate structure includes a gate polysilicon layer 5, a hard mask layer 4, a silicon oxide layer 3, and a silicon nitride layer 2, formed sequentially from the inside out. See also... Figure 3 In this process, a hard mask layer 4 covers the outside of the gate polysilicon layer 5, a silicon oxide layer 3 covers the outside of the hard mask layer 4, and a silicon nitride layer 2 covers the outside of the silicon oxide layer 3.

[0026] Step 2. Perform a polishing process to polish the first oxide layer 1 until its surface is flush. See [link to relevant documentation]. Figure 4 The grinding process ensures the uniformity and precision of the grinding process.

[0027] Step 3. Perform an etching process to thin the remaining first oxide layer 1 to expose the top of the silicon nitride layer 2. See [link to etching process]. Figure 5 By utilizing the high selectivity etching of oxides, the etching rate of oxides is ensured to be higher than that of other materials, thus protecting non-oxide materials.

[0028] Step 4. Perform an etching process to remove a portion of the top and sidewalls of silicon nitride layer 2 (with a certain amount of OE (over-etching), where OE refers to the amount of additional etching performed after the main etching target has been achieved to ensure complete removal of all target material) to expose the top of silicon oxide layer 3. See [link to relevant documentation]. Figure 6 By utilizing the high selectivity of SIN etching, a higher etching rate for silicon nitride compared to other materials is ensured, effectively removing the silicon nitride layer while reducing the etching impact on other materials.

[0029] Step 5. Perform a polishing process to thin the remaining first oxide layer 1, and remove the top of the silicon oxide layer 3 and the hard mask layer 4 until the top surface of the gate polysilicon layer 5 is reached. See [link to relevant documentation]. Figure 7 This ensures highly precise control.

[0030] In this embodiment, the etching process is a dry etching process.

[0031] In this embodiment, the grinding process employs chemical mechanical polishing.

[0032] In one possible embodiment, the hard mask layer is made of silicon nitride.

[0033] This method, through a combination of chemical mechanical polishing and dry etching, can precisely adjust the height difference between NMOS and PMOS regions without altering the existing layout. This technology not only simplifies the manufacturing process but also avoids the design complexity and cost increases that can result from modifying the semiconductor layout, thereby significantly improving production efficiency and product yield.

[0034] This method effectively reduces the impact of patterning load on the ILD0 CMP process by optimizing the process and employing advanced CMP technology. This not only reduces non-uniformity and scratches during CMP, but also improves the flatness and consistency of the ILD0 layer, providing a more reliable foundation for subsequent transistor manufacturing and interconnection.

[0035] This method eliminates the traditional PREB process, thereby reducing the number of photomasks and process steps. This change not only simplifies the production process but also significantly reduces manufacturing and time costs. Furthermore, by avoiding the errors and uncertainties that may be introduced by the PREB process, product quality and reliability are further improved.

[0036] This method, through two CMP processes and a high-selectivity OX / SIN dry etching technique, can completely remove the multilayer structure on top of the gate, thereby eliminating the height difference between the NMOS and PMOS regions caused by the EPI process. This technique not only improves transistor performance and consistency, but also further reduces the loading effect during the CMP process by using a single CMP polishing layer, thus improving the uniformity and precision of the polishing process.

[0037] In this first embodiment, a semiconductor structure includes an intermediate product, which is manufactured using the method for improving the height difference between NMOS and PMOS as described in this first embodiment.

[0038] In this first embodiment, a semiconductor device adopts the semiconductor structure as shown in this first embodiment.

[0039] Example 2 like Figure 8 As shown, a method for improving the height difference between NMOS and PMOS transistors achieves height adjustment without altering the existing layout, simplifying the manufacturing process and improving production efficiency and product yield. The method includes the following steps: Step 1. Provide an intermediate product (i.e., from wafer preparation to polysilicon gate structure formation, at which point the gate of the transistor device is not yet fully formed). The intermediate product includes at least a PMOS region and an NMOS region. Polysilicon gate structures are formed on both the PMOS and NMOS regions. The polysilicon gate structure includes a gate polysilicon layer 5, a hard mask layer 4 covering the gate polysilicon layer 5, a silicon oxide layer 3 covering the hard mask layer 4, and a silicon nitride layer 2 covering the silicon oxide layer 3. A first oxide layer 1 is covered outside the silicon nitride layer 2. See [link to relevant documentation]. Figure 3 .

[0040] Step 2. Perform a polishing process to polish the first oxide layer 1 until its surface is flush. See [link to relevant documentation]. Figure 4 .

[0041] Step 3. Perform an etching process to thin the remaining first oxide layer 1 to expose the top of the silicon nitride layer 2. See [link to etching process]. Figure 5 By utilizing the high selectivity etching of oxides, the etching rate of oxides is ensured to be higher than that of other materials, thus protecting non-oxide materials.

[0042] Step 4. Perform an etching process to remove a portion of the top and sidewalls of silicon nitride layer 2 (with a certain amount of OE (over-etching), where OE refers to the amount of additional etching performed after the main etching target has been achieved to ensure complete removal of all target material) to expose the top of silicon oxide layer 3. See [link to relevant documentation]. Figure 6 By utilizing the high selectivity of SIN etching, a higher etching rate for silicon nitride compared to other materials is ensured, effectively removing the silicon nitride layer while reducing the etching impact on other materials.

[0043] Step 5. Perform a polishing process to thin the remaining first oxide layer 1 and remove the top of the silicon oxide layer 3 to expose the hard mask layer 4. See [link to relevant documentation]. Figure 9 .

[0044] Step 6. Perform an etching process to remove the top of the hard mask layer 4 and part of the sidewalls of the silicon nitride layer 2 and silicon oxide layer 3 to expose the top surface of the gate polysilicon layer 5. See [link to relevant documentation]. Figure 10 .

[0045] Step 7. Perform a polishing process to thin the remaining first oxide layer 1 until the top surface of the gate polysilicon layer 5 is reached. See [link to relevant documentation]. Figure 7 .

[0046] Compared to Example 1, the method described in Example 2 employs more steps in removing each layer (i.e., step 5 in Example 1 is broken down into three steps, namely steps 5 to 7 in Example 2). The advantage of this breakdown is that it allows for greater control over the polishing results, which helps to obtain a more uniform and flat surface when finally polishing to the top of the gate polysilicon layer. Furthermore, because the removal of each layer is more precise, the risk of damage to the gate polysilicon layer due to over-polishing or etching is reduced, thereby improving product reliability.

[0047] In this second embodiment, the etching process adopts a dry etching process, and the polishing process adopts a chemical mechanical polishing process.

[0048] In this second embodiment, a semiconductor structure includes an intermediate product, which is manufactured using the method for improving the height difference between NMOS and PMOS as described in this second embodiment.

[0049] In this second embodiment, a semiconductor device adopts the semiconductor structure shown in this second embodiment.

[0050] Example 3 like Figure 11 As shown, a method for improving the height difference between NMOS and PMOS transistors achieves height adjustment without altering the existing layout, simplifying the manufacturing process and improving production efficiency and product yield. The method includes the following steps: Step 1. Provide an intermediate product (i.e., from wafer preparation to polysilicon gate structure formation, at which point the gate of the transistor device is not yet fully formed). The intermediate product includes at least a PMOS region and an NMOS region. Polysilicon gate structures are formed on both the PMOS and NMOS regions. The polysilicon gate structure includes a gate polysilicon layer 5, a hard mask layer 4 covering the gate polysilicon layer 5, a silicon oxide layer 3 covering the hard mask layer 4, and a silicon nitride layer 2 covering the silicon oxide layer 3. A first oxide layer 1 is covered outside the silicon nitride layer 2. See [link to relevant documentation]. Figure 3 .

[0051] Step 2. Perform a polishing process to polish the first oxide layer 1 until its surface is flush. See [link to relevant documentation]. Figure 4 .

[0052] Step 3. Perform an etching process to thin the remaining first oxide layer 1 to expose the top of the silicon nitride layer 2. See [link to etching process]. Figure 5 By utilizing the high selectivity etching of oxides, the etching rate of oxides is ensured to be higher than that of other materials, thus protecting non-oxide materials.

[0053] Step 4. Perform an etching process to remove a portion of the top and sidewalls of silicon nitride layer 2 (with a certain amount of OE (over-etching), where OE refers to the amount of additional etching performed after the main etching target has been achieved to ensure complete removal of all target material) to expose the top of silicon oxide layer 3. See [link to relevant documentation]. Figure 6 By utilizing the high selectivity of SIN etching, a higher etching rate for silicon nitride compared to other materials is ensured, effectively removing the silicon nitride layer while reducing the etching impact on other materials.

[0054] Step 5. Perform a polishing process to thin the remaining first oxide layer 1 and remove the top of the silicon oxide layer 3 to expose the hard mask layer 4. See [link to relevant documentation]. Figure 9 .

[0055] Step 6. Perform an etching process to remove the top of the hard mask layer 4 and part of the sidewalls of the silicon nitride layer 2 and silicon oxide layer 3 to expose the top surface of the gate polysilicon layer 5. See [link to relevant documentation]. Figure 10 .

[0056] Step 7. Deposit a second oxide layer 6 above the gate polysilicon layer 5, see below. Figure 12 Then perform a polishing process until the top surface of the gate polysilicon layer 5 is reached. See [link to relevant documentation]. Figure 7 .

[0057] In this third embodiment, after step 6 is completed, the method described in this third embodiment adds a crucial step compared to the method described in the second embodiment: depositing a thin second oxide layer 6. This oxide deposition does not need to be too thick; its main purpose is to facilitate subsequent polishing operations. Considering that the first oxide layer 1 may be damaged during the previous dry etching step, resulting in insufficient retention, direct polishing might increase the difficulty of control and affect process accuracy. Therefore, by depositing this thin second oxide layer 6, the difficulty of the polishing process can be effectively alleviated, making the planarization process easier to achieve, thereby ensuring the stability and controllability of the entire process flow.

[0058] In this third embodiment, the second oxide layer 6 is made of the same material as the first oxide layer 1, such as silicon dioxide, which can reduce CMP loading.

[0059] In this third embodiment, the etching process adopts a dry etching process, and the grinding process adopts a chemical mechanical polishing process.

[0060] In this third embodiment, a semiconductor structure includes an intermediate product, which is manufactured using the method for improving the height difference between NMOS and PMOS as described in this third embodiment.

[0061] In this third embodiment, a semiconductor device adopts the semiconductor structure shown in this third embodiment.

[0062] This invention achieves multiple technical benefits by using innovative grinding and etching processes, optimizing grinding processes, simplifying process steps, and improving grinding uniformity. These benefits include precisely adjusting the height difference between NMOS and PMOS without changing the semiconductor layout, reducing pattern load, optimizing the ILD0 CMP process, reducing manufacturing and time costs, and improving product quality and reliability.

[0063] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A method for improving the height difference between NMOS and PMOS, characterized in that, Includes the following steps: Step 1. Provide an intermediate product, the intermediate product including at least a PMOS region and an NMOS region, a polysilicon gate structure and a first oxide layer (1) covering the polysilicon gate structure are formed on the PMOS region and the NMOS region, the polysilicon gate structure including a gate polysilicon layer (5), a hard mask layer (4), a silicon oxide layer (3) and a silicon nitride layer (2) formed sequentially from the inside to the outside. Step 2. Perform a grinding process to grind the first oxide layer (1) until the surface of the first oxide layer (1) is flush; Step 3. Perform an etching process to thin the remaining first oxide layer (1) to expose the top of the silicon nitride layer (2); Step 4. Perform an etching process to remove a portion of the top and sidewalls of the silicon nitride layer (2) to expose the top of the silicon oxide layer (3); Step 5. Perform a polishing process to thin the remaining first oxide layer (1) and remove the top of the silicon oxide layer (3) and the hard mask layer (4) until the top surface of the gate polysilicon layer (5) is reached.

2. The method for improving the height difference between NMOS and PMOS according to claim 1, characterized in that, The hard mask layer (4) covers the outside of the gate polysilicon layer (5), the silicon oxide layer (3) covers the outside of the hard mask layer (4), and the silicon nitride layer (2) covers the outside of the silicon oxide layer (3).

3. A semiconductor structure, characterized in that: Includes intermediate products, which are manufactured using the method for improving the height difference between NMOS and PMOS as described in claim 1 or 2.

4. A semiconductor device, characterized in that... The semiconductor structure described in claim 3 is adopted.

5. A method for improving the height difference between NMOS and PMOS, characterized in that, Includes the following steps: Step 1. Provide an intermediate product, the intermediate product including at least a PMOS region and an NMOS region, a polysilicon gate structure and a first oxide layer (1) covering the polysilicon gate structure are formed on the PMOS region and the NMOS region, the polysilicon gate structure including a gate polysilicon layer (5), a hard mask layer (4), a silicon oxide layer (3) and a silicon nitride layer (2) formed sequentially from the inside to the outside. Step 2. Perform a grinding process to grind the first oxide layer (1) until the surface of the first oxide layer (1) is flush; Step 3. Perform an etching process to thin the remaining first oxide layer (1) to expose the top of the silicon nitride layer (2); Step 4. Perform an etching process to remove a portion of the top and sidewalls of the silicon nitride layer (2) to expose the top of the silicon oxide layer (3); Step 5. Perform a polishing process to thin the remaining first oxide layer (1) and remove the top of the silicon oxide layer (3) to expose the hard mask layer (4). Step 6. Perform an etching process to remove the top of the hard mask layer (4) and remove part of the sidewalls of the silicon nitride layer (2) and silicon oxide layer (3) to expose the top surface of the gate polysilicon layer (5); Step 7. Perform a polishing process to thin the remaining first oxide layer (1) until the top surface of the gate polysilicon layer (5) is reached.

6. The method for improving the height difference between NMOS and PMOS according to claim 5, characterized in that: In step 7, before performing the polishing process, a second oxide layer (6) is deposited on top of the gate polysilicon layer (5).

7. The method for improving the height difference between NMOS and PMOS according to claim 6, characterized in that... The second oxide layer (6) is made of the same material as the first oxide layer (1).

8. The method for improving the height difference between NMOS and PMOS according to claim 5, characterized in that, The hard mask layer (4) covers the outside of the gate polysilicon layer (5), the silicon oxide layer (3) covers the outside of the hard mask layer (4), and the silicon nitride layer (2) covers the outside of the silicon oxide layer (3).

9. A semiconductor structure, characterized in that: Includes intermediate products, which are manufactured using the method for improving the height difference between NMOS and PMOS as described in any one of claims 5 to 8.

10. A semiconductor device, characterized in that... The semiconductor structure described in claim 9 is adopted.

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