Memory system boot sequence with reduced latency

Abstract

The invention relates to a memory system boot sequence with reduced latency. A host system may assert a signal (e.g., a fast boot signal) to a pin of a memory system, which may instruct the memory system to communicate data at a first data rate (e.g., a relatively lower data rate) prior to negotiating to a higher data rate (e.g., a highest data rate). The host system may output the fast boot signal to the memory system based on an estimated size of the data to be transferred, a dynamic measurement of the data, an application associated with the data, or any combination thereof. Based on transferring the data, the host system and the memory system may negotiate to an increased data rate (e.g., up to a highest supported data rate).

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 19 / 170,636, filed April 4, 2025, entitled "Memory System Boot Sequence with Reduced Latency," and U.S. Patent Application No. 63 / 640,777, filed April 30, 2024, entitled "Memory System Boot Sequence with Reduced Latency," each of which is assigned to its assignee and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to boot sequences for memory systems with reduced latency. Background Technology

[0004] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access stored information, the memory device can read (e.g., sense, detect, retrieve, determine) the state from the memory cell. To store information, the memory device can write (e.g., program, set, assign) states to the memory cell.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), self-select memory, chalcogenide memory technology, NOR and NAND memory devices, and others. Memory cells can be described according to volatile or non-volatile configurations. Memory cells configured as non-volatile can maintain their stored logic state for a long time, even without external power. Memory cells configured as volatile will lose their stored state when disconnected from external power. Summary of the Invention

[0006] A method performed by a memory system is described. The method may include: initiating a startup sequence to transition the memory system from a first power state to a second power state; receiving first signaling from a host system based on initiating the startup sequence to indicate that the startup sequence is a first type of sequence associated with lower latency; performing first data communication with the host system at a first data rate based on receiving the first signaling; and increasing the rate used for communication with the host system from the first data rate to a second data rate after transmitting the first data, wherein the first data rate is slower than the second data rate when used for communication with the host system.

[0007] A non-transitory computer-readable medium is described, which stores code. The code may contain instructions executable by one or more processors to: initiate a boot sequence to transition a memory system from a first power state to a second power state; receive first signaling from a host system based on initiating the boot sequence to indicate that the boot sequence is a first type of sequence associated with lower latency; perform first data communication with the host system at a first data rate based on receiving the first signaling; and, after transmitting the first data, increase the rate used for communication with the host system from the first data rate to a second data rate, wherein the first data rate is slower than the second data rate when used for communication with the host system.

[0008] A memory system is described. The memory system may include: one or more memory devices; and a processing circuitry system coupled to and configured to cause the memory system to: initiate a startup sequence to transition the memory system from a first power state to a second power state; receive first signaling from a host system based on initiating the startup sequence to indicate that the startup sequence is a first type of sequence associated with lower latency; perform first data communication with the host system at a first data rate based on receiving the first signaling; and, after transmitting the first data, increase the rate used for communication with the host system from the first data rate to a second data rate, wherein the first data rate is slower than the second data rate when used for communication with the host system. Attached Figure Description

[0009] Figure 1 Examples of systems that support memory system boot sequences with reduced latency, based on the examples disclosed herein, are presented.

[0010] Figure 2 Examples of systems that support memory system boot sequences with reduced latency, based on the examples disclosed herein, are presented.

[0011] Figure 3 Examples of process flowcharts demonstrating support for memory system boot sequences with reduced latency, based on the examples disclosed herein.

[0012] Figure 4 A block diagram is shown illustrating a memory system that supports a memory system boot sequence with reduced latency, based on examples disclosed herein.

[0013] Figure 5 The flowchart illustrates one or more methods for supporting memory system boot sequences with reduced latency, based on the examples disclosed herein. Detailed Implementation

[0014] The host system and memory system can support different data rates for transferring data between the host system and the memory system. In such instances, the host system and memory system can negotiate a data rate supported by both systems (e.g., the highest data rate). For example, the host system and memory system can negotiate the data rate in response to the memory system transitioning from a first power state to a second power state (e.g., upon power-on, after a boot sequence, or after exiting sleep mode). In some instances, the negotiation between the host system and memory system can be based on the latency of the boot sequence caused by increasing the data rate through a defined sequence. For example, a memory system supporting a relatively high data rate can negotiate an initial data rate and then negotiate the next data rate before negotiating a relatively high data rate (e.g., the highest supported data rate). Some applications (e.g., time-sensitive applications) can benefit from a faster boot sequence, where the host system accesses data from the memory system to initialize the application without the latency caused by negotiating the highest data rate.

[0015] The systems, methods, and techniques described herein support host system assertions (e.g., fast boot signals) to instruct the memory system to start and transmit data at a first data rate (e.g., a relatively low data rate) before negotiating a higher data rate. This process allows low-latency dependent applications to initialize quickly after starting at the first data rate. Subsequently, a second data rate can be configured after the low-latency dependent application completes its task. For example, the host system can assert a fast boot signal to a pin of the memory system, which instructs the memory system to start and initially transmit data at the lowest supported data rate. In some instances, the host system can output the fast boot signal based on an estimated size of the data to be transmitted, dynamic measurements of the data, the application associated with the data, or any combination thereof. Based on the transmitted data, the host system and the memory system can negotiate a higher data rate (e.g., up to the highest supported data rate) as part of the startup sequence. By transmitting data to the host system at a first data rate before increasing to a second data rate, the memory system enables applications (e.g., reversing camera feeds) to initialize relatively quickly, which reduces latency and improves overall system performance.

[0016] Beyond its application in the memory systems described herein, techniques for memory system boot sequences with reduced latency can typically be implemented to improve the performance of various electronic devices and systems, including artificial intelligence (AI) applications, augmented reality (AR) applications, virtual reality (VR) applications, and games. Some electronic device applications, including high-performance applications such as AI, AR, VR, and games, are associated with relatively high processing demands to meet user expectations. Therefore, improving the processing power of electronic devices by reducing response time, improving power consumption, reducing complexity, increasing data throughput or access speed, reducing communication time, or increasing memory capacity or density, as well as other performance metrics, can improve user experience or appeal. Implementing the techniques described herein can improve the performance of electronic devices by initializing high-performance applications by transmitting data at a lower data rate before negotiating a higher data rate, which can reduce latency, improve response time, or otherwise improve user experience and other benefits.

[0017] Features of this disclosure are described and illustrated in the context of systems, apparatus, and circuits. Features of this disclosure are further described and illustrated in the context of process flowcharts.

[0018] Figure 1Examples of system 100 supporting memory system boot sequences with reduced latency, based on the examples disclosed herein, are shown. System 100 includes a host system 105 coupled to memory system 110. System 100 may be included in a computing device such as a desktop computer, laptop computer, web server, mobile device, vehicle, Internet of Things (IoT) enabled device, embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or networked commercial device), or any other computing device including memory and processing devices.

[0019] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other devices.

[0020] System 100 may include a host system 105 that can be coupled to memory system 110. In some instances, this coupling may include an interface to host system controller 106, which may be an instance of a controller or control component configured to cause host system 105 to perform various operations according to the examples described herein. Host system 105 may include one or more devices and, in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, host system 105 may include an application configured to communicate with memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to host system 105 or included in host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). For example, host system 105 may use memory system 110 to write data to and read data from memory system 110. Although Figure 1 The diagram shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0021] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., exchanging or otherwise transmitting control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include (but are not limited to) SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Double Data Rate (DDR) interfaces, DIMM interfaces (e.g., DIMM slot interfaces supporting DDR), Open NAND Flash Interface (ONFI), and Low Power Double Data Rate (LPDDR) interfaces. In some instances, one or more such interfaces may be included in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface of each memory device 130 included in memory system 110 or via a corresponding physical host interface of each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0022] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, then the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0023] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory device 130, and other such operations, which may be collectively referred to as access operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise associated with commands from the host system 105). For example, the memory system controller 115 may translate responses (e.g., data packets or other signals) associated with the memory device 130 into corresponding signals for the host system 105.

[0024] The memory system controller 115 can be configured for other operations associated with the memory device 130. For example, the memory system controller 115 can perform or manage operations such as wear leveling, discarded item collection, error control (e.g., error detection or error correction), encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0025] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include a circuit system having dedicated (e.g., hard-coded) logic that performs the operations attributed to the memory system controller 115 herein. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuit system.

[0026] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for, for example, internal storage or computation related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, local memory 120 may be used as a cache for the memory system controller 115. For example, data may be stored in local memory 120 when read from or written to memory device 130, and the data may be available in local memory 120 for subsequent retrieval by the host system 105 or manipulated by the host system 105 (e.g., updates) according to a caching strategy (e.g., with reduced latency relative to memory device 130).

[0027] although Figure 1 The example of memory system 110 described herein includes memory system controller 115, but in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135, which may be located within memory device 130 to perform the functions attributed herein to memory system controller 115. Generally, one or more functions attributed herein to memory system controller 115 may, in some cases, be performed by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130, at least partially managed by memory system controller 115, may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0028] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), selectable memory, other chalcogenide-based memories, ferroelectric random access memory (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0029] In some instances, memory device 130 may include (e.g., on the same die, within the same package) a local controller 135 that can operate on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115 or perform one or more functions attributed herein to memory system controller 115. For example, such as Figure 1 As described above, memory device 130-a may include local controller 135-a and memory device 130-b may include local controller 135-b.

[0030] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a die 160 (e.g., a memory die). For example, in some cases, memory device 130 may be a package including one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 170, wherein each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0031] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information, which may be referred to as a multi-level cell (MLC) when configured to store two bits of information, a three-level cell (TLC) when configured to store three bits of information, a four-level cell (QLC) when configured to store four bits of information, or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density compared to SLC memory cells, but in some cases may involve narrower read or write margins or greater complexity to support the circuitry.

[0032] In some cases, plane 165 may refer to several groups of blocks 170, and in some cases, concurrent operations may be performed on different planes 165. For example, concurrent operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, individual blocks 170 may be referred to as physical blocks, and virtual blocks 180 may refer to a group of blocks 170 within which concurrent operations can occur. For example, concurrent operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as virtual blocks 180. In some cases, a virtual block may contain blocks 170 from different memory devices 130 (e.g., blocks in one or more planes including memory devices 130-a and 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be “block 0” of plane 165-a, block 170-b may be “block 0” of plane 165-b, etc.). In some cases, performing concurrent operations in different planes 165 may be subject to one or more restrictions, such as performing concurrent operations on memory cells in different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0033] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled to a common word line), and memory cells in the same string may share a common digital line (which may alternatively be called a bit line) (e.g., coupled to a common digital line).

[0034] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level or a portion thereof) but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 may be the smallest unit of memory (e.g., a group of memory cells) that can be independently programmed or read (e.g., partially concurrently programmed or read as a single programming or read operation), and block 170 may be the smallest unit of memory (e.g., a group of memory cells) that can be independently erased (e.g., partially concurrently erased as a single erase operation). Furthermore, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Therefore, for example, in some cases, a used page 175 cannot be updated until the entire block 170 containing page 175 has been erased.

[0035] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include one or more memory arrays and associated circuitry, for example, in combination with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0036] Host system 105 and memory system 110 may support different data rates for transferring data between host system 105 and memory system 110. In such instances, host system 105 and memory system 110 may negotiate a data rate supported by both systems (e.g., a maximum data rate). For example, host system 105 and memory system 110 may negotiate a data rate in response to memory system 110 transitioning from a first power state to a second power state (e.g., upon power-on, after a startup sequence, or after exiting sleep mode). In some instances, the negotiation between host system 105 and memory system 110 may introduce latency based on increasing the data rate through a defined sequence. For example, memory system 110 supporting a relatively high data rate may negotiate an initial data rate and then negotiate a next data rate before negotiating a relatively high data rate (e.g., the highest supported data rate). Some applications (e.g., time-sensitive applications) may benefit from host system 105 accessing data from the memory system to initialize the application without the latency introduced by negotiating the maximum data rate.

[0037] As described herein, host system 105 may assert a signal (e.g., a fast boot signal) to instruct memory system 110 to transmit data at a first data rate (e.g., a relatively low data rate) before negotiating a higher data rate. For example, host system 105 may assert a fast boot signal on a pin of memory system 110, which may instruct memory system 110 to transmit data at the lowest supported data rate. In some instances, host system 105 may output a fast boot signal based on an estimated size of the data to be transmitted, dynamic measurements of the data, applications associated with the data, or any combination thereof. Based on the transmitted data, host system 105 and memory system 110 may negotiate a higher data rate (e.g., up to the highest supported data rate). By transmitting data to host system 105 at a first data rate before increasing to a second data rate, memory system 110 can enable applications (e.g., reversing camera feeds) to initialize relatively quickly, which reduces latency and improves the overall performance of memory system 110.

[0038] Figure 2 An example of system 200 supporting a memory system boot sequence with reduced latency, based on the examples disclosed herein, is shown. System 200 may be used as a reference. Figure 1 The system 100 or an example of its aspects is described. System 200 may include a memory system 210 configured to store data received from host system 205 and send data to host system 205 when requested by host system 205 using access commands (e.g., read commands or write commands). System 200 may implement references Figure 1 The described aspects of system 100. For example, memory system 210 and host system 205 may be instances of memory system 110 and host system 105, respectively.

[0039] Memory system 210 may include one or more memory devices 240 to (e.g., in response to receiving an access command from host system 205) store data transferred between memory system 210 and host system 205. Memory device 240 may include references. Figure 1 The memory device 240 may include one or more memory devices. For example, memory device 240 may include NAND memory, PCM, self-select memory, 3D cross-point or other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM or OxRAM and other examples.

[0040] Memory system 210 may include a memory controller 230 for controlling the direct transfer of data to and from memory device 240 (e.g., for storing data, retrieving data, and determining memory locations where data is stored and retrieved). The memory controller 230 may communicate directly with memory device 240 or via a bus (not shown), and may include protocols specific to each type of memory device 240. In some cases, a single memory controller 230 may be used to control multiple memory devices 240 of the same or different types. In some cases, memory system 210 may include multiple memory controllers 230 (e.g., different memory controllers 230 for each type of memory device 240). In some cases, the memory controller 230 may implement a reference... Figure 1 Aspects of the local controller 135 described.

[0041] The memory system 210 may include an interface 220 (e.g., a peripheral component interface (PCI) or a peripheral component fast interface (PCIe)) for communicating with the host system 205 and a buffer 225 for temporarily storing data transferred between the host system 205 and the memory device 240. The interface 220, buffer 225, and memory controller 230 may support data transfer between the host system 205 and the memory device 240 (e.g., as shown by data path 250) and may be collectively referred to as the data path component.

[0042] Using buffer 225 to temporarily store data during transmission allows data to be buffered while commands are being processed, which reduces latency between commands and supports arbitrary data sizes associated with commands. This also allows command bursts to be handled, and buffered data can be stored or transmitted, or both (e.g., after the burst stops). Buffer 225 may include relatively fast memory (such as some type of volatile memory, such as SRAM or DRAM) or hardware accelerators, or both, to allow data to be quickly stored in and retrieved from buffer 225. Buffer 225 may include data path switching components for bidirectional data transfer between buffer 225 and other components.

[0043] In some cases, one or more queues (e.g., command queue 260, buffer queue 265, storage queue 270) can be used to control the processing of access commands and the movement of corresponding data. Data transferred between host system 205 and memory device 240 may be passed in memory system 210 along a path different from non-data information (e.g., commands, status information). For example, system components in memory system 210 may communicate with each other using bus 235, while data may use data path 250 via data path components instead of bus 235. In some instances, pin 245 may be decoupled from the bus 235 that delivers data. For example, signals output from host system 205 to pin 245 may be passed along a non-data path. Memory system controller 215 may control how and whether data is transferred between host system 205 and memory device 240 by communicating with data path components via bus 235 (e.g., using a protocol specific to memory system 210).

[0044] After determining that an access command has been received, the memory system controller 215 may execute the access command. For a read command, this may include obtaining data from one or more memory devices 240 and transferring data to the host system 205. For a write command, this may include receiving data from the host system 205 and moving data to one or more memory devices 240. In either case, the memory system controller 215 may use a buffer 225 to temporarily store data received from or sent to the host system 205, as well as other data. To process a write command received from the host system 205, the memory system controller 215 may determine whether the buffer 225 has sufficient available space to store the data associated with the command.

[0045] In some cases, buffer queue 265 can be used to control the flow of commands associated with data stored in buffer 225, including write commands. Buffer queue 265 may contain access commands associated with data currently stored in buffer 225. In some cases, commands in command queue 260 may be moved to buffer queue 265 by memory system controller 215 and may remain in buffer queue 265 while the associated data is stored in buffer 225. Using buffer queue 265, multiple access commands can be received sequentially from host system 205 and at least a portion of the access commands can be processed concurrently.

[0046] If buffer 225 has sufficient space to store the write data, then memory system controller 215 may cause interface 220 to transmit an availability indication (e.g., a "transfer ready" indication) to host system 205, which may be executed according to a protocol (e.g., UFS protocol, eMMC protocol). When interface 220 receives data associated with a write command from host system 205, interface 220 may use data path 250 to transfer the data to buffer 225 for temporary storage. In some cases, interface 220 may obtain the location of the stored data within buffer 225 (e.g., from buffer 225, from buffer queue 265). Interface 220 may indicate to memory system controller 215 (e.g., via bus 235) whether the data transfer to buffer 225 has been completed.

[0047] After data is written and stored in buffer 225 via interface 220, the data can be transferred from buffer 225 and stored in memory device 240, which may involve the operation of memory controller 230. Memory controller 230 may (e.g., via bus 235) indicate to memory system controller 215 that data transfer to one or more memory devices 240 has been completed. In some cases, memory queue 270 may support write data transfers. For example, memory system controller 215 may push write commands from buffer queue 265 (e.g., via bus 235) to memory queue 270 for processing. Memory queue 270 may contain entries for each access command. In some cases, memory controller 230 may (e.g., from buffer 225, from buffer queue 265, from memory queue 270) obtain the location within buffer 225 from which data was obtained. Memory controller 230 may manage the location within memory device 240 for storing data (e.g., performing wear leveling, performing discarded item collection).

[0048] To process a read command received from host system 205, memory system controller 215 may determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may (e.g., via firmware, via controller firmware) determine the amount of space within buffer 225 available to store the data associated with the read command. In some cases, buffer queue 265 may support buffered storage of data associated with the read command in a manner similar to that discussed with write commands. Storage controller 230 may (e.g., via bus 235) indicate to memory system controller 215 when data transfer to buffer 225 has been completed.

[0049] In some cases, the storage queue 270 can be used to facilitate data transfer. For example, the memory system controller 215 can push read commands to the storage queue 270 for processing. In some cases, the storage controller 230 can obtain the location within one or more memory devices 240 from which data is retrieved (e.g., from the buffer 225, from the storage queue 270).

[0050] After data is stored in buffer 225 by storage controller 230, the data can be transferred from buffer 225 and sent to host system 205. For example, storage system controller 215 may cause interface 220 to retrieve data from buffer 225 using data path 250 and transfer the data to host system 205 (e.g., according to a protocol, such as UFS or eMMC). For example, interface 220 may process commands from command queue 260 and may (e.g., via bus 235) indicate to storage system controller 215 that the data transfer to host system 205 has been completed.

[0051] The memory system controller 215 can execute received commands according to a sequence (e.g., first-in-first-out order, or according to the order of command queue 260). For each command, the memory system controller 215 can cause data corresponding to the command to be shifted into and out of buffer 225, as discussed herein. While data is shifted into and stored in buffer 225, the command may remain in buffer queue 265. If the processing of the command has been completed (e.g., if the data corresponding to the access command has been shifted out of buffer 225), then the command may be (e.g., by the memory system controller 215) removed from buffer queue 265. If the command is removed from buffer queue 265, then the address where data associated with this command was previously stored can be used to store data associated with the new command.

[0052] In some instances, memory system controller 215 may be configured for operations associated with one or more memory devices 240. For example, memory system controller 215 may perform or manage operations such as wear leveling, discard item collection, error control operations such as error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., LBAs) associated with commands from host system 205 and physical addresses (e.g., physical block addresses) associated with memory cells within memory device 240. In some cases, memory controller 230 may be configured to perform one or more of the described operations in conjunction with or in place of memory system controller 215. In some cases, memory system controller 215 may perform the functions of memory controller 230, and memory controller 230 may be omitted.

[0053] In some instances, host system 205 and memory system 210 may support different data rates for transmitting data. For example, memory system 210 may support one data rate and host system 205 may support another data rate higher than the data rate supported by memory system 210. Based on the different data rates, host system 205 and memory system 210 may negotiate their links (e.g., connections via interface 220) to the data rates supported by both systems. That is, as used herein, "negotiate" or "negotiate data rates" may refer to any process or operation in which memory system 210 and host system 205 exchange or otherwise indicate capability information (e.g., supported data rates), determine the data rates supported by each system based on the capability information, and transmit data according to the data rates. In some instances, host system 205 and memory system 210 negotiate the data rate to the highest rate supported by each system. For example, a memory system 210 that supports a data rate of 6Gb / s (e.g., based on the supported data rate of one or more memory devices 240) may begin data communication with the host system 205 at a data rate of 1.5Gb / s before negotiating (e.g., increasing the data rate) to 6Gb / s.

[0054] Negotiating a higher data rate can be based on a known (e.g., predefined or normalized) sequence between the host system 205 and the memory system 210. For example, a memory system 210 supporting multiple data rates (e.g., Gen1, Gen2, Gen4, etc.) can begin communication at an initial data rate (e.g., Gen1), increase the communication speed to the next data rate (e.g., Gen2), and finally increase to the highest data rate (e.g., Gen4). In some instances, the host system 205 and the memory system 210 can negotiate the data rate based on the memory system 210 transitioning from a lower power state to a higher power state (e.g., powering on or exiting sleep mode).

[0055] In some instances, negotiating a higher data rate increases the latency and time-to-readiness (TTR) of the memory system 210. For example, the host system 205 may default to negotiating the highest supported data rate with the memory system 210 because communicating with the memory system 210 at the highest data rate is preferable. However, continuously negotiating the highest supported data rate between the host system 205 and the memory system 210 can degrade performance because the host system 205 has to wait longer to perform access operations to the memory system 210 during the data rate negotiation.

[0056] In some instances, host system 205 can benefit from avoiding negotiation of a higher data rate after memory system 210 transitions to a higher power state. For example, host system 205 can serve data (e.g., high-priority data) from memory system 210 to one or more time-sensitive applications before host system 205 and memory system 210 increase communication speed to the maximum data rate. This saves valuable time, allowing memory system 210 to perform time-sensitive functions before incurring the additional latency associated with negotiating the maximum data rate.

[0057] In some instances, one or more time-sensitive applications may be initialized when the memory system 210 transitions to a power state. In some examples, time-sensitive applications may be associated with relatively high-priority data. Such time-sensitive applications may be, or may include, automotive applications such as reversing camera feeds, infotainment systems, parking sensors, and the like. The techniques described herein enable functions associated with such time-sensitive applications to execute before the host system 205 and memory system 210 increase communication speeds to maximum data rates, allowing for relatively rapid execution of time-sensitive application functions.

[0058] The host system 205 may output a signal (e.g., a hardware signal) to pin 245 at interface 220 to instruct the memory system 210 to negotiate a data rate lower than the highest supported data rate (e.g., the lowest supported data rate between two systems). The host system 205 may set the pin to a first value to negotiate the link at a lower data rate for transmitting high-priority data (e.g., performing fast boot), or the host system 205 may set the pin to a second value to negotiate the link at a higher data rate (e.g., performing normal boot). See reference... Figure 3 Further described, memory system 210 may receive signals based on one or more applications, the size of high-priority data, or any combination thereof. In some instances, memory system 210 may receive signals after transitioning from a relatively low-power state (e.g., memory system 210 is off or in sleep mode) to a higher-power state. After host system 205 receives high-priority data, memory system 210 and host system 205 may negotiate a higher data rate. For example, based on transmitting high-priority data (e.g., and initializing one or more applications), memory system 210 may perform one or more access operations according to the highest data rate supported by both systems.

[0059] Figure 3 An example of a process flowchart 300 supporting a memory system boot sequence with reduced latency, based on the examples disclosed herein, is shown. Process flowchart 300 can be found in the references... Figure 1 and 2 The implementation of the described memory system and host system aspects.

[0060] Examples of systems that can utilize the fast-start techniques described herein include automotive applications. Many vehicles are equipped with memory systems that support other vehicle components, such as a rearview camera, infotainment system, and / or advanced driver assistance systems (ADAS). After the vehicle is started, some users expect certain functionalities to initialize immediately. For example, some drivers may start the vehicle and then immediately reverse (e.g., along a lane or out of a parking space). The startup sequence of the memory systems in the vehicle can cause a delay in initializing the vehicle's rearview camera. To reduce the delay in initializing some systems (such as the vehicle's rearview camera), the memory system can incorporate these techniques to perform a fast-start sequence. In this sequence, the memory system may initially begin transmitting data at a slower data transfer rate, allowing some applications (such as the vehicle's rearview camera) to begin operation after a short delay. Then, at a later time, the memory system may negotiate a faster data transfer rate after the low-latency application initialization.

[0061] At 305, the memory system may enter a low-power state (e.g., power-off or sleep mode). In some instances, at 310, the host system (e.g., host system 205) may determine whether to output a signal (e.g., a fast boot signal). The fast boot signal may instruct the memory system to transmit a certain amount of data at a first rate. For example, the fast boot signal may instruct the memory system to transmit data at a lower data rate than the highest data rate supported by both the memory system and the host system (e.g., the minimum supported data rate), as referenced. Figure 2 Further description. In some instances, data may be associated with a first priority (e.g., the data is relatively high priority data). For example, a memory system (e.g., memory system 210) may transfer data associated with a first priority to initialize one or more applications, such as a reversing camera, various sensors (e.g., monitoring sensors), an infotainment system, or the like.

[0062] In some instances, the host system may determine whether to output a fast boot signal to the memory system. For example, the host system may assert or not assert (e.g., normal boot) a fast boot signal by default. Alternatively, the host system may output a signal based on one or more conditions. For example, one or more applications (e.g., time-sensitive applications such as reversing camera feeds, parking sensors, or the like) may initialize faster based on the memory system communicating with the host system at a lower data rate but with higher priority data. The memory system may receive signals based on one or more applications (e.g., the host system may determine that one or more applications benefit from a fast boot signal and output the signal to the memory system).

[0063] In some instances, the memory system may receive a signal based on an estimated amount of data, the amount of data, or any combination thereof. For example, the host system, the memory system (e.g., memory system controller 215), or both may determine whether the amount of data meets a first threshold. Alternatively, the host system, the memory system, or both may determine that the estimated amount of data meets a second threshold (e.g., equal to or different from the first threshold).

[0064] In some instances, the threshold (e.g., a first threshold, a second threshold, or both) may correspond to the duration for which the memory system transmits a certain amount of data, which is less than or equal to the duration for which the host system and the memory system negotiate the highest data rate (e.g., if transmitting high-priority data relatively quickly is faster than negotiating to the highest data rate, then the memory system may receive a signal). In other instances, the threshold may correspond to the amount of data associated with initializing the application. For example, the application may be initialized based on a variable amount of data, and the host system, memory system, or both may estimate the amount of data to initialize the application. The memory system may receive a fast boot signal based on the amount of data meeting a first threshold or the estimated amount of data meeting a second threshold.

[0065] At 315, the host system can assert down to the pin (e.g., reference). Figure 2 The fast boot signal is described on pin 245. At 320, the memory system can negotiate a lower data rate (e.g., minimum supported data rate) than the highest data rate supported by both the memory system and the host system based on the signal received from the pin. For example, the memory system can sample the fast boot signal at power-on and negotiate the slowest link speed with the host system for relatively fast access (e.g., compared to negotiating to the highest data rate). At 325, the host system can perform one or more access operations to deliver a certain amount of data according to the lower data rate. For example, the host system can read or write to the memory system at the slowest supported data rate.

[0066] At 330, the host system and memory system may increase the data rate to a higher data rate than a lower data rate based on the amount of data being transmitted. At 335, the memory system may perform access operations (e.g., read or write) at a higher data rate (e.g., the highest data rate). In some instances, data transmitted according to the higher data rate may be associated with a second priority that is lower than a first priority of the amount of data transmitted according to the lower data rate.

[0067] In some instances, at 340, the host system may determine not to output a fast boot signal (e.g., based on one or more non-time-sensitive applications). In such instances, the host system and memory system can negotiate a higher data rate (e.g., the highest supported data rate) than the lower data rate, without requiring the memory system to boot to the lower data rate first. The memory system and host system can continue to 335, where the memory system can perform access operations (e.g., read or write) at the higher data rate. By transferring data to the host system at a lower data rate before ramping up to the higher data rate, the memory system can enable some applications (e.g., reversing camera feeds) to initialize relatively quickly, which reduces latency and improves the overall performance of the memory system.

[0068] Figure 4 A block diagram 400 illustrates a memory system 420 with a memory system boot sequence that supports reduced latency, based on examples disclosed herein. Memory system 420 may be used as a reference. Figures 1 to 3 Examples of aspects of the described memory system. Memory system 420 or its various components may be examples of means for performing various aspects of a memory system boot sequence with reduced latency, as described herein. For example, memory system 420 may include boot component 425, boot type indication component 430, data communication component 435, data rate component 440, data quantity component 445, pin component 450, interface component 455, access command component 460, or any combination thereof. Components of each of these components or their sub-components (e.g., one or more processors, one or more memories) may communicate directly or indirectly with each other (e.g., via one or more buses).

[0069] The boot component 425 may be configured or otherwise supported to support means for initiating a boot sequence to transition the memory system from a first power state to a second power state. The boot type indication component 430 may be configured or otherwise supported to support means for receiving first signaling from the host system based on the initiation of a boot sequence to indicate that the boot sequence is a first type of sequence associated with lower latency. The data communication component 435 may be configured or otherwise supported to support means for performing first data communication with the host system at a first data rate based on receiving the first signaling. The data rate component 440 may be configured or otherwise supported to support means for increasing the rate used for communication with the host system from the first data rate to a second data rate after transmitting first data, wherein the first data rate is slower than the second data rate when used for communication with the host system.

[0070] In some instances, data communication component 435 may be configured or otherwise supported for second data communication with the host system at a second data rate based on increasing the rate used for communication with the host system from a first data rate to a second data rate. In some instances, the first data is associated with a first priority and the second data is associated with a second priority that is different from the first priority.

[0071] In some instances, data rate component 440 may be configured or otherwise supported to support means for increasing the rate of communication with the host system from a second data rate to a third data rate. In some instances, data communication component 435 may be configured or otherwise supported to support means for performing third data communication with the host system at a third data rate based on increasing the rate of communication with the host system from a second data rate to a third data rate, wherein the third data rate is faster than both the first and second data rates when used for communication with the host system.

[0072] In some instances, the data quantity component 445 may be configured or otherwise supported for determining whether the quantity of first data meets a threshold based on the initiation startup sequence, wherein receiving the first signaling is based on determining that the quantity of the first data meets the threshold. In some instances, the memory system is configured to initiate using a second type of sequence associated with a higher latency than the first type of sequence. In some instances, the first signaling is received via a first pin of the memory system. In some instances, the first data communicates with the host system via an interface different from the first pin.

[0073] In some instances, to support initial data communication with the host system, the access command component 460 may be configured or otherwise supported for receiving one or more read commands, transmitting one or more write commands, or both.

[0074] In some instances, the first data rate is associated with the slowest data rate used to communicate with the host system. In some instances, the transmission of first data according to the first data rate is based on the application associated with the first data. In some instances, the first power state is associated with a lower power state than the second power state.

[0075] In some instances, the described functionality of memory system 420 or its various components may be supported by or refer to at least a portion of at least one processor, wherein the at least one processor may comprise one or more processing elements (e.g., controller, microprocessor, microcontroller, digital signal processor, state machine, discrete gate logic, discrete transistor logic, discrete hardware component, or any combination of one or more of such elements). In some instances, the described functionality of memory system 420 or its various components may be implemented at least in part by instructions executable by the at least one processor (e.g., stored in memory, non-transitory computer-readable medium).

[0076] Figure 5 The flowchart illustrates a method 500 for supporting a memory system boot sequence with reduced latency, based on examples disclosed herein. Operation of method 500 can be implemented by the memory system or its components described herein. For example, operation of method 500 can be achieved by referring to... Figures 1 to 4 The described memory system performs the function. In some instances, the memory system may execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the memory system may use dedicated hardware to perform aspects of the described function.

[0077] At 505, the method may include initiating a startup sequence to transition the memory system from a first power state to a second power state. In some instances, aspects of operation 505 may be referenced. Figure 4 The described startup component 425 and Figure 3 The operations described at points 315 and 340 are executed.

[0078] At 510, the method may include receiving a first signaling from the host system based on the initiation of a startup sequence to indicate that the startup sequence is a first type of sequence associated with lower latency. In some instances, aspects of operation 510 may be referenced. Figure 4 The described startup type indicates that component 430 executes and references Figure 3 The operation described at point 315 in the text and Figure 2 Pin 245 is described in the diagram.

[0079] At point 515, the method may include performing first data communication with the host system at a first data rate based on receiving a first signaling. In some instances, aspects of operation 515 may be referenced. Figure 4 The data communication component 435 described herein and Figure 3 The operation described at point 325 in the document is executed.

[0080] At 520, the method may include increasing the rate used for communication with the host system from a first data rate to a second data rate after transmitting the first data, wherein the first data rate is slower than the second data rate when used for communication with the host system. In some instances, aspects of operation 520 may be referenced. Figure 4 The data rate component 440 described and Figure 3 The operation described at point 330 in the document is executed.

[0081] In some instances, the device described herein may perform one or more methods, such as method 500. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) or any combination thereof for performing aspects of this disclosure:

[0082] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: initiating a boot sequence to transition a memory system from a first power state to a second power state; receiving first signaling from a host system based on initiating the boot sequence to indicate that the boot sequence is a first type of sequence associated with lower latency; performing first data communication with the host system at a first data rate based on receiving the first signaling; and increasing the rate for communicating with the host system from the first data rate to a second data rate after transmitting the first data, wherein the first data rate is slower than the second data rate when communicating with the host system.

[0083] Aspect 2: The method, apparatus, or non-transitory computer-readable medium according to aspect 1 further includes an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for performing second data communication with the host system at the second data rate based on increasing the rate for communicating with the host system from the first data rate to the second data rate.

[0084] Aspect 3: The method, device, or non-transitory computer-readable medium according to aspect 2, wherein the first data is associated with a first priority and the second data is associated with a second priority different from the first priority.

[0085] Aspect 4: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 3, further comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: increasing the rate for communicating with the host system from the second data rate to a third data rate; and performing third data communication with the host system at the third data rate based on increasing the rate for communicating with the host system from the second data rate to the third data rate, wherein the third data rate is faster than the first data rate and the second data rate when used for communicating with the host system.

[0086] Aspect 5: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 4, further comprising an operation, feature, circuit system, logic, component, or instruction or any combination thereof for: determining that the quantity of the first data satisfies a threshold based on initiating the initiation sequence, wherein receiving the first signaling is based on determining that the quantity of the first data satisfies the threshold.

[0087] Aspect 6: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 5, wherein the memory system is configured to start using a sequence of a second type associated with a higher latency than the sequence of the first type.

[0088] Aspect 7: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 6, wherein the first signaling is received via a first pin of the memory system and the first data communicates with the host system via an interface different from the first pin.

[0089] Aspect 8: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 7, wherein the first data communication with the host system comprises operations, features, circuitry, logic, components, or instructions or any combination thereof for receiving one or more read commands, transmitting one or more write commands, or both.

[0090] Aspect 9: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 8, wherein the first data rate is associated with the slowest data rate used for communicating with the host system.

[0091] Aspect 10: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 9, wherein the first data is transmitted according to the first data rate based on an application associated with the first data.

[0092] Aspect 11: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 10, wherein the first power state is associated with a power state lower than the second power state.

[0093] It should be noted that the described techniques include possible implementations, and the operation and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions from two or more of the methods can be combined.

[0094] The information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols referred to throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, a signal can represent a signal bus, where the bus can have various bit widths.

[0095] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to a relationship between components that supports the flow of signals between them. Components are considered to be in electronic communication (or in conductive contact, connection, or coupling) if any conductive path exists between them that can support the flow of signals between them at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connection, or coupling) may be open or closed based on the operation of the device containing the connected component. The conductive path between connected components may be a direct conductive path between the components, or it may be an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some instances, the flow of signals between connected components may be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

[0096] The term "coupling" (e.g., "electrical coupling") can refer to a condition that changes from an open-circuit relationship between components (where signals cannot currently travel between components via conductive paths) to a closed-circuit relationship between components (where signals can travel between components via conductive paths). If, for example, a component of a controller couples other components together, then the component triggers a change that allows signals to flow between other components via conductive paths that were previously not permitted to allow signals.

[0097] The term "isolation" refers to a relationship between components in which signals cannot currently flow between them. If there is an open circuit between components, then the components are isolated from each other. For example, if a switch positioned between two components is turned on, then the components separated by the switch are isolated from each other. If a controller isolates two components, then the controller causes a change that prevents signals from flowing between the components using previously permitted conductive paths.

[0098] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe the connection between conditional actions, conditional procedures, or parts of a procedure.

[0099] The term "in response to" can refer to a condition or action that occurs at least partially (if not entirely) as a result of a preceding condition or action. For example, a first condition or action may be performed and a second condition or action may occur at least partially as a result of the preceding condition or action (whether directly after the first condition or action or after one or more other intermediate conditions or actions that occur after the first condition or action).

[0100] Additionally, the terms "directly in response to" or "directly responding to" may refer to a condition or action occurring directly as a result of a preceding condition or action. In some instances, a first condition or action may be performed and a second condition or action may occur directly as a result of a preceding condition or action, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed and a second condition or action may occur directly as a result of a preceding condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being performed "based on," "at least in part based on," or "in response to" a certain other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) be performed "directly in response to" or "directly responding to" this other condition or action.

[0101] The devices discussed herein (including memory arrays) can be formed on semiconductor substrates, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some other instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG) or silicon-on-sapphire (SOP)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species, including (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0102] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be covered by an insulating gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "off" or "deactivated."

[0103] The descriptions presented herein, taken in conjunction with the accompanying drawings, illustrate exemplary configurations and do not represent all instances that may be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" rather than "preferred" or "superior to other instances." "Detailed Description" contains specific details used to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concept of the described instances.

[0104] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by adding a hyphen after the reference numeral and a second numeral to differentiate similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0105] The functions described herein can be implemented in hardware, software executed by a processing system (e.g., one or more processors, one or more controllers, control circuitry, processing circuitry, logic circuitry), firmware, or any combination thereof. If implemented in software executed by a processing system, the functions can be stored as one or more instructions (e.g., code) on or transmitted via a computer-readable medium. Due to the nature of software, the functions described herein can be implemented using software executed by a processing system, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions can be physically located at various locations, including distributed portions of the functions implemented at different physical locations.

[0106] The descriptive blocks and modules described herein may be implemented or executed by one or more processors (e.g., DSP, ASIC, FPGA, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof) designed to perform the functions described herein. The processor may be an instance of a microprocessor, controller, microcontroller, state machine, or other type of processor. The processor may also be implemented as at least one of one or more computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0107] As used herein (included in the claims), the word "or" in a list of items (e.g., a list of items beginning with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0108] As used herein (included in the claims), the article “a” preceding a noun is open-ended and should be understood to refer to “at least one” or “one or more” of the nouns. Therefore, the terms “a,” “at least one,” “one or more,” and “at least one of one or more” are interchangeable. For example, if a claim describes a “component” performing one or more functions, then each of the individual functions can be performed by a single component or any combination of components. Therefore, the term “component” having a characteristic or performing a function can refer to “at least one of one or more components” having a particular characteristic or performing a particular function. The subsequent use of the term “the / said” to refer to a component introduced by the article “a” can refer to any or all of one or more components. For example, a component introduced by the article “a” can be understood to mean “one or more components,” and the subsequent reference to “the / said” in a claim can be understood to be equivalent to referring to “at least one of the one or more components.” Similarly, the subsequent use of the term "the / said" to refer to a component introduced as "one or more components" can refer to any or all of the one or more components. For example, the subsequent reference to "the one or more components" in a claim can be understood as equivalent to referring to "at least one of the one or more components".

[0109] Computer-readable media includes both non-transitory computer storage media and communication media, encompassing any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media can be any available media or combination of media that is accessible by a computer. For example, but not limited to, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory media or combination of media that can be used to carry or store desired program code elements in the form of instructions or data structures and are accessible by a computer or one or more processors.

[0110] The description herein is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will understand that various modifications to this disclosure are possible, and that the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method performed by a memory system, comprising: Initiate a startup sequence to transition the memory system from a first power state to a second power state; Based on initiating the startup sequence, a first signaling is received from the host system to indicate that the startup sequence is a first type of sequence associated with lower latency; Based on receiving the first signaling, first data communication is performed with the host system at a first data rate; and After transmitting the first data, the rate used for communicating with the host system is increased from the first data rate to a second data rate, wherein the first data rate is slower than the second data rate when used for communicating with the host system.

2. The method according to claim 1, further comprising: Second data communication is performed with the host system at the second data rate by increasing the rate used for communication with the host system from the first data rate to the second data rate.

3. The method of claim 2, wherein the first data is associated with a first priority and the second data is associated with a second priority that is different from the first priority.

4. The method of claim 1, further comprising: The rate used for communicating with the host system is increased from the second data rate to the third data rate; and Third data communication is performed with the host system at the third data rate, which is increased from the second data rate to the third data rate for communicating with the host system, wherein the third data rate is faster than the first data rate and the second data rate when used for communicating with the host system.

5. The method of claim 1, further comprising: The quantity of the first data is determined to meet a threshold based on initiating the start sequence, wherein receiving the first signaling is based on determining that the quantity of the first data meets the threshold.

6. The method of claim 1, wherein the memory system is configured to start using a second type of sequence associated with a higher latency than the first type of sequence.

7. The method according to claim 1, wherein: The first signaling is received via a first pin of the memory system; and The first data communicates with the host system via an interface different from the first pin.

8. The method of claim 1, wherein performing the first data communication with the host system comprises: Receive one or more read commands, transmit one or more write commands, or both.

9. The method of claim 1, wherein the first data rate is associated with the slowest data rate used for communicating with the host system.

10. The method of claim 1, wherein conveying the first data according to the first data rate is based on an application associated with the first data.

11. A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to: Initiate a startup sequence to transition the memory system from a first power state to a second power state; Based on initiating the startup sequence, a first signaling is received from the host system to indicate that the startup sequence is a first type of sequence associated with lower latency; Based on receiving the first signaling, first data communication is performed with the host system at a first data rate; and After transmitting the first data, the rate used for communicating with the host system is increased from the first data rate to a second data rate, wherein the first data rate is slower than the second data rate when used for communicating with the host system.

12. The non-transitory computer-readable medium of claim 11, wherein the instructions are further executable by the one or more processors to: Second data communication is performed with the host system at the second data rate by increasing the rate used for communication with the host system from the first data rate to the second data rate.

13. The non-transitory computer-readable medium of claim 12, wherein the first data is associated with a first priority and the second data is associated with a second priority different from the first priority.

14. The non-transitory computer-readable medium of claim 11, wherein the instructions are further executable by the one or more processors to: The rate used for communicating with the host system is increased from the second data rate to the third data rate; and Third data communication is performed with the host system at the third data rate, which is increased from the second data rate to the third data rate for communicating with the host system, wherein the third data rate is faster than the first data rate and the second data rate when used for communicating with the host system.

15. The non-transitory computer-readable medium of claim 11, wherein the instructions are further executable by the one or more processors to: The quantity of the first data is determined to meet a threshold based on initiating the start sequence, wherein receiving the first signaling is based on determining that the quantity of the first data meets the threshold.

16. The non-transitory computer-readable medium of claim 11, wherein the memory system is configured to be started using a second type of sequence associated with a higher latency than the first type of sequence.

17. The non-transitory computer-readable medium of claim 11, wherein: The first signaling is received via a first pin of the memory system; and The first data communicates with the host system via an interface different from the first pin.

18. The non-transitory computer-readable medium of claim 11, wherein the instructions for performing the first data communication with the host system are executable by the one or more processors to: Receive one or more read commands, transmit one or more write commands, or both.

19. The non-transitory computer-readable medium of claim 11, wherein the first data rate is associated with the slowest data rate for communicating with the host system, or wherein the communication of the first data according to the first data rate is based on an application associated with the first data.

20. A memory system comprising: One or more memory devices; and A processing circuitry system coupled to and configured to cause the memory system to: Initiate a startup sequence to transition the memory system from a first power state to a second power state; Based on initiating the startup sequence, a first signaling is received from the host system to indicate that the startup sequence is a first type of sequence associated with lower latency; Based on receiving the first signaling, first data communication is performed with the host system at a first data rate; and After transmitting the first data, the rate used for communicating with the host system is increased from the first data rate to a second data rate, wherein the first data rate is slower than the second data rate when used for communicating with the host system.

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