Fault diagnosis method and system for integrated circuit

Abstract

The invention provides a fault diagnosis method and system for an integrated circuit, and relates to the technical field of circuit diagnosis, and the method comprises the steps: calculating ideal output values corresponding to all pre-generated test vectors based on a Boolean expression of a directed acyclic graph of a to-be-diagnosed circuit, and carrying out the fault detection through combining with a preset actual measurement output set; when a fault is detected, traversing all signal lines in the directed acyclic graph to generate a candidate fault set; performing priority ranking on the candidate fault set based on the Boolean difference sensitivity and the test coverage rate, and performing hierarchical simulation matching on the candidate fault set according to a ranking result; and performing multi-fault combination optimization verification on a fault matching result obtained after layered simulation matching through Boolean differential analysis, and outputting a fault diagnosis result after optimization verification, so that the efficiency and accuracy of fault diagnosis are improved, the misjudgment and missed judgment rates are reduced, and the product research and development cost and time are reduced.

Description

Technical Field

[0001] This invention relates to the field of circuit diagnostic technology, and in particular to a method and system for diagnosing faults in integrated circuits. Background Technology

[0002] With the rapid development of integrated circuit technology, chip size and complexity are increasing daily, significantly increasing the difficulty of fault diagnosis. Traditional integrated circuit fault diagnosis methods have many limitations, such as insufficient precision and comprehensiveness in fault detection, making it difficult to effectively cover multiple fault types; during fault location, facing a large number of possible fault points, the lack of efficient screening and sorting mechanisms leads to low diagnostic efficiency and long processing times; and for multiple fault combinations, the lack of effective verification and optimization methods easily results in misdiagnosis or missed diagnosis. These problems severely restrict the accuracy and efficiency of integrated circuit fault diagnosis, increasing product development costs and time.

[0003] Therefore, it is necessary to provide a fault diagnosis method and system for integrated circuits to solve the above-mentioned technical problems. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides a fault diagnosis method and system for integrated circuits, achieving more efficient and accurate fault diagnosis through multi-stage innovation and optimization.

[0005] This invention provides a fault diagnosis method for integrated circuits, the method comprising the following steps:

[0006] The Boolean expression of the directed acyclic graph of the circuit to be diagnosed is used to calculate the ideal output value corresponding to all pre-generated test vectors, and the fault detection is performed by combining the preset set of measured outputs.

[0007] When a fault is detected, all signal lines in the directed acyclic graph are traversed to generate a candidate fault set;

[0008] The candidate fault set is prioritized based on Boolean difference sensitivity and test coverage, and hierarchical simulation matching is performed on the candidate fault set according to the ranking results.

[0009] The fault matching results obtained after hierarchical simulation matching are optimized and verified by Boolean difference analysis, and the optimized and verified fault diagnosis results are output.

[0010] Preferably, the fault detection specifically includes:

[0011] A network model for generating Boolean expressions based on the directed acyclic graph of the circuit to be diagnosed;

[0012] The Boolean expression network model is used to calculate the ideal output value corresponding to all pre-generated test vectors.

[0013] The ideal output value is compared bit by bit with the preset set of measured outputs, and the existence of a fault is determined based on the comparison results.

[0014] Preferably, the generation of the candidate fault set includes:

[0015] When a fault exists, extract the set of all signal lines in the directed acyclic graph to be analyzed;

[0016] Based on the set of all signal lines, an initial fault set is generated that includes the assumption of a single fixed type fault for each signal line;

[0017] Based on the initial fault set, a fault combination enumeration operation is performed, and the size of the combination space is controlled by a preset maximum number of fault points to generate a multiple fixed fault extension set.

[0018] The initial fault set is combined with the extended set of multiple fixed faults to form a candidate fault set.

[0019] Preferably, the priority sorting includes:

[0020] Calculate the Boolean difference sensitivity of each fault point in the candidate fault set and calculate the coverage of each fault point by the test vector;

[0021] Extract the structural feature set of each fault point, wherein the structural feature set includes logic depth, fan-out coefficient and sensitive path density;

[0022] Based on Boolean difference sensitivity, coverage, and structural feature set, a ranking weight is calculated using a ranking weight function, and the data is then ranked. The expression for the ranking weight function is as follows:

[0023]

[0024] Where, ω i Let α represent the priority score of the i-th fault point, α represent the sensitivity adjustment coefficient, and Δf(x) represent the sensitivity adjustment coefficient. i ) represents the signal line x corresponding to the i-th fault point. i Boolean difference sensitivity, β represents the coverage adjustment coefficient, C i Let γ represent the coverage of the i-th fault point, γ represent the structural characteristic adjustment coefficient, and D represent the coverage of the ith fault point. i The signal line x represents the i-th fault point in the candidate fault set. i The minimum logic gate distance to the nearest main output, F i The signal line x corresponding to the i-th fault point i The number of directly driven lower-level logic gates, P i The signal line x corresponding to the i-th fault point iThe number of times F appears in the sensitization path with non-zero Boolean difference. max P represents the maximum value of the fan-out coefficient of all signal lines in the circuit to be diagnosed. max The maximum value of sensitive path density for all fault points.

[0025] Preferably, the hierarchical simulation matching includes:

[0026] Based on the priority sorting results, the top N fault points with the highest sorting weight are extracted as the high-sorting fault set, where N is dynamically calculated according to the scale and fault density of the circuit to be diagnosed.

[0027] Simulations are injected into each fault point in the high-ranking fault set, and the simulated output response of the corresponding preset test vector is calculated.

[0028] The matching degree between the simulated output response and the preset set of measured outputs is evaluated;

[0029] When no consistency faults are found in the matching evaluation, the fault set is expanded to the next sorted area according to the sorting weight, and the simulation and matching evaluation are repeated.

[0030] Preferably, the formula for calculating N is:

[0031]

[0032] Where M represents the total number of fault points in the candidate fault set, G represents the total number of gates in the circuit to be diagnosed, and ρ is the fault density.

[0033] Preferably, the verification of multi-fault combination optimization through Boolean difference analysis includes:

[0034] For each fault combination in the fault matching result set, calculate the combined Boolean difference sensitivity value;

[0035] Based on the combined Boolean difference sensitivity value, the tabu search algorithm is used to perform spatial reduction on the fault matching result set, and the reduced optimized fault combination set is output as the fault diagnosis result.

[0036] Preferably, the spatial reduction includes:

[0037] A solution space evaluation function is constructed based on the combined Boolean difference sensitivity value, wherein the evaluation function value is equal to the corresponding combined Boolean difference sensitivity value;

[0038] Tabu search optimization is performed based on the solution space evaluation function, and the optimization terminates when the termination condition is met after multiple consecutive iterations.

[0039] The present invention also provides a fault diagnosis system for integrated circuits, used to execute the aforementioned fault diagnosis method for integrated circuits, the system comprising:

[0040] The fault detection module is used to calculate the ideal output value corresponding to all pre-generated test vectors based on the Boolean expression of the directed acyclic graph of the circuit to be diagnosed, and to perform fault detection in combination with the preset set of measured outputs.

[0041] The fault set generation module is used to traverse all signal lines in the directed acyclic graph to generate a candidate fault set when a fault is detected.

[0042] The hierarchical simulation matching module is used to prioritize the candidate fault set based on Boolean difference sensitivity and test coverage, and to perform hierarchical simulation matching on the candidate fault set according to the ranking result.

[0043] The optimization and verification module is used to perform multi-fault combination optimization and verification on the fault matching results obtained after hierarchical simulation matching through Boolean difference analysis, and output the optimized and verified fault diagnosis results.

[0044] Compared with related technologies, the fault diagnosis method and system for integrated circuits provided by this invention have the following beneficial effects:

[0045] This invention enables accurate fault detection based on directed acyclic graph Boolean expressions. When generating the candidate fault set, both single and multiple fixed faults are considered, comprehensively covering all possible fault scenarios. Priority ranking comprehensively considers Boolean difference sensitivity, test coverage, and structural feature sets, ensuring a scientific and reasonable approach. Hierarchical simulation matching dynamically selects fault points for simulation based on priority, improving diagnostic efficiency. Multiple fault combination optimization verification, through Boolean difference analysis and tabu search algorithms, ensures the accuracy of the diagnostic results. Overall, this method improves the efficiency and accuracy of fault diagnosis, reduces false positives and false negatives, and decreases product development costs and time. Attached Figure Description

[0046] Figure 1 A flowchart of a fault diagnosis method for an integrated circuit provided by the present invention;

[0047] Figure 2 This invention provides a module structure diagram of an integrated circuit fault diagnosis system. Detailed Implementation

[0048] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the drawings, not all structures. Moreover, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0049] It should also be noted that, for ease of description, the accompanying drawings show only the parts relevant to the invention and not all of them. Before discussing exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the operations (or steps) as sequential processes, many of the operations can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the operations can be rearranged. The process can be terminated when its operation is completed, but it may also have additional steps not included in the drawings. The process may correspond to a method, function, procedure, subroutine, subprogram, etc.

[0050] Example 1

[0051] This invention provides a fault diagnosis method for integrated circuits, with reference to... Figure 1 As shown, the method includes the following steps:

[0052] S1: Calculate the ideal output value corresponding to all pre-generated test vectors based on the Boolean expression of the directed acyclic graph of the circuit to be diagnosed, and perform fault detection by combining it with the preset set of measured outputs.

[0053] Specifically, step S1 includes the following steps:

[0054] S11: Directed acyclic graph generation Boolean expression network model based on the circuit to be diagnosed.

[0055] In this embodiment, the role of step S11 in the entire technical solution is to transform the physical structure of the circuit to be diagnosed into a computable logical model, providing a mathematical basis for subsequent fault detection.

[0056] In practice, the gate-level netlist file of the integrated circuit (such as a Verilog or VHDL description) is first parsed to extract all logic gates (including AND, OR, NOT, etc.) and their interconnections. Then, a directed acyclic graph (DAG) is constructed, where nodes represent logic gates or raw input / output ports, and directed edges represent signal transmission directions. Finally, a corresponding Boolean expression is generated for each node. For example, for the output Z of an AND gate node, the expression is Z = A·B (where A and B are input signals). For multi-level logic chains, sub-expressions are recursively combined to form a complete Boolean expression network model. Those skilled in the art can automate the parsing using the API of standard EDA tools (such as Synopsys Design Compiler) or manually construct the model using graph theory algorithms (such as depth-first traversal) to ensure that the Boolean expressions are strictly equivalent to the circuit behavior.

[0057] S12: Calculate the ideal output value corresponding to all pre-generated test vectors using the Boolean expression network model.

[0058] In this embodiment, step S12 is used to simulate the expected behavior of the circuit under fault-free conditions and generate benchmark data for fault comparison.

[0059] The specific implementation process includes: traversing the Boolean expression network model generated in step S11, performing logic simulation on each pre-generated test vector (output by an ATPG tool such as Tetramax). For a single test vector, calculation is performed starting from the original input port according to the DAG topology sorting, substituting into the Boolean expression level by level for evaluation; for sequential circuits, clock cycle simulation is added to capture the output value within a specified time window; finally, the logic value sequence (0 / 1 bit stream) of all main output terminals under each test vector is collected to form a complete set of ideal output values. Those skilled in the art can use commercial simulators (such as ModelSim) to ensure that the calculation results conform to the IEEE 1364 logic simulation standard.

[0060] S13: Compare the ideal output value with the preset measured output set bit by bit, and determine whether a fault exists based on the comparison results.

[0061] In this embodiment, step S13 is used to identify circuit anomalies by quantifying differences, thereby providing a trigger signal for fault diagnosis.

[0062] In specific implementation: The ideal output value calculated in step S12 is compared bit by bit with the preset measured output set (binary response data captured by the ATE device). A difference bit counter is used to compare the logical values ​​vector by vector and port by port. When the number of mismatched bits exceeds a preset threshold (the default threshold is ≥1 bit), a fault presence flag is triggered. Those skilled in the art can implement bit-level XOR operations (difference bit = ideal value ⊕ measured value) using Python scripts, or call the automatic comparison instructions of the ATE interface library (such as SVF or STIL library), and finally output a fault status report (including the coordinates of the difference bits and the statistical difference rate).

[0063] S2: When a fault is detected, traverse all signal lines in the directed acyclic graph to generate a candidate fault set.

[0064] Specifically, step S2 includes the following steps:

[0065] S21: When a fault exists, extract the set of all signal lines in the directed acyclic graph to be analyzed.

[0066] In this embodiment, when a circuit fault is detected, the signal line extraction process is initiated. Adjacency list information is read from the stored directed acyclic graph structure, and a depth-first search algorithm is used to traverse all logic nodes. For each gate node, the program parses the names of the metal interconnects connecting the input and output terminals, and identifies valid signal line identifiers using specific format rules. Subsequently, a signal line hash table is constructed, a topology level value is assigned to each line, and the shortest path length from the signal to the main output is calculated. During signal filtering, the system automatically removes power lines, clock lines, and single-ended connections. Finally, an ordered set of signal lines containing key information such as unique identifiers, network names, and level values ​​is generated. The data is stored as a structured table with an index to optimize access efficiency, laying the foundation for subsequent fault analysis.

[0067] S22: Based on the set of all signal lines, generate an initial fault set containing the assumption of a single fixed fault for each signal line.

[0068] In this embodiment, the system initializes the fault database structure based on the collected signal line set. Two fixed fault records are created for each signal line: a low-level signal latch and a high-level signal latch. Each fault record contains detailed fields such as a unique fault identifier, network name, fault type, associated gate unit, and pin location. For special circuits with multiple drive sources, the system reverse-tracks the circuit netlist to obtain complete drive information. Database integrity rules ensure the accuracy of fault types, and distributed processing technology is employed to handle large-scale circuits. The final generated fault record table establishes a multi-dimensional indexing mechanism to support rapid querying of different types of faults.

[0069] S23: Based on the initial fault set, perform fault combination enumeration operation, control the size of the combination space by the preset maximum number of fault points constraint, and generate a multiple fixed fault extension set.

[0070] In this embodiment, the system uses single-point fault records as a basis and configures a maximum fault point threshold parameter. First, two-point fault combinations are generated. A partitioning technique is used to divide the massive number of fault identifiers into multiple blocks, and a pairwise combination algorithm is executed within each block. Each fault combination undergoes compatibility verification, checking for potential short-circuit conflicts between signal lines and the degree of timing level differences. Verified combinations proceed to the type expansion stage, where the system automatically generates all possible fault type combination schemes. After completing the two-point combinations, the system uses a recursive approach to handle more complex multi-point fault scenarios. The final output multi-fault set undergoes hash deduplication to ensure the integrity and uniqueness of the results, forming a structured, high-density fault data set.

[0071] S24: Combine the initial fault set with the extended set of multiple fixed faults to form a candidate fault set.

[0072] In this embodiment, a distributed key-value storage structure is created to integrate single-point basic faults and multiple complex faults. Each fault combination is assigned a unique hash identifier and includes a detailed list of signal lines, fault type configuration, and combination hierarchy information during storage. Single-point fault records are directly injected into the storage system, while multi-point fault data is imported in batches using streaming processing technology. An efficient filtering mechanism is employed to remove duplicate records, and a global index system is built to achieve a reverse mapping relationship from network identifiers to fault hashes. The final candidate fault set generates statistical information, including key parameters such as the total number of fault points, providing a complete dataset for subsequent optimization analysis.

[0073] S3: Prioritize the candidate fault set based on Boolean difference sensitivity and test coverage, and perform hierarchical simulation matching on the candidate fault set according to the ranking results.

[0074] Specifically, in step S3, the priority ranking step plays a core screening role in the technical solution. It assesses the importance of fault points through multi-dimensional feature quantification, thereby improving diagnostic efficiency. In practice: the system first reads fault records one by one from the candidate fault set database, and concurrently executes three calculation tasks for each fault point:

[0075] Boolean differential sensitivity calculation: Lock the signal line corresponding to the fault point to the fault state (fixed 0 or 1), obtain the original output and fault output through logic simulation, perform bitwise XOR operation to count the number of difference bits, and normalize the result to the [0,1] interval;

[0076] Test coverage statistics: Retrieve the pre-stored test vector-fault coverage matrix, count the number of valid test vectors that detected the fault, and divide by the total number of test vectors to calculate the coverage;

[0077] Structural feature extraction: Real-time calculation of logic depth (the minimum number of gate stages from the current signal to the nearest main output), fan-out coefficient (the number of lower-level gates driven), and sensitization path density (the frequency of occurrence of the signal in the non-zero Boolean differential path).

[0078] The logic depth is used to measure the shortest path length from the signal line to the main output. The calculation process executes the following steps in sequence:

[0079] Main output identification: Screen out the main output port type from all output ports of the entire circuit. These ports are usually marked as key signal output points that can be directly observed.

[0080] Shortest path search: Starting from the signal line corresponding to the fault point, use network traversal to search for the path to the main output level by level.

[0081] The counter increments by one level for each logic gate (such as AND gate or OR gate) passed through;

[0082] Simultaneous tracking of multiple parallel paths;

[0083] Record the current level immediately when any path reaches the main output for the first time.

[0084] Path comparison optimization: When multiple arrival paths exist simultaneously, the path with the fewest gates is automatically selected as the final depth.

[0085] Special handling for loops: If the circuit contains special structures such as feedback loops, the system will establish a virtual path cutting mechanism to prevent infinite loops.

[0086] The fan-out coefficient quantizes the signal line's driving capability and is accurately calculated through the following process:

[0087] Direct-drive gate identification: Accurately locate the next-level logic gate directly connected to the signal line in the circuit connection relationship;

[0088] Physical drive counting rules:

[0089] Each independent gate input pin is counted as 1 drive point;

[0090] Multi-input gates are counted separately based on the actual number of pins;

[0091] Bus structure is segmented and statistically analyzed according to data bit width;

[0092] Driver type distinction:

[0093] Combinational logic gates are counting normally;

[0094] Sequential logic gates (such as register clock terminals) are classified separately;

[0095] The tri-state gate controller is identified as a special drive type.

[0096] Global extreme value acquisition: After counting all signal lines, the maximum driving value is automatically selected as the reference.

[0097] Sensitization path density reflects the activity level of a signal in the fault propagation path. The measurement process includes:

[0098] Sensitization path definition: Only physical pathways that can transmit fault effects to the output under certain test conditions are included in the statistics.

[0099] The full-path detection mechanism includes:

[0100] Traverse all possible signal transmission paths from the circuit's inputs to its outputs;

[0101] Preset test conditions are applied to each pathway;

[0102] The detection of whether a pathway is active can transmit fault effects.

[0103] Signal activity determination includes:

[0104] A signal is marked as a valid occurrence when it successfully transmits the fault to the output under specific test conditions.

[0105] The cumulative count is calculated when the same path appears repeatedly under different test conditions.

[0106] Efficient statistical algorithms, including:

[0107] A tiered caching mechanism is used to record known active paths;

[0108] The addition of a path determines whether it has already been recorded by comparing and detecting feature values.

[0109] The final result is the total number of times the signal appears in all active paths.

[0110] Reference value establishment: After all signal statistics are completed, the maximum count value is automatically found as the reference.

[0111] The dynamic weight calculation engine is then activated: based on the loading coefficient configuration for the diagnostic phase (initial phase: α = 0.6, β = 0.8, γ = 0.4; precise positioning phase: α = 0.9, β = 0.5, γ = 0.3, phase switching is controlled by the fault matching success rate, specifically: initial phase: cumulative matching success rate less than 40%, precise positioning phase: matching success rate greater than or equal to 40%), the following formula for the sorting weight function is applied for matrix-based parallel computation. Finally, the fault points are sorted in descending order using a heap sort algorithm to generate a priority queue for simulation matching. Those skilled in the art can use a CUDA parallel architecture to accelerate computation and use Scikit-learn's MinMaxScaler to implement feature normalization.

[0112] The expression for the sorting weight function is:

[0113]

[0114] Where, ω i Let α represent the priority score of the i-th fault point, α represent the sensitivity adjustment coefficient, and Δf(x) represent the sensitivity adjustment coefficient. i ) represents the signal line x corresponding to the i-th fault point. i Boolean difference sensitivity, β represents the coverage adjustment coefficient, C i Let γ represent the coverage of the i-th fault point, γ represent the structural characteristic adjustment coefficient, and D represent the coverage of the ith fault point. i The signal line x represents the i-th fault point in the candidate fault set. i The minimum logic gate distance to the nearest main output, F i The signal line x corresponding to the i-th fault point iThe number of directly driven lower-level logic gates, P i The signal line x corresponding to the i-th fault point i The number of times F appears in the sensitization path with non-zero Boolean difference. max P represents the maximum value of the fan-out coefficient of all signal lines in the circuit to be diagnosed. max The maximum value of sensitive path density for all fault points.

[0115] Specifically, the hierarchical simulation matching significantly reduces computational complexity through a partitioned verification mechanism. In practice: the system first generates a fault point weight queue based on priority ranking, dynamically calculating the size parameter of the high-ranking region, which is jointly determined by the total number of circuit gates, the total number of candidate fault points, and the fault density. A parallel simulation engine is established to inject fault states into fault points in the high-ranking region in batches: the fault point configuration is read one by one, the logic state of the corresponding signal line is forcibly modified in the circuit simulation model (fixed to 0 or 1 level), a pre-generated test vector set is applied, and the simulated response values ​​of each main output port are collected. The system automatically compares the simulated output with the measured data bit by bit, and uses the Hamming distance algorithm to calculate the matching score: a perfect match scores 1, and points are deducted proportionally for any discrepancies. When no fault point with a matching score exceeding the set threshold (≥0.95) is found in the high-ranking region, the system automatically extracts the next segment of fault points from the weight queue, iteratively executing the injection simulation and matching evaluation process until a qualified fault point is found or the entire candidate set is traversed.

[0116] The hierarchical simulation matching includes:

[0117] First, based on the priority sorting results, the top N fault points with the highest sorting weight are extracted as the high-sorting fault set, where N is dynamically calculated according to the size and fault density of the circuit to be diagnosed.

[0118] In this embodiment, the dynamic calculation of the high-order region size parameter N is the core control mechanism of the hierarchical strategy. The system acquires three key parameters in real time: the total number of candidate fault points, the total number of circuit gates, and the fault point density per unit number of gates. The verification scale is comprehensively evaluated through a nonlinear function model: the square root of the total number of circuit gates reflects the basic scale requirement, the fault point density serves as a weight adjustment factor, and the logarithmic function of the total number of candidate fault points suppresses scale expansion. The calculation results are processed by double threshold constraints: the lower limit ensures the minimum verification scale (at least 5 fault points), and the upper limit prevents resource overload (no more than 50 fault points). During implementation, the distributed computing nodes are called to synchronize parameters, a dynamic partitioning scheme is generated in microseconds, and partitioning instructions are sent to the simulation engine.

[0119] Specifically, the formula for calculating N is:

[0120]

[0121] Where M represents the total number of fault points in the candidate fault set, G represents the total number of gates in the circuit to be diagnosed, and ρ is the fault density, that is, the number of fault points per unit number of gates, reflecting the density of fault distribution.

[0122] Secondly, simulations are injected into each fault point in the high-ranking fault set to calculate the simulated output response of the corresponding preset test vector.

[0123] In this embodiment, fault injection employs hardware-in-the-loop (HIL) technology: the system parses the fault point configuration file and locates the physical coordinates (gate cell / pin coordinates) of the target signal line. Fault instructions are written to the simulation model via a digital twin interface: for single-point faults, the signal drive values ​​are directly modified (SA0 is set to 0 level, SA1 to 1 level); for combined faults, multiple fault states are written in batches. Test vectors drive the simulation model according to a preset clock cycle: the original input port receives the vector bit stream, and the logic state propagation is advanced in clock cycles within the register transfer stage model. Output response capture uses a window sampling mechanism: the main output port value is captured during stable periods to eliminate metastability. Finally, a structured response dataset (test vector ID - output port - logic value matrix) is generated, providing input for accurate matching.

[0124] Next, the simulated output response is compared with a preset set of measured outputs to evaluate the degree of matching.

[0125] In this embodiment, the simulated response data and the measured data are aligned by port, and an XOR operation is performed bit by bit. The total number of differing bits is dynamically counted, and the matching score is calculated according to the formula. Two trigger thresholds are set: a perfect match (match degree = 1) immediately outputs the diagnostic result; a highly suspected match (match degree ≥ 0.9) generates a list to be verified; and if the match degree is below the threshold, partition expansion is activated.

[0126] The partition expansion employs a sliding window mechanism: starting from the end point of the current verification interval in the global fault point weight queue, the next segment is extracted according to dynamically calculated new scale parameters. Historical simulation data is cached to avoid repeatedly injecting the same fault point, while the verification status mapping table is updated to achieve seamless transitions between multiple verification rounds. The termination condition is set to successful matching or cumulative verification coverage ≥ 95%.

[0127] Finally, when no consistency faults are found in the matching evaluation, the fault set is expanded to the next sorted area according to the sorting weight, and the simulation and matching evaluation are repeated.

[0128] S4: For the fault matching results obtained after hierarchical simulation matching, Boolean difference analysis is used to perform multi-fault combination optimization verification, and the optimized and verified fault diagnosis results are output.

[0129] Specifically, step S4 includes the following steps:

[0130] S41: For each fault combination in the fault matching result set, calculate the combined Boolean difference sensitivity value.

[0131] In this embodiment, the calculation of the combined Boolean difference sensitivity value plays a core role in the optimization of multiple fault verification in the technical solution. By quantifying the combined impact of fault combinations on the overall circuit output, the limitations of single-point sensitivity assessment are solved.

[0132] In practice: The fault matching result set (containing multiple candidate fault combinations) output from the hierarchical simulation matching is received, and a cooperative sensitivity analysis is performed on each fault combination C. First, all faulty signal lines in the combination are locked, and each signal line is injected with its corresponding fault state (fixed to 0 or 1). Then, cooperative logic simulation is performed under test vector drive, acquiring the baseline output f_0 in fault-free mode and the output f_C when there is a fault combination. Finally, the difference pattern is calculated through a bitwise XOR operation: ΔF_C = f_0 ⊕ f_C, where each bit difference represents the sensitivity response of the output port to the fault combination. The result is normalized to a comprehensive sensitivity value in the [0,1] interval, with the formula |ΔF_C| = number of difference bits / (number of output ports × number of vectors).

[0133] S42: Based on the combined Boolean difference sensitivity value, the tabu search algorithm is used to perform spatial reduction on the fault matching result set, and the reduced optimized fault combination set is output as the fault diagnosis result.

[0134] In this embodiment, the spatial reduction step is used to compress the size of candidate solutions, filter high-probability fault combinations based on sensitivity values, and avoid wasting diagnostic resources.

[0135] The specific implementation includes: first, establishing an evaluation function mapping table, directly associating the unique identifier of each combination with its combination Boolean difference sensitivity value |ΔF_C|; then configuring the tabu search algorithm parameters, including the neighborhood radius (single-point change), tabu list length (recommended 50-100), and termination condition (continuous). (No improvement here, M is the total number of combinations). The algorithm initializes by selecting the combination with the highest sensitivity as the current solution, iteratively generating a neighborhood solution set: new combinations are generated by adding, deleting, or replacing individual fault points, and recently accessed taboo solutions are filtered out. During the evaluation phase, a preset sensitivity value table is directly queried to select the optimal solution and update the current solution. When the termination condition is met, the historical best solution set (usually retaining the Top 3) is output.

[0136] The spatial reduction includes:

[0137] First, a solution space evaluation function is constructed based on the combined Boolean difference sensitivity value, wherein the evaluation function value is equal to the corresponding combined Boolean difference sensitivity value.

[0138] In this embodiment, the function provides a mathematical definition of the optimization direction in the technical solution and serves as the decision basis for tabu search. The specific construction process is as follows: a global dictionary data structure is created, with the key being the sorted index (e.g., a hash value) of the fault combination, and the value being the pre-calculated combination Boolean difference sensitivity value |ΔF_C|. When the algorithm needs to evaluate the quality of the solution, the corresponding value is retrieved from the dictionary in real time based on the combination identifier, without secondary calculation.

[0139] Secondly, tabu search optimization is performed based on the solution space evaluation function, and the optimization is terminated when the termination condition is met after multiple consecutive iterations.

[0140] In this embodiment, the optimization process achieves efficient exploration of the solution space through an intelligent iterative mechanism, thus solving the combinatorial explosion problem.

[0141] Specific process: After initialization, enter the loop processing stage. In each round, generate a neighborhood solution set and filter taboo solutions; select the optimal candidate solution through the evaluation function. If it is better than the current optimal solution, update the global optimal record; regardless of whether there is improvement, add the current operation feature (such as the changed fault point index) to the taboo table; check the termination condition (no quality improvement after K consecutive iterations).

[0142] This step ultimately leads to an actionable diagnostic conclusion, establishing a complete closed loop for the technical solution.

[0143] Specific process: Convert the optimized fault combination set output by tabu search into an engineering-readable format; generate a diagnostic report for each combination, including a fault signal line location map, sensitivity analysis map, and repair suggestions.

[0144] Example 2

[0145] This invention also provides a fault diagnosis system for integrated circuits, used to execute the aforementioned fault diagnosis method for integrated circuits, with reference to... Figure 2 As shown, the system includes:

[0146] The fault detection module 100 is used to calculate the ideal output value corresponding to all pre-generated test vectors based on the Boolean expression of the directed acyclic graph of the circuit to be diagnosed, and to perform fault detection in combination with the preset set of measured outputs.

[0147] The fault set generation module 200 is used to traverse all signal lines in the directed acyclic graph to generate a candidate fault set when a fault is detected.

[0148] The hierarchical simulation matching module 300 is used to prioritize the candidate fault set based on Boolean difference sensitivity and test coverage, and to perform hierarchical simulation matching on the candidate fault set according to the ranking result.

[0149] The optimization and verification module 400 is used to perform multi-fault combination optimization and verification on the fault matching results obtained after hierarchical simulation matching through Boolean difference analysis, and output the optimized and verified fault diagnosis results.

[0150] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0151] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, including read-only memory (ROM), random access memory (RAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), one-time programmable read-only memory (OTPROM), electrically-Erasable Programmable Read-Only Memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, disk storage, magnetic tape storage, or any other computer-readable medium capable of carrying or storing data.

[0152] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

Claims

1. A fault diagnosis method for integrated circuits, characterized in that, The method includes the following steps: The Boolean expression of the directed acyclic graph of the circuit to be diagnosed is used to calculate the ideal output value corresponding to all pre-generated test vectors, and the fault detection is performed by combining the preset set of measured outputs. When a fault is detected, all signal lines in the directed acyclic graph are traversed to generate a candidate fault set; The candidate fault set is prioritized based on Boolean difference sensitivity and test coverage, and hierarchical simulation matching is performed on the candidate fault set according to the ranking results. The fault matching results obtained after hierarchical simulation matching are optimized and verified by Boolean difference analysis, and the optimized and verified fault diagnosis results are output.

2. The fault diagnosis method for an integrated circuit according to claim 1, characterized in that, The fault detection specifically includes: A network model for generating Boolean expressions based on the directed acyclic graph of the circuit to be diagnosed; The Boolean expression network model is used to calculate the ideal output value corresponding to all pre-generated test vectors. The ideal output value is compared bit by bit with the preset set of measured outputs, and the existence of a fault is determined based on the comparison results.

3. The fault diagnosis method for an integrated circuit according to claim 2, characterized in that, The generation of the candidate fault set includes: When a fault exists, extract the set of all signal lines in the directed acyclic graph to be analyzed; Based on the set of all signal lines, an initial fault set is generated that includes the assumption of a single fixed type fault for each signal line; Based on the initial fault set, a fault combination enumeration operation is performed, and the size of the combination space is controlled by a preset maximum number of fault points to generate a multiple fixed fault extension set. The initial fault set is combined with the extended set of multiple fixed faults to form a candidate fault set.

4. The fault diagnosis method for an integrated circuit according to claim 3, characterized in that, The priority sorting includes: Calculate the Boolean difference sensitivity of each fault point in the candidate fault set and calculate the coverage of each fault point by the test vector; Extract the structural feature set of each fault point, wherein the structural feature set includes logic depth, fan-out coefficient and sensitive path density; Based on Boolean difference sensitivity, coverage, and structural feature set, a ranking weight is calculated using a ranking weight function, and the data is then ranked. The expression for the ranking weight function is as follows: Where, ω i Let α represent the priority score of the i-th fault point, α represent the sensitivity adjustment coefficient, and Δf(x) represent the sensitivity adjustment coefficient. i ) represents the signal line x corresponding to the i-th fault point. i Boolean difference sensitivity, β represents the coverage adjustment coefficient, C i Let γ represent the coverage of the i-th fault point, γ represent the structural characteristic adjustment coefficient, and D represent the coverage of the ith fault point. i The signal line x represents the i-th fault point in the candidate fault set. i The minimum logic gate distance to the nearest main output, F i The signal line x corresponding to the i-th fault point i The number of directly driven lower-level logic gates, P i The signal line x corresponding to the i-th fault point i The number of times F appears in the sensitization path with non-zero Boolean difference. max P represents the maximum value of the fan-out coefficient of all signal lines in the circuit to be diagnosed. max The maximum value of sensitive path density for all fault points.

5. A fault diagnosis method for an integrated circuit according to claim 4, characterized in that, The hierarchical simulation matching includes: Based on the priority sorting results, the top N fault points with the highest sorting weight are extracted as the high-sorting fault set, where N is dynamically calculated according to the scale and fault density of the circuit to be diagnosed. Simulations are injected into each fault point in the high-ranking fault set, and the simulated output response of the corresponding preset test vector is calculated. The matching degree between the simulated output response and the preset set of measured outputs is evaluated; When no consistency faults are found in the matching evaluation, the fault set is expanded to the next sorted area according to the sorting weight, and the simulation and matching evaluation are repeated.

6. The fault diagnosis method for an integrated circuit according to claim 5, characterized in that, The formula for calculating N is: Where M represents the total number of fault points in the candidate fault set, G represents the total number of gates in the circuit to be diagnosed, and ρ is the fault density.

7. A fault diagnosis method for an integrated circuit according to claim 6, characterized in that, The verification of multi-fault combination optimization through Boolean difference analysis includes: For each fault combination in the fault matching result set, calculate the combined Boolean difference sensitivity value; Based on the combined Boolean difference sensitivity value, the tabu search algorithm is used to perform spatial reduction on the fault matching result set, and the reduced optimized fault combination set is output as the fault diagnosis result.

8. A fault diagnosis method for an integrated circuit according to claim 7, characterized in that, The spatial reduction includes: A solution space evaluation function is constructed based on the combined Boolean difference sensitivity value, wherein the evaluation function value is equal to the corresponding combined Boolean difference sensitivity value; Tabu search optimization is performed based on the solution space evaluation function, and the optimization terminates when the termination condition is met after multiple consecutive iterations.

9. A fault diagnosis system for an integrated circuit, used to perform a fault diagnosis method for an integrated circuit as described in any one of claims 1 to 8, characterized in that, The system includes: The fault detection module is used to calculate the ideal output value corresponding to all pre-generated test vectors based on the Boolean expression of the directed acyclic graph of the circuit to be diagnosed, and to perform fault detection in combination with the preset set of measured outputs. The fault set generation module is used to traverse all signal lines in the directed acyclic graph to generate a candidate fault set when a fault is detected. The hierarchical simulation matching module is used to prioritize the candidate fault set based on Boolean difference sensitivity and test coverage, and to perform hierarchical simulation matching on the candidate fault set according to the ranking result. The optimization and verification module is used to perform multi-fault combination optimization and verification on the fault matching results obtained after hierarchical simulation matching through Boolean difference analysis, and output the optimized and verified fault diagnosis results.

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