A model order reduction method, system, terminal and computer readable storage medium for multi-port linear circuits

Abstract

The application discloses a model order reduction method, system, terminal and computer readable storage medium of a multi-port linear circuit. The method comprises the following steps: obtaining a to-be-reduced circuit model, reducing the number of ports of the to-be-reduced circuit model according to a port reduction strategy, and obtaining a target circuit model; based on the target circuit model, a residual module and a tensor mapping structure, a target mapping equation is constructed, the tensor mapping structure is used to represent the correlation between the to-be-reduced circuit model and the target circuit model, and the residual module is used to predict the corresponding output according to the input; training data sets are generated according to the to-be-reduced circuit model, the residual module and the tensor mapping structure in the target mapping equation are trained, and a trained target mapping equation is obtained; and a reduced order result is generated according to the target circuit model and the trained target mapping equation. The application can use the trained target mapping equation on the basis of the target circuit model, so that the accuracy of the multi-port model after order reduction can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of linear system model order reduction, and in particular, to a model order reduction method, system, terminal and computer readable storage medium for a multi-port linear circuit. BACKGROUND

[0002] Model order reduction (MOR) techniques for linear systems have been widely applied in multiple stages of the electronic design automation (EDA) flow to accelerate the exploration and optimization of the design space. However, the traditional projection-based MOR methods have significant efficiency bottlenecks when facing systems with a large number of input / output ports. To address this issue, current methods either compress the input / output matrices through singular value decomposition (SVD) or decouple the input / output ports to reduce the number of ports involved in modeling, or model for specific inputs.

[0003] However, among the current methods for addressing the problem of large port numbers, input-independent MOR methods cannot balance modeling accuracy and computational resources, while MOR methods that rely entirely on specific inputs lack flexibility and robustness, making it difficult to meet the growing demand for power modeling in advanced integrated circuit design and affecting the implementation of electronic design automation.

[0004] Therefore, the prior art still needs to be improved and developed. SUMMARY

[0005] The main purpose of the present application is to provide a model order reduction method, system, terminal and computer readable storage medium for a multi-port linear circuit, which aims to solve the problem that in the prior art, input-independent MOR methods cannot balance modeling accuracy and computational resources, while MOR methods that rely entirely on specific inputs lack flexibility and robustness, making it difficult to meet the growing demand for power modeling in advanced integrated circuit design and affecting the implementation of electronic design automation.

[0006] To achieve the above-mentioned purpose, the present application provides a model order reduction method for a multi-port linear circuit, which comprises the following steps:

[0007] Obtaining a circuit model to be reduced, reducing the number of ports of the circuit model to be reduced according to a port reduction strategy to obtain a target circuit model;

[0008] construct a target mapping equation based on the target circuit model, the residual module and the tensor mapping structure, wherein the tensor mapping structure is used to represent the correlation between the to-be-reduced-order circuit model and the target circuit model, and the residual module is used to predict the corresponding output according to the input;

[0009] generate a training data set according to the to-be-reduced-order circuit model, and train the residual module and the tensor mapping structure in the target mapping equation according to the training data set to obtain a training completed target mapping equation;

[0010] generate a reduced-order result according to the target circuit model and the training completed target mapping equation.

[0011] Optionally, the to-be-reduced-order circuit model is obtained, and the number of ports of the to-be-reduced-order circuit model is reduced according to a port reduction strategy to obtain a target circuit model, and specifically includes:

[0012] The to-be-reduced-order circuit model is obtained, and singular value decomposition is performed on the input and output of the to-be-reduced-order circuit model according to a port reduction strategy to obtain a first to-be-reduced-order circuit model after the number of ports is reduced.

[0013] The first to-be-reduced-order circuit model is reduced according to a preset model reduction algorithm to obtain a target circuit model.

[0014] Optionally, the target mapping equation is constructed based on the target circuit model, the residual module and the tensor mapping structure, and specifically includes:

[0015] The target mapping equation is constructed based on the target circuit model, the residual module and the tensor mapping structure, and the target mapping equation is represented as:

[0016] ;

[0017] wherein, represents the input, represents the residual module between high and low precision, represents the residual module calculation result, represents the tensor mapping structure, represents the second precision output, represents the first precision output.

[0018] Optionally, the training data set is generated according to the to-be-reduced-order circuit model, and specifically includes:

[0019] Time domain simulation is performed on the to-be-reduced-order circuit model for a preset number of times, and the second precision output obtained by each time domain simulation is obtained;

[0020] According to all time domain simulation inputs and corresponding second-precision outputs, a training data set is generated.

[0021] Optionally, the residual module and the tensor mapping structure in the target mapping equation are trained according to the training data set, and a training completed target mapping equation is obtained.

[0022] According to the training data set, the residual module and the tensor mapping structure in the target mapping equation are trained based on a joint optimization method.

[0023] When the training reaches a preset requirement, the training is ended, and the training completed target mapping equation is obtained according to the residual module and the tensor mapping structure obtained in the last training.

[0024] Optionally, the residual module and the tensor mapping structure in the target mapping equation are trained according to the training data set based on a joint optimization method, and the training completed target mapping equation is obtained.

[0025] The time domain simulation input in the training data set is input into a target circuit model to obtain a training first-precision output, and the training first-precision output is input into the target mapping equation to obtain a mapping output and residual data.

[0026] The residual prediction output by the tensor mapping structure is obtained, and the residual module and the tensor mapping structure are optimized according to the residual data and the residual prediction.

[0027] Optionally, the time domain simulation input in the training data set is input into a target circuit model to obtain a training first-precision output, and the training first-precision output is input into the target mapping equation to obtain a mapping output and residual data.

[0028] The time domain simulation input in the training data set is input into a target circuit model to obtain a training first-precision output.

[0029] The training first-precision output is input into the target mapping equation, and a mapping output is generated according to the tensor mapping structure in the target mapping equation.

[0030] The training first-precision output, the second-precision output and the mapping output are substituted into the target mapping equation to obtain residual data.

[0031] In addition, to achieve the above object, the application further provides a model order reduction system of a multi-port linear circuit, wherein the model order reduction system of the multi-port linear circuit comprises:

[0032] An order reduction module is configured to obtain a to-be-reduced circuit model, reduce the number of ports of the to-be-reduced circuit model according to a port reduction strategy, and obtain a target circuit model.

[0033] a construction module, configured to construct a target mapping equation based on the target circuit model, a residual module and a tensor mapping structure, wherein the tensor mapping structure is used to represent the correlation between the to-be-reduced-order circuit model and the target circuit model, and the residual module is used to predict the corresponding output according to the input;

[0034] a training module, configured to generate a training data set according to the to-be-reduced-order circuit model, and train the residual module and the tensor mapping structure in the target mapping equation according to the training data set, to obtain a trained target mapping equation;

[0035] a result generation module, configured to generate a reduced-order result according to the target circuit model and the trained target mapping equation.

[0036] In addition, to achieve the above object, the present application also provides a terminal, wherein the terminal comprises a memory, a processor and a model reduction program of a multi-port linear circuit stored in the memory and executable on the processor, and the model reduction program of the multi-port linear circuit implements the steps of the model reduction method of the multi-port linear circuit when executed by the processor.

[0037] In addition, to achieve the above object, the present application also provides a computer readable storage medium, wherein the computer readable storage medium stores a model reduction program of a multi-port linear circuit, and the model reduction program of the multi-port linear circuit implements the steps of the model reduction method of the multi-port linear circuit when executed by a processor.

[0038] In the present application, a to-be-reduced-order circuit model is acquired, the number of ports of the to-be-reduced-order circuit model is reduced according to a port reduction strategy to obtain a target circuit model; a target mapping equation is constructed based on the target circuit model, a residual module and a tensor mapping structure, wherein the tensor mapping structure is used to represent the correlation between the to-be-reduced-order circuit model and the target circuit model, and the residual module is used to predict the corresponding output according to the input; a training data set is generated according to the to-be-reduced-order circuit model, and the residual module and the tensor mapping structure in the target mapping equation are trained according to the training data set to obtain a trained target mapping equation; and a reduced-order result is generated according to the target circuit model and the trained target mapping equation. The present application reduces the port dimension of the system through the port reduction strategy, then acquires a low-precision reduced-order model in combination with the traditional MOR technology, and then corrects the deviation between the low-precision model and the real system behavior based on the target mapping equation, and the correlation of the system in the port dimension and the time dimension is fully mined through the tensor mapping structure, so that more accurate output prediction is realized under limited samples, and thus the reduced-order result that can output accurate results is obtained. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 is a flow chart of a preferred embodiment of the model order reduction method of the multi-port linear circuit of the present invention;

[0040] Figure 2 is a conceptual diagram of the accuracy compensation in the model order reduction method of the multi-port linear circuit of the present invention;

[0041] Figure 3 is a diagram of the overall implementation framework in the model order reduction method of the multi-port linear circuit of the present invention;

[0042] Figure 4 is a prediction visualization display diagram of the tensor mapping learning in the model order reduction method of the multi-port linear circuit of the present invention;

[0043] Figure 5 is a structural diagram of a preferred embodiment of the model order reduction system of the multi-port linear circuit of the present invention;

[0044] Figure 6 is a structural diagram of a preferred embodiment of the terminal of the present invention. DETAILED DESCRIPTION

[0045] In order to make the objects, technical solutions and advantages of the present invention clearer and more explicit, the present invention will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0046] Model reduction techniques for linear systems have been widely applied in multiple stages of the electronic design automation (EDA) flow to accelerate the exploration and optimization of the design space. One key application scenario of MOR is chip power modeling (CPM), in which the large-scale power delivery network (PDN) inside a chip is usually modeled as a large RLC network and reduced to a smaller equivalent model by MOR techniques to support co-simulation analysis of the chip and package. Currently, subspace-based Krylov subspace methods, such as the PRIMA (Passive Reduced-Order Interconnect Macromodeling Algorithm) algorithm, are widely adopted as the mainstream MOR solution due to their good matrix matching ability, efficient processing of sparse matrices, and good compression rate. However, traditional projection-based MOR methods have significant efficiency bottlenecks when facing systems with a large number of input / output ports. Taking PRIMA as an example, its computational overhead and the size of the final reduced-order model (ROM) usually increase linearly or even faster with the number of ports. With the continuous increase in the complexity of integrated circuits (ICs), especially in emerging multi-core three-dimensional integrated architectures, the scale of PDN nodes can reach millions, and the number of ports can reach tens of thousands. The reduction modeling of such ultra-large-scale networks has become a key bottleneck for power integrity design and optimization. To alleviate the problem caused by a large number of ports, existing technologies mainly fall into two categories: one is to compress the input / output matrix through singular value decomposition (SVD) or decouple the input / output ports to reduce the number of ports involved in modeling. This class of methods has input independence, and the resulting ROM can be reused for any input scenario, but usually has a large error because it no longer strictly satisfies the matrix matching condition of the original system. The other class of methods models for specific inputs, which has higher accuracy and modeling efficiency, but lacks reusability and cannot cope with complex and variable input patterns in actual design. Therefore, among the existing methods for alleviating the problem caused by a large number of ports, the input-independent MOR method is difficult to balance modeling accuracy and computational resources, and the MOR method that relies entirely on specific inputs lacks flexibility and robustness, which cannot meet the growing demand for power modeling in advanced integrated circuit design, thereby affecting the implementation of electronic design automation.

[0047] To address one or more of the above-mentioned problems, this invention obtains a circuit model to be reduced in order, reduces the number of ports in the circuit model to be reduced in order according to a port reduction strategy, and obtains a target circuit model; based on the target circuit model, residual modules, and tensor mapping structure, a target mapping equation is constructed; based on the circuit model to be reduced in order, a training dataset is generated, and the residual modules and tensor mapping structure in the target mapping equation are trained based on the training dataset to obtain a trained target mapping equation; based on the target circuit model and the trained target mapping equation, a reduction in order result is generated.

[0048] The preferred embodiment of the present invention describes a model reduction method for multi-port linear circuits, such as... Figure 1 As shown, the model reduction method for the multi-port linear circuit includes the following steps:

[0049] Step S10: Obtain the circuit model to be downgraded, and reduce the number of ports in the circuit model to be downgraded according to the port reduction strategy to obtain the target circuit model.

[0050] Specifically, in this invention, for the circuit model to be reduced in order, the number of ports in the system is first reduced, and the corresponding order reduction process is performed to obtain the corresponding target circuit model, which is a low-precision circuit model.

[0051] Further, the step of obtaining the circuit model to be downgraded, and reducing the number of ports in the circuit model to be downgraded according to the port reduction strategy to obtain the target circuit model, specifically includes:

[0052] Obtain the circuit model to be downgraded, and perform singular value decomposition on the input and output of the circuit model to be downgraded according to the port reduction strategy to obtain the first circuit model to be downgraded after the number of ports is reduced.

[0053] The first circuit model to be reduced in order is reduced according to the preset model reduction algorithm to obtain the target circuit model.

[0054] Specifically, most current methods for reducing the number of ports in a system rely on complex mathematical formulas, which leads to significant implementation complexity and computational overhead. This invention employs a method based on input and output matrices. A simple port reduction method for decomposition.

[0055] In this invention, the input matrix is ​​made to... and output matrix Same, that is ,right B and L Matrix operation (Singular value decomposition). This yields the following expression:

[0056] ;

[0057] wherein, is the left singular vector of matrix, is the singular value matrix, is the right singular vector matrix, T denotes the transpose; and are the truncated sub-matrices, the present invention selects the first r largest singular values , is the original port number, through this truncated approximation, the original transfer function will be from the original :

[0058] ;

[0059] into the following form:

[0060] ;

[0061] wherein, denotes the changed transfer function, denotes the complex frequency variable, , is the angular frequency, denotes the real part, denotes the imaginary part, i.e. the imaginary unit, denotes the conductance matrix, which is composed of linear elements such as resistance, admittance, etc., and reflects the conductance relationship between nodes, denotes the capacitance matrix, which is composed of energy storage elements such as capacitance, inductance, etc.

[0062] the middle part, i.e. is changed into the new model of the present invention which needs to be reduced, i.e. the first to-be-reduced circuit model, wherein the port number of the middle part has been reduced from to , wherein denotes the transfer function corresponding to the middle part. In the method of reducing the port number by singular value decomposition proposed in the present invention, any model reduction method, such as , can be applied to this less-port system to obtain a reduced model (the reduced model is obtained by through or other model reduction algorithms). After that, the original circuit with ports can be restored by the formula:

[0063] ;

[0064] wherein, is the restored model of the original circuit with ports, it is worth noting that the model order reduction process of the core is only applied to a system with only ports, so the calculation efficiency and the final order of the explained model will be improved. The restored port model is used for subsequent simulation to ensure port compatibility with the original circuit.

[0065] The target circuit model obtained by reducing the order of the first circuit model to be reduced in order by the preset model order reduction method is used for subsequent processing. The preset model order reduction method is preselected. In an embodiment of the present application, the preset model order reduction method can be .

[0066] Step S20, based on the target circuit model, the residual module and the tensor mapping structure, constructing a target mapping equation, wherein the tensor mapping structure is used to represent the correlation between the circuit model to be reduced in order and the target circuit model, and the residual module is used to predict the corresponding output according to the input.

[0067] Specifically, in the present application, the compressed circuit is obviously inaccurate because it not only contains the error of model order reduction, but also contains the error of port compression step. Since only a small part of singular values can be retained, this port reduction error is particularly serious for high port number. In order to solve this accuracy problem, the original model is represented as a high-precision model, and the corresponding solution or output is taken as the true value or high-precision data. Then use these two multi-precision data with differences to train a compensation network at a specific representative input, that is, the corresponding residual module and tensor mapping structure. The trained residual module can generate the corresponding output according to each input, and the trained tensor mapping structure can correspond to represent the correlation between the circuit model to be reduced in order and the target circuit model, so that the target mapping equation can optimize the output of the target circuit model to approach the corresponding high-precision output. This compensation network is mainly used to improve the accuracy of the low-precision output to the high-precision level, and the corresponding improvement is achieved by using the target mapping equation, wherein the target mapping equation is a multi-precision mapping equation. The specific concept diagram of this accuracy compensation is shown in Figure 2 .

[0068] Further, the target mapping equation is constructed based on the target circuit model, the residual module and the tensor mapping structure, and specifically includes:

[0069] Based on the target circuit model, the residual module and the tensor mapping structure, a target mapping equation is constructed, and the target mapping equation is represented as:

[0070] ;

[0071] wherein, represents an input, represents a residual module between high and low precision, represents a residual module calculation result, represents a tensor mapping structure, represents a second precision output, represents a first precision output.

[0072] wherein, and are transient simulation outputs of high-precision and low-precision models respectively, and an input and an output are determined through a mapping equation, that is: then a target mapping equation can be constructed.

[0073] In step S30, a training data set is generated according to the to-be-reduced circuit model, and the residual module and the tensor mapping structure in the target mapping equation are trained according to the training data set, so as to obtain a training completed target mapping equation.

[0074] Specifically, in the present application, is defined as a high-precision data set, is defined as a low-precision data set, and an input represents a voltage input to a circuit and a current source excitation , and are transient simulation outputs of high-precision and low-precision models respectively, wherein the high-precision model is the to-be-reduced circuit model, and a corresponding training data set can be obtained, and the residual module and the tensor mapping structure in the corresponding target mapping equation are trained by using the training data set.

[0075] The training data set is generated according to the to-be-reduced circuit model, and specifically includes:

[0076] A preset number of time domain simulations are performed on the to-be-reduced circuit model, and a second precision output obtained by each time domain simulation is acquired;

[0077] A training data set is generated according to all time domain simulation inputs and corresponding second precision outputs.

[0078] Specifically, the corresponding training data set is acquired through time domain simulation, and then the residual module and the tensor mapping structure are trained.

[0079] Further, the residual module and the tensor mapping structure in the target mapping equation are trained according to the training data set, and a training completed target mapping equation is obtained.

[0080] According to the training data set, the residual module and the tensor mapping structure in the target mapping equation are trained based on a joint optimization method.

[0081] When the training reaches a preset requirement, the training is ended, and a training completed target mapping equation is obtained according to the residual module and the tensor mapping structure obtained by the last training.

[0082] The specific training process is as shown in Figure 3 , including a training route, a prediction route and a component part in a framework scheme that needs to be learned by weight, and it can be seen that the prediction of the input of the present application is realized by an ANN (Artificial Neural Network, artificial neural network) network, and the prediction from to is realized by mapping processing of two tensor mapping matrices. When the corresponding training reaches a preset requirement, the corresponding training is ended, and the preset requirement is a preset training number or model accuracy.

[0083] Further, the residual module and the tensor mapping structure in the target mapping equation are trained according to the training data set, and a training completed target mapping equation is obtained.

[0084] The time domain simulation input in the training data set is input into a target circuit model to obtain a training first accuracy output, and the training first accuracy output is input into the target mapping equation to obtain a mapping output and residual data.

[0085] The residual prediction output by the tensor mapping structure is obtained, and the residual module and the tensor mapping structure are optimized according to the residual data and the residual prediction.

[0086] Specifically, in the present application, in order to learn the correlation between high and low precision data, a tensor mapping structure component is proposed, specifically, a low precision input tensor

[0087] is given, wherein represents a real number set, is a data amount, is a dimension of data in each dimension, is 1 to N, and a series of mapping matrices corresponding to a tensor mode n are defined. After the input tensor, the following operations are performed:

[0088] ;

[0089] represents the tensor matrix multiplication with modulo-n, where the tensor matrix multiplication is represented as:

[0090] ;

[0091] represents the tensor matrix to be multiplied, i and j represents the modulo of the tensor matrix, where, j represents the corresponding modulo that needs to perform the modulo-n tensor multiplication, i represents the rest of the modulo.

[0092] In the present application, the multi-precision tensor mapping structure is mainly used to utilize the correlation between the ports and the time of the data. This is because there is a correlation between the output responses of the ports and the time of the ports, and the time in the same system, and the utilization of these correlations can significantly improve the learning ability and the efficiency of the compensation network. According to the actual needs, is organized into such a three-dimensional tensor ; and represent the number of ports and the simulation step length, respectively, represents the batch size. In this tensor mapping, two learnable mapping matrices are introduced, where, is responsible for the response correlation between different ports at the same time point, is responsible for the response correlation between different time points of the same port, where, represents the number of ports of the high-precision circuit, represents the simulation time of the high-precision circuit; then the mapped tensor can be calculated as:

[0093] ;

[0094] are two learnable tensor mapping matrices that are initialized as diagonal matrices, because at the beginning, the model will consider that there is no timing correlation between different ports and different times. During the training process, the non-diagonal learnable variables gradually learn the correlation information between the ports and the ports, and the timing and the timing. Through the calculation of , the two learnable mapping matrices will finally help the overall algorithm to calculate the final compensation result, which will calculate an MSE loss (Mean Squared Error Loss) with the true result, and finally update the learnable parameters of the matrix through the backpropagation process of pytorch.

[0095] like Figure 4 As shown, a simple example explains why this mapping matrix can achieve this function; the trained matrix... It is no longer a diagonal matrix. For the given example, the low-precision output... It is The matrix, where each column represents the output of all ports at a time step. The first line and The result of multiplying the first column is the predicted output of the sample at the first time point of the first port.

[0096] Furthermore, the present invention mainly includes two learnable components: a tensor learning structure. and a residual network The residual network is implemented using a multilayer perceptron network. During training, and The parameters in the model are jointly trained to ensure that the learned mappings are consistent with the residual predictions. Specifically, the Adam optimizer is used, and the learning rate during training is set. The MSE loss is calculated using the final compensation result predicted by the overall framework and the true result to represent the overall final loss. Finally, gradient backpropagation and weight updates are performed through PyTorch's backpropagation process. Here, both the ANN and the two mapping matrices update the weight parameters through backpropagation.

[0097] The step of inputting the time-domain simulation input from the training dataset into the target circuit model to obtain the first-precision training output, and then inputting the first-precision training output into the target mapping equation to obtain the mapping output and residual data, specifically includes:

[0098] The time-domain simulation input from the training dataset is input into the target circuit model to obtain the first precision output of the training;

[0099] The first precision output of the training is input into the target mapping equation, and a mapping output is generated according to the tensor mapping structure in the target mapping equation;

[0100] Substituting the training first precision output, second precision output, and mapping output into the target mapping equation yields the residual data.

[0101] Specifically, given a low-precision response output First, it goes through a tensor mapping structure. Obtain the mapped output Then the residual data is passed through get( This refers to the high-precision result corresponding to the low-precision response, i.e., the simulation output obtained from the original model. i.e. residual network target output to be predicted, input In the present invention, the simulation containing port voltage or current excitation in the whole simulation range is needed to be organized into and respond to the output of the same dimension. The input is needed to be input into the residual network to predict the corresponding prediction result .

[0102] Step S40, generating the order reduction result according to the target circuit model and the trained target mapping equation.

[0103] After obtaining the target circuit model and the trained target mapping equation, the order reduction result is obtained, which corresponds to the low-precision result for each input voltage and current source excitation to the circuit, and obtains the accurate result by using the trained target mapping equation.

[0104] The present application obtains a to-be-reduced circuit model, reduces the number of ports of the to-be-reduced circuit model according to a port reduction strategy to obtain a target circuit model; constructs a target mapping equation based on the target circuit model, a residual module and a tensor mapping structure, wherein the tensor mapping structure is used to represent the correlation between the to-be-reduced circuit model and the target circuit model, and the residual module is used to predict the corresponding output according to the input; generates a training data set according to the to-be-reduced circuit model, trains the residual module and the tensor mapping structure in the target mapping equation according to the training data set to obtain a trained target mapping equation; and generates an order reduction result according to the target circuit model and the trained target mapping equation. The present application reduces the port dimension of the system through the port reduction strategy, then obtains a low-precision order reduction model by combining the traditional MOR technology, and then corrects the deviation between the low-precision model and the real system behavior based on the target mapping equation, and the correlation of the system in the port dimension and the time dimension is fully mined through the tensor mapping structure, so that more accurate output prediction is realized under limited samples, so that the order reduction result that can output accurate results is obtained.

[0105] Further, as Figure 5 shown, based on the above-mentioned model order reduction method of multi-port linear circuit, the present application also correspondingly provides a model order reduction system of multi-port linear circuit, wherein the model order reduction system of multi-port linear circuit comprises:

[0106] An order reduction module 51 is used to obtain a to-be-reduced circuit model, reduce the number of ports of the to-be-reduced circuit model according to a port reduction strategy, and obtain a target circuit model.

[0107] The constructing module 52 is configured to construct a target mapping equation based on the target circuit model, a residual module and a tensor mapping structure, wherein the tensor mapping structure is used to represent the correlation between the to-be-reduced circuit model and the target circuit model, and the residual module is used to predict a corresponding output according to an input;

[0108] The training module 53 is configured to generate a training data set according to the to-be-reduced circuit model, and train the residual module and the tensor mapping structure in the target mapping equation according to the training data set to obtain a trained target mapping equation.

[0109] The result generating module 54 is configured to generate a reduced result according to the target circuit model and the trained target mapping equation.

[0110] Further, as shown in the following, Figure 6 Based on the model reduction method and system of the multi-port linear circuit, the application further provides a terminal, which comprises a processor 10, a memory 20 and a display 30. Figure 6 Only some components of the terminal are shown, but it should be understood that all the shown components are not required, and more or less components can be alternatively implemented.

[0111] The memory 20 can be an internal storage unit of the terminal in some embodiments, such as a hard disk or a memory of the terminal. The memory 20 can also be an external storage device of the terminal in other embodiments, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. Further, the memory 20 can include both the internal storage unit and the external storage device of the terminal. The memory 20 is used to store application software and various data installed in the terminal, such as program codes of the terminal, etc. The memory 20 can also be used to temporarily store data that has been output or will be output. In an embodiment, the memory 20 stores a model reduction program 40 of a multi-port linear circuit, which can be executed by the processor 10 to implement the model reduction method of the multi-port linear circuit.

[0112] The processor 10 can be a central processing unit (CPU), a microprocessor or other data processing chip in some embodiments, which is used to run program codes or process data stored in the memory 20, such as to execute the model reduction method of the multi-port linear circuit, etc.

[0113] The display 30 can in some embodiments be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, an OLED (Organic Light-Emitting Diode) touch, etc. The display 30 is used to display information at the terminal and to display a visualized user interface.

[0114] In an embodiment, the steps of the above method of model order reduction of a multi-port linear circuit are implemented when the processor 10 executes the model order reduction program 40 of a multi-port linear circuit in the memory 20.

[0115] The application also provides a computer-readable storage medium, wherein the computer-readable storage medium stores a model order reduction program of a multi-port linear circuit, and the model order reduction program of the multi-port linear circuit, when executed by a processor, implements the following steps:

[0116] Obtaining a circuit model to be reduced, reducing the number of ports of the circuit model to be reduced according to a port reduction strategy to obtain a target circuit model;

[0117] Based on the target circuit model, a residual module and a tensor mapping structure, a target mapping equation is constructed, wherein the tensor mapping structure is used to represent the correlation between the circuit model to be reduced and the target circuit model, and the residual module is used to predict the corresponding output according to the input;

[0118] According to the circuit model to be reduced, a training data set is generated, and the residual module and the tensor mapping structure in the target mapping equation are trained according to the training data set to obtain a trained target mapping equation;

[0119] According to the target circuit model and the trained target mapping equation, a reduced order result is generated.

[0120] The obtaining of the circuit model to be reduced, the reduction of the number of ports of the circuit model to be reduced according to the port reduction strategy, and the obtaining of the target circuit model specifically include:

[0121] Obtaining a circuit model to be reduced, performing singular value decomposition on the input and output of the circuit model to be reduced according to a port reduction strategy to obtain a first circuit model to be reduced after reduction of the number of ports;

[0122] According to a preset model order reduction algorithm, the first circuit model to be reduced is reduced to obtain a target circuit model.

[0123] The construction of the target mapping equation based on the target circuit model, the residual module and the tensor mapping structure specifically includes:

[0124] Based on the target circuit model, the residual module and the tensor mapping structure, a target mapping equation is constructed, and the target mapping equation is represented as:

[0125] ;

[0126] wherein, represents an input, represents a residual module between high and low precision, represents a residual module calculation result, represents a tensor mapping structure, represents a second precision output, represents a first precision output.

[0127] The training data set is generated according to the to-be-reduced-order circuit model, and specifically includes:

[0128] The preset number of time domain simulations are performed on the to-be-reduced-order circuit model, and the second precision output obtained by each time domain simulation is obtained;

[0129] The training data set is generated according to all time domain simulation inputs and corresponding second precision outputs.

[0130] The residual module and the tensor mapping structure in the target mapping equation are trained according to the training data set, and a trained target mapping equation is obtained, and specifically includes:

[0131] The residual module and the tensor mapping structure in the target mapping equation are trained based on a joint optimization method according to the training data set;

[0132] When the training reaches a preset requirement, the training is ended, and the trained target mapping equation is obtained according to the residual module and the tensor mapping structure obtained by the last training.

[0133] The residual module and the tensor mapping structure in the target mapping equation are trained based on a joint optimization method according to the training data set, and specifically includes:

[0134] The time domain simulation input in the training data set is input into the target circuit model to obtain a training first precision output, and the training first precision output is input into the target mapping equation to obtain a mapping output and residual data;

[0135] The residual prediction output by the tensor mapping structure is obtained, and the residual module and the tensor mapping structure are optimized according to the residual data and the residual prediction.

[0136] The time domain simulation input in the training data set is input into a target circuit model to obtain a training first precision output, the training first precision output is input into a target mapping equation, and mapping output and residual data are obtained.

[0137] The time domain simulation input in the training data set is input into a target circuit model to obtain a training first precision output.

[0138] The training first precision output is input into a target mapping equation, and mapping output is generated according to a tensor mapping structure in the target mapping equation.

[0139] The training first precision output, the second precision output and the mapping output are substituted into the target mapping equation to obtain residual data.

[0140] It should be noted that in this paper, the term "includes", "contains" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or terminal including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or includes elements inherent to such process, method, article or terminal. Without more limitations, the element defined by the statement "includes a" does not exclude the presence of another identical element in the process, method, article or terminal including the element.

[0141] Of course, those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing related hardware (such as a processor, a controller, etc.) to complete, and the program can be stored in a computer readable computer readable storage medium, and the program can include the processes of the above-mentioned method embodiments when executed. The computer readable storage medium can be a memory, a magnetic disc, an optical disc, etc.

[0142] It should be understood that the application of the present application is not limited to the above examples, and those skilled in the art can improve or change according to the above description, and all these improvements and changes should belong to the protection scope of the claims of the present application.

Claims

1. A model order reduction method for multi-port linear circuits, characterized by, The model order reduction method of the multi-port linear circuit comprises: Obtaining a circuit model to be reduced, reducing the number of ports of the circuit model to be reduced according to a port reduction strategy, and obtaining a target circuit model; Based on the target circuit model, a residual module and a tensor mapping structure, a target mapping equation is constructed, wherein the tensor mapping structure is used to represent the correlation between the circuit model to be reduced and the target circuit model, and the residual module is used to predict the corresponding output according to the input; According to the circuit model to be reduced, a training data set is generated, and the residual module and the tensor mapping structure in the target mapping equation are trained according to the training data set to obtain a trained target mapping equation; According to the target circuit model and the trained target mapping equation, a reduced order result is generated; The obtaining of the circuit model to be reduced, the reduction of the number of ports of the circuit model to be reduced according to the port reduction strategy, and the obtaining of the target circuit model specifically comprise: Obtaining a circuit model to be reduced, performing singular value decomposition on the input and output of the circuit model to be reduced according to a port reduction strategy, and obtaining a first circuit model to be reduced after the number of ports is reduced; According to a preset model order reduction algorithm, the first circuit model to be reduced is reduced to obtain a target circuit model; The construction of the target mapping equation based on the target circuit model, the residual module and the tensor mapping structure specifically comprises: Based on the target circuit model, the residual module and the tensor mapping structure, a target mapping equation is constructed, wherein the target mapping equation is represented as: ； wherein, denotes input, denotes a residual module between high and low precision, denotes a residual module calculation result, denotes a tensor mapping structure, denotes a second precision output, denotes a first precision output; The generation of the training data set according to the circuit model to be reduced specifically comprises: Time domain simulation is performed on the circuit model to be reduced for a preset number of times, and a second accuracy output obtained by each time domain simulation is obtained; According to all time domain simulation inputs and corresponding second accuracy outputs, a training data set is generated.

2. The model order reduction method of multi-port linear circuits of claim 1, wherein, The training of the residual module and the tensor mapping structure in the target mapping equation according to the training data set to obtain a trained target mapping equation specifically comprises: According to the training data set, the residual module and the tensor mapping structure in the target mapping equation are trained based on a joint optimization method; When the training reaches a preset requirement, the training is ended, and the trained target mapping equation is obtained according to the residual module and the tensor mapping structure obtained by the last training.

3. The model order reduction method of multi-port linear circuits of claim 2, wherein, The training of the residual module and the tensor mapping structure in the target mapping equation according to the training data set based on the joint optimization method specifically comprises: The time domain simulation input in the training data set is input into the target circuit model to obtain a training first accuracy output, and the training first accuracy output is input into the target mapping equation to obtain a mapping output and residual data; The residual prediction output by the tensor mapping structure is obtained, and the residual module and the tensor mapping structure are optimized according to the residual data and the residual prediction.

4. The model order reduction method of multi-port linear circuits of claim 3, wherein, The input of the time domain simulation input in the training data set into the target circuit model to obtain the training first accuracy output, the input of the training first accuracy output into the target mapping equation to obtain the mapping output and the residual data specifically comprise: inputting the time-domain simulation input in the training data set into a target circuit model to obtain a training first-precision output; inputting the training first-precision output into a target mapping equation to generate a mapping output according to a tensor mapping structure in the target mapping equation; substituting the training first-precision output, a second-precision output and the mapping output into the target mapping equation to obtain residual data.

5. A reduced-order system model of a multi-port linear circuit, characterized by, The model reduction system of the multi-port linear circuit is used to implement the model reduction method of the multi-port linear circuit according to any one of claims 1-4, and the model reduction system of the multi-port linear circuit comprises: a reduction module configured to obtain a circuit model to be reduced, reduce the number of ports of the circuit model to be reduced according to a port reduction strategy, and obtain a target circuit model; a construction module configured to construct a target mapping equation based on the target circuit model, a residual module and a tensor mapping structure, wherein the tensor mapping structure is used to represent the correlation between the circuit model to be reduced and the target circuit model, and the residual module is used to predict the corresponding output according to the input; a training module configured to generate a training data set according to the circuit model to be reduced, train the residual module and the tensor mapping structure in the target mapping equation according to the training data set, and obtain a training completed target mapping equation; a result generation module configured to generate a reduction result according to the target circuit model and the training completed target mapping equation.

6. A terminal, characterized by comprising: The terminal comprises a memory, a processor and a model reduction program of a multi-port linear circuit stored on the memory and executable on the processor, and the model reduction program of the multi-port linear circuit implements the steps of the model reduction method of the multi-port linear circuit according to any one of claims 1-4 when executed by the processor.

7. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a model reduction program of a multi-port linear circuit, and the model reduction program of the multi-port linear circuit implements the steps of the model reduction method of the multi-port linear circuit according to any one of claims 1-4 when executed by the processor.

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