Wide-range speed regulation control method of high-voltage frequency converter and sampling and conditioning circuit

Abstract

The invention provides a wide-range speed regulation control method of a high-voltage frequency converter and a sampling and conditioning circuit, and belongs to the technical field of high-voltage frequency converters. A working frequency range is divided into three sections by setting a frequency boundary threshold value, and a three-phase acquisition unit is used for sampling the output voltage of the high-voltage frequency converter in real time; a multi-path phase calculation strategy is executed based on a frequency range, an integrating circuit is adopted to cooperate with 90-degree lead phase compensation at a high frequency, a low-pass filter circuit is adopted to carry out non-lagging processing at a low frequency, a smooth switching algorithm is adopted to carry out weighted fusion on two signals at an intermediate frequency, and a self-adaptive PID control algorithm is adopted to execute feedback adjustment. Coordinated balance of energy consumption and precision is achieved by applying a double-layer game, optimized control parameters are transmitted to a driving port to achieve wide-range speed regulation control, and the technical problem that it is difficult for the high-voltage frequency converter to guarantee phase precision and speed regulation control stability at the same time in a wide frequency range is solved.

Description

Technical Field

[0001] This invention belongs to the field of high-voltage frequency converter technology, and specifically relates to a wide-range speed control method and sampling and conditioning circuit for a high-voltage frequency converter. Background Technology

[0002] High-voltage frequency converters, as core equipment in industrial motor drive systems, are widely used in the speed control of high-power AC motors in heavy industries such as petrochemicals, steel, and power. Traditional high-voltage frequency converter speed control methods mainly employ constant voltage-frequency ratio control strategies and vector control technology, achieving precise control of motor speed by adjusting the output frequency and voltage amplitude. They play a crucial role in various industrial production lines, fan and pump systems, and compressor drives. However, traditional technologies have significant shortcomings when facing wide-range speed control requirements, especially at high and low frequencies. Phase detection accuracy deteriorates severely, and at high frequencies, the 90-degree phase lag introduced by the integral circuit leads to sluggish control system response. At low frequencies, signal amplitude attenuation and noise interference result in insufficient phase detection accuracy. Furthermore, there is a lack of effective signal processing strategies in the mid-frequency transition region. Simultaneously, traditional single control strategies cannot achieve a dynamic balance between energy consumption optimization and control accuracy. In the existing technology, due to the lack of adaptive signal processing mechanisms and multi-objective coordinated optimization strategies for different frequency ranges, the phase detection error of high-voltage frequency converters accumulates severely when operating over a wide frequency range, resulting in a decrease in speed regulation accuracy and a deterioration in system stability. In other words, the existing technology has the technical problem that high-voltage frequency converters cannot simultaneously guarantee phase accuracy and speed control stability over a wide frequency range. Summary of the Invention

[0003] In view of this, the present invention provides a wide-range speed control method and sampling and conditioning circuit for a high-voltage frequency converter, which can solve the technical problem in the prior art that it is difficult to simultaneously ensure phase accuracy and speed control stability of a high-voltage frequency converter over a wide frequency range.

[0004] The present invention is implemented as follows: A first aspect of the present invention provides a wide-range speed control method for a high-voltage frequency converter, comprising: setting speed control parameters for the high-voltage frequency converter, including a target speed range and frequency boundary thresholds. and Based on phase compensation coefficient and control accuracy requirements, an initial state parameter set for speed control is established; a three-phase acquisition unit is used to sample the output voltage of the high-voltage frequency converter in real time to obtain a digitized voltage signal; a multi-path phase calculation strategy is executed based on different ranges of the high-voltage frequency converter's output frequency, and when the output frequency is greater than the frequency boundary threshold... The high-frequency sampling signal output by the integrator circuit is used, and a 90-degree lead phase compensation operation is performed in the DSP computing unit. When the output frequency is less than the frequency boundary threshold... The low-frequency sampled signal output by the low-pass filter circuit is used for hysteresis-free phase calculation. When the output frequency is at... to A smooth switching algorithm is used to weightedly fuse the outputs of the integrator circuit and the low-pass filter circuit. A convex optimization solution model for minimizing speed error is established, transforming the wide-range speed control problem into a parameter optimization problem under multiple constraints. The Lagrange multiplier method is used to solve for the optimal frequency adjustment and phase correction. Adaptive feedback regulation is performed based on the deviation between the target speed and the actual speed, and an adaptive PID control algorithm is used to calculate the frequency adjustment and phase correction. A two-level game coordination optimization model is applied to coordinate system parameters. The optimal control parameters output by the game coordination optimization model are transmitted to the drive port of the high-voltage frequency converter.

[0005] In the step of setting the speed control parameters of the high-voltage frequency converter, Set to 5Hz. Set to 2Hz.

[0006] Specifically, the three-phase acquisition unit includes three identical unit acquisition circuits. Each unit acquisition circuit, through the cooperation of a sampling voltage divider circuit, a common-mode differential operational amplifier, an integrator circuit, a low-pass filter circuit, and an AD analog-to-digital converter chip, converts the high voltage output by the high-voltage frequency converter into a digital signal and simultaneously outputs a high-frequency sampling signal and a low-frequency sampling signal.

[0007] The AD analog-to-digital converter chip transmits digitized high-frequency and low-frequency sampling signals to the DSP computing unit via the SPI bus. The DSP computing unit calculates the phase information of the high-voltage frequency converter at high-frequency, low-frequency, or medium-frequency voltages based on the signals from the AD analog-to-digital converter chip.

[0008] Specifically, the smooth switching algorithm is used to process frequency boundary thresholds. to The intermediate frequency voltage signal between the two frequencies is used to calculate the intermediate frequency voltage phase through the output results of a weighted fusion integrator circuit and a low-pass filter circuit. The weighting coefficients are based on the current output frequency and the frequency boundary threshold. and The relative position is dynamically determined.

[0009] Specifically, the convex optimization solution model has an objective function that minimizes the deviation between the target speed and the actual speed. The constraints include frequency change rate constraints, phase change constraints, power limit constraints, and system stability constraints. The inputs include the target speed, the actual speed, the frequency adjustment amount, the phase correction amount, and the system power parameters. The output is the optimal frequency adjustment amount and phase correction amount that satisfy all constraints.

[0010] The high-frequency sampling signal has the same frequency as the high-frequency voltage output by the high-voltage inverter, and its phase lags behind the high-frequency voltage output by the high-voltage inverter by 90 degrees. The low-frequency sampling signal has the same frequency as the low-frequency voltage output by the high-voltage inverter, and its phase has no lag.

[0011] Specifically, the two-layer game-theoretic coordination optimization model includes an upper-layer energy consumption optimization model and a lower-layer precision optimization model. The objective function of the upper-layer energy consumption optimization model is formed by adding the exponentially weighted term of the total system power consumption and the logarithmic penalty term of the switching loss, then combining it with the product term of the harmonic current and the reciprocal of the system efficiency, and finally adding the energy consumption precision coupling term. The objective function of the lower-layer precision optimization model is formed by adding the product term of the reciprocal of the standard deviation of control precision and the reciprocal of the response time, the exponentially weighted term of the stability index and the robustness index, and finally subtracting the energy consumption precision coupling term.

[0012] Specifically, the energy consumption and accuracy coupling term is used to describe the mutual constraint relationship between energy consumption optimization and accuracy optimization. The inputs include total system power consumption, control accuracy standard deviation, frequency adjustment, phase correction, and load change rate. The output is a coupling coefficient that reflects the strength of the trade-off between the two optimization objectives.

[0013] Specifically, the 90-degree leading phase compensation operation is used to counteract the inherent 90-degree phase lag effect of the integrator circuit, ensuring that the DSP computing unit obtains accurate high-frequency voltage phase information.

[0014] Specifically, the adaptive PID control algorithm dynamically adjusts the proportional gain, integral gain, and derivative gain parameters according to the current frequency range and load conditions. The inputs include speed error, frequency range identifier, and load characteristic parameters, and the outputs are frequency adjustment and phase correction.

[0015] Specifically, the game equilibrium is used to find a stable state where both the upper-level energy consumption optimization model and the lower-level accuracy optimization model simultaneously reach their optimal solutions. This is achieved through iterative solving, resulting in a coordinated balance between minimizing energy consumption and maximizing accuracy. The two-layer game-theoretic coordinated optimization model, through the coordination mechanism between upper-level energy consumption optimization and lower-level accuracy optimization, achieves a dynamic balance between minimizing system power consumption and maximizing control accuracy over a wide frequency range. The multi-path phase calculation strategy, by employing different signal processing paths and phase compensation methods for different frequency ranges, eliminates the technical deficiency of insufficient phase detection accuracy in a wide frequency range inherent in traditional single-processing strategies.

[0016] A second aspect of the present invention also provides a sampling and conditioning circuit for wide-range speed control of a high-voltage frequency converter using the above-described method. The circuit includes a high-voltage frequency converter, an AC motor, and a load, with the output terminal of the high-voltage frequency converter, the AC motor, and the load connected sequentially. The circuit is characterized by further including a three-phase acquisition unit and a DSP calculation unit. The three-phase acquisition unit includes three identical unit acquisition circuits, each of which includes a sampling voltage divider circuit, a common-mode differential operational amplifier, an integrator circuit, a low-pass filter circuit, and an analog-to-digital converter (ADC) chip. The voltage output terminal of the high-voltage frequency converter is also connected to the input of the common-mode differential operational amplifier via the sampling voltage divider circuit. The output of the common-mode differential operational amplifier is connected to the input of the integrator circuit and the low-pass filter circuit, respectively. The outputs of the integrator circuit and the low-pass filter circuit are connected to the input of the ADC chip, and the output of the ADC chip is connected to the input of the DSP calculation unit. The output of the DSP calculation unit is connected to the drive port of the high-voltage frequency converter. The anti-common-mode differential operational amplifier samples the voltage frequency of the high-voltage inverter through the sampling voltage divider circuit; the integrator circuit and the low-pass filter circuit obtain the high-frequency voltage signal and the low-frequency voltage signal of the high-voltage inverter respectively through the anti-common-mode differential operational amplifier, and send them to the DSP computing unit for calculation through the AD analog-to-digital converter chip; the DSP computing unit calculates the phase of the high-voltage inverter at high-frequency voltage, low-frequency voltage, or medium-frequency voltage based on the signal from the AD analog-to-digital converter chip.

[0017] This invention effectively solves the problems of insufficient phase detection accuracy and single control strategy in traditional technologies by constructing a wide-range speed control method based on a frequency-adaptive multi-path phase calculation strategy and a two-layer game-theoretic coordination optimization model. For three different frequency ranges (high frequency, low frequency, and medium frequency), this invention employs differentiated signal processing strategies: high-frequency sampling with an integral circuit combined with 90-degree lead phase compensation, low-frequency sampling with no hysteresis through a low-pass filter circuit, and weighted fusion using a smooth switching algorithm. This eliminates the adverse effects of frequency changes on phase detection accuracy. Simultaneously, it achieves accurate calculation of frequency adjustment and phase correction through a convex optimization solution model and an adaptive PID control algorithm. Through a two-layer game-theoretic coordination mechanism consisting of an upper-layer energy consumption optimization model and a lower-layer accuracy optimization model, a dynamic balance is achieved between minimizing system power consumption and maximizing control accuracy. In summary, this invention solves the technical problem of high-voltage frequency converters struggling to simultaneously guarantee phase accuracy and speed control stability over a wide frequency range through multi-path adaptive phase processing and game-theoretic coordination optimization. Attached Figure Description

[0018] Figure 1 This is a flowchart of the method of the present invention.

[0019] Figure 2 This is a schematic diagram of the box connection structure in Example 2.

[0020] Figure 3 This is a block diagram showing the connection structure of one unit acquisition circuit with the high-voltage frequency converter, AC motor, load and DSP computing unit in Example 2.

[0021] Figure 4 This is a schematic diagram of the circuit structure in Example 2.

[0022] Figure 5 The diagram shows the amplitude-frequency response characteristics of the three-phase acquisition unit in Example 3 at different frequencies.

[0023] Figure 6 This is a comparison diagram of the phase compensation effect in Example 3.

[0024] Figure 7 The graph shows the test results of the speed control accuracy in Example 3.

[0025] Figure 8 This is a diagram illustrating the convergence process of the game optimization algorithm in Example 3.

[0026] Figure 9 This is a diagram showing the overall system performance evaluation results in Example 3.

[0027] The reference numerals in the attached figures are explained as follows: 1. Anti-common-mode differential operational amplifier; 2. Integrator circuit; 3. Low-pass filter circuit; 4. AD analog-to-digital converter chip; 5. DSP computing unit; 6. High-voltage frequency converter; 7. AC motor; 8. Load; 9. Sampling voltage divider circuit; 10. Three-phase acquisition unit; 11. Unit acquisition circuit. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0029] like Figure 1 The diagram shown is a flowchart of a wide-range speed control method for a high-voltage frequency converter provided in the first aspect of the present invention. This method includes the following steps: S01. Set the speed control parameters of the high-voltage frequency converter, including the target speed range, frequency boundary thresholds ω1 and ω2, phase compensation coefficient and control accuracy requirements, and establish the initial state parameter set for speed control, where ω1 is set to 5Hz and ω2 is set to 2Hz. S02. A three-phase acquisition unit is used to sample the output voltage of the high-voltage frequency converter in real time. The three-phase acquisition unit includes three identical unit acquisition circuits. Each unit acquisition circuit includes a sampling voltage divider circuit, a common-mode differential operational amplifier, an integrator circuit, a low-pass filter circuit, and an AD analog-to-digital converter chip. The sampling voltage divider circuit converts the high voltage output of the high-voltage frequency converter into a low voltage signal and sends it to the input terminal of the common-mode differential operational amplifier. The common-mode differential operational amplifier processes the sampled signal and sends it to the integrator circuit and the low-pass filter circuit simultaneously. S03. Based on different ranges of the output frequency of the high-voltage frequency converter, a multi-path phase calculation strategy is implemented. When the output frequency is greater than the frequency boundary threshold ω1, the high-frequency sampling signal output by the integrator circuit is used and a 90-degree leading phase compensation operation is performed in the DSP calculation unit. When the output frequency is less than the frequency boundary threshold ω2, the low-frequency sampling signal output by the low-pass filter circuit is used for hysteresis-free phase calculation. When the output frequency is between ω1 and ω2, a smooth switching algorithm is used to weight and fuse the output results of the integrator circuit and the low-pass filter circuit. S04. Establish a convex optimization solution model to minimize speed error, transform the wide-range speed control problem into a parameter optimization problem under multiple constraints, and use the Lagrange multiplier method to solve for the optimal frequency adjustment and phase correction, so as to realize the accurate speed control of the high-voltage frequency converter in a wide frequency range.

[0030] S05. Based on the deviation between the target speed and the actual speed, adaptive feedback adjustment is performed. An adaptive PID control algorithm is used to calculate the frequency adjustment and phase correction, and the drive parameters of the high-voltage frequency converter are dynamically updated to reduce the speed error. S06. A two-layer game-theoretic coordination optimization model is applied to coordinate system parameters. The upper-layer energy consumption optimization model aims to minimize the total power consumption of the system by optimizing the frequency adjustment strategy through a combination function of exponential weighting and logarithmic penalty. The lower-layer precision optimization model aims to maximize control precision by optimizing the phase compensation parameters through a product objective function. The coordination and balance between energy consumption and precision are achieved through game equilibrium. S07. The optimal control parameters output by the game coordination optimization model are transmitted to the drive port of the high-voltage frequency converter to realize wide-range speed regulation control of the AC motor, and the output status is continuously monitored to perform closed-loop regulation to maintain stable system operation.

[0031] The smooth switching algorithm is used to process the mid-frequency voltage signal between the frequency boundary thresholds ω1 and ω2. The mid-frequency voltage phase is calculated by the output results of the weighted fusion integral circuit and the low-pass filter circuit. The weighting coefficients are dynamically determined according to the relative position of the current output frequency with the frequency boundary thresholds ω1 and ω2.

[0032] The objective function of the convex optimization solution model is used to minimize the deviation between the target speed and the actual speed. The constraints include frequency change rate constraint, phase change constraint, power limit constraint and system stability constraint. The inputs include target speed, actual speed, frequency adjustment amount, phase correction amount and system power parameters. The output is the optimal frequency adjustment amount and phase correction amount that satisfy all constraints.

[0033] The adaptive PID control algorithm dynamically adjusts the proportional gain, integral gain, and derivative gain parameters according to the current frequency range and load conditions. The inputs include speed error, frequency range identifier, and load characteristic parameters, and the outputs are frequency adjustment and phase correction.

[0034] The two-layer game-theoretic coordination optimization model includes an upper-layer energy consumption optimization model and a lower-layer accuracy optimization model. The objective function of the upper-layer energy consumption optimization model is formed by adding the exponentially weighted term of the total system power consumption and the logarithmic penalty term of the switching loss, then combining it with the product term of the harmonic current and the reciprocal of the system efficiency, and finally adding the energy consumption and accuracy coupling term. The objective function of the lower-layer accuracy optimization model is formed by adding the product term of the reciprocal of the standard deviation of control accuracy and the reciprocal of the response time, the exponentially weighted term of the stability index and the robustness index, and finally subtracting the energy consumption and accuracy coupling term.

[0035] The energy consumption and accuracy coupling term is used to describe the mutual constraint relationship between energy consumption optimization and accuracy optimization. The inputs include total system power consumption, control accuracy standard deviation, frequency adjustment, phase correction and load change rate. The output is the coupling coefficient reflecting the strength of the trade-off between the two optimization objectives.

[0036] The game equilibrium is used to find a stable state in which the upper-level energy consumption optimization model and the lower-level accuracy optimization model simultaneously reach the optimal solution. The coordinated balance between minimizing energy consumption and maximizing accuracy is achieved through iterative solution.

[0037] The high-frequency sampling signal has the same frequency as the high-frequency voltage output by the high-voltage inverter, and the phase of the high-frequency sampling signal lags behind the phase of the high-frequency voltage output by the high-voltage inverter by 90 degrees.

[0038] The frequency of the low-frequency sampling signal is the same as the frequency of the low-frequency voltage output by the high-voltage frequency converter, and the phase of the low-frequency sampling signal has no hysteresis.

[0039] The 90-degree leading phase compensation operation is used to counteract the inherent 90-degree phase lag effect of the integrator circuit, ensuring that the DSP computing unit obtains accurate high-frequency voltage phase information.

[0040] The specific implementation of the above steps is described in detail below. Step S01 is implemented by first determining the target speed range based on load characteristics and process requirements. Typically, the speed ratio between the highest and lowest speeds is set to exceed 100:1 to meet wide-range speed regulation requirements. Next, frequency boundary thresholds ω1 and ω2 are set to 5Hz and 2Hz, respectively. These thresholds distinguish the processing methods for high-frequency, medium-frequency, and low-frequency voltage signals. Signals above 5Hz are processed using an integrator circuit, while those below 2Hz are processed using a low-pass filter circuit. Then, a phase compensation coefficient is configured, typically set to a value between 0.8 and 1.2, to correct the 90-degree phase lag introduced by the integrator circuit. Finally, control accuracy requirements are set, with the speed accuracy error controlled within 0.1% of the target speed. An initial state parameter set for speed regulation control, including the aforementioned parameters, is established. The purpose of these steps is to provide basic parameter configuration for subsequent wide-range speed regulation control, ensuring that the system has an accurate control reference under different operating conditions.

[0041] The specific implementation of step S02 involves synchronously sampling the three-phase output voltage of the high-voltage frequency converter using a three-phase acquisition unit. Each acquisition circuit first uses a sampling voltage divider circuit to step down the kilovolt-level voltage output from the high-voltage frequency converter to a low volt-level signal via a voltage divider network consisting of a sixth voltage divider resistor R6 and a seventh voltage divider resistor R7. The sixth voltage divider resistor R6 is typically selected with a megohm-level resistance, and the seventh voltage divider resistor R7 is selected with a kilohm-level resistance. The voltage division ratio is set between 1000:1 and 10000:1. The stepped-down signal then enters a common-mode differential operational amplifier. This common-mode differential operational amplifier consists of a first operational amplifier U1, a bidirectional TVS diode DZ1, and a first resistor R1. The bidirectional TVS diode DZ1 is used for overvoltage protection, the first resistor R1 is used for current limiting, and the first operational amplifier U1 amplifies the differential signal and suppresses common-mode interference. The signal output from the common-mode differential operational amplifier is simultaneously fed into an integrator circuit and a low-pass filter circuit. The integrator circuit consists of an inverting integrator structure formed by a second operational amplifier U2, a second resistor R2, a third resistor R3, and a first capacitor C1. The low-pass filter circuit consists of an active low-pass filter structure formed by a third operational amplifier U3, a fourth resistor R4, a fifth resistor R5, and a second capacitor C2. These steps employ analog signal processing principles, utilizing the virtual short and virtual open characteristics of the operational amplifiers to achieve linear transformation and filtering of the signal. The relevance of this circuit design lies in providing different processing paths for signals within different frequency ranges.

[0042] The specific implementation of step S03 involves executing a segmented phase calculation strategy based on the numerical range of the high-voltage inverter's output frequency. When the output frequency is detected to be greater than the frequency boundary threshold ω1 (5Hz), the DSP calculation unit selects the high-frequency sampling signal output by the integrator circuit as the processing object. Due to the transfer function characteristics of the integrator circuit, the output signal phase lags the input signal by 90 degrees. Therefore, the DSP calculation unit performs a 90-degree lead compensation operation on the phase information output by the integrator circuit to obtain the true high-frequency voltage phase. When the output frequency is detected to be less than the frequency boundary threshold ω2 (2Hz), the DSP calculation unit selects the low-frequency sampling signal output by the low-pass filter circuit. Since the phase response of the low-pass filter circuit is close to zero in the low-frequency band, the phase information of the signal is directly used for calculation. When the output frequency is in the mid-frequency range of 2Hz to 5Hz, a smooth switching algorithm is used to weight and fuse the outputs of the integrator circuit and the low-pass filter circuit. The weighting coefficient is determined by linear interpolation based on the distance between the current frequency and the boundary frequency. This step adopts a segmented processing principle, avoiding the performance limitations of a single processing method across the entire frequency range by segmenting the frequency, ensuring accurate phase information can be obtained over a wide frequency range.

[0043] The specific implementation of step S04 involves modeling the wide-range speed control problem as a convex optimization problem under multiple constraints. Input parameters include target speed, actual speed, current frequency, current phase, and load torque. Output parameters are the optimal frequency adjustment and phase correction. First, an objective function is constructed with the sum of squared speed errors as the main term. Penalty terms for frequency and phase change rates are added to prevent drastic changes in the control quantity. Constraints include a frequency change rate constraint, typically limited to a change rate not exceeding 1 Hz per second; a phase change constraint limiting the change amplitude to no more than 5 degrees per control cycle; a power limit constraint ensuring the output power does not exceed 110% of the inverter's rated power; and a stability constraint using a Lyapunov function to ensure system convergence. The constrained optimization problem is transformed into an unconstrained optimization problem using the Lagrange multiplier method, and the optimal solution is iteratively solved using a gradient descent algorithm. This step employs convex optimization theory, utilizing the global optimality property of convex functions to ensure the uniqueness and stability of the solution. Its relevance to speed control lies in transforming a complex multivariable control problem into a standard mathematical optimization problem.

[0044] The specific implementation of step S05 is based on the deviation between the target speed and the actual speed to achieve closed-loop feedback control. Input parameters include speed error, the time integral of the speed error, and the time derivative of the speed error. Output parameters are frequency adjustment and phase correction. First, the speed error is calculated as a proportional control term. Then, the speed error is integrated over time as an integral control term to eliminate steady-state error. Next, the time derivative of the speed error is calculated as a derivative control term to improve dynamic response. The adaptive PID control algorithm dynamically adjusts the three gain parameters according to the current frequency range and load changes. In the high-frequency range, the proportional gain is increased to improve response speed; in the low-frequency range, the integral gain is increased to reduce steady-state error; and during sudden load changes, the derivative gain is increased to suppress overshoot. The adjustment of the gain parameters adopts the fuzzy logic control principle, reasoning based on a preset fuzzy rule base and membership function. This step uses the PID control principle from classical control theory, combined with adaptive control ideas to achieve online parameter adjustment. Its relevance to wide-range speed regulation lies in providing differentiated control strategies for different frequency ranges and load conditions.

[0045] The specific implementation of step S06 involves constructing a two-layer game structure of an upper-layer energy consumption optimization model and a lower-layer accuracy optimization model. The input parameters of the upper-layer model include total system power consumption, switching losses, harmonic current, system efficiency, and an energy consumption-accuracy coupling term. The output parameter is the optimal frequency regulation strategy. The input parameters of the lower-layer model include the standard deviation of control accuracy, response time, stability index, robustness index, and an energy consumption-accuracy coupling term. The output parameter is the optimal phase compensation parameter. The upper-layer model adopts a combined function structure of exponential weighting and logarithmic penalty. The exponential function amplifies the impact of power consumption changes, while the logarithmic function smooths the fluctuations in switching losses. The final objective function is a nonlinear combination of all terms. The lower-layer model adopts a product-type objective function structure, multiplying the reciprocals of accuracy-related indicators to achieve multi-objective collaborative optimization. The game solution employs Nash equilibrium theory, using an iterative algorithm to find a stable solution that optimizes both sides. This step utilizes game theory principles, modeling energy consumption optimization and accuracy optimization as a competitive and cooperative relationship. Its relevance to wide-range speed control lies in achieving multi-objective coordinated optimization of system performance.

[0046] The specific implementation of step S07 involves converting the optimal control parameters output by the game-theoretic coordination optimization model into PWM drive signals via a digital signal processor to drive the power switching devices of the high-voltage frequency converter to generate the required three-phase AC voltage. First, the optimal frequency adjustment is converted into carrier frequency parameters, and a reference signal corresponding to the frequency is generated using a sine wave modulation algorithm. Then, the optimal phase correction is converted into phase offset parameters, and a 120-degree phase difference and phase correction are applied to the three-phase reference signals respectively. Next, space vector pulse width modulation technology is used to convert the reference signals into a drive pulse sequence for the switching devices, and the duty cycle of the drive signal is dynamically adjusted according to the voltage amplitude requirement. Simultaneously, a status monitoring module is activated to continuously collect operating parameters such as motor speed, current, and temperature, comparing them with target values ​​to form new control deviations. When a deviation exceeding a preset threshold is detected, the aforementioned control steps are re-executed to form closed-loop regulation. This step employs the principle of pulse width modulation and closed-loop control theory, achieving precise voltage and frequency control through the high-frequency switching of the switching devices. Its relevance to wide-range speed regulation lies in converting digital control commands into analog voltage outputs to drive the motor.

[0047] The key technical ideas of this invention include a multi-path phase calculation strategy, a two-layer game-theoretic coordination optimization, and adaptive circuit signal processing. The multi-path phase calculation strategy employs a segmented processing approach: an integrator circuit for high-frequency signals, a low-pass filter circuit for low-frequency signals, and a smooth switching algorithm for intermediate-frequency signals. Compared to traditional single-filter methods, this approach offers high accuracy across the entire frequency band, solving the problems of insufficient accuracy in extremely low-frequency bands and slow response in extremely high-frequency bands, achieving a frequency range extension of over 100 times. The two-layer game-theoretic coordination optimization, through a competitive and cooperative mechanism between the upper-layer energy consumption model and the lower-layer accuracy model, offers a multi-objective coordinated balance compared to traditional single-objective optimization methods. This avoids the performance trade-offs caused by the mutual constraints between energy consumption and accuracy in traditional methods, achieving the advantage of optimal overall system performance. The adaptive circuit signal processing, through analog signal preprocessing using anti-common-mode differential operational amplifiers, integrator circuits, and low-pass filter circuits, offers higher signal-to-noise ratio and stronger real-time performance compared to traditional purely digital processing methods. It reduces quantization errors and delays in digital sampling, improving weak signal detection capabilities and fast response characteristics. The synergistic effect of the three key technical approaches is that multi-path phase calculation provides accurate state information for game optimization, game optimization provides optimal parameter configuration for adaptive control, and adaptive circuit processing provides a high-quality signal source for phase calculation, forming a positive loop of information flow and mutual promotion of performance. Compared with the traditional independent design method, it achieves a system-level synergistic effect, and simultaneously achieves the technical goals of high-precision control and low-energy operation in a wide frequency range.

[0048] Furthermore, a specific implementation of the sampling and conditioning circuit provided in the second aspect of the present invention is as follows: The three-phase output voltage of the high-voltage frequency converter is synchronously sampled by a three-phase acquisition unit. The three-phase acquisition unit includes three identical unit acquisition circuits, each corresponding to one phase output of the high-voltage frequency converter, realizing independent sampling and signal conditioning of phases A, B, and C. Each unit acquisition circuit integrates key functional modules such as a sampling voltage divider circuit, a common-mode differential operational amplifier, an integrator circuit, a low-pass filter circuit, and an AD analog-to-digital converter chip. Through the organic combination of analog signal processing and digital conversion, the frequency and phase information of the high-voltage frequency converter output voltage are accurately extracted.

[0049] The specific implementation of the sampling voltage divider circuit involves using a resistor voltage divider network to step down the kilovolt-level output voltage of the high-voltage frequency converter to a voltage level suitable for subsequent circuit processing. One end of the sixth voltage divider resistor R6 is directly connected to the voltage output terminal of the high-voltage frequency converter and simultaneously connected to the input terminal of the AC motor, forming a voltage sampling point. The other end of the sixth voltage divider resistor R6 is connected to one end of the seventh voltage divider resistor R7, forming a voltage divider node. This node is also connected to the input terminal of the common-mode differential operational amplifier. The other end of the seventh voltage divider resistor R7 is grounded, forming a complete voltage divider loop. The sixth voltage divider resistor R6 is typically a high-resistance resistor in the megaohm range, with typical values ​​ranging from 10MΩ to 100MΩ, to minimize the impact on the output current of the high-voltage frequency converter. The seventh voltage divider resistor R7 is a resistor in the kiloohm range, with typical values ​​ranging from 10kΩ to 100kΩ. Through a reasonable resistance ratio design, a voltage division ratio of 1000:1 to 10000:1 is achieved, safely and reliably converting the kilovolt-level high voltage into a low voltage signal below 5V.

[0050] The specific implementation of the common-mode differential operational amplifier involves using a high-precision differential amplifier in conjunction with a protection circuit to achieve differential signal amplification and common-mode interference suppression. The first operational amplifier U1 uses a differential amplifier chip, such as the AD629AR chip, which features high input impedance, low offset voltage, and strong common-mode rejection capability. The bidirectional TVS diode DZ1 and the first resistor R1 are connected in parallel between the inverting and non-inverting input terminals of the first operational amplifier U1 to form an input protection network. The bidirectional TVS diode DZ1 is selected as a device with a breakdown voltage of 6V to 15V to clamp overvoltage signals and prevent damage to the operational amplifier from electrostatic discharge and transient overvoltage. The first resistor R1 is selected as a 1kΩ to 10kΩ current-limiting resistor, which works with the TVS diode to limit fault current. The output of the first operational amplifier U1 is connected to the input of both the integrator circuit and the low-pass filter circuit, enabling a signal distribution function with one input and two outputs. The anti-common-mode differential operational amplifier amplifies the differential signal provided by the sampling voltage divider circuit and reverses the signal polarity, meaning the output signal is 180 degrees out of phase with the input signal, providing a standardized signal interface for unified processing by subsequent circuits.

[0051] The specific implementation of the integrator circuit employs an active integrator structure to perform integration operations on the input signal, used for processing high-frequency voltage signals. One end of the second resistor R2 is connected to the output terminal of the common-mode differential operational amplifier, serving as the input resistor of the integrator circuit. The other end of the second resistor R2 is connected to the inverting input terminal of the second operational amplifier U2, forming a virtual ground node. The first capacitor C1 and the third resistor R3 are connected in parallel between the inverting input terminal and the output terminal of the second operational amplifier U2, forming an integration feedback network. The first capacitor C1 is the integrating capacitor, and its capacitance value determines the integration time constant, typically ranging from 0.1μF to 1μF. The third resistor R3 is a bleed resistor, preventing output saturation of the operational amplifier due to input bias current; its resistance value is typically from 1MΩ to 10MΩ. The non-inverting input terminal of the second operational amplifier U2 is connected to analog ground to ensure that the operational amplifier operates in the linear region. The second operational amplifier U2 uses a low-noise, high-precision operational amplifier, such as the OP284ES chip. The output of the integrator circuit is directly connected to the input channel of the AD analog-to-digital converter chip. The integrator circuit has an amplitude-frequency characteristic of -20dB / decade and a constant phase characteristic of -90 degrees in the frequency domain. It is particularly suitable for processing high-frequency signals and can provide a stable phase reference while maintaining the signal amplitude.

[0052] The specific implementation of the low-pass filter circuit employs an active low-pass filter structure to achieve selective amplification of low-frequency signals and effective suppression of high-frequency interference. It is used to process low-frequency voltage signals. One end of the fifth resistor R5 is connected to the output of the anti-common-mode differential operational amplifier, receiving the same input signal in parallel with the integrator circuit. The other end of the fifth resistor R5 is connected to the inverting input of the third operational amplifier U3, serving as the input resistor of the filter circuit. The second capacitor C2 and the fourth resistor R4 are connected in parallel between the inverting input and output of the third operational amplifier U3, forming a feedback network for the low-pass filter. The second capacitor C2 is the filter capacitor, and its capacitance value, together with the resistance value of the fourth resistor R4, determines the cutoff frequency of the filter. Through proper design, the cutoff frequency is positioned between 2Hz and 5Hz, ensuring good transmission performance for low-frequency signals and effective suppression of high-frequency noise. The fourth resistor R4 is a feedback resistor and determines the passband gain of the filter. Its resistance ratio to the fifth resistor R5 determines the amplification factor. The non-inverting input of the third operational amplifier U3 is connected to analog ground. It uses the same operational amplifier chip as the integrator circuit to ensure consistency and comparability of the two signal processing paths. The output of the low-pass filter circuit is connected to another input channel of the AD converter chip. This filter circuit has a flat amplitude-frequency response and a near-zero phase response below the designed cutoff frequency, making it particularly suitable for the precise processing of extremely low-frequency signals.

[0053] The specific implementation of the AD analog-to-digital converter (ADC) chip involves using a high-precision ADC with multi-channel synchronous sampling to convert analog signals to digital signals. The AD7606 chip is selected, featuring 16-bit resolution, eight differential input channels, synchronous sampling, and an SPI interface. The output signals of the integrating circuit and low-pass filter circuit are connected to different input channels of the AD ADC chip. Synchronous sampling ensures the consistency of the time base of the two signals. The sampling frequency is set from 10kHz to 100kHz, meeting the Nyquist theorem requirements for wide-frequency range signal sampling. The AD ADC chip integrates an input buffer, sample-and-hold circuit, successive approximation ADC, and digital interface circuit, enabling the conversion of analog voltage signals into 16-bit digital quantities with a conversion accuracy of 0.0015%, meeting the requirements for high-precision phase detection. The AD ADC chip communicates with the DSP computing unit via an SPI bus. The SPI interface includes a chip select signal CS, a clock signal SCLK, a master-output-slave-in signal MISO, and a master-in-slave-output signal MOSI, achieving a data transmission rate of up to 20Mbps to ensure real-time performance.

[0054] The specific implementation of the DSP computing unit employs a high-performance digital signal processor to execute phase calculation and control algorithms. The DSP computing unit uses a TMS320F28377S DSP chip, which features a 200MHz operating frequency, a dual-core CPU architecture, and abundant peripheral interfaces. The DSP computing unit receives digitized sampling data from the AD analog-to-digital converter chip via the SPI interface. Based on the current output frequency range of the high-voltage inverter, it executes the corresponding phase calculation algorithm. When the frequency is greater than 5Hz, it uses data from an integral circuit and performs 90-degree lead compensation; when the frequency is less than 2Hz, it directly uses data from a low-pass filter circuit; and when the frequency is between 2Hz and 5Hz, it uses a smooth switching algorithm for data fusion processing. The output of the DSP computing unit is connected to the control port of the high-voltage inverter via a drive interface. The output signals include frequency control commands, phase control commands, and amplitude control commands, providing precise vector control parameters for the high-voltage inverter and achieving the technical goal of wide-range speed control. The entire circuit system, through the organic combination of analog and digital signal processing, achieves high-precision detection of the output voltage frequency and phase of the high-voltage inverter, providing a reliable technical foundation for precise speed control over a wide frequency range.

[0055] Specifically, the principle of this invention is as follows: The fundamental principle behind this invention's ability to solve the problems of phase accuracy and speed regulation stability in high-voltage frequency converters over a wide frequency range lies in establishing a frequency-adaptive multi-path signal processing mechanism and a multi-objective coordinated optimization framework. The reason why traditional technologies perform poorly over a wide frequency range is mainly because they employ a single signal processing path and a fixed control strategy, which cannot adapt to the significant differences in signal characteristics at different frequencies. This invention divides the entire operating frequency range into three intervals—high frequency, low frequency, and mid-frequency—by setting frequency boundary thresholds ω1 and ω2. Different processing strategies are adopted for the signal characteristics of each interval. In the high-frequency region, the high-frequency response characteristics of the integrator circuit are used to obtain accurate amplitude information, while a 90-degree leading phase compensation is performed by the DSP computing unit to offset the inherent phase lag of the integrator circuit. In the low-frequency region, a low-pass filter circuit is used to suppress high-frequency noise interference and maintain phase lag-free characteristics. In the mid-frequency transition region, a smooth switching algorithm is used to dynamically weight and fuse the two signal processing results, avoiding signal abrupt changes during frequency switching. At the control strategy level, this invention constructs a convex optimization solution model with the goal of minimizing speed error, transforming the complex wide-range speed control problem into a parameter optimization problem under multiple constraints. The optimal solution is obtained through the Lagrange multiplier method, ensuring the global optimality of the control parameters. The adaptive PID control algorithm dynamically adjusts the control parameters according to the current frequency range and load conditions, enhancing the system's adaptability. The design concept of the two-layer game-theoretic coordinated optimization model is to treat energy consumption optimization and accuracy optimization as two mutually constraining and interdependent game subjects. The upper-layer model optimizes the frequency adjustment strategy to minimize system power consumption through a combination function of exponential weighting and logarithmic penalty, while the lower-layer model optimizes the phase compensation parameters to maximize control accuracy through a product-type objective function. Information exchange and constraint transmission are achieved between the two layers through an energy consumption-accuracy coupling term. The game equilibrium mechanism ensures that the two optimization objectives maintain an optimal coordinated balance under dynamically changing operating conditions. This multi-layered coordinated optimization mechanism theoretically guarantees that the system can simultaneously meet the requirements of phase accuracy and speed regulation stability within any frequency range.

[0056] The following provides a specific embodiment 1 of the method provided by the present invention. The specific implementation of each step in this embodiment 1 is described in detail below.

[0057] In this embodiment, the specific implementation of step S01 is the same as described above, and will not be repeated in detail here.

[0058] The specific implementation of step S02 is to perform voltage division sampling on the output voltage of the high-voltage frequency converter by a three-phase acquisition unit. The formula for calculating the voltage division ratio of the sampling voltage division circuit is as follows: ; In the formula, The partial pressure ratio; The resistance value of the sixth voltage divider resistor; This is the resistance value of the seventh voltage divider resistor.

[0059] The output voltage of the common-mode differential op-amp is expressed as: ; In the formula, To suppress the common-mode differential operational amplifier output voltage; The magnification factor is usually set between 10 and 50. This is the in-phase input voltage; This is the inverting input voltage.

[0060] The transfer function of the integrator circuit is: ; In the formula, Let be the transfer function of the integrator circuit in the Laplace domain; For the Laplace operator; The second resistor value is typically 10kΩ to 100kΩ; This is the capacitance value of the first capacitor, typically ranging from 0.1μF to 1μF.

[0061] The transfer function of the low-pass filter circuit is: ; In the formula, The transfer function of the low-pass filter circuit; This is the resistance value of the fourth resistor; This is the resistance value of the fifth resistor; This is the capacitance value of the second capacitor.

[0062] The parameter acquisition method is as follows: The resistance value was obtained through experimental measurement, using a digital multimeter to measure the resistance value in a power-off state. Obtain using the same method; The standard signal is input into a signal generator, and the output voltage ratio is measured to determine the value. and Obtained by measuring with a capacitance tester.

[0063] The specific implementation of step S03 involves performing segmented phase calculations based on the output frequency of the high-voltage frequency converter. The phase fusion formula for the smooth switching algorithm is as follows: ; In the formula, The phase of the intermediate frequency voltage; This refers to the phase information of the output signal of the integrator circuit after it is 90 degrees ahead of the DSP computing unit. This refers to the phase information of the output signal of the low-pass filter circuit. This is the current output frequency; The high-frequency boundary threshold is set to 5Hz; The low-frequency boundary threshold is set to 2Hz.

[0064] The high-frequency phase compensation formula is: ; In the formula, The compensated high-frequency phase; This represents the original phase output by the integrator circuit.

[0065] The low-frequency phase can be directly expressed using the formula: ; In the formula, Low-frequency phase; This is the output phase of the low-pass filter circuit.

[0066] The parameter acquisition method is as follows: The frequency domain peak value is obtained by sampling through an AD analog-to-digital converter chip and then calculating it using a fast Fourier transform. and The instantaneous phase is obtained by calculating the Hilbert transform.

[0067] The specific implementation of step S04 is to establish a convex optimization solution model, and the objective function is expressed as: ; In the formula, The objective function value; This represents the number of sampling points; For the first The target rotational speed at each sampling point; For the first The actual rotational speed at each sampling point; For the first Frequency adjustment amount per sampling point; For the first Phase correction amount per sampling point; The weighting coefficient is adjusted for frequency, with a typical value of 0.01 to 0.1; This is the phase correction weighting coefficient, with a typical value of 0.005 to 0.05.

[0068] The constraint matrix is ​​represented as follows: ; In the formula, This is the matrix of equality constraint coefficients; This is the inequality constraint coefficient matrix; The vector on the right-hand side of the equation constrains the expression. The vector on the right-hand side of the inequality constraint; Adjust the frequency vector; This is the phase correction vector.

[0069] The Lagrange function is: ; In the formula, It is a Lagrange function; The Lagrange multiplier vector; This is the constraint coefficient matrix; For decision variable vectors; To constrain the vector on the right.

[0070] The parameter acquisition method is as follows: It is set by the host computer and obtained through the communication interface; The rotational speed is obtained by measuring the speed with an encoder and then filtering it. and The optimal value was determined through a systematic identification experiment.

[0071] The specific implementation of step S05 is to use an adaptive PID control algorithm, and the PID controller output formula is: ; In the formula, For the controller at time The output; For proportional gain; For integral gain; This is the differential gain; For a moment The rotational speed error; For a moment The rotational speed error.

[0072] The adaptive gain adjustment formula is: ; ; ; In the formula, , , The basic gain parameter; , , This is an adaptive adjustment coefficient, with a typical value range of 0.1 to 0.5; This is the current output frequency.

[0073] The formula for calculating rotational speed error is: ; In the formula, Reference speed; To measure rotational speed.

[0074] The parameter acquisition method is as follows: , , Obtained through step response experiment debugging; Calculated from speed control commands; The speed is measured in real time by a speed sensor.

[0075] The specific implementation of step S06 is to construct a two-layer game coordination optimization model, where the objective function of the upper-layer energy consumption optimization model is: ; In the formula, The objective function of the upper-level model; This represents the total power consumption of the system. This represents the change in switching losses. This represents the effective value of the harmonic current. For system efficiency; This is a coupling term for energy consumption accuracy; , , This is the weighting coefficient, with a typical value range of 0.1 to 1.0; This is the exponential adjustment coefficient, with a typical value of 0.01 to 0.1.

[0076] The objective function of the lower-level accuracy optimization model is: ; In the formula, The objective function for the lower-level model; To control the standard deviation of accuracy; This refers to the system response time. For stability indicators; For robustness indicators; , , , This is the weighting coefficient, with a typical value range of 0.1 to 2.0.

[0077] The formula for calculating the energy consumption accuracy coupling term is: ; In the formula, , , The coupling coefficient; For frequency adjustment amplitude; For phase correction amplitude; This represents the load change rate.

[0078] The equilibrium condition for the game is: ; In the formula, For upper-level decision variables; For lower-level decision variables; This is the gradient operator.

[0079] The parameter acquisition method is as follows: Obtained through real-time measurement using a power sensor; The speed deviation was calculated by statistically analyzing the speed deviation over the most recent 100 control cycles. The coupling coefficient was obtained through step response testing; the coupling coefficient was determined through multi-objective optimization experiments.

[0080] The specific implementation method of step S07 is the same as described above, and will not be repeated in detail here.

[0081] It should be noted that the formula for common-mode differential op-amps... Based on the differential amplification principle of operational amplifiers, a protection network consisting of bidirectional TVS diodes and current-limiting resistors is used to achieve differential amplification and common-mode interference suppression of the voltage signal after voltage division. Compared with the traditional single-ended amplification method, this circuit design has stronger anti-interference capabilities, effectively suppressing electromagnetic interference and common-mode noise generated during the operation of high-voltage frequency converters, improving the signal-to-noise ratio, and ensuring a stable and reliable voltage sampling signal even in complex electromagnetic environments, laying the foundation for accurate wide-range speed control.

[0082] Integrator circuit transfer function This circuit embodies the frequency domain characteristics of an ideal integrator, with its amplitude-frequency response attenuating as frequency increases and its phase-frequency response lagging by a fixed 90 degrees. In wide-range speed control of high-voltage frequency converters, this integrator circuit functions as a frequency adaptive filter, exhibiting excellent tracking performance for high-frequency signals. Compared to traditional fixed-cutoff-frequency filters, it maintains higher signal amplitude and a stable phase relationship in the high-frequency band, solving the problem of decreased detection accuracy caused by severe signal attenuation in traditional methods at high frequencies, and achieving accurate extraction of phase information in the high-frequency band.

[0083] low-pass filter circuit transfer function This constitutes the standard form of a first-order active low-pass filter, whose cutoff frequency is determined by the product of the resistor and capacitor, and whose passband gain is determined by the resistor ratio. Designed for low-frequency signals, this low-pass filter circuit offers better low-frequency selectivity and noise suppression compared to traditional broadband filters. It effectively filters out high-frequency interference and noise, maintaining the integrity and phase accuracy of low-frequency signals. It solves the technical challenges of weak and easily interfered signals in extremely low-frequency bands using traditional methods, providing a reliable signal processing foundation for applications such as low-speed turning gears.

[0084] Smooth switching algorithm formula By employing the principle of linear interpolation, a smooth transition of the output results of the integrator circuit and the low-pass filter circuit in the mid-frequency range is achieved. This algorithm avoids the phase jump problem at the switching point in traditional piecewise control methods through continuous variation of the weighting coefficients. Compared with hard switching, it significantly reduces oscillations and instability in the control system, ensuring the continuity and smoothness of phase information across the entire wide frequency range. This solves the problems of decreased control accuracy and system oscillation caused by abrupt switching in traditional multipath signal processing.

[0085] High-frequency phase compensation formula Based on the inherent 90-degree phase lag characteristic of the integrator circuit, the phase delay of the analog integrator circuit is offset by phase lead compensation in the digital domain. Compared with traditional hardware phase correction methods, this compensation strategy has the advantages of high accuracy, flexible adjustment, and good temperature stability. It avoids the influence of analog circuit parameter drift on phase accuracy, realizes accurate recovery of phase information in the high-frequency band, and provides a reliable phase reference for precise vector control of high-voltage frequency converters in high-frequency operating conditions.

[0086] Convex optimization objective function A quadratic objective function was constructed, comprising a principal term for speed error and a penalty term for control input, satisfying the basic requirements of convex optimization problems. Compared to traditional single-objective optimization methods, this objective function design can simultaneously consider control accuracy and control smoothness. By reasonably setting the weighting coefficients, it achieves a coordinated balance among multiple objectives, avoiding system oscillations and actuator wear problems caused by drastic changes in control input in traditional methods, and improving the stability of wide-range speed control and the service life of equipment.

[0087] PID controller formula By combining an adaptive gain adjustment mechanism, dynamic optimization of control parameters with frequency and load conditions is achieved. The adaptive gain formula adjusts the three gain parameters through a power function relationship of frequency. Compared with the traditional fixed-parameter PID controller, it can maintain good control performance over a wide frequency range, solving the contradiction between slow response in the low-frequency range and severe overshoot in the high-frequency range of the traditional method, and realizing high-precision speed control across the entire frequency range.

[0088] The two-level game model optimizes the energy consumption function in the upper level. and lower-level precision optimization function The competitive and cooperative mechanism achieves global optimization of system performance. The exponential term in the upper-level function... The impact of changes in switching losses was amplified, affecting several terms. The fluctuations in harmonic currents are smoothed out, and the product term... This illustrates the trade-off between power consumption and efficiency. The product term in the lower-level function... Simultaneously optimize accuracy and response speed, exponential term This underscores the importance of stability and robustness. Coupling terms. The power function relationship describes the nonlinear interaction between energy consumption and accuracy. Compared with the traditional linear weighted multi-objective optimization method, it can more accurately reflect the complex correlation between various performance indicators in the actual system, achieve a coordinated balance between minimizing energy consumption and maximizing control accuracy, and significantly improve the comprehensive performance of wide-range speed control of high-voltage frequency converters.

[0089] The following provides a specific embodiment 2 of the adoption and conditioning circuit provided in the second aspect of the present invention, such as... Figure 2-4 As shown, the system includes a high-voltage frequency converter 6, an AC motor 7, a load 8, a three-phase acquisition unit 10, and a DSP computing unit 5. The output of the high-voltage frequency converter 6, the AC motor 7, and the load 8 are connected in sequence.

[0090] The high-voltage frequency converter 6 has a three-phase output. The three-phase acquisition unit 10 includes three identical unit acquisition circuits 11. Each unit acquisition circuit 11 is connected to one phase of the three-phase output of the high-voltage frequency converter 6. Each unit acquisition circuit 11 includes a common-mode differential operational amplifier 1, an integrator circuit 2, a low-pass filter circuit 3, and an AD analog-to-digital converter chip 4.

[0091] The voltage output terminal of the high-voltage frequency converter 6 is also connected to the input of the common-mode differential operational amplifier 1 through the sampling voltage divider circuit 9. The output of the common-mode differential operational amplifier 1 is connected to the input of the integrating circuit 2 and the low-pass filter circuit 3. The output of the integrating circuit 2 and the low-pass filter circuit 3 is connected to the input of the AD analog-to-digital converter chip 4. The output of the AD analog-to-digital converter chip 4 is connected to the DSP computing unit 5. The output of the DSP computing unit 5 is connected to the drive port of the high-voltage frequency converter 6.

[0092] Each of the aforementioned unit acquisition circuits includes a common-mode differential operational amplifier 1, comprising a bidirectional TVS diode DZ1, a first resistor R1, and a first operational amplifier U1. The bidirectional TVS diode DZ1 and the first resistor R1 are connected in parallel between the inverting and non-inverting input terminals of the first operational amplifier U1. The output of the first operational amplifier U1 is connected to the inputs of the integrating circuit 2 and the low-pass filter circuit 3, respectively. The first operational amplifier U1 may be an AD629AR chip manufactured by Analog Devices.

[0093] The integrating circuit 2 of each unit acquisition circuit includes a second operational amplifier U2, a second resistor R2, a third resistor R3, and a first capacitor C1. One end of the second resistor R2 is connected to the common-mode differential operational amplifier, and the other end of the second resistor R2 is connected to the inverting input terminal of the second operational amplifier U2. The first capacitor C1 and the third resistor R3 are connected in parallel between the inverting input terminal and the output terminal of the second operational amplifier U2. The non-inverting input terminal of the second operational amplifier U2 is connected to analog ground. The output terminal of the second operational amplifier U2 is connected to the AD analog-to-digital converter chip 4.

[0094] The low-pass filter circuit 3 of each unit acquisition circuit includes a third operational amplifier U3, a fourth resistor R4, a fifth resistor R5, and a second capacitor C2. One end of the fifth resistor R5 is connected to the common-mode differential operational amplifier, and the other end of the fifth resistor R5 is connected to the inverting input terminal of the third operational amplifier U3. The second capacitor C2 and the fourth resistor R4 are connected in parallel between the inverting input terminal and the output terminal of the third operational amplifier U3. The non-inverting input terminal of the third operational amplifier U3 is connected to analog ground, and the output terminal of the third operational amplifier U3 is connected to the AD analog-to-digital converter chip 4.

[0095] The frequency output by the integrator circuit 2 is the same as the frequency output by the low-pass filter circuit 3, but the phases are different.

[0096] The AD analog-to-digital converter chip of each unit acquisition circuit transmits data to the DSP computing unit via the SPI bus.

[0097] Each of the unit acquisition circuits includes a sampling voltage divider circuit comprising a sixth voltage divider resistor R6 and a seventh voltage divider resistor R7. One end of the sixth voltage divider resistor R6 is connected to the output terminal of the high-voltage frequency converter and the AC motor, respectively. The other end of the sixth voltage divider resistor R6 is connected to the common-mode differential operational amplifier and one end of the seventh voltage divider resistor R7, and the other end of the seventh voltage divider resistor R7 is grounded. The sampling voltage divider circuit samples the output voltage of the high-voltage frequency converter, converts the high voltage to a low voltage, and then sends it to the input of the corresponding common-mode differential operational amplifier.

[0098] The second operational amplifier U2 and the third operational amplifier U3 can each be an OP284ES amplifier manufactured by Analog Devices. The AD analog-to-digital converter chip 4 can be an AD7606 chip manufactured by Analog Devices. The DSP computing unit 5 can be a TMS6747 chip manufactured by Texas Instruments.

[0099] The common-mode differential operational amplifier 1 multiplies the sampled signal from the sampling voltage divider circuit 9 by -1 and sends it to the integrator circuit 2 and the low-pass filter circuit 3. This ensures that the outputs of the subsequent integrator circuit 2 and low-pass filter circuit 3 have opposite polarity to the input, ultimately resulting in a positive number for easier subsequent DSP processing.

[0100] The anti-common-mode differential operational amplifier samples the voltage frequency of the high-voltage inverter through the sampling voltage divider circuit; the integrator circuit and the low-pass filter circuit obtain the high-frequency voltage signal and the low-frequency voltage signal of the high-voltage inverter through the anti-common-mode differential operational amplifier, respectively, and send them to the DSP computing unit for calculation through the AD analog-to-digital converter chip; The DSP computing unit calculates the phase of the high-voltage frequency converter at high frequency, low frequency, or medium frequency voltage based on the signal from the AD analog-to-digital converter chip.

[0101] The frequency and phase information of the high-voltage inverter output voltage obtained by the DSP computing unit can provide accurate information for subsequent vector control, ensuring high-precision control can be achieved over a wide frequency range.

[0102] Specifically, when the high-voltage inverter outputs a high-frequency voltage greater than ω1, the integrating circuit 2 converts the sampled high-frequency voltage signal into a high-frequency sampling signal, outputs it to the AD analog-to-digital converter chip for analog-to-digital conversion, and then sends it to the DSP calculation unit. The DSP calculation unit calculates the phase of the high-frequency voltage output by the high-voltage inverter based on the high-frequency sampling signal; where ω1 = 5Hz.

[0103] The frequency of the high-frequency sampling signal output by the integrator circuit is the same as the frequency of the high-frequency voltage output by the high-voltage inverter. The phase of the high-frequency sampling signal lags behind the phase of the high-frequency voltage output by the high-voltage inverter by 90°. Therefore, the actual phase of the high-frequency voltage output by the high-voltage inverter is: the phase of the high-frequency sampling signal is increased by 90°. This process is completed in the DSP calculation unit.

[0104] When the high-voltage inverter outputs a low-frequency voltage with a frequency less than ω2, the low-pass filter circuit converts the sampled low-frequency voltage signal into a low-frequency sampling signal, outputs it to the AD analog-to-digital converter chip for analog-to-digital conversion, and then sends it to the DSP calculation unit. The DSP calculation unit calculates the phase of the low-frequency voltage output by the high-voltage inverter based on the low-frequency sampling signal; where ω2 = 2Hz. The low-frequency sampling signal generated by the low-pass filter circuit after sampling has an amplified amplitude, and its frequency is the same as the low-frequency voltage output by the high-voltage inverter, with no phase hysteresis.

[0105] The frequency of the high-frequency sampling signal output by the integrator circuit is the same as the frequency of the low-frequency sampling signal output by the low-pass filter circuit, which is ω. When the high-voltage inverter outputs a medium-frequency voltage between ω1 and ω2, and simultaneously utilizes the sampling results from the low-pass filter circuit and the integrator circuit, the DSP calculation unit calculates the medium-frequency voltage phase using the following formula through smooth switching: Intermediate frequency voltage phase=a1(ω-ω1) / (ω2-ω1)+a2(ω2-ω) / (ω2-ω1), Where a1 is the phase information of the output signal of the integrator circuit after it is 90° ahead in the DSP computing unit, and a2 is the phase information of the output signal of the low-pass filter circuit.

[0106] To better understand and implement this invention, Example 3, a specific application scenario, is provided below: A 6kV high-voltage frequency converter drives an asynchronous motor with a rated power of 5MW, requiring precise speed control across the entire range from an extremely low frequency of 0.1Hz turning gear to a high frequency of 150Hz. The research team first set the speed control parameters, determining the target speed range as 3rpm to 9000rpm, and the frequency boundary threshold... Set to 5Hz. The frequency was set to 2Hz, the phase compensation coefficient to 0.9, and the control accuracy requirement to be within 0.05% of the target speed. The established initial state parameter set for speed control includes 15 core parameters, covering aspects such as frequency control, phase adjustment, power limiting, and stability assurance.

[0107] In the design and implementation of the three-phase acquisition unit, the research team configured an independent acquisition circuit for each phase output of the high-voltage frequency converter. The sampling voltage divider circuit uses a high-precision resistor R6 of 22MΩ for the sixth voltage divider and a precision resistor R7 of 47kΩ for the seventh voltage divider, achieving a voltage division ratio of approximately 470:1, safely reducing the 6kV high voltage to below 12.8V. The common-mode differential operational amplifier uses the AD629AR chip, with a gain set to 15x, and forms an input protection network with a bidirectional TVS diode with a breakdown voltage of 6.8V and a 2.2kΩ current-limiting resistor. The integrator circuit uses an OP284ES operational amplifier, with a second resistor R2 of 33kΩ, a first capacitor C1 of 0.47μF, and a third resistor R3 of 4.7MΩ, forming an integrator with a time constant of 15.5ms. The low-pass filter circuit also uses an OP284ES operational amplifier, with the fifth resistor R5 being 33kΩ, the fourth resistor R4 being 100kΩ, and the second capacitor C2 being 2.2μF, forming a first-order low-pass filter with a cutoff frequency of 0.72Hz. The AD7606 analog-to-digital converter chip is selected, with a sampling frequency set to 50kHz and a resolution of 16 bits.

[0108] During the implementation of the segmented phase calculation strategy, the research team executed a multi-path phase calculation algorithm using the DSP computing unit TMS320F28377S. When the output frequency of the high-voltage inverter is detected to be higher than 5Hz, the system automatically selects the integrator circuit channel and performs a 90-degree lead compensation operation on the obtained phase information in the DSP. The compensation formula... This ensures the accuracy of phase information in the high-frequency band. When the output frequency is below 2Hz, the system switches to the low-pass filter circuit channel, directly using its output phase information to avoid phase distortion in the low-frequency band. In the mid-frequency range of 2Hz to 5Hz, the smooth switching algorithm dynamically calculates the weighting coefficients based on the current frequency value, achieving a smooth transition between the two channel signals and effectively avoiding phase jump phenomena at the switching point.

[0109] The convex optimization solution model employs a sliding window with 180 sampling points, and the frequency-adjusted weighting coefficients in the objective function... Set to 0.05, phase correction weighting coefficient The value is set to 0.02. Constraints include a frequency change rate limited to within 0.5 Hz per second, a phase change limited to within 2 degrees per control cycle, and power limited to within 105% of rated power. Iterative calculations using the Lagrange multiplier method are completed within each control cycle, with the calculation time controlled within 2 ms to meet real-time control requirements. The convergence criterion for the optimization calculation is set as the rate of change of the objective function being less than... Or the number of iterations exceeds 50.

[0110] In the implementation of the adaptive PID control algorithm, the basic gain parameter is set as follows: =1.2, =0.8, =0.15, adaptive adjustment coefficient =0.3, =0.25, =0.35. The controller adjusts the gain parameters in real time according to the current frequency range and load changes. At extremely low frequencies of 0.1Hz, the proportional gain is automatically adjusted to 2.8 and the integral gain to 3.2. At high frequencies of 100Hz, the proportional gain is adjusted to 0.6 and the derivative gain to 0.8. The calculation accuracy of the speed error reaches 0.1rpm, and the integral term adopts an anti-integral saturation algorithm to prevent integrator saturation.

[0111] In the implementation of the two-level game coordination optimization model, the weight coefficients of the upper-level energy consumption optimization model are set as follows: =0.6, =0.3, =0.4, Exponential adjustment coefficient =0.08. The weight coefficients of the lower-level accuracy optimization model are set to... =1.5, =1.2, =0.4, =0.6. The coupling coefficients of the energy consumption accuracy coupling terms are respectively =0.03, =0.008, =0.25. The iterative solution of the game equilibrium adopts the alternating optimization algorithm. Each iteration includes two stages: upper-level model optimization and lower-level model optimization. The convergence condition is set as the rate of change of the objective function in three consecutive iterations being less than 0.1%.

[0112] The key control parameters during implementation are shown in Table 1: Table 1 Key Parameters for Wide-Range Speed ​​Control of High-Voltage Frequency Converters

[0113] During the system debugging phase, the research team conducted detailed tests on the control performance at different frequency bands. Figure 5 The amplitude-frequency response characteristics of the three-phase acquisition unit at different frequencies are demonstrated, clearly showing the excellent performance of the integrating circuit and the low-pass filter circuit in their respective applicable frequency bands. Figure 6 The comparison of phase compensation effects is depicted, verifying the effectiveness of the 90-degree lead compensation algorithm in the high-frequency range. The test results for speed control accuracy are as follows: Figure 7 As shown, this demonstrates the control accuracy advantage of the method of the present invention across the entire frequency range. The convergence process of the game optimization algorithm is as follows: Figure 8 As shown, this reflects the fast convergence characteristic of the two-level game model. The overall system performance evaluation results are as follows: Figure 9 As shown, this comprehensively demonstrates the coordinated effect of energy consumption optimization and accuracy improvement.

[0114] Test data shows that in the extremely low frequency (0.1Hz) turning stage, the speed control accuracy reaches ±0.02rpm, and the speed fluctuation rate is reduced to within 0.8%, which is a significant improvement compared to the ±0.5rpm accuracy and 3.5% fluctuation rate of the traditional method. In the mid-frequency (2.5Hz) transition stage, the smooth switching algorithm effectively avoids the ±15-degree phase jump caused by the traditional hard switching method, achieving a smooth transition with a phase continuity error of less than ±0.5 degrees. In the high-frequency (100Hz) test stage, the phase lag compensation reduces the 12-degree lag of the traditional method to within ±1 degree, and the frequency response speed is improved to complete 90% of the frequency jump within 50ms, which is more than 60% shorter than the traditional method.

[0115] The game-theoretic optimization model exhibits good adaptability in actual operation, reducing the total system power consumption by 8.5% compared to the single-objective optimization method, while improving control accuracy by more than 40%. The introduction of the energy consumption-accuracy coupling term allows the system to maintain a relatively low power consumption level even under high-precision control, avoiding the contradiction between accuracy and energy consumption inherent in traditional methods. The system demonstrates excellent dynamic response during load abrupt changes; during a load abrupt change from 20% to 80% of rated power, the speed overshoot is controlled within 2%, and the settling time is shortened to 1.5 seconds, showcasing excellent robustness and rapid response capabilities.

[0116] The technological advancements brought about by this invention compared to traditional speed control methods are mainly reflected in three fundamental breakthroughs. First, the multi-path phase calculation strategy overcomes the frequency domain limitations of traditional single-filter methods. Through the collaborative efforts of the integrator circuit and the low-pass filter circuit, the frequency tracking characteristics of the integrator circuit are used to maintain signal strength at high frequencies, the noise suppression capability of the low-pass filter circuit is used to improve the signal-to-noise ratio at low frequencies, and a smooth switching algorithm is used to achieve seamless transitions at mid-frequency frequencies, fundamentally solving the problem of performance imbalance in the wide frequency domain of traditional methods. Second, the two-layer game-theoretic coordinated optimization overcomes the limitations of traditional linear weighted multi-objective optimization. Through the competitive cooperation mechanism between the upper and lower layer models and the introduction of nonlinear coupling terms, it more accurately describes the complex relationship between energy consumption and accuracy in the actual system, achieving a global optimal solution rather than a local optimal solution, avoiding the overall performance degradation caused by the mutual constraints of various performance indicators in traditional methods. Finally, adaptive circuit signal processing breaks through the accuracy bottleneck of traditional digital processing methods. By combining high-precision signal preprocessing of analog circuits with flexible calculation of digital algorithms, it not only ensures the accurate detection of weak signals but also realizes the high-speed execution of complex algorithms, providing a high-quality signal foundation and powerful computing support for wide-range speed control.

[0117] It should be noted that the variables involved in this invention are explained in detail in Tables 2 and 3.

[0118] Table 2. Variable Explanation Table (Part 1)

[0119] Table 3. Variable Explanation Table (Part Two)

[0120] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A wide-range speed control method for a high-voltage frequency converter, characterized in that, include: Set the speed control parameters for the high-voltage frequency converter, including the target speed range and frequency boundary thresholds. and Based on phase compensation coefficient and control accuracy requirements, an initial state parameter set for speed control is established; a three-phase acquisition unit is used to sample the output voltage of the high-voltage frequency converter in real time to obtain a digitized voltage signal; a multi-path phase calculation strategy is executed based on different ranges of the high-voltage frequency converter's output frequency, and when the output frequency is greater than the frequency boundary threshold... The high-frequency sampling signal output by the integrator circuit is used, and a 90-degree lead phase compensation operation is performed in the DSP computing unit. When the output frequency is less than the frequency boundary threshold... The low-frequency sampled signal output by the low-pass filter circuit is used for hysteresis-free phase calculation. When the output frequency is at... to A smooth switching algorithm is used to weightedly fuse the outputs of the integrator circuit and the low-pass filter circuit. A convex optimization solution model for minimizing speed error is established, transforming the wide-range speed control problem into a parameter optimization problem under multiple constraints. The Lagrange multiplier method is used to solve for the optimal frequency adjustment and phase correction. Adaptive feedback regulation is performed based on the deviation between the target speed and the actual speed, and an adaptive PID control algorithm is used to calculate the frequency adjustment and phase correction. A two-level game coordination optimization model is applied to coordinate system parameters. The optimal control parameters output by the game coordination optimization model are transmitted to the drive port of the high-voltage frequency converter.

2. The method according to claim 1, characterized in that, In the steps of setting the speed control parameters of the high-voltage frequency converter Set to 5Hz. Set to 2Hz.

3. The method according to claim 2, characterized in that, The steps of the three-phase acquisition unit specifically include three identical unit acquisition circuits. Each unit acquisition circuit, through the cooperation of a sampling voltage divider circuit, an anti-common-mode differential operational amplifier, an integrator circuit, a low-pass filter circuit, and an AD analog-to-digital converter chip, converts the high voltage output by the high-voltage frequency converter into a digital signal and simultaneously outputs a high-frequency sampling signal and a low-frequency sampling signal.

4. The method according to claim 3, characterized in that, The AD analog-to-digital converter chip transmits the digitized high-frequency and low-frequency sampling signals to the DSP computing unit via the SPI bus. The DSP computing unit calculates the phase information of the high-voltage frequency converter at high-frequency, low-frequency, or medium-frequency voltages based on the signals from the AD analog-to-digital converter chip.

5. The method according to claim 4, characterized in that, The smooth switching algorithm is specifically used to handle frequency boundary thresholds. to The intermediate frequency voltage signal between the two frequencies is used to calculate the intermediate frequency voltage phase through the output results of a weighted fusion integrator circuit and a low-pass filter circuit. The weighting coefficients are based on the current output frequency and the frequency boundary threshold. and The relative position is dynamically determined.

6. The method according to claim 5, characterized in that, The convex optimization solution model specifically uses an objective function to minimize the deviation between the target speed and the actual speed. The constraints include frequency change rate constraints, phase change constraints, power limit constraints, and system stability constraints. The inputs include the target speed, actual speed, frequency adjustment amount, phase correction amount, and system power parameters. The output is the optimal frequency adjustment amount and phase correction amount that satisfy all constraints.

7. The method according to claim 6, characterized in that, The frequency of the high-frequency sampling signal is the same as the frequency of the high-frequency voltage output by the high-voltage inverter, and the phase of the high-frequency sampling signal lags behind the phase of the high-frequency voltage output by the high-voltage inverter by 90 degrees; the frequency of the low-frequency sampling signal is the same as the frequency of the low-frequency voltage output by the high-voltage inverter, and the phase of the low-frequency sampling signal has no lag.

8. The method according to claim 7, characterized in that, The two-layer game-theoretic coordination optimization model specifically includes an upper-layer energy consumption optimization model and a lower-layer accuracy optimization model. The objective function of the upper-layer energy consumption optimization model is formed by adding the exponentially weighted term of the total system power consumption and the logarithmic penalty term of the switching loss, then combining it with the product term of the harmonic current and the reciprocal of the system efficiency, and finally adding the energy consumption and accuracy coupling term. The objective function of the lower-layer accuracy optimization model is formed by adding the product term of the reciprocal of the standard deviation of control accuracy and the reciprocal of the response time, the exponentially weighted term of the stability index and the robustness index, and finally subtracting the energy consumption and accuracy coupling term.

9. The method according to claim 8, characterized in that, The energy consumption and accuracy coupling term is specifically used to describe the mutual constraint relationship between energy consumption optimization and accuracy optimization. The inputs include total system power consumption, standard deviation of control accuracy, frequency adjustment, phase correction and load change rate. The output is the coupling coefficient reflecting the strength of the trade-off between the two optimization objectives.

10. A sampling and conditioning circuit for wide-range speed control of a high-voltage frequency converter, characterized in that, The circuit used in the method according to any one of claims 1 to 9 includes a high-voltage frequency converter, an AC motor, and a load, wherein the output terminal of the high-voltage frequency converter, the AC motor, and the load are connected in sequence, characterized in that: it further includes a three-phase acquisition unit and a DSP computing unit, wherein the three-phase acquisition unit includes three identical unit acquisition circuits, each of the unit acquisition circuits including a sampling voltage divider circuit, a common-mode differential operational amplifier, an integrator circuit, a low-pass filter circuit, and an AD analog-to-digital converter chip; the voltage output terminal of the high-voltage frequency converter is also connected to the input of the common-mode differential operational amplifier through the sampling voltage divider circuit, the output of the common-mode differential operational amplifier is connected to the input of the integrator circuit and the low-pass filter circuit, the output of the integrator circuit and the low-pass filter circuit is connected to the input of the AD analog-to-digital converter chip, the output of the AD analog-to-digital converter chip is connected to the input of the DSP computing unit; the output of the DSP computing unit is connected to the drive port of the high-voltage frequency converter; The anti-common-mode differential operational amplifier samples the voltage frequency of the high-voltage inverter through the sampling voltage divider circuit; the integrator circuit and the low-pass filter circuit obtain the high-frequency voltage signal and the low-frequency voltage signal of the high-voltage inverter respectively through the anti-common-mode differential operational amplifier, and send them to the DSP computing unit for calculation through the AD analog-to-digital converter chip; the DSP computing unit calculates the phase of the high-voltage inverter at high-frequency voltage, low-frequency voltage, or medium-frequency voltage based on the signal from the AD analog-to-digital converter chip.

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