High-precision R-2R voltage type digital-to-analog converter based on binary weighting code and thermometer code

Abstract

The invention discloses a high-precision R-2R voltage type digital-to-analog converter based on a binary weighted code and a thermometer code, the digital-to-analog converter comprises a weighted resistance network, a thermometer decoder circuit and an operational amplifier module with a self-calibration function, the output of the weighted resistance network is connected with the operational amplifier module with the self-calibration function, and the output of the thermometer decoder circuit is connected with the operational amplifier module with the self-calibration function. The output of the thermometer decoder circuit is connected with a thermometer code part of the weighted resistance network, an external clock CLK signal and a common-mode voltage serve as input signals of the operational amplifier module with the self-calibration function, and an output signal of the weighted resistance network passes through the operational amplifier module with the self-calibration function to obtain final analog voltage output. The resistance network adopts a mixture of thermometer codes and an R-2R structure, static indexes of the DAC can be effectively optimized, the impedance matching problem of the resistance network is reduced, a self-calibration operational amplifier technology is further applied, the influence of offset voltage of an operational amplifier on output precision can be eliminated, and the output driving capacity of the DAC is improved.

Description

Technical Field

[0001] This invention belongs to the field of high-precision analog-to-digital converters, and relates to a digital-to-analog converter, specifically a high-precision R-2R voltage-type digital-to-analog converter based on binary weighted code and thermometer code. Background Technology

[0002] DACs are usually not presented as standalone chips, but rather integrated into application-specific integrated circuits. With the advancement of technology, the requirements for the accuracy and power consumption of DACs are becoming increasingly stringent.

[0003] Based on the weighting network type, DACs can be categorized into the following types: voltage proportional, charge proportional, and current proportional. Voltage proportional DACs typically employ a resistor network, utilizing resistor voltage division to make the output signal relatively monotonic with the input signal, achieving higher accuracy. Through segmented resistor design, the overall error is distributed across multiple independent segments, each undertaking only a portion of the voltage division task, significantly reducing the impact of a single resistor error on the overall result. Low-temperature-sensitive resistor technologies can be used, minimizing temperature drift. Voltage proportional DACs directly generate analog voltage through voltage distribution, resulting in greater stability and eliminating non-monotonic distortion compared to the capacitor charging / discharging process of charge-type DACs and the glitches introduced by current-type switches. Therefore, voltage proportional DACs hold significant research value.

[0004] However, traditional voltage proportional structure requires a large layout area, and its core resistor network needs a large number of precisely matched resistor units. For an 8-bit Kelvin voltage divider, the required resistors are... The resistors have a large RC delay, resulting in a slow switching speed. A DC current path always exists in the resistor divider path, and regardless of the switching state, the total current flows to ground or the op-amp input through the resistor network. This generates significant static power consumption in the resistor divider path.

[0005] In summary, the quality of the digital-to-analog converter (DAC) structure determines the quality and accuracy of the digital-to-analog signal conversion. Speed ​​and power consumption are among the bottlenecks that DAC technology often needs to overcome for further development. Therefore, the design of DAC circuits has always been highly valued. Summary of the Invention

[0006] This invention provides a high-precision R-2R voltage-type digital-to-analog converter based on binary weighted code and thermometer code. Compared with other types of DACs, its resistor network uses a hybrid thermometer code and R-2R structure, which can effectively optimize the static performance of the DAC. It also has excellent characteristics such as small area and high precision, which can reduce the impedance matching problem of the resistor network. Furthermore, it applies self-calibrating operational amplifier technology, which can eliminate the influence of operational amplifier offset voltage on output accuracy and improve the DAC output drive capability.

[0007] The objective of this invention is achieved through the following technical solution:

[0008] A high-precision R-2R voltage-type digital-to-analog converter based on binary weighted code and thermometer code comprises three parts: a weighted resistor network, a thermometer decoder circuit, and an operational amplifier module with self-calibration.

[0009] The output of the weighted resistor network is connected to the operational amplifier module with self-calibration function. The output of the thermometer decoder circuit is connected to the thermometer code part of the weighted resistor network. The external clock CLK signal and the common-mode voltage vcm are used as the input signals of the operational amplifier module with self-calibration function. The output signal of the weighted resistor network is passed through the operational amplifier module with self-calibration function to obtain the final analog voltage output VOUT.

[0010] The weighted resistor network includes a thermometer code resistor network and an R-2R structure resistor network;

[0011] The thermometer code resistor network consists of seven pairs of resistors with the same resistance value R and a CMOS switch with an equivalent resistance value r0 connected in series. The thermometer code resistor network is sequentially controlled by the seven-bit thermometer code output by the thermometer decoder circuit through the input high three-bit control signal.

[0012] The R-2R resistor network consists of an inverted T-shaped network formed by resistors with resistance values ​​of R and 2R. The 2R resistor is connected to vref or gnd via a CMOS switch with an equivalent resistance of 2r0. The R resistor is connected to a CMOS switch with an equivalent resistance of r0 that is always on, achieving precise impedance matching. The switches in the R-2R resistor network are sequentially controlled by the lower 5 bits of the input signal. The weighted resistor network achieves 8-bit DAC conversion, satisfying the formula... Among them, V ref This is the reference voltage for the DAC. ~ The circuit connection states are listed in order from the most significant bit to the least significant bit. =0 indicates that the bit is not connected to the circuit. =1 indicates that this bit is connected to the circuit, V out This refers to the output voltage of the DAC circuit.

[0013] The thermometer decoder circuit is responsible for converting the input high three binary bits into a seven-bit thermometer code, thereby controlling the high seven bits of the analog-to-digital converter.

[0014] The thermometer decoding circuit is composed of standard CMOS static basic logic gates, including inverters, three-input NAND gates, two-input NAND gates, and two-input NOR gates. The logic operation is performed by the above basic logic gates. The input three-bit binary code is enhanced and driven by the inverter, and the signal is shaped. Then, the intermediate signal is generated by the sub-decoding unit. Finally, the output signal is amplified by the inverter with a large driving force to ensure the load driving capability.

[0015] The operational amplifier module with self-calibration function includes a main operational amplifier, an auxiliary operational amplifier, and a clock buffer circuit;

[0016] The output of the main operational amplifier is connected to the auxiliary operational amplifier through a capacitor. The main positive input terminal of the main operational amplifier is connected to the DAC resistor network, and the main negative input terminal is directly connected to the output of the main operational amplifier to form unity gain. The auxiliary positive input terminal and the auxiliary negative input terminal are connected to the offset storage capacitor of the main operational amplifier, and the auxiliary negative input terminal is connected to the common-mode level point.

[0017] The main positive input terminal and the main negative input terminal of the auxiliary operational amplifier are controlled by two control signals, which are respectively connected to the common-mode level and the output of the weighted resistor network through switches. The auxiliary positive input terminal and the auxiliary negative input terminal of the auxiliary operational amplifier are connected to the offset storage capacitor of the auxiliary operational amplifier, and the auxiliary positive input terminal is connected to the common-mode level point.

[0018] The clock buffer circuit adopts a domino inverter chain structure, which increases the driving capability step by step and generates two inverted control signals CLK1 and CLK2 to control the timing state of the operational amplifier module with self-calibration, thereby realizing the switching between self-calibration state and amplification state.

[0019] The main operational amplifier and the auxiliary operational amplifier are controlled by a two-phase clock. In the first timing state, the offset voltage of the auxiliary operational amplifier is stored on the capacitor. In the second timing state, the offset of the auxiliary operational amplifier is eliminated during signal amplification. The offset voltage of the main operational amplifier is eliminated through the action of the auxiliary operational amplifier with no offset voltage, thereby achieving low offset conversion of digital code.

[0020] Compared to traditional voltage-type DAC circuits, this invention has the following advantages:

[0021] 1. It has high layout utilization and conversion accuracy. The high-order part adopts a thermometer code resistor network, and the low-order part adopts an R-2R structure resistor network.

[0022] 2. The output voltage of the resistor network is passed through a self-calibrating operational amplifier module to improve the output drive capability.

[0023] 3. The operational amplifier employs self-calibration technology to eliminate the effects of offset voltage and improve accuracy and stability. Attached Figure Description

[0024] Figure 1 A schematic diagram of a high-precision R-2R voltage-type digital-to-analog converter for binary weighted code and thermometer code;

[0025] Figure 2 A schematic diagram of the specific structure of a thermometer decoder;

[0026] Figure 3 This is a schematic diagram of the switch structure;

[0027] Figure 4 This is a schematic diagram of an operational amplifier module with self-calibration function. Detailed Implementation

[0028] The technical solution of the present invention will be further described below with reference to the accompanying drawings, but it is not limited thereto. Any modifications or equivalent substitutions to the technical solution of the present invention that do not depart from the spirit and scope of the technical solution of the present invention should be covered within the protection scope of the present invention.

[0029] This invention provides a high-precision R-2R voltage-type digital-to-analog converter based on binary weighted code and thermometer code, such as... Figure 1 As shown, the digital-to-analog converter (DAC) circuit consists of three parts: a weighted resistor network, a thermometer decoder circuit, and an operational amplifier module with self-calibration. The weighted resistor network is composed of CMOS switches and resistor networks, divided into a thermometer code resistor network and an R-2R structure resistor network. The thermometer code resistor network is controlled by the output of the thermometer decoder, while the resistor arrangement of the R-2R structure resistor network corresponds to the binary weights, allowing direct input of binary code. The decoder circuit consists of standard CMOS static basic logic gates, responsible for converting the three-input binary code into a seven-bit thermometer code, thereby controlling the high three bits of the DAC. The operational amplifier module with self-calibration consists of a main operational amplifier (amp) and an auxiliary operational amplifier (aux). In the first timing state, the offset voltage of the auxiliary operational amplifier is stored on a capacitor. In the second timing state, the offset voltage of the main operational amplifier is eliminated through the auxiliary operational amplifier with no offset voltage, achieving low-offset conversion of the digital code. The specific structure is as follows:

[0030] I. Weighted Resistor Network:

[0031] The weighted resistor network consists of two parts: a thermometer-coded resistor network and an R-2R structure resistor network. The thermometer-coded resistor network is composed of seven pairs of resistors with the same resistance value R and a CMOS switch (switch1) with an equivalent resistance value of r0 connected in series. The switch in the thermometer-coded resistor network is sequentially controlled by the seven-bit thermometer code output from the thermometer decoder circuit via the three highest-order control signals. Figure 1 As shown, the specific connection method of the thermometer code resistor network is as follows:

[0032] R11's upper end is connected to the DAC resistor network output vin_vdd, and its lower end is connected to the upper end of switch1. The switch1 control signal is connected to Q1, and its lower ends are connected to gnd and Vref, respectively. R12's upper end is connected to the DAC resistor network output vin_vdd, and its lower end is connected to the upper end of switch1. The switch1 control signal is connected to Q2, and its lower ends are connected to gnd and Vref, respectively. R13's upper end is connected to the DAC resistor network output vin_vdd, and its lower end is connected to the upper end of switch1. The switch1 control signal is connected to Q3, and its lower ends are connected to gnd and Vref, respectively. R14's upper end is connected to the DAC resistor network output vin_vdd, and its lower end is connected to switch1. The upper end of R15 is connected to the DAC resistor network output vin_vdd, and the lower end is connected to the upper end of switch1. The switch1 control signal is connected to Q4, and the lower two ends are connected to gnd and Vref respectively. The upper end of R16 is connected to the DAC resistor network output vin_vdd, and the lower end is connected to the upper end of switch1. The switch1 control signal is connected to Q6, and the lower two ends are connected to gnd and Vref respectively. The upper end of R17 is connected to the DAC resistor network output vin_vdd, and the lower end is connected to the upper end of switch1. The switch1 control signal is connected to Q7, and the lower two ends are connected to gnd and Vref respectively.

[0033] The R-2R resistor network consists of resistors with resistance values ​​of R and 2R, forming an inverted T-shaped network. The 2R resistor is connected to either vref or gnd via a CMOS switch (switch2) with an equivalent resistance of 2r0. The R resistor is connected to a CMOS switch (switch1) with an equivalent resistance of r0, which is always on, achieving impedance matching. The switches in the R-2R resistor network are sequentially controlled by the lower 5 bits of the input signal. For example... Figure 1 As shown, the specific connection method of the R-2R structure resistor network is as follows:

[0034] R1 connects its left end to gnd and its right end to the left end of switch2. The switch2 control signal is connected to vdd. The right end of switch2 connects to the top of R3. The bottom end of R3 connects to switch2. The switch2 control signal is connected to A8, and its lower ends are connected to gnd and Vref respectively. R2 connects its left end to the top of R3 and its right end to the left end of switch1. The switch1 control signal is connected to vdd. The right end of switch1 connects to the top of R5 and its lower end to switch2. The switch2 control signal is connected to A7, and its lower ends are connected to gnd and Vref respectively. R4 connects its left end to the top of R5 and its right end to the left end of switch1. The switch1 control signal is connected to vdd. The right end of switch1 connects to the top of R7 and its lower end to switch2. The switch2 control signal is connected to A6, and its lower ends are connected to gnd and Vref respectively. R6 connects its left end to the top of R7 and its right end to the left end of switch1. The control signal of switch1 is connected to Vdd. The right end of switch1 is connected to the upper end of R9, and the lower end of R9 is connected to switch2. The control signal of switch2 is connected to A5, and the lower two ends are connected to GND and Vref respectively. The left end of R8 is connected to the upper end of R9, and the right end of R8 is connected to the left end of switch1. The control signal of switch1 is connected to Vdd. The right end of switch1 is connected to the upper end of R10, and the lower end of R10 is connected to switch2. The control signal of switch2 is connected to A4, and the lower two ends are connected to GND and Vref respectively. The upper end of R10 is connected to the DAC resistor network output vin_vdd.

[0035] II. Thermometer Decoder Circuit:

[0036] Thermometer decoder circuit such as Figure 2As shown, the three-bit binary code (A, B, C) is converted into thermometer codes (Q1-Q7). The basic unit of this circuit is a digital logic circuit composed of CMOS basic logic gates. The inverter uses a push-pull complementary operation of PMOS and NMOS transistors to achieve logic inversion. The two-input NAND gate uses a push-pull complementary structure of two series-connected NMOS transistors and two parallel-connected PMOS transistors. The three-input NAND gate uses a push-pull complementary structure of three series-connected N-channel MOS transistors and three parallel-connected P-channel MOS transistors. The two-input NOR gate uses a push-pull complementary structure of two parallel-connected NMOS transistors and two series-connected PMOS transistors. The overall decoder circuit is composed of the above digital logic gates, and the specific connection method is as follows: the three input signals (A, B, C) are connected to the left end of the inverter, and the right end of the inverter... The system outputs signals AN, BN, and CN. AN, BN, and CN are connected to the inputs of a three-input NAND gate, and the NAND gate output generates output signal Q1. A and B are connected to a NOR gate, and the output is then connected to the input of an inverter to obtain output signal Q2. B and C are connected to a NAND gate, then to the input of an inverter, then to the input of an NOR gate, and finally to an inverter to obtain output signal Q3. AN is connected to the input of an inverter to obtain output signal Q4. B and C are connected to the inputs of an NOR gate, and the output is then connected to the input of an inverter. The output is then connected to the input of a NAND gate and then through an inverter to obtain output signal Q5. A and B are connected to the inputs of a two-input NAND gate, and the output is connected to the input of an inverter to obtain output signal Q6. A, B, and C are connected to the inputs of a three-input NAND gate, and the output is then connected to the input of an inverter to obtain output signal Q7.

[0037] III. Operational amplifier module with self-calibration:

[0038] The self-calibrating operational amplifier module includes a main operational amplifier, an auxiliary operational amplifier, and a clock buffer circuit. Clock signals CLK2 and CLK1 control a dummy switch, altering the timing state of the self-calibrating operational amplifier module. In the first timing state, CLK2, the offset voltage of the auxiliary operational amplifier is stored in capacitor C1. In subsequent operations, this offset voltage is amplified along with the input signal, eliminating the offset voltage of the auxiliary operational amplifier. In the second timing state, CLK1, the offset voltage is amplified by the auxiliary operational amplifier and input to the main operational amplifier. When the gain of the auxiliary operational amplifier is significantly greater than the gain of the main operational amplifier, the offset voltage will be eliminated. Figure 4As shown, the specific connection method is as follows: The positive input terminal of the main operational amplifier is connected to vin_vdd, its AUP port is connected to the upper end of C2, the lower end of C2 is connected to the common-mode level vcm, its AUN port is connected to the common-mode level vcm, and the negative input terminal is connected to vout, forming a unity-gain operational amplifier, which is connected to the upper end of switch SW1. Switch SW1 is controlled by PH2, and its lower end is connected to the negative input terminal of the auxiliary operational amplifier. The output terminal of the auxiliary operational amplifier is fed back to the AUN terminal of the auxiliary operational amplifier through capacitor C1; vin_vdd is connected to the upper end of switch SW3, and its lower end is connected to the positive input terminal of the auxiliary operational amplifier. Simultaneously connect the left end of switch SW4, and the right end of switch SW4 to the negative input terminal of the auxiliary operational amplifier. Switch SW3 is controlled by PH2, and switch SW4 is controlled by PH1. The auxiliary operational amplifier AUP is connected to the common-mode level VCM, AUN is connected to the upper end of capacitor C1, and the lower end of C1 is connected to the common-mode level VCM. The output of the auxiliary operational amplifier is connected to SW5, which is controlled by PH1, and SW6, which is controlled by PH2. The lower end of SW5 is connected to the upper end of capacitor C1, and the lower end of SW6 is connected to the upper end of capacitor C2. The common-mode level VCM is connected to the positive input terminal of the main operational amplifier. Clocks PH1 and PH2 are two inverted clocks.

[0039] The main operational amplifier in the self-calibrating operational amplifier module adopts an operational amplifier structure with a double-folded cascode current mirror load. It has two pairs of differential inputs, one pair for the normal input voltage and the other pair for storing the offset voltage and eliminating its own offset voltage through amplification. The cascode amplification structure can increase the bandwidth to meet the DAC frequency range requirements. The cascode current mirror load can improve the output swing to meet the DAC output range requirements.

[0040] The auxiliary operational amplifier in the self-calibrating operational amplifier module adopts a high-gain operational amplifier structure with a two-stage Miller-compensated, double-folded, cascaded current mirror load and a cascaded current source load. It has two pairs of differential inputs: one pair for the normal input voltage and the other pair for storing the offset voltage and using amplification to eliminate its own offset voltage. The cascaded amplification structure increases the bandwidth to meet the DAC frequency range requirements. The cascaded current mirror load improves the output swing to meet the DAC output range requirements. The two-stage structure achieves high gain, meets the offset voltage elimination requirements, and improves DAC accuracy. Miller compensation enhances the operational amplifier's stability.

[0041] The operational amplifier module with self-calibration employs dummy switches to effectively reduce charge injection effects. It utilizes basic CMOS transfer gates and two pairs of source-drain connected CMOS modules, such as... Figure 3As shown, the specific connections are as follows: The control signal CLK is connected to the inverter, outputting an inverted CLK control signal; the source and drain terminals of N1, N3, N4, and N6 are connected together; the input VIN is connected to the drain terminal of N1, the source terminal of N1 is connected to the drain terminal of N2, the source terminal of N2 is connected to the drain terminal of N3, and the source terminal of N3 is connected to VOUT; the input VIN is connected to the drain terminal of N4, the source terminal of N4 is connected to the drain terminal of N5, the source terminal of N5 is connected to the drain terminal of N6, and the source terminal of N6 is connected to VOUT; the gate terminals of N1, N3, and N5 are connected to the CLK control signal, and the gate terminals of N2, N4, and N6 are connected to the inverted CLK control signal.

[0042] In this invention, the circuit design converts the input 8-bit signal into an analog voltage output, and the final expression of the two presents a binary relationship, that is... Because traditional voltage-type DACs have a large area and limited accuracy, the weighted resistor network of this invention uses a hybrid of a thermometer-code resistor network and an R-2R structure resistor network. The more bits the thermometer structure occupies, the more complex the circuit structure and the larger the layout area, but the better the circuit performance and monotonicity. Conversely, the more bits the binary structure occupies, the simpler the circuit structure, but the worse the overall circuit performance.

[0043] Taking all factors into consideration, the weighted resistor network in this DAC structure combines a 3-bit thermometer structure with a 5-bit R-2R structure, splitting the input digital signal into high-order segments (A1-A3) and low-order segments (A4-A8). The high-order segments are converted to 2D signals by a thermometer decoder. n -1 independent switch control signal (e.g., 3 high bits correspond to 7 switches) ensures that each valid code value only conducts the corresponding number of equivalent resistors, eliminating glitches and nonlinear errors generated during high-bit binary transitions. The low-bit segment uses an R-2R ladder resistor network for binary weight allocation, and utilizes an alternating R and 2R resistor structure to achieve current shunting, exponentially reducing the number of required resistors (e.g., only 5 sets of R-2R units are needed for 5 low bits).

[0044] In this invention, the thermometer code resistor network can eliminate differential nonlinearity error (DNL), significantly improving the DAC output accuracy. The three highest control signals (A1-A3) have a higher weight and are therefore used to control the switching of the thermometer code resistor network. The three highest control signals (A1-A3) of the thermometer code are converted into 7-bit thermometer codes (Q1-Q7) by the thermometer decoder circuit, which are used to control the switching of the thermometer code resistor network. When any branch is connected to... A connection is equivalent to a voltage of Vref being applied to the circuit. Taking a one-digit thermometer code as an example, at this point, the output of the weighted resistor network is connected to... The equivalent resistance of the R-R-2R structure resistor network where the connected branch is located, and the equivalent resistance of the remaining thermometer code resistor network connected to ground. After parallel connection, voltage division is performed to satisfy... That is, the output corresponding to the LSB of the thermometer code section. Similarly, the weights corresponding to the three high-order digits controlled by the thermometer decoder are as follows: , , .

[0045] In this invention, the lower 5 bits employ an R-2R ladder network, which saves a significant amount of area. The lower bit signals (A4-A8) control the switch to switch the path. When a certain path is connected to... When connected. Taking A4 as an example, when the A4 control switch is on, the resistance of the A4 path itself is 2R, the equivalent resistance looking to the left from the top node is 2R, and the equivalent resistance looking to the right is... The resistance after parallel connection is After being connected in series with its own resistance 2R to divide the voltage, the node voltage is Similarly, the corresponding outputs for controlling the conduction of A5~A8 can be obtained. ~ .

[0046] In this invention, a thermometer decoder circuit is used to convert a three-bit binary code (A, B, C) into a thermometer code (Q1-Q7). Since the thermometer code changes continuously, glitches can be effectively reduced, improving the static performance of the circuit. The basic unit of this circuit is a digital logic circuit composed of CMOS basic logic gates. The inverter achieves logic inversion by using a push-pull complementary operation of PMOS and NMOS transistors. The three-input NAND gate is composed of a push-pull complementary structure of three N-channel MOS transistors (NMOS) connected in series and three P-channel MOS transistors (PMOS) connected in parallel. The two-input NAND gate is composed of a push-pull complementary structure of two NMOS transistors connected in series and two PMOS transistors connected in parallel. The two-input NOR gate is composed of a push-pull complementary structure of two NMOS transistors connected in parallel and two PMOS transistors connected in series. The width-to-length ratio of the equivalent PDN and PUN of all basic logic gates satisfies the minimum delay design. The three input signals (A, B, C) first pass through the inverter to shape the input signals and improve anti-interference capability and reduce noise. The original signal and the inverted signals AN, BN, and CN are processed together through logic gates to realize the function of the thermometer decoder.

[0047] In this invention, the operational amplifier module with self-calibration can reduce the impact of operational amplifier offset voltage on measurement accuracy. Unlike traditional self-zeroing and chopping techniques, this structure can operate in closed-loop mode for continuous signal amplification, with the output directly fed back to the input. This improves DAC accuracy by enhancing load capacity and eliminating the effects of offset voltage without affecting the DAC output signal value. The module has two main timing states. The input signal CLK passes through a domino-inverter chain clock buffer circuit, outputting two inverted control signals CLK1 and CLK2 to control the timing state. The input signal CLK first passes through multiple inverters to increase drive capability, then is delayed to obtain CLK2. CLK2 then passes through an inverter and is delayed again to obtain CLK1. The delay reduces charge injection effects.

Claims

1. A high-precision R-2R voltage-type digital-to-analog converter based on binary weighted code and thermometer code, characterized in that... The digital-to-analog converter comprises three parts: a weighted resistor network, a thermometer decoder circuit, and an operational amplifier module with self-calibration. The output of the weighted resistor network is connected to an operational amplifier module with self-calibration function. The output of the thermometer decoder circuit is connected to the thermometer code section of the weighted resistor network. The external clock CLK signal and the common-mode voltage vcm serve as the input signals of the operational amplifier module with self-calibration function. The output signal of the weighted resistor network is passed through the operational amplifier module with self-calibration function to obtain the final analog voltage output VOUT.

2. The high-precision R-2R voltage-type digital-to-analog converter based on binary weighted code and thermometer code according to claim 1, characterized in that... The weighted resistor network includes a thermometer code resistor network and an R-2R structure resistor network, wherein: The thermometer code resistor network consists of seven pairs of resistors with the same resistance value R and a CMOS switch with an equivalent resistance value r0 connected in series. The thermometer code resistor network is sequentially controlled by the seven-bit thermometer code output by the thermometer decoder circuit through the input high three-bit control signal. The R-2R resistor network consists of an inverted T-shaped network formed by resistors with resistance values ​​of R and 2R. The 2R resistor is connected to vref or gnd via a CMOS switch with an equivalent resistance of 2r0. The R resistor is connected to a CMOS switch with an equivalent resistance of r0 that is always on, achieving precise impedance matching. The switches in the R-2R resistor network are sequentially controlled by the lower 5 bits of the input signal. The weighted resistor network achieves 8-bit DAC conversion, satisfying the formula... Among them, V ref This is the reference voltage for the DAC. ~ The circuit connection states are listed in order from the most significant bit to the least significant bit. =0 indicates that the bit is not connected to the circuit. =1 indicates that this bit is connected to the circuit, V out This is the output voltage of the DAC circuit.

3. The high-precision R-2R voltage-type digital-to-analog converter based on binary weighted code and thermometer code according to claim 2, characterized in that... The specific connection method of the thermometer code resistor network is as follows: R11's upper end is connected to the DAC resistor network output vin_vdd, and its lower end is connected to the upper end of switch1. The switch1 control signal is connected to Q1, and its lower ends are connected to gnd and Vref respectively. R12's upper end is connected to the DAC resistor network output vin_vdd, and its lower end is connected to the upper end of switch1. The switch1 control signal is connected to Q2, and its lower ends are connected to gnd and Vref respectively. R13's upper end is connected to the DAC resistor network output vin_vdd, and its lower end is connected to the upper end of switch1. The switch1 control signal is connected to Q3, and its lower ends are connected to gnd and Vref respectively. R14's upper end is connected to the DAC resistor network output vin_vdd. The lower end of R15 is connected to the upper end of switch1, the switch1 control signal is connected to Q4, and the lower two ends are connected to gnd and Vref respectively; the upper end of R15 is connected to the DAC resistor network output vin_vdd, the lower end is connected to the upper end of switch1, the switch1 control signal is connected to Q5, and the lower two ends are connected to gnd and Vref respectively; the upper end of R16 is connected to the DAC resistor network output vin_vdd, the lower end is connected to the upper end of switch1, the switch1 control signal is connected to Q6, and the lower two ends are connected to gnd and Vref respectively; the upper end of R17 is connected to the DAC resistor network output vin_vdd, the lower end is connected to the upper end of switch1, the switch1 control signal is connected to Q7, and the lower two ends are connected to gnd and Vref respectively. The specific connection method of the R-2R structure resistor network is as follows: The left end of R1 is connected to gnd, and the right end is connected to the left end of switch2. The switch2 control signal is connected to vdd. The right end of switch2 is connected to the upper end of R3. The lower end of R3 is connected to switch2. The switch2 control signal is connected to A8, and the lower two ends are connected to gnd and Vref respectively. The left end of R2 is connected to the upper end of R3, and the right end of R2 is connected to the left end of switch1. The switch1 control signal is connected to vdd. The right end of switch1 is connected to the upper end of R5. The lower end of R5 is connected to switch2. The switch2 control signal is connected to A7, and the lower two ends are connected to gnd and Vref respectively. The left end of R4 is connected to the upper end of R5, and the right end of R4 is connected to the left end of switch1. The switch1 control signal is connected to vdd, and the right end of switch1 is connected to... Connect the top of R7, and the bottom of R7 to switch2. The control signal of switch2 is connected to A6, and the bottom two ends are connected to gnd and Vref respectively. Connect the left end of R6 to the top of R7, and the right end of R6 to the left end of switch1. The control signal of switch1 is connected to Vdd. Connect the right end of switch1 to the top of R9, and the bottom of R9 to switch2. The control signal of switch2 is connected to A5, and the bottom two ends are connected to gnd and Vref respectively. Connect the left end of R8 to the top of R9, and the right end of R8 to the left end of switch1. The control signal of switch1 is connected to Vdd. Connect the right end of switch1 to the top of R10, and the bottom of R10 to switch2. The control signal of switch2 is connected to A4, and the bottom two ends are connected to gnd and Vref respectively. Connect the top of R10 to the DAC resistor network output vin_vdd.

4. The high-precision R-2R voltage-type digital-to-analog converter based on binary weighted code and thermometer code according to claim 1, characterized in that... The thermometer decoder circuit is responsible for converting the input high three binary bits into a seven-bit thermometer code, thereby controlling the high seven bits of the analog-to-digital converter.

5. The high-precision R-2R voltage-type digital-to-analog converter based on binary weighted code and thermometer code according to claim 1 or 4, characterized in that... The thermometer decoding circuit consists of standard CMOS static basic logic gates, including inverters, three-input NAND gates, two-input NAND gates, and two-input NOR gates. The logic operation is performed by the above basic logic gates. The input three-bit binary code is amplified and driven by the inverter, and the signal is shaped. Then, the intermediate signal is generated by the sub-decoding unit. Finally, the output signal is amplified by the inverter with a large driving force to ensure the load driving capability.

6. The high-precision R-2R voltage-type digital-to-analog converter based on binary weighted code and thermometer code according to claim 5, characterized in that... The specific connection method of the thermometer decoding circuit is as follows: The three input signals A, B, and C are respectively connected to the left end of the inverter. The right end of the inverter outputs output signals AN, BN, and CN. AN, BN, and CN are connected to the input terminals of a three-input NAND gate. The NAND gate output generates output signal Q1. A and B are connected to a NOR gate, and the output is then connected to the input terminal of the inverter to obtain output signal Q2. B and C are connected to a NAND gate, then connected to the input terminal of the inverter, and then connected to the NOR gate input terminal of A, and then connected to the inverter to obtain output signal Q3. AN is connected to the input terminal of the inverter to obtain output signal Q4. B and C are connected to the NOR gate input terminal, and the output is then connected to the input terminal of the inverter. The output is then connected to the NAND gate input terminal of A and then through the inverter to obtain output signal Q5. A and B are connected to the input terminals of a two-input NAND gate, and the output is connected to the input terminal of the inverter to obtain output signal Q6. A, B, and C are connected to the input terminals of a three-input NAND gate, and the output is then connected to the input terminal of the inverter to obtain output signal Q7.

7. The high-precision R-2R voltage-type digital-to-analog converter based on binary weighted code and thermometer code according to claim 1, characterized in that... The operational amplifier module with self-calibration function includes a main operational amplifier, an auxiliary operational amplifier, and a clock buffer circuit, wherein: The output of the main operational amplifier is connected to the auxiliary operational amplifier through a capacitor. The main positive input terminal of the main operational amplifier is connected to the DAC resistor network, and the main negative input terminal is directly connected to the output of the main operational amplifier to form unity gain. The auxiliary positive input terminal and the auxiliary negative input terminal are connected to the offset storage capacitor of the main operational amplifier, and the auxiliary negative input terminal is connected to the common-mode level point. The main positive input terminal and the main negative input terminal of the auxiliary operational amplifier are controlled by two control signals, which are respectively connected to the common-mode level and the output of the weighted resistor network through switches. The auxiliary positive input terminal and the auxiliary negative input terminal of the auxiliary operational amplifier are connected to the offset storage capacitor of the auxiliary operational amplifier, and the auxiliary positive input terminal is connected to the common-mode level point. The clock buffer circuit adopts a domino inverter chain structure, which increases the driving capability step by step and generates two inverted control signals CLK1 and CLK2 to control the timing state of the operational amplifier module with self-calibration, thereby realizing the switching between self-calibration state and amplification state. The main operational amplifier and the auxiliary operational amplifier are controlled by a two-phase clock. In the first timing state, the offset voltage of the auxiliary operational amplifier is stored on the capacitor. In the second timing state, the offset of the auxiliary operational amplifier is eliminated during signal amplification. The offset voltage of the main operational amplifier is eliminated through the action of the auxiliary operational amplifier with no offset voltage, thereby achieving low offset conversion of digital code.

8. The high-precision R-2R voltage-type digital-to-analog converter based on binary weighted code and thermometer code according to claim 7, characterized in that... The specific connection method of the operational amplifier module with self-calibration is as follows: the positive input terminal of the main operational amplifier is connected to vin_vdd, its AUP port is connected to the upper end of C2, the lower end of C2 is connected to the common-mode level vcm, its AUN port is connected to the common-mode level vcm, and the negative input terminal is connected to vout, forming a unity-gain operational amplifier, and connected to the upper end of switch SW1. Switch SW1 is controlled by PH2, and its lower end is connected to the negative input terminal of the auxiliary operational amplifier. The output terminal of the auxiliary operational amplifier is fed back to the AUN terminal of the auxiliary operational amplifier through capacitor C1; vin_vdd is connected to the upper end of switch SW3, and its lower end is connected to the auxiliary operational amplifier. The positive input terminal of the main operational amplifier is connected to the left end of switch SW4, and the right end of switch SW4 is connected to the negative input terminal of the auxiliary operational amplifier. Switch SW3 is controlled by PH2, and switch SW4 is controlled by PH1. The auxiliary operational amplifier AUP is connected to the common-mode level VCM, and AUN is connected to the upper end of capacitor C1. The lower end of C1 is connected to the common-mode level VCM. The output of the auxiliary operational amplifier is connected to SW5, which is controlled by PH1, and SW6, which is controlled by PH2. The lower end of SW5 is connected to the upper end of capacitor C1, and the lower end of SW6 is connected to the upper end of capacitor C2. The common-mode level VCM is connected to the positive input terminal of the main operational amplifier. Clocks PH1 and PH2 are two inverted clocks.

9. The high-precision R-2R voltage-type digital-to-analog converter based on binary weighted code and thermometer code according to claim 7, characterized in that... The main operational amplifier adopts an operational amplifier structure with a double-folded common-source cascode cross-current mirror load.

10. The high-precision R-2R voltage-type digital-to-analog converter based on binary weighted code and thermometer code according to claim 7, characterized in that... The auxiliary operational amplifier adopts a high-gain operational amplifier structure with two-stage Miller compensation, double-folded common-source cascade, cascaded current mirror load, and common-source load.

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