Clock recovery method, electronic device, readable medium and program product

Abstract

The invention provides a clock recovery method. The clock recovery method comprises the following steps: determining a sampling phase deviation based on any subcarrier in demultiplexed subcarriers; and obtaining a subcarrier signal after clock recovery based on the sampling phase deviation and the center frequency of the subcarrier after demultiplexing. The invention further provides electronic equipment, a readable medium and a program product.

Description

Technical Field

[0001] This disclosure relates to the field of communication technology, and in particular to a clock recovery method, electronic device, readable medium, and program product. Background Technology

[0002] In coherent optical communication systems, sampling phase deviation is one of the main factors affecting signal quality and a key bottleneck restricting the stability of optical communication systems. Clock recovery methods for Digital Subcarrier Multiplexing (DSCM) systems include hybrid analog-digital clock recovery and all-digital clock recovery. All-digital clock recovery has two structures: one involves performing phase detection and digital domain interpolation on each subcarrier after subcarrier demultiplexing; however, this method requires phase detection for each subcarrier, resulting in a waste of computational resources. Summary of the Invention

[0003] This disclosure provides a clock recovery method, an electronic device, a readable medium, and a program product.

[0004] In a first aspect, embodiments of this disclosure provide a clock recovery method, including:

[0005] The sampling phase deviation is determined based on any one of the demultiplexed subcarriers.

[0006] The clock-recovered subcarrier signal is obtained based on the sampling phase deviation and the center frequency of the demultiplexed subcarrier.

[0007] Secondly, embodiments of this disclosure provide an electronic device, which includes a memory and a processor; the memory stores a computer program that can be executed by the processor, and when the computer program is executed by the processor, it implements any one of the clock recovery methods provided in embodiments of this disclosure.

[0008] Thirdly, embodiments of this disclosure provide a computer-readable medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements any of the clock recovery methods provided in embodiments of this disclosure.

[0009] Fourthly, embodiments of this disclosure provide a computer program product comprising a computer program that, when executed by a processor, implements any one of the clock recovery methods provided in embodiments of this disclosure.

[0010] The clock recovery method provided in this disclosure determines the sampling phase deviation based on any one of the demultiplexed subcarriers; and obtains the clock-recovered subcarrier signal based on the sampling phase deviation and the center frequency of the demultiplexed subcarrier. That is, the sampling phase deviation is determined using one subcarrier, and all subcarriers use this sampling phase deviation for clock recovery, without calculating their respective sampling phase deviations separately. This can reduce the waste of computing resources and also reduce latency. Attached Figure Description

[0011] In the accompanying drawings of the embodiments disclosed herein:

[0012] Figure 1 A schematic diagram of a coherent optical transmission system is shown.

[0013] Figure 2 This diagram illustrates a flowchart of how the receiving DSP processes digital signals in an embodiment of this disclosure.

[0014] Figure 3 This diagram illustrates a flowchart of a clock recovery method provided in an embodiment of the present disclosure;

[0015] Figure 4 A graph showing the power density of the four subcarrier signals is provided.

[0016] Figure 5 A flowchart illustrating another clock recovery method provided in an embodiment of this disclosure is shown;

[0017] Figure 6 This diagram illustrates a block diagram of an electronic device provided in an embodiment of the present disclosure. Detailed Implementation

[0018] To enable those skilled in the art to better understand the technical solutions of this disclosure, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0019] The present disclosure will be described more fully below with reference to the accompanying drawings; however, the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of the disclosure.

[0020] The accompanying drawings of the embodiments disclosed herein are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the detailed embodiments to explain this disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the description of the detailed embodiments with reference to the accompanying drawings.

[0021] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0022] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. The term "and / or" as used in this disclosure includes any and all combinations of one or more of the associated enumerated entries. The singular forms "a" and "the" as used in this disclosure are also intended to include the plural forms, unless the context clearly indicates otherwise. The terms "comprising," "made of," etc., as used in this disclosure specify the presence of the stated feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0023] Unless otherwise specified, all terms used in this disclosure (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined in this disclosure.

[0024] This disclosure is not limited to the embodiments shown in the accompanying drawings, but includes modifications to the configuration based on the manufacturing process. Therefore, the areas illustrated in the drawings are schematic, and the shapes of the areas shown illustrate specific shapes of the areas of an element, but are not intended to be limiting.

[0025] Figure 1 A schematic diagram of a coherent optical transmission system is shown. Figure 1 As shown, the coherent optical transmission system includes:

[0026] The transmitter digital signal processing (DSP) 100 is used to generate digital signals.

[0027] Waveform generator 200 is used to convert digital signals into analog signals and can generate analog signals with arbitrary waveforms.

[0028] The in-phase / quadrature (IQ) modulator 300 is used to convert analog signals into optical signals. The IQ modulator 300 modulates the analog signal onto the optical carrier under the condition that the first laser 310 provides the optical carrier.

[0029] The transmission channel 400 is used to transmit optical signals to the optical coupler 500. The transmission channel 400 includes an optical fiber 410 and an optical amplifier 420. The optical fiber 410 is the carrier for transmitting optical signals, and the optical amplifier 420 is used to amplify the optical signals.

[0030] Optical coupler 500 is used to split optical signals, and the split optical signals can be measured by spectrometer 510.

[0031] The coherent receiver 600 is used to coherently mix the signal light with the local oscillator light provided by the second laser 610 and convert the optical signal into an analog signal.

[0032] The sampling oscilloscope 700 is used to convert analog signals into digital signals.

[0033] The receiving end DSP800 is used to process the digital signal obtained by the sampling oscilloscope 700. During the processing, clock recovery can be performed according to the method provided in the embodiments of this disclosure.

[0034] Figure 2 This diagram illustrates a flowchart of the digital signal processing performed by the receiving DSP in an embodiment of this disclosure. For example... Figure 2 As shown, the steps for the receiving end DSP to process digital signals include:

[0035] Step S201, IQ imbalance compensation processing, that is, the digital signals XI, YI, XQ, and YQ are processed by IQ imbalance compensation to obtain the X-polarized signal and the Y-polarized signal.

[0036] Step S202, subcarrier demultiplexing processing, that is, performing subcarrier demultiplexing processing on the X-polarized signal and the Y-polarized signal to obtain the demultiplexed subcarrier signal.

[0037] Step S203, dispersion compensation processing, that is, performing dispersion compensation processing on the demultiplexed subcarrier signal to compensate for the phase change caused by dispersion during transmission.

[0038] Step S204, clock recovery processing, that is, clock recovery processing is performed on the demultiplexed subcarrier signal.

[0039] During clock recovery, a single sampling phase deviation can be used to calculate the frequency domain compensation phase (interpolation coefficient), and frequency domain phase shifting can be performed on each asynchronously sampled subcarrier to achieve clock recovery.

[0040] Step S205, adaptive equalization processing, that is, performing adaptive equalization processing on the frequency domain signal and outputting the equalized frequency domain signal.

[0041] Step S206, frequency offset estimation and compensation processing, that is, calculating the frequency offset estimate and compensating the frequency domain signal according to the frequency offset estimate to obtain the frequency offset compensated subcarrier.

[0042] In this embodiment of the disclosure, the frequency offset estimate is estimated using one subcarrier, and different subcarriers share the frequency offset estimate for frequency offset compensation.

[0043] Step S207, phase recovery processing, that is, the phase of the subcarrier is recovered to obtain the phase-recovered subcarrier.

[0044] Step S208, decision processing, that is, making a decision on the subcarriers that have undergone equalization processing, frequency offset compensation, and phase recovery, and generating a decision signal.

[0045] In a first aspect, embodiments of this disclosure provide a clock recovery method.

[0046] Figure 3 A flowchart illustrating a clock recovery method provided in an embodiment of this disclosure is shown. Figure 3 As shown in the embodiments of this disclosure, a clock recovery method includes:

[0047] Step S301: Determine the sampling phase deviation based on any one of the subcarriers after demultiplexing.

[0048] This disclosure does not limit the method of subcarrier demultiplexing. For example, subcarrier separation can be achieved by demultiplexing the input optical signal through frequency domain shifting and frequency domain resampling. This disclosure does not limit the modulation format of the subcarriers, and the clocks of all subcarriers are from the same source.

[0049] Step S302: Obtain the clock-recovered subcarrier signal based on the sampling phase deviation and the center frequency of the demultiplexed subcarrier.

[0050] The embodiments of this disclosure utilize one subcarrier in a digital subcarrier system to determine the sampling phase deviation, and share this sampling phase deviation with all subcarriers for corresponding phase adjustment. This eliminates the need to calculate the sampling phase deviation for each subcarrier separately, thereby reducing the waste of computing resources and lowering latency.

[0051] In some embodiments, determining the sampling phase deviation based on any one of the demultiplexed subcarriers includes: obtaining a phase detection value using a phase detection algorithm based on any one of the demultiplexed subcarriers; and determining the sampling phase deviation based on the phase detection value, wherein the sampling phase deviation is a sampling phase deviation shared by all subcarrier signals.

[0052] Phase detection is performed on any one of the demultiplexed subcarriers to obtain a phase detection value. This phase detection value is then filtered through a loop to obtain the sampled phase deviation. In this embodiment, all subcarriers share this sampled phase deviation.

[0053] This disclosure allows for the selection of subcarrier signals before frequency-domain phase shift via a feedforward structure, or after frequency-domain phase shift via a feedback structure. The different subcarrier signal selection methods lead to different phase detection algorithms for calculating the phase detection value. This disclosure does not limit the phase detection algorithm; for example, the Godard phase detection algorithm can be used.

[0054] In some embodiments, obtaining a phase detection value based on any one of the demultiplexed subcarriers using a phase detection algorithm includes: using a feedforward structure to obtain the frequency domain signal of any one of the subcarriers after demultiplexing and before frequency domain phase shift; determining a phase detection vector using a phase detection algorithm based on the frequency domain signal of the subcarrier and a preset signal block length, and using the argument of the phase detection vector as the phase detection value.

[0055] The frequency domain signal of the subcarrier can be a discrete frequency domain signal or a continuous frequency domain signal.

[0056] In some embodiments, obtaining a phase detection value based on any one of the demultiplexed subcarriers using a phase detection algorithm includes: obtaining the frequency domain signal of any one of the demultiplexed and frequency-domain phase-shifted subcarriers using a feedback structure; determining a phase detection vector using a phase detection algorithm based on the frequency domain signal of the subcarrier and the signal block length of the subcarrier, and using the imaginary part of the phase detection vector as the phase detection value.

[0057] The signal block length is determined by dividing the subcarrier signal into blocks of a fixed length, and then performing phase detection on the signal blocks to obtain the phase detection value.

[0058] Feedforward structures acquire frequency domain signals with lower latency and faster sampling phase deviation tracking speed; feedback structures can acquire more stable frequency domain signals.

[0059] Taking the Godard phase detection algorithm as an example, the phase detection value can be obtained according to equation (1).

[0060]

[0061] Where ε represents the phase detection value, N represents the signal block length, X(k) represents the frequency domain signal of any subcarrier, k represents the index of the discrete Fourier transform, * represents taking the conjugate, and imag and angle represent taking the imaginary part and the argument angle, respectively.

[0062] In some embodiments, determining the sampling phase deviation based on the phase detection value includes: determining the loop filter input value for the current round based on the phase detection value for the current round; determining the proportional path output value for the current round based on the loop filter input value for the current round and the proportional path coefficient of the loop filter; determining the integral path output value for the current round based on the loop filter input value for the current round, the integral path coefficient, and the integral path output value for the previous round; the initial value of the integral path output value is a preset value; determining the sampling phase deviation for the current round based on the proportional path output value for the current round, the integral path output value for the current round, and the sampling phase deviation for the previous round; and taking the sampling phase deviation for the current round as the sampling phase deviation if the difference between the integral path output value for the current round and the integral path output value for the previous round is within a certain range.

[0063] In some embodiments, determining the loop filter input value for the current round based on the phase detection value of the current round includes: in the case of a feedforward structure, determining the loop filter input value for the current round based on the phase detection value of the current round and the sampling phase deviation of the previous round; in the case of a feedback structure, using the phase detection value of the current round as the loop filter input value for the current round.

[0064] For example, the sampling phase deviation is calculated using equations (2) to (5).

[0065]

[0066] LF1(n)=k1·Δε(n) (3)

[0067] LF2(n)=k2·Δε(n)+LF2(n-1) (4)

[0068] τ(n)=τ(n-1)+LF1(n)+LF2(n) (5)

[0069] Where Δε represents the input value of the loop filter, τ represents the sampling phase deviation, n represents the number of calculation rounds, k1 and k2 represent the proportional path coefficient and integral path coefficient, respectively, LF1 and LF2 represent the proportional path output and integral path output, respectively, and the initial values ​​of τ and LF2 can be 0.

[0070] In some embodiments, obtaining the clock-recovered subcarrier signal based on the sampling phase deviation and the center frequency of the demultiplexed subcarrier includes: determining the frequency domain compensation phase based on the sampling phase deviation and the center frequency of the demultiplexed subcarrier; and obtaining the clock-recovered subcarrier signal based on the frequency domain signal of the demultiplexed subcarrier and the frequency domain compensation phase.

[0071] In some embodiments, determining the frequency domain compensation phase based on the sampling phase deviation and the center frequency of the demultiplexed subcarrier includes: determining the additional frequency offset compensation phase of the subcarrier based on the sampling phase deviation and the center frequency of the demultiplexed subcarrier; determining the sampling phase deviation compensation phase based on the sampling phase deviation, the sampling rate, and the signal block length; and determining the frequency domain compensation phase of the subcarrier based on the sampling phase deviation compensation phase and the additional frequency offset compensation phase of the subcarrier.

[0072] For example, the sampling phase deviation compensation phase is calculated using equation (6).

[0073]

[0074] in, Indicates the sampling phase deviation compensation phase, f s τ represents the sampling rate, τ represents the sampling phase deviation, and N represents the length of the signal block.

[0075] The additional frequency offset compensation phase is calculated using equation (7).

[0076]

[0077] in, Indicates the additional frequency offset compensation phase, f c τ represents the center frequency of the subcarrier, and τ represents the sampling phase deviation.

[0078] The frequency domain compensated phase can be obtained by adding the sampling phase deviation compensation phase and the additional frequency offset compensation phase, as shown in equation (8).

[0079]

[0080] in, Indicates frequency domain compensation phase, This indicates the additional frequency offset compensation phase. This indicates the sampling phase deviation compensation phase.

[0081] Based on the frequency domain signal of the demultiplexed subcarrier and the frequency domain compensated phase, the frequency domain signal after phase compensation can be represented by equation (9).

[0082]

[0083] Where X(k) represents the frequency domain signal of the subcarrier, Indicates frequency domain compensation phase, This indicates the additional frequency offset compensation phase. This represents the sampling phase deviation compensation phase, and j represents the imaginary part.

[0084] In some embodiments, the subcarrier with the sampling phase deviation is determined to be the subcarrier located in the middle region among the demultiplexed subcarriers.

[0085] The subcarrier used for phase detection and frequency offset estimation can be any subcarrier. However, because subcarriers in the edge region are significantly affected by device bandwidth, using subcarriers in the middle region for phase detection and frequency offset estimation can improve the accuracy of clock recovery. It should be noted that the middle region and edge region refer to their positions on the frequency spectrum.

[0086] In some embodiments, after obtaining the clock-recovered subcarrier signal based on the sampling phase deviation and the center frequency of the demultiplexed subcarrier, the method further includes: calculating a frequency offset estimate based on one clock-recovered subcarrier, and using the frequency offset estimate to perform frequency offset compensation on all subcarriers.

[0087] In some embodiments, after the subcarrier signal undergoes clock recovery and adaptive equalization, an arbitrary subcarrier is selected to calculate the frequency offset estimate, and all subcarriers are compensated for frequency offset using the same frequency offset estimate.

[0088] In some embodiments, after the subcarrier signal undergoes clock recovery and adaptive equalization, each subcarrier can calculate its own frequency offset estimate, and then use its own frequency offset estimate to compensate for the frequency offset of the subcarrier.

[0089] To better understand the technical principles of the embodiments of this disclosure, taking a continuous signal as an example, the principle of using only one subcarrier to determine the sampling phase deviation and all subcarriers sharing the sampling phase deviation for corresponding phase adjustment is introduced.

[0090] The sampling phase deviation τ of the receiver can be expressed in the time domain as Equation (10).

[0091] τ(t)=k p ·t (10)

[0092] Where t represents time, k p The cumulative acceleration of the sampling phase deviation is represented by τ, where τ represents the sampling phase deviation.

[0093] In this embodiment of the disclosure, k p Related to the sampling frequency offset, its typical value is in the range of ±100ppm. The influence of the local oscillator frequency offset and the sampling phase deviation τ on the subcarrier multiplexed signal x(t) can be expressed in the time domain as Equation (11).

[0094] x′(t)=x(t+τ)·e j·2π·Δf·(t+τ) (11)

[0095] Where x′ represents the continuous time-domain signal after the influence of local oscillator frequency deviation and sampling phase deviation, x represents the continuous time-domain signal before the influence of local oscillator frequency deviation and sampling phase deviation, Δf represents local oscillator frequency deviation, t represents time, and τ represents sampling phase deviation.

[0096] The signal after subcarrier demultiplexing can be expressed as equation (12):

[0097]

[0098] The condition for "≈" to hold is k. p <<1, x′ represents the continuous time-domain signal after the influence of local oscillator frequency deviation and sampling phase deviation, x represents the continuous time-domain signal before the influence of local oscillator frequency deviation and sampling phase deviation, Δf represents local oscillator frequency deviation, t represents time, and τ represents sampling phase deviation.

[0099] From equation (12), we can deduce that the actual frequency offset of the subcarrier is Δf+k. p ·f c Furthermore, the frequency offsets of different subcarriers are different. Combining equation (10), the additional frequency offset k caused by the sampling frequency offset and subcarrier demultiplexing is... p ·f c The compensation phase can be expressed in the time domain as Equation (13).

[0100]

[0101] in, Indicates the additional frequency offset compensation phase, f c τ represents the subcarrier center frequency, kp represents the cumulative acceleration rate of the sampling phase deviation, and τ represents the sampling phase deviation.

[0102] Since the sampling phase deviation τ is relatively stable in a short time, the compensation phase in equation (13) can be approximated as a constant phase for each sampling phase deviation. The sampling phase deviation compensation phase can be expressed in the frequency domain as equation (14).

[0103]

[0104] in, τ represents the sampling phase deviation compensation phase, f represents the frequency, and τ represents the sampling phase deviation.

[0105] Combining equations (13) and (14), the total frequency domain compensation phase can be expressed as equation (15).

[0106]

[0107] in, Indicates frequency domain compensation phase, This indicates the additional frequency offset compensation phase. This indicates the sampling phase deviation compensation phase, where f represents the frequency. c τ represents the center frequency of the subcarrier, and τ represents the sampling phase deviation.

[0108] Based on the above derivation, clock recovery can add the compensation phase for the additional frequency offset to the compensation phase for the sampling phase deviation, thereby achieving simultaneous compensation. After compensation, the frequency offset value of each subcarrier is Δf, which allows the subsequent frequency offset estimation in the DSP to use only the frequency offset estimate of one subcarrier shared by all subcarriers, thus reducing computational complexity.

[0109] The clock recovery method provided in this disclosure is applicable to coherent optical communication digital subcarrier multiplexing systems, serving as a step in the receiver-side DSP process within such systems. Clock recovery is performed using a single subcarrier, and compensation for the additional frequency offset caused by subcarrier demultiplexing is achieved by phase compensation based on the subcarrier's center frequency, thus compensating for the sampling phase deviation after subcarrier demultiplexing. During frequency offset estimation after clock recovery, only one subcarrier is needed, eliminating the need to estimate the frequency offset of each subcarrier separately. This effectively reduces the loop delay of clock recovery and the computational complexity of the DSP algorithm, while ensuring that the performance of the coherent optical communication system is not degraded, thereby improving system stability. Furthermore, it can be applied in the all-digital domain without requiring analog devices to adjust the reference clock, thus reducing operating costs.

[0110] To better understand this embodiment, the following explanation uses four subcarriers as an example. Figure 4 The graph shows the power density of a four-subcarrier signal, where the horizontal axis represents frequency (GHz) and the vertical axis represents power density (dB / Hz). Figure 4 As shown, the center frequency of each subcarrier is different.

[0111] For example, Figure 5 A flowchart illustrating another clock recovery method provided by an embodiment of this disclosure is shown. Figure 5 As shown, the clock recovery method provided in this embodiment includes:

[0112] Step S501: Perform phase detection using a phase detection algorithm based on any one of the subcarriers to obtain the phase detection value.

[0113] This refers to any one of the subcarriers after subcarrier demultiplexing. Phase detection can be performed using either a feedforward structure or a feedback structure.

[0114] Taking the Godard algorithm as an example, the phase detection value can be obtained according to equation (16).

[0115]

[0116] Among them, X i(k) represents the frequency domain signal of the i-th subcarrier, i = 1, 2, ..., N SC N SC In this embodiment, N represents the number of subcarriers. SC =4, ε represents the phase detection value, N represents the signal block length, X(k) represents the frequency domain signal of any subcarrier, k represents the index of the discrete Fourier transform, * represents taking the conjugate, imag and angle represent taking the imaginary part and taking the argument, respectively.

[0117] Select the appropriate phase detection algorithm based on the feedforward or feedback structure, and calculate the sampling phase deviation.

[0118] Step S502: Obtain the sampling phase deviation based on the phase detection value.

[0119] The sampling phase deviation is calculated based on the phase detection value using equations (2) to (5) through loop filtering. The sampling phase deviation is obtained by loop filtering, and noise is filtered out at the same time.

[0120] When calculating the sampling phase deviation, iterative calculation can be performed by dividing the signal into multiple frequency domain signals. When the loop converges, that is, when the difference between the current integral path output value and the previous integral path output value is within a certain range, the sampling phase deviation is determined based on the current proportional path output value, the current integral path output value, and the previous sampling phase deviation.

[0121] Step S503: Obtain the frequency domain compensated phase.

[0122] Based on the center frequency and sampling phase deviation of each subcarrier, the sampling phase deviation compensation phase, the additional frequency offset compensation phase, and the total frequency domain compensation phase of the four subcarriers can be obtained.

[0123]

[0124] Among them, f c_i This represents the center frequency of the i-th subcarrier. This represents the additional frequency offset compensation phase of the i-th subcarrier. f represents the total frequency domain compensation phase of the i-th subcarrier. s τ represents the sampling rate, τ represents the sampling phase deviation, and N represents the signal block length.

[0125] By utilizing clock recovery, the additional frequency offset caused by subcarrier demultiplexing and sampling phase deviation can be compensated for, thereby improving the performance of coherent optical communication systems.

[0126] After step S503, frequency domain phase shift is performed on each subcarrier signal.

[0127] Phase compensation based on the frequency domain of each subcarrier Phase shifting is performed on each subcarrier separately.

[0128]

[0129] Among them, X i (k) represents the frequency domain signal of the i-th subcarrier. This represents the total frequency domain compensation phase of the i-th subcarrier. This represents the additional frequency offset compensation phase of the i-th subcarrier. This represents the sampling phase deviation compensation phase, and j represents the imaginary part.

[0130] The frequency domain compensation phase is determined based on the sampling phase deviation and the center frequency of the demultiplexed subcarrier.

[0131] The clock recovery method provided in this disclosure determines the sampling phase deviation based on any one of the demultiplexed subcarriers; and obtains the clock-recovered subcarrier signal based on the sampling phase deviation and the center frequency of the demultiplexed subcarrier. That is, the sampling phase deviation is determined using one subcarrier, and all subcarriers use this sampling phase deviation for clock recovery, without calculating their respective sampling phase deviations separately. This can reduce the waste of computing resources and also reduce latency.

[0132] Secondly, embodiments of this disclosure provide an electronic device.

[0133] Figure 6 This diagram illustrates a block diagram of an electronic device provided in an embodiment of the present disclosure. Figure 6 As shown, an electronic device provided in this embodiment includes a processor 601 and a memory 602; the memory 602 stores a computer program that can be executed by the processor 601, and when the computer program is executed by the processor 601, it implements any one of the clock recovery methods in this embodiment.

[0134] In some embodiments, the electronic device further includes an I / O interface (read / write interface) 603, which is connected between the processor 601 and the memory 602 and enables information interaction between the memory 602 and the processor 601. The I / O interface 603 includes, but is not limited to, a data bus.

[0135] Among them, the processor is a device with data processing capabilities, including but not limited to the central processing unit (CPU); the memory is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and flash memory (FLASH); the I / O interface (read-write interface) is connected between the processor and the memory, enabling information exchange between the memory and the processor, including but not limited to the data bus (Bus).

[0136] Those skilled in the art will understand that all or some of the steps, systems, and devices disclosed above, as functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0137] This disclosure also provides a computer-readable medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements any of the clock recovery methods described in the above embodiments.

[0138] This disclosure also provides a computer program product, which includes a computer program that, when executed by a processor, implements any of the clock recovery methods described in the above embodiments.

[0139] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be executed by several physical components working together.

[0140] Those skilled in the art will understand that all or some of the steps, systems, and devices disclosed above, as functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0141] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be executed by several physical components working together.

[0142] Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technique for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk storage; read-only optical disc (CD-ROM), digital versatile disc (DVD) or other optical disc storage; magnetic cartridges, magnetic tapes, disk storage or other magnetic storage; and any other media that can be used to store desired information and can be accessed by a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0143] This disclosure has disclosed exemplary embodiments, and although specific terminology has been used, it is for general illustrative purposes only and should not be construed as limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A clock recovery method, comprising: The sampling phase deviation is determined based on any one of the demultiplexed subcarriers. The clock-recovered subcarrier signal is obtained based on the sampling phase deviation and the center frequency of the demultiplexed subcarrier.

2. The method according to claim 1, wherein, The process of obtaining the clock-recovered subcarrier signal based on the sampling phase deviation and the center frequency of the demultiplexed subcarrier includes: The frequency domain compensation phase is determined based on the sampling phase deviation and the center frequency of the demultiplexed subcarrier; The clock-recovered subcarrier signal is obtained based on the frequency domain signal of the demultiplexed subcarrier and the frequency domain compensated phase.

3. The method according to claim 2, wherein, The step of determining the frequency domain compensation phase based on the sampling phase deviation and the center frequency of the demultiplexed subcarrier includes: The additional frequency offset compensation phase of the subcarrier is determined based on the sampling phase deviation and the center frequency of the demultiplexed subcarrier; The sampling phase deviation compensation phase is determined based on the sampling phase deviation, sampling rate, and signal block length. The frequency domain compensation phase of the subcarrier is determined based on the sampling phase deviation compensation phase and the additional frequency offset compensation phase of the subcarrier.

4. The method according to claim 1, wherein, The determination of the sampling phase deviation based on any one of the demultiplexed subcarriers includes: A phase detection value is obtained by using a phase detection algorithm based on any one of the demultiplexed subcarriers; The sampling phase deviation is determined based on the phase detection value, and the sampling phase deviation is a sampling phase deviation shared by all subcarrier signals.

5. The method according to claim 4, wherein, The step of obtaining a phase detection value based on any one of the demultiplexed subcarriers using a phase detection algorithm includes: The frequency domain signal of any one of the subcarriers after demultiplexing and before frequency domain phase shift is obtained using a feedforward structure; Based on the frequency domain signal of the subcarrier and the preset signal block length, the phase detection algorithm is used to determine the phase detection vector, and the argument of the phase detection vector is used as the phase detection value.

6. The method according to claim 4, wherein, The step of obtaining a phase detection value based on any one of the demultiplexed subcarriers using a phase detection algorithm includes: The frequency domain signal of any one of the subcarriers after demultiplexing and frequency domain phase shift is obtained using a feedback structure; Based on the frequency domain signal of the subcarrier and the signal block length of the subcarrier, the phase detection algorithm is used to determine the phase detection vector, and the imaginary part of the phase detection vector is used as the phase detection value.

7. The method according to claim 4, wherein, Determining the sampling phase deviation based on the phase detection value includes: The loop filter input value for the current round is determined based on the phase detection value of the current round; the phase detection value for each round is obtained by dividing the subcarrier signal into blocks. Determine the proportional path output value for the current round based on the loop filter input value and the proportional path coefficient of the loop filter. The integral path output value for the current round is determined based on the loop filter input value, the integral path coefficient, and the integral path output value of the previous round; the initial value of the integral path output value is a preset value. The sampling phase deviation for the current round is determined based on the proportional path output value, the integral path output value, and the sampling phase deviation of the previous round. If the difference between the integral path output value of the current round and the integral path output value of the previous round is within a certain range, the sampling phase deviation of the current round is taken as the sampling phase deviation.

8. The method according to claim 7, wherein, The step of determining the loop filter input value for the current round based on the phase detection value of the current round includes: In the case of a feedforward structure, the loop filter input value for the current round is determined based on the phase detection value of the current round and the sampling phase deviation of the previous round. In the case of a feedback structure, the phase detection value of the current round is used as the input value of the loop filter for the current round.

9. The method according to claim 1, wherein, The subcarrier whose sampling phase deviation is determined is the subcarrier located in the middle region among the demultiplexed subcarriers.

10. The method according to claim 1, wherein, After obtaining the clock-recovered subcarrier signal based on the sampling phase deviation and the center frequency of the demultiplexed subcarrier, the method further includes: A frequency offset estimate is calculated based on one of the subcarriers after clock recovery, and the frequency offset estimate is used to compensate for the frequency offset of all subcarriers.

11. An electronic device comprising a memory and a processor; the memory storing a computer program executable by the processor, wherein the computer program, when executed by the processor, implements the clock recovery method according to any one of claims 1 to 10.

12. A computer-readable medium having a computer program stored thereon, which, when executed by a processor, implements the clock recovery method of any one of claims 1 to 10.

13. A computer program product comprising a computer program that, when executed by a processor, implements the clock recovery method according to any one of claims 1 to 10.

Images