Semiconductor device, forming method thereof and storage system

Abstract

The embodiment of the invention provides a semiconductor device, a forming method thereof and a storage system, and the semiconductor device comprises a plurality of conductive wires which extend along a first direction and are arranged at intervals along a second direction; the first direction and the second direction intersect with each other; and a contact structure extending in the third direction and connected to at least a first conductive line of the plurality of conductive lines, the contact structure including a first sub-contact structure connected to the first conductive line and a second sub-contact structure located on the first sub-contact structure; in the second direction, the first size of the first sub-contact structure at the junction is smaller than the second size of the second sub-contact structure at the junction. Wherein the third direction is perpendicular to the first direction and the second direction.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and includes, but is not limited to, a semiconductor device and its formation method, and a memory system. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration. However, as the density and size of semiconductor devices increase, the manufacturing process becomes more difficult, leading to a significant reduction in the performance of the resulting semiconductor devices. Summary of the Invention

[0003] In view of the above, embodiments of the present disclosure provide a semiconductor device and a method for forming the same, as well as a memory system.

[0004] According to a first aspect of the present disclosure, a semiconductor device is provided, comprising: a plurality of conductive lines extending along a first direction and spaced apart along a second direction; the first direction and the second direction intersecting each other; and a contact structure extending along a third direction and at least connected to a first conductive line among the plurality of conductive lines, the contact structure comprising a first sub-contact structure connected to the first conductive line and a second sub-contact structure located on the first sub-contact structure; in the second direction, a first dimension of the first sub-contact structure at the junction of the two is smaller than a second dimension of the second sub-contact structure at the junction of the two; wherein the third direction is perpendicular to both the first direction and the second direction.

[0005] In one alternative embodiment, the dimension of the first sub-contact structure along the second direction is the same as the dimension of the first conductive line along the second direction.

[0006] In one alternative implementation, in the second direction, the size of the first sub-contact structure remains constant along the third direction, while the size of the second sub-contact structure varies along the third direction.

[0007] In one alternative implementation, in the first direction, the third dimension of the first sub-contact structure at the junction of the two is greater than the fourth dimension of the second sub-contact structure at the junction of the two.

[0008] In one alternative implementation, half the difference between the third dimension and the fourth dimension is greater than the dimension of the first sub-contact structure along the third direction.

[0009] In one alternative embodiment, the cross-section of the second sub-contact structure perpendicular to the third direction includes any one of a circle, an ellipse, or a square.

[0010] In one optional embodiment, the semiconductor device further includes: an insulating structure located on the plurality of conductive lines at a position other than where the contact structure contacts the first conductive line; the dimension of the insulating structure along the second direction is the same as the dimension of the conductive line along the second direction; and the surface of the insulating structure that contacts the conductive line and the surface of the first sub-contact structure that contacts the first conductive line are flush.

[0011] In one alternative embodiment, the surface of the insulating structure away from the conductive line is higher than the surface of the first sub-contact structure away from the first conductive line.

[0012] In one alternative embodiment, in the first direction, half the difference between the third dimension of the first sub-contact structure at the junction of the two and the fourth dimension of the second sub-contact structure at the junction of the two is the same as the dimension of the insulating structure along the third direction.

[0013] In one alternative embodiment, the ratio between the dimension of the insulating structure along the third direction and the dimension of the first sub-contact structure along the third direction is in the range of 1.5-5.

[0014] In one optional embodiment, the insulating structure is made of silicon nitride; the size of the insulating structure along the third direction ranges from 40 nm to 60 nm.

[0015] In one alternative embodiment, an air gap is provided between two adjacent conductive lines.

[0016] In one alternative embodiment, the top surface of the air gap is not higher than the top surface of the conductive wire.

[0017] In one alternative embodiment, the ratio of the distance between adjacent conductive lines to the dimension of the air gap along the second direction is in the range of 1.5-2.5.

[0018] In one alternative implementation, the ratio of the second dimension to the first dimension is in the range of 2-5.

[0019] In one alternative embodiment, the second sub-contact structures of the contact structures located on adjacent first conductive lines are offset from each other in the second direction.

[0020] In one alternative embodiment, in the second direction, the distance between the second sub-contact structures of the contact structures located on the spaced first conductive lines is equal to the size of the second sub-contact structures.

[0021] In one alternative embodiment, the dimensions of the second sub-contact structure in the second direction range from 8 nm to 300 nm.

[0022] In one alternative implementation, the conductive line includes at least one of a bit line, a word line, or an interconnect.

[0023] In one alternative embodiment, the semiconductor device further includes: a memory array structure and a peripheral structure connected to the memory array structure; the interconnect is located at the connection between the memory array structure and the peripheral structure.

[0024] According to a second aspect of the present disclosure, a storage system is provided, comprising: at least one semiconductor device as described in any of the first aspects; and a controller configured to control the semiconductor device.

[0025] According to a third aspect of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a plurality of conductive lines extending along a first direction and spaced apart along a second direction, the first direction and the second direction intersecting each other; forming a contact structure extending along a third direction and at least connected to a first conductive line among the plurality of conductive lines; the contact structure comprising a first sub-contact structure connected to the first conductive line and a second sub-contact structure located on the first sub-contact structure; in the second direction, a first dimension of the first sub-contact structure at the junction of the two is smaller than a second dimension of the second sub-contact structure at the junction of the two; wherein the third direction is perpendicular to both the first direction and the second direction.

[0026] In one optional embodiment, forming the plurality of conductive lines includes: sequentially forming a conductive material layer and a patterned mask layer along the third direction; the patterned mask layer includes an insulating structure in contact with the conductive material layer; removing a portion of the conductive material layer using the patterned mask layer to form the conductive lines; removing the portion of the patterned mask layer other than the insulating structure; the dimension of the insulating structure along the second direction is the same as the dimension of the conductive lines along the second direction.

[0027] In one alternative embodiment, forming the contact structure includes: forming a dielectric layer that at least covers the insulating structure; removing a portion of the dielectric layer and a portion of the insulating structure on the first conductive line to form a contact via; and filling the contact via with a conductive material to form a contact structure connecting the first conductive line.

[0028] In one optional embodiment, forming the contact via includes: removing a portion of the dielectric layer to form a first via, the bottom of the first via exposing the surface of the insulating structure on the first conductive line away from the first conductive line and a portion of its sidewall; the surface of the insulating structure in contact with the conductive line is lower than the bottom surface of the first via; along the first via, removing at least a portion of the insulating structure on the first conductive line using wet etching to form a second via, the bottom of the second via exposing the top surface of the first conductive line; the first via and the second via constitute the contact via.

[0029] In an optional embodiment, the method further includes: forming first through holes that are staggered from each other along the second direction on two adjacent first conductive lines.

[0030] In one alternative embodiment, in the second direction, the distance between the first through holes located on the spaced first conductive lines is equal to the size of the first through holes.

[0031] In one alternative embodiment, the dimension of the second through hole along the second direction is the same as the dimension of the conductive line along the second direction.

[0032] In one alternative implementation, in the second direction, the size of the second through hole remains constant along the third third direction, while the size of the first through hole varies along the third third direction.

[0033] In one alternative embodiment, in the second direction, the size of the second through hole is smaller than the size of the first through hole.

[0034] In one alternative implementation, in the first direction, the size of the second through hole is larger than the size of the first through hole.

[0035] In one alternative implementation, in the first direction, half the difference between the size of the second through-hole and the size of the first through-hole is equal to the height of the insulating structure along the third direction.

[0036] In an alternative embodiment, the method further includes forming an air gap between two adjacent conductive lines before forming a contact structure on a first conductive line of the plurality of conductive lines.

[0037] In one alternative embodiment, the etching rates of the insulating structure and the dielectric layer are different.

[0038] The semiconductor device provided in this embodiment removes a portion of the insulating structure on the first conductive line to reserve the formation position of the first sub-contact structure of the contact structure. In the second direction, the first dimension of the first sub-contact structure at the junction of the two is smaller than the second dimension of the second sub-contact structure at the junction of the two. In this way, the alignment accuracy between the contact structure and the first conductive line can be effectively improved, the contact resistance between the contact structure and the first conductive line can be reduced, and the overall resistance of the contact structure can be reduced. In addition, it can also avoid the damage to the air gap between the conductive lines caused by over-etching during the formation of the contact structure, thereby improving the performance of the semiconductor device. Attached Figure Description

[0039] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this disclosure and should not be construed as limiting the scope of this disclosure.

[0040] Figure 1 This is a cross-sectional schematic diagram of the main process steps in forming a semiconductor device according to an embodiment of the present disclosure. Figure 1 ;

[0041] Figure 2 This is a cross-sectional schematic diagram of the main process steps in forming a semiconductor device according to an embodiment of the present disclosure. Figure 2 ;

[0042] Figure 3 A schematic diagram illustrating the specific implementation flow of a method for forming a semiconductor device according to another embodiment of this disclosure;

[0043] Figure 4 A cross-sectional schematic diagram of the process of forming a semiconductor device according to another embodiment of this disclosure. Figure 1 ;

[0044] Figure 5A A cross-sectional schematic diagram of the process of forming a semiconductor device according to another embodiment of this disclosure. Figure 2 ;

[0045] Figure 5B To and Figure 5A Corresponding top view diagram;

[0046] Figure 6A A cross-sectional schematic diagram of the process of forming a semiconductor device according to another embodiment of this disclosure. Figure 3 ;

[0047] Figure 6B To and Figure 6A Corresponding top view diagram;

[0048] Figure 7A A cross-sectional schematic diagram of the process of forming a semiconductor device according to another embodiment of this disclosure. Figure 4 ;

[0049] Figure 7B To and Figure 7A Corresponding top view diagram;

[0050] Figure 8A Fifthly, a cross-sectional schematic diagram of the process of forming a semiconductor device according to another embodiment of this disclosure;

[0051] Figure 8B To and Figure 8A Corresponding top view diagram;

[0052] Figure 9A Sixth schematic cross-sectional view of the process of forming a semiconductor device according to another embodiment of this disclosure;

[0053] Figure 9B To and Figure 9A Corresponding cross-sectional diagram seven;

[0054] Figure 9C and Figure 9A Corresponding side view diagram;

[0055] Figure 10A Eighth schematic cross-sectional view of the process of forming a semiconductor device according to another embodiment of this disclosure;

[0056] Figure 10B for Figure 10A Enlarged view of region A in the middle;

[0057] Figure 10C To and Figure 10A Corresponding sectional view diagram nine;

[0058] Figure 10D for Figure 10C Enlarged view of region B in the middle;

[0059] Figure 10E To and Figure 10A Corresponding top view diagram;

[0060] Figure 11 This is a schematic diagram of an exemplary system having a storage system according to an embodiment of the present disclosure;

[0061] Figure 12A This is a schematic diagram of an exemplary memory card having a storage system according to an embodiment of this application;

[0062] Figure 12B This is a schematic diagram of an exemplary solid-state drive with a storage system according to an embodiment of this application. Detailed Implementation

[0063] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0064] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise scale, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0065] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “below” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0066] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0067] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0068] The manufacture of semiconductor devices involves a series of processes. Traditionally, these processes are divided into two main sub-processes: front-end of line (FEOL) and back-end of line (BEOL). Back-end of line processes include the formation of various conductive interconnect structures (such as copper interconnects), which are crucial for achieving electrical connections between semiconductor devices. However, as the critical dimension (CD) of semiconductor devices shrinks, defects are more likely to occur during the formation of conductive interconnect structures in back-end of line processes, leading to poor reliability and failure to meet requirements.

[0069] Figure 1 and Figure 2 This is a cross-sectional schematic diagram of the main process steps in forming a semiconductor device according to an embodiment of the present disclosure. The following is in conjunction with... Figure 1 and Figure 2 A method for forming a semiconductor device according to this embodiment is described.

[0070] like Figure 1 As shown, multiple conductive lines 102 extending along a first direction and spaced apart along a second direction are formed; a first dielectric layer 101 is disposed between the multiple conductive lines 102; and a second dielectric layer 103 is formed on the conductive lines 102 and the first dielectric layer 101.

[0071] In some embodiments, an air gap 104 is provided between adjacent conductive lines 102, which can improve the resistive-capacitive delay (RCDelay) between conductive lines since the dielectric constant of air is much lower than that of oxides.

[0072] like Figure 2 As shown, a contact hole is formed in the second dielectric layer 103. Figure 2 (Not shown), a contact structure 105 extending in a third direction is formed by filling the contact hole with conductive material.

[0073] It should be noted that, here and below, the first direction can be the direction in which the conductive lines extend, the second direction can be the direction in which the conductive lines are spaced apart, and the third direction can be the direction in which the contact structure extends. The third direction is parallel to the thickness direction of the first dielectric layer, and both the first and second directions are perpendicular to the third direction. The first and second directions intersect each other; in some specific embodiments, the first direction is perpendicular to the second direction. For example, the first direction can be the extension direction of the x-axis shown in the figures, the second direction can be the extension direction of the y-axis shown in the figures, and the third direction can be the extension direction of the z-axis shown in the figures.

[0074] As critical dimensions in semiconductor processes shrink, the etching of contact holes may become misaligned. Specifically, the contact hole may be partially etched to the conductive line 102, while another part may be etched into the first dielectric layer 103 between the conductive lines 102, thereby disrupting the air gap 104 of the first dielectric layer 103 between the conductive lines 102 and affecting the performance of the semiconductor device.

[0075] Based on this, the present disclosure provides a method for forming a semiconductor device. Figure 3 This is a schematic diagram illustrating a specific implementation flow of a method for forming a semiconductor device according to another embodiment of this disclosure. For example... Figure 3 As shown, the specific steps of the method for forming this semiconductor device include:

[0076] Step S10: Form multiple conductive lines, which extend along a first direction and are spaced apart along a second direction, with the first and second directions intersecting each other;

[0077] Step S20: Form a contact structure extending along a third direction and connected to at least one of the multiple conductive lines, including a first conductive line; the contact structure includes a first sub-contact structure connected to the first conductive line and a second sub-contact structure located on the first sub-contact structure; in a second direction, the first dimension of the first sub-contact structure at the junction of the two is smaller than the second dimension of the second sub-contact structure at the junction of the two; wherein the third direction is perpendicular to both the first and second directions.

[0078] Please refer to the following. Figures 4 to 10E The process of forming a semiconductor device according to another embodiment of the present disclosure will be further described in detail.

[0079] refer to Figures 4 to 6B Step S10 is executed to form multiple conductive lines.

[0080] like Figure 4 As shown, a substrate 400 is provided, on which a conductive material layer 401', an insulating material layer 402', and a mask material layer are sequentially formed along a third direction. Exemplarily, the substrate 400 can be a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc. It can also be a substrate including other elemental semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (e.g., a gallium nitride substrate or a gallium arsenide substrate), or a stacked structure, such as Si / SiGe, etc., or other epitaxial structures, such as silicon-germanium-on-insulator (SGOI), etc.

[0081] In some embodiments, the process of forming the conductive material layer 401', the insulating material layer 402' and the mask material layer may include any process known in the art, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, and atomic layer deposition (ALD).

[0082] In some embodiments, the material of the conductive material layer 401' includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), gold (Au), silver (Ag), nickel (Ni), etc.

[0083] In some embodiments, the material of the insulating layer 402' includes, but is not limited to, silicon nitride.

[0084] In some embodiments, the mask material layer comprises one or more of photoresist (PR), silicon oxynitride (SiON), and hard mask (HM). For example, as... Figure 4 As shown, the mask material layer includes a hard mask layer 403', a silicon oxynitride material layer 404', and a photoresist layer 405, wherein the photoresist layer 405 has an opening.

[0085] In some embodiments, forming multiple conductive lines includes: sequentially forming a conductive material layer and a patterned mask layer along a third direction; the patterned mask layer includes an insulating structure in contact with the conductive material layer; removing a portion of the conductive material layer using the patterned mask layer to form conductive lines; removing the portion of the patterned mask layer other than the insulating structure; the dimension of the insulating structure along a second direction is the same as the dimension of the conductive lines along the second direction.

[0086] refer to Figure 5A and Figure 5B and combined Figure 4 Through the opening in the photoresist 405, a portion of the insulating material layer 402' and the mask material layer are removed along a third direction to form a patterned mask layer 406. The patterned mask layer 406 includes an insulating structure 402 in contact with the conductive material layer 401', a hard mask 403, a silicon oxynitride layer 404, and photoresist 405. The patterned mask layer 406 exposes a portion of the top surface of the conductive material layer 401'.

[0087] refer to Figure 6A and Figure 6BA patterned mask layer is used to remove part of the conductive material layer, forming multiple conductive lines 401. These conductive lines 401 extend along a first direction and are spaced apart along a second direction, with the first and second directions intersecting each other. The portion of the patterned mask layer, excluding the insulating structure 402, is removed. Since the insulating structure 402 and the conductive lines 401 are formed using the same patterned mask layer, the insulating structure 402 also extends along the first direction and is spaced apart along the second direction. Specifically, the dimensions of the insulating structure 402 along the second direction are the same as the dimensions of the conductive lines 401 along the second direction.

[0088] refer to Figures 7A to 10E Step S20 is executed to form a contact structure that extends along a third direction and is at least connected to the first conductive line among the plurality of conductive lines.

[0089] In some embodiments, forming a contact structure includes: forming a dielectric layer that at least covers an insulating structure; removing a portion of the dielectric layer and a portion of the insulating structure on a first conductive line to form a contact via; and filling the contact via with a conductive material to form a contact structure connecting the first conductive line.

[0090] refer to Figure 7A and Figure 7B A dielectric layer 409 is formed that at least covers the insulating structure 402. In some embodiments, a hard mask layer 403', a silicon oxynitride material layer 404', and a photoresist 407 are sequentially formed on the dielectric layer 409, wherein the photoresist 407 has an opening 408, the size of the opening 408 in the second direction being larger than the size of the insulating structure 402 in the second direction.

[0091] It should be noted that, Figure 7A for Figure 7B The cross-sectional view shown in the diagram along the tangent AA' is intended to visually illustrate the positional relationship between the opening 408 and the insulating structure 402. Figure 7B for Figure 7A The top view of opening 408, insulation structure 402 and base 400 is shown only after omitting other structures.

[0092] In some embodiments, such as Figure 7A As shown, an air gap 410 is formed between two adjacent conductive lines to reduce the capacitance between the conductive lines.

[0093] In some embodiments, such as Figure 7A and Figure 7B As shown, the photoresist above the first conductive line of the multiple conductive lines 401 has an opening 408 corresponding to the first conductive line.

[0094] In some embodiments, such as Figure 7BAs shown, the openings 408 of the photoresist located on adjacent first conductive lines are staggered in the second direction.

[0095] refer to Figures 8A to 8B In some embodiments, forming a contact via includes: removing a portion of the dielectric layer 409 to form a first via 411, the bottom of the first via 411 exposing the surface of the insulating structure 402 on the first conductive wire away from the first conductive wire and a portion of the sidewall; the surface of the insulating structure 402 in contact with the conductive wire 401 is lower than the bottom surface of the first via 411.

[0096] It should be noted that, Figure 8A for Figure 8B The cross-sectional view shown in the diagram along the tangent AA' is intended to visually illustrate the positional relationship between the first through hole 411 and the insulating structure 402. Figure 8B for Figure 8A The top view of the first through hole 411, the insulating structure 402 and the dielectric layer 409 is shown after omitting other structures, and the dielectric layer 409 is presented in a perspective manner.

[0097] In some embodiments, such as Figure 8B As shown, forming a contact via also includes: between two adjacent first conductive lines ( Figure 8B On the first conductive line (not shown), first through holes 411 are formed that are staggered with each other along the second direction. In this way, the problem of short circuits between the first conductive lines in subsequent processes caused by the first through holes 411 located on two adjacent first conductive lines being connected to each other can be avoided in the second direction, thus maintaining the performance of the semiconductor device.

[0098] In some embodiments, in the second direction, the distance between the first through holes located on the spaced first conductive lines is equal to the size of the first through holes. In some embodiments, the size of the first through holes remains constant in the third direction along the first / second direction.

[0099] In other embodiments, due to the large depth-to-width ratio of the first via 411, insufficient etching sources reach the bottom during the formation of the first via 411. The reduced reactant concentration leads to a decrease in the reaction rate at the bottom region of the first via 411. Therefore, when etching the dielectric layer 409 from top to bottom, the formed first via 411 will be an inverted trapezoidal shape, wider at the top and narrower at the bottom. Thus, as... Figure 8A As shown, in the second direction, the size of the first through hole 411 changes along the third direction. Specifically, in the second direction, the size of the first through hole 411 gradually decreases from top to bottom. Here, the size D2 of the first through hole 411 in the second direction refers to the top size of the first through hole 411 in the second direction.

[0100] like Figure 8A and Figure 8B As shown, in some embodiments, in the second direction, the distance D1 between the first through holes 411 located on the spaced first conductive lines is equal to the size D2 of the first through holes 411.

[0101] In this way, a larger first through hole can be formed to reduce the contact resistance in subsequent processes, and in the second direction, the risk of short circuit in subsequent processes caused by the first through holes located on the spaced first conductive lines being connected can be avoided.

[0102] In some embodiments, D1 and D2 are both in the range of 8nm to 300nm. More specifically, D1 and D2 can be 8nm, 50nm, 100nm, 150nm, 200nm, 250nm or 300nm.

[0103] refer to Figure 9A , Figure 9B and Figure 9C In some embodiments, forming a contact via further includes: along the first via 411, using wet etching to remove at least a portion of the insulating structure 402 on the first conductive line 401-1 to form a second via 412, the bottom of the second via 412 exposing the top surface of the first conductive line 401-1 among the plurality of conductive lines 401; the first via 411 and the second via 412 constitute a contact via 413.

[0104] It is understandable that the second conductive line 401-2 is not exposed by the second through hole 412 among the multiple conductive lines 401.

[0105] It should be noted that, Figure 9A for Figure 9C The cross-sectional view shown is along the tangent AA' direction. Figure 9B for Figure 9C The cross-sectional view shown in the diagram along the tangent BB' direction is intended to visually illustrate the positional relationship between the first through hole 411 and the insulating structure 402. Figure 9C for Figure 9A The top view of the first through hole 411, the second through hole 412, the insulating structure 402, the conductive line and the dielectric layer 409 is shown after omitting other structures, and the dielectric layer 409 is presented in a perspective manner.

[0106] In this embodiment of the disclosure, Figure 9A and Figure 9B The dashed line shown in the contact via 413 is only used to distinguish the first via 411 and the second via 412 of the contact via 413. It should be emphasized that this dashed line does not exist in actual semiconductor devices.

[0107] Since the second through hole 412 is formed at the location where the partial insulation structure 402 on the first conductive line 401-1 is removed, the second through hole 412 has the same morphology as the removed partial insulation structure 402.

[0108] In some embodiments, reference Figures 9A to 9C The dimension D3 of the second through hole 412 along the second direction is the same as the dimension of the conductive line (e.g., the first conductive line 401-1) along the second direction.

[0109] In some embodiments, such as Figure 9A and Figure 9B As shown, the dimension of the second through hole 412 along the third direction is the same as the dimension D6 of the insulating structure 402 in the third direction.

[0110] In some embodiments, the second through-hole 412 formed by wet etching to remove part of the insulating structure 402 has uniform and vertical sidewalls, such as... Figure 9A and Figure 9B As shown, in the second direction, the size of the second through hole 412 remains unchanged along the third direction.

[0111] In some embodiments, the size of the first through hole remains constant along a third direction in the first / second direction.

[0112] In some embodiments, in the second direction, the size of the second through hole is smaller than the size of the first through hole.

[0113] In some embodiments, in the first direction, the size of the second through hole is larger than the size of the first through hole.

[0114] In some embodiments, the size of the first through-hole varies along the first / second direction in the third direction; exemplarily, the first through-hole is an inverted trapezoid that is wider at the top and narrower at the bottom. It is understood that the size of the first through-hole gradually decreases from top to bottom in the first / second direction, and the size of the first through-hole in the first / second direction refers to the size of the top of the first through-hole.

[0115] like Figure 9A and Figure 9C As shown, in some embodiments, in the second direction, the size D3 of the second through hole 412 is smaller than the size D2 of the first through hole 411.

[0116] In some embodiments, when a second through-hole 412 is formed by wet etching to remove a portion of the insulating structure 402 on at least the first conductive line 401-1 along the first through-hole 411, due to the isotropic nature of wet etching, the etching solution will act uniformly on the material surface, that is, the etching effect from the etching solution on the insulating structure 402 is uniform, so a portion of the insulating structure 402 will also be removed in its extension direction (first direction).

[0117] like Figure 9B and Figure 9C As shown, in some embodiments, in the first direction, the size D5 of the second through hole 412 is larger than the size D4 of the first through hole 411.

[0118] like Figure 9B and Figure 9C In some embodiments, in the first direction, half the difference between the size D5 of the second through hole 412 and the size D4 of the first through hole 411 is equal to the height D6 of the insulating structure 402 in the third direction.

[0119] In some embodiments, the etching rates of the insulating structure 402 and the dielectric layer 409 are different. When a portion of the dielectric layer 409 is removed to form the first via 411, the insulating structure 402 can serve as a stop layer to control the depth of the first via 411.

[0120] For example, the insulating structure is made of silicon nitride, and the dielectric layer 409 is made of tetraethyl orthosilicate (TEOS).

[0121] Furthermore, since the insulation structure 402 has a certain thickness in the third direction, even if... Figure 8A As shown, when the first through hole 411 is formed, over etching occurs, and the bottom surface of the first through hole 411 will also be higher than the bottom surface of the insulating structure 402 in contact with the conductive line 401. Therefore, the conductive line 401 below the insulating structure 402 can be protected from damage, and further, the air gap 410 between adjacent conductive lines 401 can be avoided.

[0122] It should be noted that the thickness of the insulation structure in the third direction is greater than the depth of over-etching of the dielectric layer. The thickness of the insulation structure in the third direction can be set according to actual needs.

[0123] refer to Figures 10A to 10E The formation of the contact structure includes filling the contact through hole with conductive material to form a contact structure 416 connecting the first conductive line 401-1.

[0124] It should be noted that, Figure 10A for Figure 10E The cross-sectional view shown is along the tangent AA' direction. Figure 10C for Figure 10E The schematic cross-sectional view shown is along the tangent BB' direction. Figure 10B for Figure 10A An enlarged schematic diagram of region A in the middle. Figure 10D for Figure 10C An enlarged schematic diagram of region B. This is to facilitate a clear and intuitive description of the positional relationship between contact structure 416 and insulation structure 402. Figure 10E for Figure 10A The top view of the contact structure 416, the insulation structure 402 and the dielectric layer 409 is shown after omitting other structures, and the dielectric layer 409 is presented in a perspective manner.

[0125] In some embodiments, the conductive material includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), gold (Au), silver (Ag), nickel (Ni), etc.

[0126] In some embodiments, such as Figure 10A and Figure 10B As shown, the contact structure 416 includes a first sub-contact structure 415 connected to the first conductive line 401-1 and a second sub-contact structure 414 located on the first sub-contact structure 415; in the second direction, the first dimension W1 of the first sub-contact structure 415 at the junction of the two is smaller than the second dimension W2 of the second sub-contact structure 414 at the junction of the two.

[0127] In some implementations, the dimension of the second sub-contact structure remains unchanged in the second direction. For example, in the second direction, the second dimension of the second sub-contact structure at the junction of the two is the same as the dimension of the top of the second sub-contact structure.

[0128] In other embodiments, in the second direction, such as Figure 10A and Figure 10B The second dimension W2 of the second sub-contact structure shown is smaller than the dimension W3 of the top of the second sub-contact structure at the junction of the two.

[0129] It should be noted that the first sub-contact structure 415 is formed in Figure 9A and Figure 9B In the first region of the second through hole 412 shown, the second sub-contact structure 414 is formed in the first through hole 411 and Figure 9A and Figure 9B In the second region of the second through hole 412 shown, the first region and the second region together constitute the second through hole 412.

[0130] In some implementations, the dimension D7 of the first sub-contact structure 415 in the third direction is smaller than the dimension D6 of the insulating structure 402 in the third direction.

[0131] In this embodiment, by removing part of the insulation structure on the first conductive line to reserve the formation position of the first sub-contact structure of the contact structure, and forming the first sub-contact structure at the reserved position, the alignment accuracy between the contact structure and the first conductive line can be effectively improved, avoiding the problem of short circuit between adjacent conductive lines caused by excessive deviation of the contact structure relative to the first conductive line, reducing the contact resistance between the contact structure and the first conductive line, and avoiding the damage to the air gap between the conductive lines caused by over-etching during the formation of the contact structure, thus improving the performance of the semiconductor device.

[0132] This disclosure also provides a semiconductor device, with reference to... Figures 10A to 10E The semiconductor device includes: a plurality of conductive lines 401 extending along a first direction and spaced apart along a second direction; the first direction and the second direction intersect each other; and a contact structure 416 extending along a third direction and at least connected to a first conductive line 401-1 among the plurality of conductive lines 401. The contact structure 416 includes a first sub-contact structure 415 connected to the first conductive line 401-1 and a second sub-contact structure 414 located on the first sub-contact structure 415. In the second direction, a first dimension W1 of the first sub-contact structure 415 at the junction of the two is smaller than a second dimension W2 of the second sub-contact structure 414 at the junction of the two. In this way, the contact area between the first sub-contact structure 415 and the second sub-contact structure can be increased, and the contact resistance can be reduced. The third direction is perpendicular to both the first direction and the second direction.

[0133] In some embodiments, the larger size of the second sub-contact structure compared to the first sub-contact structure helps to reduce the overall resistance of the contact structure.

[0134] In some embodiments, such as Figure 10A As shown, the semiconductor device also includes a substrate 400, on which multiple conductive lines 401 are located. Exemplarily, the substrate 400 can be a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon carbide substrate, silicon-on-insulator (substrate or germanium-on-insulator substrate, etc.), or a substrate including other elemental semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (e.g., gallium nitride substrate or gallium arsenide substrate, etc.), or a stacked structure, such as Si / SiGe, or other epitaxial structures, such as germanium-silicon-on-insulator, etc.

[0135] It should be noted that, in combination Figure 10A and Figure 10E The first conductive wire 401-1 among the multiple conductive wires 401 has a contact structure, while the second conductive wire 401-2 among the multiple conductive wires 401 does not have a contact structure. Both the first conductive wire 401-1 and the second conductive wire 401-2 can be referred to as conductive wires. Because... Figure 10A for Figure 10E The schematic cross-sectional view shown is along the tangent AA' direction, therefore in Figure 10A The image only shows the contact structure 416 on one of the first conductive lines 401-1. In fact, the two adjacent first conductive lines 401-1 also have contact structures 416.

[0136] like Figure 10B As shown, in some embodiments, the ratio of the second dimension W2 to the first dimension W1 ranges from 2 to 5. More specifically, the ratio of the second dimension W2 to the first dimension W1 is 2, 3, 4, or 5.

[0137] like Figures 10A to 10E As shown, in some embodiments, the semiconductor device further includes: an insulating structure 402 located on the plurality of conductive lines 401 at a position other than where the contact structure 416 contacts the first conductive line 401-1; the dimension of the insulating structure 402 along the second direction is the same as the dimension of the conductive lines 401 along the second direction; the surface of the insulating structure 402 that contacts the conductive line 401 and the surface of the first sub-contact structure 415 that contacts the first conductive line 401-1 are flush.

[0138] In some embodiments, a second through hole is formed by removing a portion of the insulation structure 402 on the first conductive wire 401-1, and a first sub-contact structure 415 is formed in a portion of the second through hole. The dimensions of the first sub-contact structure 415 along the second direction are the same as the dimensions of the insulation structure 402 along the second direction.

[0139] Since the insulating structure 402 and the conductive line 401 are formed through the same patterned mask layer, the dimensions of the insulating structure 402 along the second direction are the same as the dimensions of the conductive line 401 along the second direction. In some specific embodiments, such as... Figure 10E As shown, the orthographic projection of the insulating structure 402 onto the substrate surface intersects with the second conductive line 401-2. Figure 10E (Not shown in the image) The orthographic projections on the substrate surface coincide.

[0140] Furthermore, such as Figure 10A and Figure 10B As shown, in some embodiments, the dimension W1 of the first sub-contact structure 415 along the second direction is the same as the dimension of the conductive line 401 (first conductive line 401-1) along the second direction.

[0141] By reserving a position so that the dimensions of the first sub-contact structure and the first conductive line are the same along the second direction, the alignment accuracy between the contact structure and the first conductive line can be effectively improved, avoiding the problem of short circuit between adjacent conductive lines caused by excessive deviation of the contact structure relative to the first conductive line. At the same time, the contact resistance between the contact structure and the first conductive line is reduced, thus improving the performance of the semiconductor device.

[0142] In some embodiments, in the second direction, the dimensions of the first sub-contact structure remain unchanged along the third direction, and the dimensions of the second sub-contact structure remain unchanged along the third direction.

[0143] In other embodiments, such as Figure 10A and Figure 10B As shown, in some embodiments, in the second direction, the size of the first sub-contact structure 415 remains constant along the third direction, while the size of the second sub-contact structure 414 changes along the third direction. The size of the second sub-contact structure 414 decreases from top to bottom along the third direction. In the second direction, the size W3 of the second sub-contact structure 414 refers to the top size of the second sub-contact structure.

[0144] like Figure 10D and Figure 10E As shown, in some embodiments, in the first direction, the third dimension W5 of the first sub-contact structure 415 is larger than the fourth dimension W4 of the second sub-contact structure. The fourth dimension W4 of the second sub-contact structure refers to the top dimension of the second sub-contact structure in the first direction.

[0145] like Figure 10D and Figure 10E As shown, in some embodiments, half the difference between the third dimension W5 and the fourth dimension W4 is greater than the dimension D7 of the first sub-contact structure 415 along the third direction.

[0146] In some embodiments, the cross-section of the second sub-contact structure 414 perpendicular to a third direction includes any one of a circle, an ellipse, or a square.

[0147] In some embodiments, the surface of the insulating structure 402 away from the conductive line 401 is higher than the surface of the first sub-contact structure 415 away from the first conductive line 401-1.

[0148] In some embodiments, in a first direction, half the difference between the third dimension W5 of the first sub-contact structure 415 and the fourth dimension W4 of the second sub-contact structure 414 is the same as the dimension of the insulating structure 402 along the third direction.

[0149] like Figure 10D As shown, in some embodiments, the ratio between the dimension D6 of the insulating structure 402 along the third direction and the dimension D7 of the first sub-contact structure 415 along the third direction ranges from 1.5 to 5. More specifically, the ratio between the dimension D6 of the insulating structure 402 along the third direction and the dimension D7 of the first sub-contact structure 415 along the third direction is 1.5, 2, 2.5, 3, 3.5, 4, 4.5, or 5.

[0150] Because the insulating structure 402 has a certain thickness in the third direction, it can prevent over-etching when forming a contact structure. The bottom surface of the second sub-contact structure 414 is higher than the bottom surface of the insulating structure 402 that contacts the conductive line 401, and the top surface of the insulating structure 402 (the surface of the insulating structure 402 away from the conductive line 401) is higher than the top surface of the first sub-contact structure 415 (the surface of the first sub-contact structure 415 away from the first conductive line 401-1). Therefore, the conductive line 401 below the insulating structure 402 can be protected from damage.

[0151] In some embodiments, the insulating structure 402 is made of silicon nitride; the dimension D6 of the insulating structure 402 along the third direction ranges from 40 nm to 60 nm. More specifically, the dimension D6 of the insulating structure 402 along the third direction is 40 nm, 50 nm, or 60 nm.

[0152] In some embodiments, such as Figure 10A and Figure 10B As shown, an air gap 410 is provided between two adjacent conductive lines 401 to reduce the capacitance between the conductive lines 401.

[0153] In some embodiments, such as Figure 10B As shown, the top surface of the air gap 410 is not higher than the top surface of the conductive line 401. Since the surfaces of the insulating structure 402 and the conductive line 401 in contact with each other, and the surfaces of the first sub-contact structure 415 and the first conductive line 401-1 in contact with each other, and the top surface of the air gap 410 is not higher than the top surface of the conductive line 401, the first sub-contact structure 415 will not damage the air gap 410, thereby improving the performance of the semiconductor device.

[0154] In some embodiments, such as Figure 10B As shown, the ratio of the distance between adjacent conductive lines 401 to the dimension of the air gap 410 along the second direction ranges from 1.5 to 2.5. More specifically, the ratio of the distance between adjacent conductive lines 401 to the dimension of the air gap 410 along the second direction is 1.5, 2, or 2.5. By appropriately setting the size of the air gap according to the distance between adjacent conductive lines, the capacitance between the conductive lines can be reduced to the greatest extent.

[0155] In some embodiments, the second sub-contact structures of the contact structures located on adjacent first conductive lines are offset from each other in a second direction. For example, as... Figure 10E As shown, the second sub-contact structures of the contact structures located on adjacent first conductive lines 401-1 are staggered in the second direction. This avoids the problem of short circuits between the first conductive lines caused by the second sub-contact structures on adjacent first conductive lines connecting to each other in the second direction.

[0156] In some embodiments, in the second direction, the distance between the second sub-contact structures of the contact structures located on the spaced first conductive lines is equal to the size of the second sub-contact structures. For example, as... Figure 10E As shown, in the second direction, the distance W6 between the second sub-contact structures of the contact structure 416 located on the spaced first conductive line 401-1 is equal to the size W3 of the second sub-contact structure.

[0157] It should be noted that, in the second direction, the dimension W3 of the second sub-contact structure refers to the dimension of the top of the second sub-contact structure along the third direction.

[0158] In this way, a larger second sub-contact structure can be formed to reduce contact resistance, and the risk of short circuit caused by the connection between the second sub-contact structures located on the spaced first conductive line can be avoided in the second direction.

[0159] In other embodiments, such as Figure 10A and Figure 10B As shown, in the second direction, the size of the second sub-contact structure 414 decreases from top to bottom along the third direction, that is, the size W3 of the second sub-contact structure 414 in the second direction is the maximum size of the second sub-contact structure.

[0160] In some embodiments, the dimensions of the second sub-contact structure 414 in the second direction range from 8 nm to 300 nm. More specifically, the dimensions of the second sub-contact structure 414 in the second direction are 8 nm, 100 nm, 150 nm, 200 nm, 250 nm, or 300 nm.

[0161] In some embodiments, the conductive line includes at least one of a bit line, a word line, or an interconnect.

[0162] In some embodiments, the semiconductor device further includes: a memory array structure and a peripheral structure connected to the memory array structure; interconnects are located at the connection points between the memory array structure and the peripheral structure. In some embodiments, the semiconductor device may be a memory or a part of a memory, including but not limited to NAND flash memory.

[0163] The semiconductor device provided in this embodiment removes a portion of the insulating structure on the first conductive line to reserve the formation position of the first sub-contact structure of the contact structure. In the second direction, the first dimension of the first sub-contact structure at the junction of the two is smaller than the second dimension of the second sub-contact structure at the junction of the two. In this way, the alignment accuracy between the contact structure and the first conductive line can be effectively improved, the contact resistance between the contact structure and the first conductive line can be reduced, and the overall resistance of the contact structure can be reduced. In addition, it can also avoid the damage to the air gap between the conductive lines caused by over-etching during the formation of the contact structure, thereby improving the performance of the semiconductor device.

[0164] According to a third aspect of the present disclosure, a storage system is provided, comprising: at least one semiconductor device as described in the foregoing embodiments; and a controller configured to control the semiconductor device.

[0165] Here, a semiconductor device can be a memory or a part of a memory. The following explanation uses a semiconductor device as an example of a memory.

[0166] Figure 11 A block diagram of an exemplary system 1000 having memory according to some aspects of the disclosure is shown. System 1000 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 11 As shown, system 1000 may include a host 1008 and a memory system 1002, the memory system 1002 having one or more memories 1004 and a controller 1006. The host 1008 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 1008 may be configured to send data to or receive data from the memory 1004.

[0167] According to some embodiments, controller 1006 is coupled to memory 1004 and host 1008 and is configured to control memory 1004. Controller 1006 can manage data stored in memory 1004 and communicate with host 1008. In some embodiments, controller 1006 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0168] In some implementations, the controller 1006 is designed to operate in a high duty cycle environment in a solid-state drive (SSD) or an embedded multimedia card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0169] The controller 1006 can be configured to control operations of the memory 1004, such as read, erase, and program operations. The controller 1006 can also be configured to manage various functions relating to data stored or to be stored in the memory 1004, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the controller 1006 is also configured to process error correction codes relating to data read from or written to the memory 1004.

[0170] Controller 1006 can also perform any other suitable function, such as formatting memory 1004. Controller 1006 can communicate with external devices (e.g., host 1008) according to a specific communication protocol. For example, controller 1006 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0171] The controller 1006 and one or more memories 1004 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the storage system 1002 can be implemented and packaged into different types of end electronic products.

[0172] In such Figure 12A In one example shown, controller 1006 and a single memory 1004 can be integrated into memory card 202. Memory card 202 may include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. Memory card 202 may also include a connection between memory card 202 and a host (e.g., Figure 11 The memory card connector 204 is coupled to the host 1008.

[0173] In such Figure 12B In another example shown, controller 1006 and multiple memories 1004 can be integrated into SSD 206. SSD 206 may also include interfaces for connecting SSD 206 to a host computer (e.g., Figure 11The SSD connector 208 is coupled to the host 1008. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0174] It should be understood that the phrases "an embodiment" or "some embodiments" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "in an embodiment" or "in some embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0175] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: Multiple conductive lines extend along a first direction and are spaced apart along a second direction; The first direction and the second direction intersect each other; as well as A contact structure extends along a third direction and is at least connected to a first conductive line among the plurality of conductive lines. The contact structure includes a first sub-contact structure connected to the first conductive line and a second sub-contact structure located on the first sub-contact structure. In the second direction, a first dimension of the first sub-contact structure at its junction is smaller than a second dimension of the second sub-contact structure at its junction. The third direction is perpendicular to both the first direction and the second direction.

2. The semiconductor device according to claim 1, characterized in that, The dimension of the first sub-contact structure along the second direction is the same as the dimension of the first conductive line along the second direction.

3. The semiconductor device according to claim 1, characterized in that, In the second direction, the size of the first sub-contact structure remains constant along the third direction, while the size of the second sub-contact structure varies along the third direction.

4. The semiconductor device according to claim 1, characterized in that, In the first direction, the third dimension of the first sub-contact structure is larger than the fourth dimension of the second sub-contact structure.

5. The semiconductor device according to claim 4, characterized in that, Half the difference between the third dimension and the fourth dimension is greater than the dimension of the first sub-contact structure along the third direction.

6. The semiconductor device according to claim 1, characterized in that, The cross-section of the second sub-contact structure perpendicular to the third direction includes any one of a circle, an ellipse, or a square.

7. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: An insulating structure is located on the plurality of conductive lines at a position other than where the contact structure contacts the first conductive line; the dimension of the insulating structure along the second direction is the same as the dimension of the conductive line along the second direction; the surface of the insulating structure that contacts the conductive line and the surface of the first sub-contact structure that contacts the first conductive line are flush.

8. The semiconductor device according to claim 7, characterized in that, The surface of the insulating structure away from the conductive line is higher than the surface of the first sub-contact structure away from the first conductive line.

9. The semiconductor device according to claim 8, characterized in that, In the first direction, half the difference between the third dimension of the first sub-contact structure and the fourth dimension of the second sub-contact structure is the same as the dimension of the insulating structure along the third direction.

10. The semiconductor device according to claim 8, characterized in that, The ratio between the dimension of the insulating structure along the third direction and the dimension of the first sub-contact structure along the third direction is in the range of 1.5-5.

11. The semiconductor device according to claim 10, characterized in that, The insulating structure is made of silicon nitride; the size of the insulating structure along the third direction ranges from 40 nm to 60 nm.

12. The semiconductor device according to claim 1, characterized in that, An air gap is provided between two adjacent conductive lines.

13. The semiconductor device according to claim 12, characterized in that, The top surface of the air gap is not higher than the top surface of the conductive wire.

14. The semiconductor device according to claim 12, characterized in that, The ratio of the distance between adjacent conductive lines to the dimension of the air gap along the second direction is in the range of 1.5-2.

5.

15. The semiconductor device according to claim 1, characterized in that, The ratio of the second dimension to the first dimension is in the range of 2-5.

16. The semiconductor device according to claim 1, characterized in that, The second sub-contact structures of the contact structures located on adjacent first conductive lines are staggered in the second direction.

17. The semiconductor device according to claim 16, characterized in that, In the second direction, the distance between the second sub-contact structures of the contact structures located on the spaced first conductive lines is equal to the size of the second sub-contact structures.

18. The semiconductor device according to claim 17, characterized in that, The dimensions of the second sub-contact structure in the second direction range from 8 nm to 300 nm.

19. The semiconductor device according to claim 1, characterized in that, The conductive lines include at least one of bit lines, word lines, or interconnect lines.

20. The semiconductor device according to claim 19, characterized in that, The semiconductor device further includes: a memory array structure and a peripheral structure connected to the memory array structure; The interconnect is located at the connection between the storage array structure and the peripheral structure.

21. A storage system, characterized in that, include: At least one semiconductor device as described in any one of claims 1 to 20; as well as A controller configured to control the semiconductor device.

22. A method for forming a semiconductor device, characterized in that, include: Multiple conductive lines are formed, which extend along a first direction and are spaced apart along a second direction, wherein the first direction and the second direction intersect each other; A contact structure is formed that extends along a third direction and is at least connected to a first conductive line among the plurality of conductive lines; the contact structure includes a first sub-contact structure connected to the first conductive line and a second sub-contact structure located on the first sub-contact structure; in the second direction, a first dimension of the first sub-contact structure at the junction of the two is smaller than a second dimension of the second sub-contact structure at the junction of the two; wherein the third direction is perpendicular to both the first direction and the second direction.

23. The method for forming a semiconductor device according to claim 22, characterized in that, Forming the plurality of conductive lines includes: A conductive material layer and a patterned mask layer are sequentially formed along the third direction; the patterned mask layer includes an insulating structure in contact with the conductive material layer; The conductive line is formed by removing a portion of the conductive material layer using the patterned mask layer. Remove the portion of the patterned mask layer other than the insulating structure; the dimension of the insulating structure along the second direction is the same as the dimension of the conductive line along the second direction.

24. The method for forming a semiconductor device according to claim 23, characterized in that, Forming the contact structure includes: Form a dielectric layer that at least covers the insulating structure; A portion of the dielectric layer and a portion of the insulating structure on the first conductive line are removed to form a contact via. The contact hole is filled with conductive material to form a contact structure that connects the first conductive wire.

25. The method for forming a semiconductor device according to claim 24, characterized in that, Forming the contact via includes: A portion of the dielectric layer is removed to form a first through-hole, the bottom of which exposes the surface and part of the sidewall of the insulating structure on the first conductive wire away from the first conductive wire; the surface of the insulating structure in contact with the conductive wire is lower than the bottom surface of the first through-hole. Along the first through-hole, at least a portion of the insulating structure on the first conductive line is removed by wet etching to form a second through-hole, the bottom of which exposes the top surface of the first conductive line; the first through-hole and the second through-hole constitute the contact through-hole.

26. The method for forming a semiconductor device according to claim 25, characterized in that, The method further includes: On two adjacent first conductive lines, first through holes are formed that are staggered from each other along the second direction.

27. The method for forming a semiconductor device according to claim 26, characterized in that, In the second direction, the distance between the first through holes located on the spaced first conductive lines is equal to the size of the first through holes.

28. The method for forming a semiconductor device according to claim 25, characterized in that, The dimension of the second through hole along the second direction is the same as the dimension of the conductive line along the second direction.

29. The method for forming a semiconductor device according to claim 25, characterized in that, In the second direction, the size of the second through hole remains constant along the third direction, while the size of the first through hole varies along the third direction.

30. The method for forming a semiconductor device according to claim 25, characterized in that, In the second direction, the size of the second through hole is smaller than the size of the first through hole.

31. The method for forming a semiconductor device according to claim 25, characterized in that, In the first direction, the size of the second through hole is larger than the size of the first through hole.

32. The method for forming a semiconductor device according to claim 31, characterized in that, In the first direction, half the difference between the size of the second through hole and the size of the first through hole is equal to the height of the insulating structure along the third direction.

33. The method for forming a semiconductor device according to claim 22, characterized in that, The method further includes: Before forming a contact structure on the first conductive line among the plurality of conductive lines, an air gap is formed between two adjacent conductive lines.

34. The method for forming a semiconductor device according to claim 24, characterized in that, The etching rates of the insulating structure and the dielectric layer are different.

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