Solar cell and preparation method thereof

Abstract

The invention discloses a solar cell and a preparation method thereof. The solar cell comprises a silicon substrate, a passivation contact structure located on the back face of the silicon substrate and a back face electrode. The passivation contact structure comprises a tunneling layer located on the back face of the silicon substrate, a first doped polycrystalline silicon layer located on the back face of the tunneling layer, a spacer layer located in a grid line area on the back face of the first doped polycrystalline silicon layer and a second doped polycrystalline silicon layer located on the back face of the spacer layer. According to the passivation contact structure, film layers in a grid line area and a non-grid line area are different in thickness, the grid line area is of a four-layer structure, the thickness is large, the grid line area is provided with two doped polycrystalline silicon layers, grid line slurry is prevented from penetrating through the doped polycrystalline silicon layers and damaging a bottom tunneling oxide layer during sintering, and therefore the field passivation effect is guaranteed; the non-grid line area only comprises the tunneling layer and the first doped polycrystalline silicon layer, so that compared with the grid line area, the thickness is greatly reduced, the parasitic absorption of light on the back surface is reduced, and the photoelectric efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of photovoltaics, and more particularly to a solar cell and its preparation method. Background Technology

[0002] TOPCon (Tunnel Oxide Passivated Contact) solar cells use a tunneling layer and a doped polycrystalline silicon layer on the back to form a passivated contact structure, achieving field passivation, reducing contact resistance, and increasing the cell's open-circuit voltage and short-circuit current, thereby improving the cell's conversion efficiency.

[0003] However, the thickness of the polycrystalline silicon layer doped on the back is between 100nm and 150nm, which affects the absorption of light on the back and thus affects the battery efficiency.

[0004] In view of this, it is necessary to provide an improved solar cell and its fabrication method to solve the above-mentioned technical problems. Summary of the Invention

[0005] This invention provides a solar cell and its preparation method, which helps to improve the passivation effect on the back of the cell, increase light utilization, and thus improve the cell efficiency.

[0006] To achieve one of the above-mentioned objectives, the present invention adopts the following technical solution:

[0007] A solar cell includes a silicon substrate, a passivation contact structure on the back side of the silicon substrate, and a back electrode on the back side of the passivation contact structure; the passivation contact structure includes a tunneling layer on the back side of the silicon substrate, a first doped polycrystalline silicon layer on the back side of the tunneling layer, a spacer layer on the back side of the first doped polycrystalline silicon layer, and a second doped polycrystalline silicon layer on the back side of the spacer layer, wherein the spacer layer is located in the gate line region of the first doped polycrystalline silicon layer.

[0008] Optionally, the spacer layer is selected from one or more of the following stacked films: silicon oxide layer or silicon oxynitride layer.

[0009] Optionally, the thickness of the spacer layer is less than the thickness of the tunneling layer.

[0010] Optionally, the thickness of the tunneling layer is 1 nm to 3 nm, and the thickness of the spacer layer is 0.5 nm to 3 nm.

[0011] Optionally, the thickness of the first doped polysilicon layer is less than the thickness of the second doped polysilicon layer; preferably, the thickness of the first doped polysilicon layer is 1 nm to 100 nm, and the thickness of the second doped polysilicon layer is 10 nm to 150 nm.

[0012] Optionally, the doping concentration of the first doped polysilicon layer is less than the doping concentration of the second doped polysilicon layer; preferably, the doping concentration of the first doped polysilicon layer is 1E20cm⁻¹. -3 ~9E20cm -3 The doping concentration of the second doped polysilicon layer is 2E20cm⁻¹. -3 ~3E21cm -3 .

[0013] Optionally, the solar cell further includes:

[0014] A back passivation layer and a back anti-reflection layer are sequentially located on the back side of the passivation contact structure. The back electrode passes through the back anti-reflection layer and the back passivation layer to contact the second doped polysilicon layer.

[0015] A front diffusion layer, a front passivation layer, a front antireflection layer, and a front electrode are sequentially disposed on the front side of a silicon substrate, wherein the front electrode passes through the front antireflection layer and the front passivation layer and contacts the front diffusion layer;

[0016] The silicon substrate is an N-type silicon wafer, the front diffusion layer is a boron diffusion layer, and the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer are phosphorus doped polycrystalline silicon layers.

[0017] This invention also provides a method for preparing a passivated contact structure for a solar cell, comprising the following steps:

[0018] A tunneling layer, a first phosphorus-doped amorphous silicon layer, a spacer layer, and a second phosphorus-doped amorphous silicon layer are sequentially deposited on the back side of a silicon substrate.

[0019] In an oxygen atmosphere, a laser is used to scan the gate line region of the second phosphorus-doped amorphous silicon layer, and an oxide layer mask is formed in the gate line region by oxidation.

[0020] Annealing process transforms the first phosphorus-doped amorphous silicon layer into a first doped polycrystalline silicon layer and the second phosphorus-doped amorphous silicon layer into a second doped polycrystalline silicon layer.

[0021] Alkaline etching solution removes the second doped polysilicon layer in the non-gate region;

[0022] Hydrofluoric acid removes the oxide layer mask and spacer layer.

[0023] Optionally, the spacer layer is selected from one or more of the following stacked films: silicon oxide layer or silicon oxynitride layer.

[0024] Optionally, the thickness of the spacer layer is less than the thickness of the tunneling layer.

[0025] Optionally, the thickness of the tunneling layer is 1 nm to 3 nm, and the thickness of the spacer layer is 0.5 nm to 3 nm.

[0026] Optionally, the thickness of the first phosphorus-doped amorphous silicon layer is less than the thickness of the second phosphorus-doped amorphous silicon layer; preferably, the thickness of the first phosphorus-doped amorphous silicon layer is 1 nm to 100 nm, and the thickness of the second phosphorus-doped amorphous silicon layer is 10 nm to 150 nm.

[0027] Optionally, the oxygen concentration is 20% to 80%; laser parameters: power 5W to 100W, frequency 5kHz to 1000kHz, scanning rate 1000mm / s to 10000mm / s, and number of processing times 1 to 100.

[0028] Optionally, the doping concentration of the first doped polysilicon layer is less than the doping concentration of the second doped polysilicon layer; preferably, the doping concentration of the first doped polysilicon layer is 1E20cm⁻¹. -3 ~9E20cm -3 The doping concentration of the second doped polysilicon layer is 2E20cm⁻¹. -3 ~3E21cm -3 .

[0029] This invention also provides a method for preparing a solar cell, comprising the following steps:

[0030] The passivated contact structure is prepared using the above-mentioned method for preparing the passivated contact structure of solar cells;

[0031] A back electrode is formed on the back side of the second doped polysilicon.

[0032] Optionally, the method for fabricating the solar cell includes the following steps in sequence:

[0033] Double-sided texturing of the silicon substrate;

[0034] A front diffusion layer is fabricated on the front side of a silicon substrate;

[0035] Polish the back side of the silicon substrate;

[0036] Preparation of passivated contact structures;

[0037] A passivation layer is formed on both the front and back sides;

[0038] An anti-reflective layer is formed on both the front and back sides;

[0039] Print the front and back electrodes, then sinter them.

[0040] Post-processing is performed via optical injection or electrical injection;

[0041] The silicon substrate is an N-type silicon wafer, and the front diffusion layer is a boron diffusion layer.

[0042] The beneficial effects of this invention are as follows: In the solar cell of this invention, the passivation contact structure has different film layers and thicknesses in the grid line region and non-grid line region. The grid line region has a four-layer structure consisting of a tunneling layer, a first doped polycrystalline silicon layer, a spacer layer, and a second doped polycrystalline silicon layer. It has a large thickness and two doped polycrystalline silicon layers, which prevents the grid line paste from penetrating the doped polycrystalline silicon layer and damaging the underlying tunneling oxide layer during sintering, thereby ensuring the field passivation effect. The non-grid line region only includes a tunneling layer and a first doped polycrystalline silicon layer, which is much thinner than the grid line region, reducing parasitic absorption of light from the back side and improving photoelectric efficiency. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention;

[0044] Figure 2 This is a flowchart of a method for preparing a passivated contact structure for a solar cell according to an embodiment of the present invention;

[0045] Figure 3 This is a flowchart of a method for preparing a solar cell according to one embodiment of the present invention.

[0046] Among them, 100-solar cell, 1-silicon substrate, 2-passivation contact structure, 21-tunneling layer, 22-first doped polycrystalline silicon layer, 22'-first phosphorus-doped amorphous silicon layer, 23-spacer layer, 24-second doped polycrystalline silicon layer, 24'-second phosphorus-doped amorphous silicon layer, 3-back passivation layer, 4-back antireflection layer, 5-back electrode, 6-textured structure, 7-front passivation layer, 8-front antireflection layer, 9-front electrode. Detailed Implementation

[0047] The present invention will now be described in detail with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the scope of protection of the present invention.

[0048] In the various figures of this invention, for ease of illustration, some dimensions of structures or parts may be exaggerated relative to other structures or parts; therefore, only the basic structure of the subject matter of this invention is used to illustrate the invention.

[0049] The inventors discovered that the doped polycrystalline silicon layer on the back of TOPCon solar cells cannot be further thinned due to limitations in the paste sintering window. However, a thicker doped polycrystalline silicon layer exhibits high parasitic absorption of light, affecting the utilization rate of light on the back side and consequently impacting cell efficiency. Based on this, this invention optimizes the passivation contact structure on the back of TOPCon solar cells, ensuring the required thickness in the grid area to prevent the grid paste from penetrating the doped polycrystalline silicon layer and damaging the underlying tunneling oxide layer during sintering, thus guaranteeing the field passivation effect. Simultaneously, the doped polycrystalline silicon layer in the non-grid area is thinned to reduce parasitic absorption of long-wavelength light on the back side.

[0050] Please refer to Figure 1 As shown, the solar cell 100 of the present invention includes: a silicon substrate 1, a passivation contact structure 2, a back passivation layer 3, a back antireflection layer 4, and a back electrode 5, which are sequentially located on the back side of the silicon substrate 1. The solar cell 100 achieves field passivation on the back side through the passivation contact structure 2, thereby improving the cell efficiency.

[0051] The silicon substrate 1 is selected from N-type silicon wafers with a resistivity of 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm. Preferably, the front side of the silicon substrate 1 has a textured structure 6 to reduce the front reflectivity; the textured structure 6 includes, but is not limited to, a pyramid textured structure 6, preferably with a pyramid size of 0.5 μm to 3 μm.

[0052] The passivation contact structure 2 has a grid line area for setting the back electrode 5 and a non-grid line area that does not require a metal electrode. The present invention optimizes the film material and thickness of the grid line area and the non-grid line area, thereby improving the back passivation effect and light utilization.

[0053] Specifically, the passivation contact structure 2 includes a tunneling layer 21 on the back side of the silicon substrate 1, a first doped polysilicon layer 22 on the back side of the tunneling layer 21, a spacer layer 23 on the back side of the first doped polysilicon layer 22, and a second doped polysilicon layer 24 on the back side of the spacer layer 23. The spacer layer 23 is located in the gate line region of the first doped polysilicon layer 22, so the second doped polysilicon layer 22 is only located in the gate line region.

[0054] The gate region has a four-layer structure consisting of a tunneling layer 21, a first doped polysilicon layer 22, a spacer layer 23, and a second doped polysilicon layer 24. Its significant thickness, including two doped polysilicon layers, prevents the gate paste from penetrating the doped polysilicon layers and damaging the underlying tunneling layer 21 during sintering, thus ensuring effective field passivation. In contrast, the non-gate region only includes the tunneling layer 21 and the first doped polysilicon layer 22, resulting in a significantly thinner structure compared to the gate region. This reduces parasitic absorption of light from the back side and improves photoelectric efficiency.

[0055] The tunneling layer 21 can be made using related technologies, such as a silicon oxide layer or a silicon oxynitride layer, with a thickness of 1 nm to 3 nm, preferably 1 nm to 2.5 nm, and more preferably 1.5 nm to 2 nm.

[0056] The first doped polysilicon layer 22 is a phosphorus-doped polysilicon layer with a doping concentration of 1E20cm⁻¹. -3 ~9E20cm -3 3E20cm is preferred -3 ~5E20cm -3 The thickness is 1nm to 100nm, preferably 20nm to 50nm.

[0057] The spacer layer 23 is selected from one or more stacked films of silicon oxide layer or silicon oxynitride layer, and is corrosion resistant to alkaline solution used to etch the second doped polysilicon layer 24. It can be used as a mask to protect the inner first doped polysilicon layer 22 when removing the second doped polysilicon layer 24 in the non-gate area; and allows phosphorus to diffuse inward during the annealing process.

[0058] Further research by the inventors revealed that the thickness of the spacer layer 23 has a significant impact on its performance. If the spacer layer 23 is too thin, it cannot effectively prevent the alkaline etching solution from corroding the first doped polysilicon layer 22 during the de-plating cleaning and removal of the second doped polysilicon layer 24; if the spacer layer 23 is too thick, it will increase the resistance to phosphorus diffusion, affecting ohmic contact.

[0059] Preferably, the thickness of the spacer layer 23 is not greater than the thickness of the tunneling layer 21. Specifically, the thickness of the spacer layer 23 is 0.5 nm to 3 nm, preferably 1 nm to 2.5 nm, and more preferably 1.5 nm to 2 nm.

[0060] The second doped polysilicon layer 24 has the same doping type as the first doped polysilicon layer 22, both being phosphorus doped polysilicon layers. This is equivalent to thickening the second doped polysilicon layer 24 on the basis of the first doped polysilicon layer 22, thereby increasing the total thickness of the gate region doped polysilicon layer.

[0061] Preferably, the doping concentration of the second doped polysilicon layer 24 is greater than the doping concentration of the first doped polysilicon layer 22, and the doping concentration of the gate region is not less than the doping concentration of the non-gate region, forming a selective emitter (SE) structure. In this invention, the doping concentration of the second doped polysilicon layer 24 is 2E20cm⁻¹. -3 ~3E21cm -3 5E20cm is preferred -3 ~2E21cm -3 .

[0062] The thickness of the second doped polysilicon layer 24 is not less than the thickness of the first doped polysilicon layer 22. This design can maximize the thickness of the passivation contact structure 2 located in the gate line region and reduce the thickness of the passivation contact structure 2 in the non-gate line region, thereby reducing parasitic absorption of light.

[0063] Preferably, the thickness of the second doped polycrystalline silicon layer 24 is 10 nm to 150 nm, more preferably 50 nm to 100 nm.

[0064] Furthermore, the presence of two spaced phosphorus-doped polysilicon layers in the gate line region provides some resistance to the penetration of the back electrode 5 paste, which helps to reduce the total thickness of the gate line region and improve the open-circuit voltage (Voc) of the battery. In this invention, the total thickness of the first doped polysilicon layer 22 and the second doped polysilicon layer 24 is 50nm to 150nm, preferably 60nm to 100nm.

[0065] The back passivation layer 3 is used to passivate the second doped polysilicon layer 24 in the gate line region and the first doped polysilicon layer 22 in the non-gate line region, but it is not an essential film layer. In this invention, the back passivation layer 3 is an aluminum oxide layer with a thickness of 2nm to 7nm, preferably 3nm to 6nm.

[0066] The back antireflection layer 4 is used to reduce the light reflectivity of the back side and is also a non-essential film layer. In this invention, the back antireflection layer 4 is selected from one or more stacked films of silicon nitride, silicon oxynitride, and silicon oxide, with a thickness of 60 nm to 130 nm.

[0067] The back metal electrode is a metal electrode that passes through the back anti-reflection layer 4 and the back passivation layer 3 and contacts the second doped polysilicon layer 24, but cannot penetrate the second doped polysilicon layer 24 to destroy the tunneling layer 21.

[0068] The structure on the front side of the silicon substrate 1 adopts relevant technologies, such as the front diffusion layer, the front passivation layer 7, the front antireflection layer 8 and the front electrode 9 being sequentially provided on the front side of the silicon substrate 1.

[0069] The front diffusion layer is a boron-doped emitter, or P+ emitter, which forms a PN junction with the silicon substrate 1. The boron doping concentration of the P+ emitter is 3E18 cm⁻¹. -3 ~3E19cm -3 The sheet resistance is 40Ω / sq to 300Ω / sq, preferably 150 to 250Ω / sq.

[0070] The front passivation layer 7 is an aluminum oxide passivation layer used to passivate the P+ emitter, with a thickness of 2nm to 7nm, preferably 3nm to 6nm.

[0071] The front antireflection layer 8 is selected from one or more stacked films of silicon nitride, silicon oxynitride, and silicon oxide. The thickness of the antireflection layer is 60nm to 130nm, which reduces the front reflectivity and improves the light utilization rate.

[0072] The front metal electrode penetrates the front antireflection layer 8 and the front passivation layer 7 to contact the P+ emitter, but cannot penetrate the P+ emitter to contact the silicon substrate 1.

[0073] In summary, the solar cell 100 of the present invention introduces multiple layers of second doped polycrystalline silicon 24 in the grid region, which has a certain ability to block the penetration of the back metal paste, helps to reduce the total thickness of the doped polycrystalline silicon layer in the grid region, and improves Voc; and while ensuring the thickness of the grid region, the doped polycrystalline silicon layer in the non-grid region is thinned without changing the paste of the back electrode 5, so as to achieve passivation and reduce parasitic absorption, improve the process window, and significantly improve the cell efficiency and bifaciality.

[0074] Please refer to Figure 2 As shown, the present invention also provides a method for preparing a passivated contact structure for a solar cell, comprising the following steps:

[0075] S1 uses PECVD and other processes to sequentially deposit a tunneling layer 21, a first phosphorus-doped amorphous silicon layer 22', a spacer layer 23, and a second phosphorus-doped amorphous silicon layer 24' on the back side of the silicon substrate 1.

[0076] S2 uses a laser to scan the gate line region of the second phosphorus-doped amorphous silicon layer 24' in a high-concentration oxygen atmosphere, and oxidizes the gate line region to form an oxide layer mask;

[0077] S3 annealing process, the first phosphorus-doped amorphous silicon layer 22' is transformed into the first doped polycrystalline silicon layer 22, and the second phosphorus-doped amorphous silicon layer 24' is transformed into the second doped polycrystalline silicon layer 24.

[0078] S4 alkaline etching solution removes the second doped polysilicon layer 24 in the non-gate region;

[0079] S5 hydrofluoric acid removes the oxide layer mask and spacer layer 23 to form the passivated contact structure 2.

[0080] In step S1, the tunneling layer 21, as described above, is a silicon oxide layer or a silicon oxynitride layer, with a thickness of 1 nm to 3 nm, preferably 1 nm to 2.5 nm, and more preferably 1.5 nm to 2 nm. The first phosphorus-doped amorphous silicon layer 22' has a thickness of 1 nm to 100 nm, preferably 20 nm to 50 nm. The spacer layer 23, as described above, is a stacked film selected from one or more of silicon oxide layers or silicon oxynitride layers, with a thickness of 0.5 nm to 3 nm, preferably 1 nm to 2.5 nm, and more preferably 1.5 nm to 2 nm. The second phosphorus-doped amorphous silicon layer 24' has a thickness of 10 nm to 150 nm, preferably 50 nm to 100 nm.

[0081] Two phosphorus-doped amorphous silicon layers (a first phosphorus-doped amorphous silicon layer 22' and a second phosphorus-doped amorphous silicon layer 24') are spaced apart. After annealing, two phosphorus-doped polycrystalline silicon layers (a first doped polycrystalline silicon layer 22' and a second doped polycrystalline silicon layer 24') are formed. This provides some resistance to the piercing of the back electrode 5 paste, helps to reduce the total thickness of the gate line region, and improves the open-circuit voltage (Voc) of the battery. In this invention, the total thickness of the first phosphorus-doped amorphous silicon layer 22' and the second phosphorus-doped amorphous silicon layer 24' is 50 nm to 150 nm, preferably 60 nm to 100 nm.

[0082] In step S2, under an oxygen concentration of 20%–80%, patterned scanning oxidation is performed on the grid line area using a laser. Laser parameters: power 5W–100W, preferably 30W–60W; frequency 5kHz–1000kHz, preferably 300kHz–600kHz; scanning rate 1000mm / s–10000mm / s, preferably 30000mm / s–60000mm / s; number of processing cycles 1–100, preferably 1–10. The high temperature of the laser is used to form an oxide layer mask on the grid line area.

[0083] In step S3, the annealing temperature is 880℃~980℃, preferably 900℃~950℃; after annealing, the doped amorphous silicon is transformed into doped polycrystalline silicon, the doped amorphous silicide is transformed into doped polycrystalline silicide, phosphorus is activated, and a tunneling passivation contact structure 2 is formed on the back side.

[0084] The surface concentration of the first doped polysilicon layer 22 is lower than that of the second doped polysilicon layer 24. Preferably, the surface concentration of the first doped polysilicon layer 22 is 1E20 cm⁻¹. -3 ~9E20 cm -3 3E20 cm is preferred -3 ~5E20cm -3 The surface concentration of the second doped polysilicon layer 24 is 2E20cm⁻¹. -3 ~3E21cm -3 5E20 cm is preferred -3~2E21cm -3 .

[0085] In step S4, when removing the second doped polysilicon layer 24 in the non-gate area, the alkaline etchant does not react with the spacer layer 23. Therefore, the reaction stops after the second doped polysilicon layer 24 is etched. At the same time, the alkaline etchant removes the plating around the front and edges.

[0086] In step S5, hydrofluoric acid is used to remove the oxide mask and spacer layer 23, followed by RCA cleaning to obtain the passivated contact structure 2. This process can also remove the PSG layer on the front side.

[0087] The present invention can control the thickness of the first doped polysilicon layer 22 left in the non-gate region through the spacer layer 23, while the doped polysilicon layer in the gate region is unaffected. Without changing the paste, passivation and parasitic absorption can be achieved at the same time, improving the process window and significantly improving the cell efficiency and bifaciality.

[0088] Please refer to Figure 3 As shown, the present invention also provides a method for fabricating a solar cell, comprising the following steps: forming a passivated contact structure 2 as described above on the back side of a silicon substrate 1 using the above method; and forming a back electrode 5 on the back side of a second doped polycrystalline silicon.

[0089] The silicon substrate 1 is selected from N-type silicon wafers with a resistivity of 0.3Ω·cm to 7Ω·cm, preferably 0.5Ω·cm to 3.5Ω·cm.

[0090] Preferably, the silicon substrate 1 has a textured surface structure 6 on its front side. The method for fabricating the solar cell further includes: forming a pyramidal textured surface structure 6 on the front side of the silicon wafer using alkaline texturing, with the pyramid size being 0.5 μm to 3 μm. It should be noted that texturing can be performed on only one side of the silicon wafer, or on both sides of the silicon wafer. The textured surface structure 6 on the back side can be retained or removed in a subsequent polishing process.

[0091] Furthermore, the method for fabricating the solar cell further includes forming a back passivation layer 3 and a back antireflection layer 4 sequentially on the back side of the passivation contact structure 2 before forming the back electrode 5.

[0092] Forming a back passivation layer 3: A layer of aluminum oxide is deposited on the back of the passivation contact structure 2 using the ALD process as a back passivation layer 3, with a thickness of 2nm to 7nm, preferably 3nm to 6nm.

[0093] Forming the back antireflection layer 4: The back antireflection layer 4 is deposited on the back side of the back passivation layer 3 using the PECVD process. The back antireflection layer 4 can be one or more stacked films of silicon nitride, silicon oxynitride, and silicon oxide, with a thickness of 60nm to 130nm.

[0094] The back electrode 5 is screen-printed. Specifically, a metal electrode is screen-printed on the back of the antireflective layer 4, and then sintered; after photo-injection or electro-injection post-treatment, an ohmic contact is formed.

[0095] In addition, the method for fabricating the solar cell further includes forming a front diffusion layer, a front passivation layer 7, a front antireflection layer 8, and a front electrode 9 on the front side of the silicon substrate 1.

[0096] Specifically, after texturing and before forming the passivation contact structure 2, a front diffusion layer is formed on the front side of the silicon substrate 1, that is, a P+ emitter is formed on the front side of the silicon substrate 1.

[0097] The front diffusion layer can be formed using, but is not limited to, the following methods: Method 1: Deposit a boron-doped amorphous silicon layer with a thickness of 10 nm to 100 nm on the front side of the silicon substrate 1 using PECVD, followed by high-temperature oxidation annealing to form the P+ emitter. Method 2: Form the P+ emitter using a boron source deposition and propagation method inside a high-temperature furnace tube.

[0098] The boron doping concentration in the P+ emitter is 3E18 cm⁻¹. -3 ~3E19cm -3 .

[0099] Based on this, the method for fabricating the solar cell further includes: after forming the front diffusion layer, polishing the back side of the silicon substrate 1. First, the back side silicon oxide is removed using hydrofluoric acid through a single-sided chain device; then, the back side is subjected to alkaline polishing to remove edge junctions and back side plating; finally, a cleaning process is performed.

[0100] Preferably, the front passivation layer 7 and the back passivation layer 3 are formed in the same step, the front antireflection layer 8 and the back antireflection layer 4 are formed in the same step, and the front gate line and the back gate line are formed in the same step; the process is simple and efficient.

[0101] Furthermore, the method for preparing the solar cell also includes testing and sorting, and testing, sorting, and storing the solar cells.

[0102] The following provides a specific embodiment to illustrate the method for preparing the solar cell of the present invention in detail.

[0103] Step 1: Double-sided texturing. An N-type silicon wafer with a resistivity of 1 Ω·cm is selected. Alkali texturing is used to form a pyramidal textured surface with a pyramid size of 2 μm.

[0104] Step 2: P+ emitter fabrication. A high-temperature furnace tube boron source deposition method was used to form a doping concentration of 3E18 cm⁻¹. -3 ~3E19cm-3 The P+ emitter;

[0105] Step 3, Backside Polishing. First, use a single-sided chain machine to remove the silicon oxide on the backside with hydrofluoric acid; then perform alkaline polishing on the backside to remove edge junctions and backside plating; finally, perform a cleaning process.

[0106] Step 4: Fabrication of the back-side tunneling passivation structure. Using PECVD, a tunneling layer 21 with a thickness of 1.8 nm is deposited on the back side; then a first phosphorus-doped amorphous silicon layer 22' with a thickness of 50 nm is deposited; then a spacer layer 23 with a thickness of 1.5 nm is deposited; and then a second phosphorus-doped amorphous silicon layer 24' with a thickness of 70 nm is deposited.

[0107] Step 5: Laser masking. In a 50% oxygen atmosphere, a laser is used to perform patterned scanning on the grid area. Laser parameters: power 30W; frequency 500kHz; scanning speed 5000mm / s; processing times 2 times. Using the high temperature of the laser, an oxide layer mask is formed on the grid area.

[0108] Step 6, Annealing Activation. Annealing is performed in a high-temperature annealing furnace at 910℃. After annealing, the doped amorphous silicon transforms into doped polycrystalline silicon, and the doped amorphous silicide transforms into doped polycrystalline silicide. Phosphorus activation is achieved, forming a tunneling passivation contact structure 2 on the back side. The surface concentration of the second phosphorus-doped amorphous silicon layer 24' is 1E21cm³. -3 The surface concentration of the first phosphorus-doped amorphous silicon layer 22' is 8E20 cm⁻¹. -3 .

[0109] Step 7, Removal of Plating Wrap-Around: Alkali etching removes the plating around the front and edges, while simultaneously removing the second phosphorus-doped amorphous silicon layer 24' in the non-gate area. Since the alkali does not react with silicon oxide, the reaction stops after the second phosphorus-doped amorphous silicon layer 24' is completely etched. Finally, hydrofluoric acid is used to remove the front PSG and back mask, followed by RCA cleaning.

[0110] Step 8, Preparation of passivation layer 3 on the front and back sides: An aluminum oxide passivation layer with a thickness of 5 nm is deposited on the front and back sides using the ALD process.

[0111] Step 9, Preparation of front and back antireflection layers 4: Antireflection layers are deposited on the front and back sides using PECVD process. The antireflection layer can be one or more stacked films of silicon nitride, silicon oxynitride, and silicon oxide, and the thickness of the antireflection layer is 90nm.

[0112] Step 10: Screen printing metal electrodes: Metal electrodes are printed on the front and back sides using screen printing technology, and then sintered and photo-injected or electro-injected to form ohmic contacts.

[0113] Step 11, Testing and Sorting: Test, sort, and store the solar cells.

[0114] In summary, the solar cell of the present invention deposits a multilayer silicon oxide and multilayer phosphorus-doped amorphous silicon stacked structure on the back side. A laser is used to oxidize the back grid line region to form an oxide layer mask. By wet etching, the outer layer of doped polycrystalline silicon (second doped polycrystalline silicon layer 24) in the non-grid line region on the back side is completely removed, while the inner doped polycrystalline silicon layer (first doped polycrystalline silicon layer 22) is retained. The thickness of the doped polycrystalline silicon layer in the non-grid line region is precisely controlled to balance lateral transport and current, thereby improving cell efficiency.

[0115] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0116] The detailed descriptions listed above are merely specific descriptions of feasible embodiments of the present invention, and are not intended to limit the scope of protection of the present invention. All equivalent embodiments or modifications made without departing from the spirit of the present invention should be included within the scope of protection of the present invention.

Claims

1. A solar cell, comprising a silicon substrate, a passivated contact structure located on the back side of the silicon substrate, and a back electrode located on the back side of the passivated contact structure; characterized in that, The passivation contact structure includes a tunneling layer on the back side of the silicon substrate, a first doped polysilicon layer on the back side of the tunneling layer, a spacer layer on the back side of the first doped polysilicon layer, and a second doped polysilicon layer on the back side of the spacer layer, wherein the spacer layer is located in the gate line region of the first doped polysilicon layer.

2. The solar cell according to claim 1, characterized in that: The spacer layer is selected from one or more stacked films of silicon oxide layer or silicon oxynitride layer.

3. The solar cell according to claim 1, characterized in that: The thickness of the spacer layer is less than the thickness of the tunneling layer.

4. The solar cell according to claim 3, characterized in that: The thickness of the tunneling layer is 1 nm to 3 nm, and the thickness of the spacer layer is 0.5 nm to 3 nm.

5. The solar cell according to claim 1, characterized in that: The thickness of the first doped polysilicon layer is less than the thickness of the second doped polysilicon layer; preferably The thickness of the first doped polysilicon layer is 1 nm to 100 nm, and the thickness of the second doped polysilicon layer is 10 nm to 150 nm.

6. The solar cell according to claim 1, characterized in that: The doping concentration of the first doped polysilicon layer is less than the doping concentration of the second doped polysilicon layer; preferably... The doping concentration of the first doped polysilicon layer is 1E20cm. -3 ~9E20cm -3 The doping concentration of the second doped polysilicon layer is 2E20cm⁻¹. -3 ~3E21cm -3 .

7. The solar cell according to claim 1, characterized in that: The solar cell also includes: A back passivation layer and a back anti-reflection layer are sequentially located on the back side of the passivation contact structure. The back electrode passes through the back anti-reflection layer and the back passivation layer to contact the second doped polysilicon layer. A front diffusion layer, a front passivation layer, a front antireflection layer, and a front electrode are sequentially disposed on the front side of a silicon substrate, wherein the front electrode passes through the front antireflection layer and the front passivation layer and contacts the front diffusion layer; The silicon substrate is an N-type silicon wafer, the front diffusion layer is a boron diffusion layer, and the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer are phosphorus doped polycrystalline silicon layers.

8. A method for preparing a passivated contact structure for a solar cell, characterized in that: Includes the following steps: A tunneling layer, a first phosphorus-doped amorphous silicon layer, a spacer layer, and a second phosphorus-doped amorphous silicon layer are sequentially deposited on the back side of a silicon substrate. In an oxygen atmosphere, a laser is used to scan the gate line region of the second phosphorus-doped amorphous silicon layer, and an oxide layer mask is formed in the gate line region by oxidation. Annealing process transforms the first phosphorus-doped amorphous silicon layer into a first doped polycrystalline silicon layer and the second phosphorus-doped amorphous silicon layer into a second doped polycrystalline silicon layer. Alkaline etching solution removes the second doped polysilicon layer in the non-gate region; Hydrofluoric acid removes the oxide mask and spacer layer.

9. The method for preparing the passivated contact structure of a solar cell according to claim 8, characterized in that: The spacer layer is selected from one or more stacked films of silicon oxide layer or silicon oxynitride layer.

10. The method for preparing the passivated contact structure of a solar cell according to claim 8, characterized in that: The thickness of the spacer layer is less than the thickness of the tunneling layer.

11. The method for preparing the passivated contact structure of a solar cell according to claim 10, characterized in that: The thickness of the tunneling layer is 1 nm to 3 nm, and the thickness of the spacer layer is 0.5 nm to 3 nm.

12. The method for preparing the passivated contact structure of a solar cell according to claim 8, characterized in that: The thickness of the first phosphorus-doped amorphous silicon layer is less than the thickness of the second phosphorus-doped amorphous silicon layer; preferably The thickness of the first phosphorus-doped amorphous silicon layer is 1 nm to 100 nm, and the thickness of the second phosphorus-doped amorphous silicon layer is 10 nm to 150 nm.

13. The method for preparing the passivated contact structure of a solar cell according to claim 8, characterized in that: Oxygen concentration is 20% to 80%; laser parameters: power 5W to 100W, frequency 5kHz to 1000kHz, scanning rate 1000mm / s to 10000mm / s, number of processing times 1 to 100.

14. The method for preparing the passivated contact structure of a solar cell according to claim 8, characterized in that: The doping concentration of the first doped polysilicon layer is less than the doping concentration of the second doped polysilicon layer; preferably... The doping concentration of the first doped polysilicon layer is 1E20cm. -3 ~9E20cm -3 The doping concentration of the second doped polysilicon layer is 2E20cm⁻¹. -3 ~3E21cm -3 .

15. A method for preparing a solar cell, characterized in that, Includes the following steps: The passivated contact structure of the solar cell is prepared using the method described in any one of claims 8 to 14. A back electrode is formed on the back side of the second doped polysilicon.

16. The method for preparing a solar cell according to claim 15, characterized in that: The steps are as follows: Double-sided texturing of the silicon substrate; A front diffusion layer is fabricated on the front side of a silicon substrate; Polish the back side of the silicon substrate; Preparation of passivated contact structures; A passivation layer is formed on both the front and back sides; An anti-reflective layer is formed on both the front and back sides; Print the front and back electrodes, then sinter them. Post-processing is performed via optical injection or electrical injection; The silicon substrate is an N-type silicon wafer, and the front diffusion layer is a boron diffusion layer.

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