Laminated ceramic electronic component

Abstract

Provided is a multilayer ceramic capacitor that can be reliably mounted on a wiring board and that can suppress the occurrence of squeal. A laminated ceramic electronic component is provided with: a laminated body (2) including an inner layer section (11) in which dielectric layers (14) and internal electrode layers (15) are alternately laminated, the laminated body (2) having two main surfaces (A) facing each other in a lamination direction (T) and two end surfaces (C) facing each other in a longitudinal direction (L); two external electrodes (3) which are respectively connected to the internal electrode layer (15) at the two end surfaces (C), and which cover the end surfaces (C) and a part of the two main surfaces (A) which are connected to the end surfaces and face each other; and two spacers (4) disposed on one of the two main surfaces (A) so as to sandwich the external electrode (3), the spacers (4) being disposed so as to sandwich the external electrode (3) between the two main surfaces (A), and the spacers (4) being disposed so as to sandwich the external electrode (3) between the two main surfaces (A), and the spacers (4) being disposed so as to sandwich the external electrode (3) between the two main surfaces (A) and the second main surface (SA2) when the surface that does not sandwich the external electrode is defined as the second main surface (SA2). The angle of the second main surface (SA2) of the spacer with respect to the main surface of the laminate (2) on which the spacer (4) is disposed is 5 degrees or less when viewed from the width direction.

Description

Technical Field

[0001] This invention relates to laminated ceramic capacitors and other laminated ceramic electronic components. Background Technology

[0002] A multilayer ceramic capacitor has an inner layer in which dielectric layers and internal electrodes are alternately stacked. Furthermore, a cuboid-shaped multilayer is formed by placing dielectric layers as outer layers on the upper and lower parts of the inner layer, and external electrodes are provided on the two end faces of the multilayer in the long side direction to form the capacitor body.

[0003] Furthermore, a multilayer ceramic capacitor is known, which, in order to suppress the occurrence of so-called "whistling", has a spacer formed in the capacitor body and mounted on one side of the substrate to cover a portion of the external electrodes.

[0004] However, depending on the shape of the spacer, there are cases where mounting the multilayer ceramic capacitor to the wiring board becomes difficult. Furthermore, if the solder that is heated and melted during mounting rises along the surface of the spacer in the height direction of the multilayer ceramic capacitor, the expansion and contraction vibration of the inner layer is transmitted to the wiring board, making it difficult to suppress the occurrence of howling.

[0005] Therefore, there is a need to develop multilayer ceramic capacitors that can be reliably mounted onto wiring boards and suppress the occurrence of whistling.

[0006] Prior art literature

[0007] Patent documents

[0008] Patent Document 1: Japanese Patent Application Publication No. 2015-216337 Summary of the Invention

[0009] The problem the invention aims to solve

[0010] The object of the present invention is to provide a multilayer ceramic capacitor that can be reliably mounted on a wiring substrate and can suppress the occurrence of howling.

[0011] Technical solutions for solving the problem

[0012] The inventors of this invention discovered that in a multilayer ceramic capacitor having spacers, if the second main surface of the spacer that bonds to the pads of the wiring substrate is configured at an angle of 5 degrees or less relative to the main surface of the multilayer on which the spacer is configured when viewed from the width direction, the gap between the pads of the wiring substrate and the spacer is reduced, and thus the multilayer ceramic capacitor can be reliably mounted, thus completing this invention.

[0013] That is, the present invention is a laminated ceramic electronic component, comprising:

[0014] A laminate includes an inner layer in which dielectric layers and internal electrode layers are alternately stacked, and has two main faces opposite each other in the stacking direction, two end faces opposite each other in the length direction intersecting the stacking direction, and two side faces opposite each other in the width direction intersecting the stacking direction and the length direction.

[0015] Two external electrodes are respectively connected to the internal electrode layer at the two end faces, and cover a portion of the end faces and two main surfaces connected to and opposite to the end faces; and

[0016] Two spacers, on one of the two main surfaces of the laminate, are configured to sandwich the external electrode between them.

[0017] When the surface of the spacer that is opposite to the external electrode in the stacking direction is designated as the first main surface and the surface that is not designated as the second main surface,

[0018] The angle between the second main surface of the spacer and the main surface of the laminate on which the spacer is disposed, when viewed from the width direction, is less than 5 degrees.

[0019] Invention Effects

[0020] According to the present invention, a multilayer ceramic capacitor capable of being reliably mounted on a wiring substrate and capable of suppressing the occurrence of sound can be provided. Attached Figure Description

[0021] Figure 1 This is a diagram showing the appearance of the multilayer ceramic capacitor 1.

[0022] Figure 2 It is along Figure 1 A cross-sectional view of the stacked ceramic capacitor 1 shown in line II-II.

[0023] Figure 3 It is along Figure 1 A cross-sectional view of the multilayer ceramic capacitor 1 shown along line III-III.

[0024] Figure 4 This is a schematic diagram of spacers of various shapes viewed from the width direction W.

[0025] Figure 5 yes Figure 2 Enlarged cross-sectional view of spacer 4 shown.

[0026] Figure 6 This is a flowchart illustrating a method for manufacturing a multilayer ceramic capacitor 1.

[0027] Figure 7This diagram illustrates the laminate manufacturing process S1, the substrate electrode layer formation process S2, and the first plating layer formation process S3.

[0028] Figure 8 This diagram illustrates the spacer configuration process S4 and the second plating layer formation process S5.

[0029] Figure 9 This is a cross-sectional view showing a multilayer ceramic capacitor 1 without the second plating layer 32.

[0030] Figure 10 This is a cross-sectional view of a multilayer ceramic capacitor 1 with reinforcing member 50.

[0031] Figure 11 This diagram illustrates the reinforcement component configuration process S6. Detailed Implementation

[0032] The following description describes a multilayer ceramic capacitor 1 as an embodiment of the multilayer ceramic electronic component of the present invention, but the present invention is not limited thereto. Furthermore, the accompanying drawings are sometimes schematically simplified for the purpose of illustrating the invention, and the dimensions of the depicted components or the ratios between the dimensions of the components may differ from those described in the specification. Additionally, the components described in the specification may sometimes be omitted in the accompanying drawings, or the number of components may be omitted, etc.

[0033] Figure 1 This is a schematic perspective view of the stacked ceramic capacitor 1 according to the embodiment. Figure 2 Along the implementation of the multilayer ceramic capacitor 1 Figure 1 A sectional view along line II-II in the diagram. Figure 3 Along the implementation of the multilayer ceramic capacitor 1 Figure 1 A sectional view along line III-III.

[0034] The multilayer ceramic capacitor 1 is generally rectangular in shape and has a capacitor body 1A comprising a multilayer body 2 and a pair of external electrodes 3 disposed at both ends of the multilayer body 2, and a spacer 4 mounted on the capacitor body 1A. In addition, the multilayer body 2 includes an inner layer portion 11 in which a dielectric layer 14 and an internal electrode layer 15 are stacked.

[0035] In the following description, as a term indicating the orientation of the multilayer ceramic capacitor 1, the direction in which a pair of external electrodes 3 are disposed is designated as the length direction L. The direction in which the dielectric layer 14 and the internal electrode layer 15 are stacked is designated as the stacking direction T. The direction intersecting both the length direction L and the stacking direction T is designated as the width direction W. Furthermore, in the embodiment, the width direction W is orthogonal to both the length direction L and the stacking direction T.

[0036] (Outer surface of layer 2)

[0037] Furthermore, among the six outer surfaces of the laminate 2, a pair of opposite surfaces in the lamination direction T are designated as the first main surface A1 and the second main surface A2; a pair of opposite surfaces in the width direction W are designated as the first side surface B1 and the second side surface B2; and a pair of opposite surfaces in the length direction L are designated as the first end surface C1 and the second end surface C2. Additionally, unless there is a specific distinction between the first main surface A1 and the second main surface A2, they are uniformly referred to as main surface A; unless there is a specific distinction between the first side surface B1 and the second side surface B2, they are uniformly referred to as side surface B; and unless there is a specific distinction between the first end surface C1 and the second end surface C2, they are uniformly referred to as end surface C.

[0038] Preferably, the edge portion R1 including the corner of the laminate 2 has rounded corners. The edge portion R1 is the part where two surfaces of the laminate 2 intersect, namely the main surface A and the side surface B, the main surface A and the end surface C, or the side surface B and the end surface C.

[0039] (Layered body 2)

[0040] The laminate 2 includes an inner layer 11 that forms an electrostatic capacitor, an outer layer 12 that is configured to sandwich the inner layer 11 from the lamination direction T, and a side gap 16 that is configured to sandwich the inner layer 11 and the outer layer 12 from the width direction W.

[0041] (Inner layer 11)

[0042] The inner layer 11 includes a dielectric layer 14 and an inner electrode layer 15 that are alternately stacked along the stacking direction T.

[0043] (Dielectric layer 14)

[0044] The dielectric layer 14 is made of a ceramic material. For example, a dielectric ceramic with BaTiO3 as the main component can be used as the ceramic material.

[0045] (Internal electrode layer 15)

[0046] The internal electrode layer 15 includes a plurality of first internal electrode layers 15a and a plurality of second internal electrode layers 15b. The first internal electrode layers 15a and second internal electrode layers 15b are arranged alternately. The first internal electrode layer 15a includes a first opposing portion 152a opposite to the second internal electrode layer 15b and a first lead-out portion 151a extending from the first opposing portion 152a toward the first end face C1. The end of the first lead-out portion 151a is exposed at the first end face C1 and is electrically connected to the first external electrode 3a described later. The second internal electrode layer 15b includes a second opposing portion 152b opposite to the first internal electrode layer 15a and a second lead-out portion 151b extending from the second opposing portion 152b toward the second end face C2. The end of the second lead-out portion 151b is electrically connected to the second external electrode 3b described later. Charge is accumulated in the first opposing portion 152a of the first internal electrode layer 15a and the second opposing portion 152b of the second internal electrode layer 15b.

[0047] The internal electrode layer 15 is preferably formed of a metallic material such as nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), silver-palladium (Ag-Pd) alloy, gold (Au).

[0048] (Outer layer 12)

[0049] The outer layer 12 can be formed of the same material as the dielectric layer 14 of the inner layer 11.

[0050] (Side gap section 16)

[0051] The capacitor has a first side gap 16a that forms the first side surface B1 of the laminated ceramic capacitor 1, and a second side gap 16b that forms the second side surface B2 of the laminated ceramic capacitor 1, which are configured to sandwich the inner layer 11 and the outer layer 12 in the width direction W. The side gap 16 can be formed of the same material as the dielectric layer 14.

[0052] (External electrode 3)

[0053] The external electrode 3 includes a first external electrode 3a disposed on the first end face C1 and a second external electrode 3b disposed on the second end face C2. The external electrode 3 covers not only the end face C, but also a portion of the main surface A and the side surface B connected to the end face C.

[0054] As described above, the end of the first lead-out portion 151a of the first inner electrode layer 15a is exposed at the first end face C1 and electrically connected to the first outer electrode 3a. Furthermore, the end of the second lead-out portion 151b of the second inner electrode layer 15b is exposed at the second end face C2 and electrically connected to the second outer electrode 3b. Thus, the first outer electrode 3a and the second outer electrode 3b form a configuration where multiple capacitor elements are electrically connected in parallel.

[0055] Furthermore, the external electrode 3 may include, for example, a base electrode layer 30 and a first plating layer 31. However, the external electrode 3 does not necessarily need to have such a layered structure.

[0056] The base electrode layer 30 is formed, for example, by applying and sintering a conductive paste containing copper (Cu). Alternatively, the base electrode layer 30 in this embodiment may also contain glass or ceramic materials. However, the structure of the base electrode layer 30 is not limited to these methods.

[0057] The first plating layer 31 includes a first nickel (Ni) plating layer 31a disposed on the surface of the substrate electrode layer 30, and a first tin (Sn) plating layer 31b disposed on the surface of the first nickel (Ni) plating layer 31a. However, the structure of the first plating layer 31 is not limited thereto.

[0058] (Spacer 4)

[0059] The spacer 4 includes a first spacer 4a and a second spacer 4b. The first spacer 4a is disposed on one end face C1 side of the capacitor body 1A on the side of the second main surface A2, which serves as the substrate mounting surface, in the longitudinal direction L, and the second spacer 4b is disposed on the other end face C2 side. When the substrate mounting surface of the capacitor body 1A is the first side surface B1, the first spacer 4a is disposed on one end face C1 side of the capacitor body 1A on the side of the first side surface B1, which serves as the substrate mounting surface, in the longitudinal direction L, and the second spacer 4b is disposed on the other end face C2 side.

[0060] Spacer 4 is disposed on the surface of the external electrode 3 of the capacitor body 1A and the surface of the second main surface A2 of the laminate 2 connected to the external electrode 3 but without the external electrode 3. When the substrate mounting surface of the capacitor body 1A is the first side surface B1, spacer 4 is disposed on the surface of the external electrode 3 of the capacitor body 1A and the surface of the first side surface B1 of the laminate 2 connected to the external electrode 3 but without the external electrode 3.

[0061] The spacer 4 is approximately cuboid in shape. Of the two opposing surfaces formed on its surface in the stacking direction T, the surface that holds the external electrode 3 between itself and the second main surface A2 of the laminate 2 is designated as the first main surface SA1, and the surface that does not hold the external electrode 3 is designated as the second main surface SA2. The angle between the second main surface SA2 of the spacer 4 and the second main surface A2 of the laminate 2, when viewed from the width direction W, is set to 5 degrees or less. This allows the laminated ceramic capacitor 1 to be positioned approximately parallel to the wiring substrate via the second main surface SA2 of the spacer 4. Therefore, when soldering, no gap is generated between the spacer 4 and the pads provided on the wiring substrate, enabling reliable bonding. Furthermore, the amount of solder entering between the two spacers 4 and the second main surface A2 of the laminate 2 can be reduced between the two spacers 4, thus suppressing changes in the relative position of the two spacers 4 due to solder shrinkage, and improving mountability. When the substrate mounting surface of the capacitor body 1A is the first side surface B1, among the two opposing surfaces of the spacer 4 formed on the surface in the width direction W, the surface that sandwiches the external electrode 3 between the first side surface B1 of the laminate 2 is designated as the first side surface SB1, and the surface that does not sandwich the external electrode 3 is designated as the second side surface SB2. When the angle of the second side surface SB2 of the spacer 4 relative to the first side surface B1 of the laminate 2 is viewed from the lamination direction T, it is set to 5 degrees or less.

[0062] As a method for determining the angle between the second principal surface SA2 of spacer 4 and the second principal surface A2 of laminate 2, for example, spacer 4 is ground perpendicular to the width direction W until the center of the width direction W is reached, and the ground surface is photographed using a microscope (BX-51) connected to a digital microscope camera (DP22, Olympus), set to a comprehensive magnification of 10x. In the photographed image, the angle formed by the line connecting the two ends of the second principal surface A2 of laminate 2 and the line connecting the two ends of the second principal surface SA2 of spacer 4 can be measured. In the case where the ends have rounded corners, the parts without rounded corners are designated as the ends.

[0063] If the solder, heated and molten during installation, travels along the surface of the spacer 4 and rises high along the end face C on the surface of the outer electrode 3 in a direction perpendicular to the mounting surface of the multilayer ceramic capacitor 1, the expansion and contraction vibration of the inner layer 11 propagates to the wiring substrate, making it sometimes difficult to suppress the occurrence of squealing. Therefore, when viewing the spacer 4 from the width direction W, the length W1 of the first main surface SA1 of the spacer 4 in the length direction L is preferably 95% or less or 105% or more of the length W3 of the second main surface SA2 of the spacer 4. This prevents the molten solder from traveling along the surface of the spacer 4.

[0064] In addition, when observing the spacer 4 in the width direction W, the length W2 in the length direction L at the central portion in the stacking direction T is preferably shorter than the length W1 in the length direction L of the first main surface SA1 and the length W3 in the length direction L of the second main surface SA2. For example, as shown in the schematic diagram Figure 4 , in the case of a shape that can be expressed as a relational expression W1 < W2 < W3 ( Figure 4 (b)), a shape that can be expressed as W1 > W2 > W3 ( Figure 4 (c)), or a shape that can be expressed as W1 > W2 and W2 < W3 ( Figure 4 (d)), it is possible to prevent the molten solder from wetting and climbing along the surface of the spacer 4. In addition, if the spacer is set to such a shape, the adhesion area with the reinforcing member described later also increases, so the adhesion between the spacer and the stacked ceramic capacitor is improved. The same applies when the substrate mounting surface of the capacitor body 1A is the first side surface B1.

[0065] As a method for measuring W1, W2, and W3, for example, the spacer 4 is polished perpendicular to the width direction W until the center in the width direction W, and a microscope (BX-51) connected to a microscope digital camera (DP22, manufactured by Olympus) is used to set the overall magnification to 10 times, and the polished surface is photographed. The lengths of each part are measured based on the photographed image.

[0066] The second plating layer 32 is arranged to cover the spacer 4 and the external electrode 3, but is not limited thereto. The second plating layer 32 may not be arranged on the spacer 4 and the external electrode 3 ( Figure 9 ). When the second plating layer 32 is arranged to cover the spacer 4 and the external electrode 3, the second plating layer 32 includes a second nickel (Ni) plating layer 32a and a second tin (Sn) plating layer 32b arranged on the surface of the second nickel (Ni) plating layer 32a.

[0067] The second plating layer 32 is arranged on the outer surface of the first tin (Sn) plating layer 31b of the first plating layer 31 in the portion where the spacer 4 is not arranged, and is arranged on the outer surface of the spacer 4 in the portion where the spacer 4 is arranged. In addition, the structure of the second plating layer 32 is not limited thereto. By arranging the second plating layer 32, the adhesion between the spacer 4 and the capacitor body 1A is improved.

[0068] In this embodiment, an external electrode 3 is shown consisting of a base electrode layer 30 and a first plating layer 31 covering the base electrode layer 30, with a spacer 4 disposed on the surface of the first plating layer 31. However, the first plating layer 31 is not necessarily required. For example, the spacer 4 can be disposed on the surface of the base electrode layer 30, and a second plating layer 32 can be disposed to cover the spacer 4 and the base electrode layer 30. By disposing of the second plating layer 32, the adhesion between the spacer 4 and the base electrode layer 30 is improved, and the mechanical strength of the spacer 4 is improved by the second plating layer 32 penetrating into the void P exposed on the surface of the spacer 4.

[0069] The spacer 4 contains either copper (Cu) or nickel (Ni) and tin (Sn) as metal powder. Copper (Cu) and nickel (Ni) can also be coated with silver (Ag). The intermetallic compound formed by adding either copper (Cu) or nickel (Ni) and tin (Sn) does not produce heat-induced deformation even when the multilayer ceramic capacitor 1 is soldered onto the wiring substrate, thus reliably maintaining the shape of the spacer 4. It is particularly preferred that an intermetallic compound formed by adding tin (Sn) to an alloy of copper (Cu) and nickel (Ni) is used as a component forming the spacer 4.

[0070] Phenolic resin may also be included in the metal region MP formed by metal powder. The phenolic resin is dispersed as particles coated with intermetallic compounds and fills the gaps between the particles. The phenolic resin may also be in a state where the particles are not completely coated with intermetallic compounds. Furthermore, by using phenolic resin, the amount of gas generated during the heat treatment when forming the spacer 4 can be reduced, thus reducing the voids P within the spacer 4. The phenolic resin may also be exposed on the surface of the spacer 4 and coat at least a portion of the surface. By coating the surface of the spacer 4 with phenolic resin, the smoothness of the surface of the spacer 4 is improved, thereby increasing the mechanical strength of the spacer 4.

[0071] Examples of phenolic resins include phenolic varnish resin, phenolic aralkyl resin, cresol phenolic varnish resin, tert-butylphenol phenolic varnish resin, nonylphenol phenolic varnish resin, etc., as well as methyl phenolic resin, poly(p-hydroxystyrene), etc.

[0072] The proportion of the area occupied by phenolic resin in the LT section perpendicular to the width direction W of the spacer 4 is preferably 1% or more and 20% or less, and particularly preferably 5% or more and 15% or less. If it is less than 1%, the effect of the phenolic resin cannot be fully utilized, and if it exceeds 20%, the adhesion strength between the spacer and the external electrode may decrease.

[0073] Additionally, as a method to determine the percentage of area occupied by phenolic resin, for example, the spacer 4 is ground along the width direction W until the center of the width direction W is reached. The ground surface is then magnified to a combined magnification of 50x using a microscope (BX-51) and photographed using a microscope digital camera (Olympus DP22). The obtained photographic image can be binarized into a metal region MP and a resin region RP. Based on the areas of the metal region MP, metal powder MF, resin region RP, and voids P, the percentage of area occupied by phenolic resin is calculated using the formula: (Area of ​​resin region RP / (Area of ​​metal region MP + Area of ​​metal powder MF + Area of ​​resin region RP + Area of ​​voids P)) × 100.

[0074] like Figure 5 As shown, metal powder MF can also be included in the resin region RP formed by phenolic resin. The metal powder MF hinders the shrinkage of phenolic resin, thereby mitigating the shrinkage stress generated by the phenolic resin.

[0075] In the region Z from the interface with the external electrode 3 to 5 μm, the porosity of the spacer 4 is preferably 20% or less. By suppressing the porosity to a lower level, the adhesion area of ​​the spacer 4 to the external electrode 3 is increased, and the adhesion force to the external electrode 3 is improved.

[0076] Additionally, as a method for determining the porosity (%), for example, the spacer 4 is ground along the width direction W until the center of the width direction W is reached. The ground surface is then magnified to a combined magnification of 50x using a microscope (BX-51) and photographed using a microscope digital camera (Olympus DP22). The obtained photographic image can be binarized into a metal region MP and a porosity P. Based on the areas of the metal region MP, metal powder MF, resin region RP, and porosity P, the porosity (%) is calculated using the formula: porosity (%) = area of ​​porosity P / (area of ​​metal region MP + area of ​​metal powder MF + area of ​​resin region RP + area of ​​porosity P) × 100.

[0077] The maximum diameter of the void P formed inside the spacer 4 is preferably less than or equal to half of the maximum dimension of the thickness of the spacer 4 in the lamination direction T. If it is greater than half, cracking becomes more likely to occur starting from the void P, and the strength of the spacer 4 decreases. When the substrate mounting surface of the capacitor body 1A is the first side surface B1, the maximum diameter of the void P formed inside the spacer 4 is preferably less than or equal to half of the maximum dimension of the thickness of the spacer 4 in the width direction W.

[0078] In the above, an example of the material for spacer 4 is shown, comprising an intermetallic compound and a phenolic resin, but it is not limited to this. It may also contain other types of metallic components, or it may contain resins such as epoxy resin, rosin, and glass components in addition to phenolic resin. Furthermore, it may be formed without resin.

[0079] Viewed from the stacking direction T, if the spacer 4 is smaller than the external electrode 3, it is preferable to add a direction-discriminating unit to at least a portion of the spacer 4. The direction-discriminating unit indicates the direction, so that when the stacked ceramic capacitor 1 is mounted on the wiring substrate, with the second main surface A2 where the spacer 4 is disposed facing the wiring substrate, units that color the spacer 4 with a different color than the external electrode 3, units that print a direction-discriminating mark such as a QR code (registered trademark), and units that provide recesses for a portion of the stack can be used. Alternatively, as a coloring unit, the phenolic resin contained in the spacer 4 can be exposed on the surface of the spacer 4, resulting in a color different from the external electrode 3. Furthermore, if the spacer 4 is larger than the external electrode 3, a direction-discriminating unit can also be provided.

[0080] like Figure 10 As shown, a reinforcing member 50 can be disposed between the first spacer 4a and the second spacer 4b, such that it covers at least a portion of at least one of the first spacer 4a and the second spacer 4b, and at least a portion of the second main surface A2 or the first side surface B1 of the laminate 2.

[0081] By configuring the reinforcing member 50, the adhesion between the spacer 4 and the external electrode 3, as well as between the spacer 4 and the laminate 2, can be improved.

[0082] The reinforcing member 50 can be continuously arranged between the first spacer 4a and the second spacer 4b, but it does not necessarily need to be continuously arranged. For example, it can also be arranged as a reinforcing member covering a part of the first spacer 4a and a part of the second main surface A2 or the first side surface B1 of the laminate 2, and a reinforcing member covering a part of the second spacer 4b and a part of the second main surface A2 or the first side surface B1 of the laminate 2.

[0083] The reinforcing member 50 can be formed from an insulating resin. The surface of the insulating resin can also be coated with an insulating hydrophobic treatment agent. By forming the reinforcing member with an insulating resin, the flexural strength is improved, and by coating it with an insulating hydrophobic treatment agent, the moisture resistance is improved. The insulating resin can also contain ceramics, glass, etc. It can also be formed solely from a hydrophobic treatment agent.

[0084] The material for the reinforcing component 50 can be epoxy resin as the main component, combined with phenolic resin as a curing agent. Other curing agents include anhydride-based, amine-based, and ester-based curing agents. Curing accelerators can also be further added to the epoxy resin.

[0085] The reinforcing member 50 can be configured to cover the side peripheral surface SW of the spacer 4. In this case, the reinforcing member 50 preferably covers the second main surface A2 or the first side surface B1 of the laminate 2, and covers the side peripheral surface SW of the spacer 4 with a height of more than 5% of the length of the spacer 4 in the lamination direction T. By covering it with the reinforcing member 50 in this way, the mechanical strength is improved, and in particular, the impact resistance when an impact is applied to the laminated ceramic capacitor 1 is improved.

[0086] (Manufacturing method of multilayer ceramic capacitor 1)

[0087] Figure 6 This is a flowchart illustrating a method for manufacturing a multilayer ceramic capacitor 1. The method for manufacturing the multilayer ceramic capacitor 1 includes a multilayer body manufacturing step S1, a substrate electrode layer formation step S2, a first plating layer formation step S3, a spacer placement step S4, and a second plating layer formation step S5. Furthermore, the multilayer ceramic capacitor 1 can be equipped with a reinforcing member 50 by proceeding to a reinforcing member placement step S6 after the spacer placement step S4. Figure 7 This diagram illustrates the laminate manufacturing process S1, the substrate electrode layer formation process S2, and the first plating layer formation process S3. Figure 8 This diagram illustrates the spacer configuration process S4 and the second plating layer formation process S5. Figure 11 This diagram illustrates the reinforcement component configuration process S6.

[0088] (Laminated body manufacturing process S1)

[0089] A ceramic slurry containing ceramic powder, binder, and solvent is formed into a sheet on the surface of a carrier film using a die coater, gravure coater, or micro-gravure coater to create a laminated ceramic green sheet 101 that forms the dielectric layer 14. Next, a conductive paste is printed into a strip on the laminated ceramic green sheet 101 using screen printing, inkjet printing, or gravure printing to create a conductive pattern 102 that forms the internal electrode layer 15, thus creating a raw material sheet 103.

[0090] Next, as Figure 7As shown in (a), multiple raw material sheets 103 are stacked such that the conductive patterns 102 face the same direction and are staggered, for example, by half a pitch, between adjacent raw material sheets 103 in the longitudinal direction. Furthermore, on both sides of the stacked raw material sheets 103, outer layer ceramic green sheets 112 are stacked to form the outer layer 12.

[0091] Multiple stacked raw material sheets 103 and the outer layer are pressed together using ceramic green sheets 112 through isostatic pressing and other methods to produce... Figure 7 The mother block 110 shown in (b)

[0092] Next, move the mother block 110 along... Figure 7 Cut along the cutting line X shown in (b) and the cutting line Y intersecting with the cutting line X to manufacture multiple [products / processes]. Figure 7 The unfired laminate 2 is shown in (c).

[0093] (Substrate electrode layer formation process S2)

[0094] Next, a conductive paste containing copper (Cu) is applied and sintered onto the end face C of the laminate 2 to form a base electrode layer 30. The base electrode layer 30 is formed to cover not only the end faces C on both sides of the laminate 2, but also to the main face A and the side face B of the laminate 2, and to cover a portion of the end face C side of the main face A. However, it is not limited to this; it may contain other metals or other components, and two base electrode layers may be provided.

[0095] (First plating layer formation process S3)

[0096] Next, a first nickel (Ni) plating layer 31a and a first tin (Sn) plating layer 31b disposed on the surface of the base electrode layer 30 are formed to manufacture the substrate electrode layer 30. Figure 7 The capacitor body 1A is shown in (d).

[0097] (Spacer configuration process S4)

[0098] Prepare spacer manufacturing paste 41 for use in spacer manufacturing.

[0099] The spacer manufacturing paste 41 contains metals including copper (Cu), nickel (Ni), tin (Sn), and silver (Ag), phenolic resin, solvent, and additives.

[0100] Examples of phenolic resins include phenolic varnish resin, phenolic aralkyl resin, cresol phenolic varnish resin, tert-butylphenol phenolic varnish resin, nonylphenol phenolic varnish resin, etc., as well as methyl phenolic resin, poly(p-hydroxystyrene), etc.

[0101] In the formation of the spacer 4, for example, a holding substrate 40 as shown Figure 8 is used.

[0102] The paste 41 for manufacturing the spacer is disposed on the holding substrate 40 by a screen printing method, a dispensing method, or the like.

[0103] Next, the capacitor body 1A is mounted on the upper surface of the holding substrate 40 in a posture where the second main surface A2 side faces the holding substrate 40 as shown in Figure 8 (b). At this time, the external electrodes 3 of the capacitor body 1A are aligned with the paste 41 for manufacturing the spacer, and the paste 41 for manufacturing the spacer adheres to the capacitor body 1A.

[0104] In this state, a heating process is performed. When at least a part of the metal in the paste forms an intermetallic compound to form the metal region MP, a part of the phenolic resin is taken into the metal region MP, and a part is discharged from the metal region MP and cured to form the spacer 4 joined to the capacitor body 1A.

[0105] After that, the capacitor body 1A and the spacer 4 are separated from the holding substrate 40 and become the state shown in Figure 8 (c).

[0106] In addition, not limited to this manufacturing method, the paste for manufacturing the spacer may be directly disposed in a desired shape on the surface of the capacitor body 1A and heat-treated to form the spacer.

[0107] In order to adjust the spacer 4 to a given shape, for example, the following method can be adopted.

[0108] In the case of a shape represented by the relational expression W1 < W2 < W3, after printing the paste for manufacturing the spacer on the unburned laminate 2 by screen printing or the like, a smooth plate-like jig is pressed against the printing surface. The height of the jig is adjusted to increase the pressing amount on the paste for manufacturing the spacer, and then heat treatment is performed.

[0109] In the case of a shape represented by the relational expression W1 > W2 > W3, after printing the paste for manufacturing the spacer on the unburned laminate 2 by screen printing or the like, a smooth plate-like jig is pressed against the printing surface. The height of the jig is adjusted to decrease the pressing amount on the paste for manufacturing the spacer, and then heat treatment is performed.

[0110] In the case of a shape represented by the relational expressions W1 > W2 and W2 < W3, after printing a paste for manufacturing spacers on the unburned laminate 2 by screen printing or the like, while adjusting the height of a smooth plate-like jig and pressing it against the paste for manufacturing spacers, heat treatment is performed in a state where the jig is moved in the separating direction to such an extent that it does not separate from the paste for manufacturing spacers.

[0111] In the above, as an example of the material of the spacer 4, a structure including an intermetallic compound and a phenolic resin is shown, but it is not limited thereto. It may also be a structure including other types of metal components, or a structure including resins such as epoxy resin and rosin, and glass components in addition to the phenolic resin. Further, it may be formed without including a resin.

[0112] (Second plating layer forming step S5)

[0113] Next, a second nickel (Ni) plating layer 32a may also be formed on the exposed portions of the first tin (Sn) plating layer 31b in the capacitor body 1A and the surface of the spacer 4, and then a second tin (Sn) plating layer 32b may be formed on the outer periphery of the second nickel (Ni) plating layer 32a.

[0114] (Reinforcement member arranging step S6)

[0115] Figure 11 FIG. is a diagram for explaining the reinforcement member arranging step S6. After the spacer arranging step S4, the surface of the capacitor body 1A on which the spacer 4 is arranged is cleaned with a solvent. As Figure 11 shown in (a) of, after the cleaning is completed, the capacitor bodies 1A on which the spacers 4 are arranged are arranged such that the spacers 4 face upward.

[0116] Next, as Figure 11 shown in (b) of, for the capacitor bodies 1A on which the spacers 4 are arranged, an insulating resin layer serving as the central portion 51 of the reinforcement member 50 is formed between the first spacer 4a and the second spacer 4b using a dispenser or screen printing. The wetting climb amount toward the side surface of the spacer 4 can be adjusted by the amount of the insulating resin.

[0117] In the case of allowing the insulating resin to enter the interface between the spacer 4 and the laminate 2, it can be made to enter by performing vacuum pumping after the insulating resin is arranged. The entering amount can be controlled by changing the time and pressure of the vacuum pumping. <0000​​​​​Then, by heating the applied insulating resin at 100–200°C for 20–80 minutes, the insulating resin is cured, forming a coating based on the reinforcing member 50 on the outer periphery of the capacitor body 1A and the side peripheral surface SW of the spacer 4. The multilayer ceramic capacitor 1 is manufactured through the above process.

[0120] In addition, in the embodiment, it is shown that the reinforcing member 50 directly covers the surface of the spacer 4, but it is not limited to this method. For example, a second plating layer 32 may be formed on the surface of the spacer 4, and the reinforcing member 50 may be disposed on the surface of the second plating layer 32 to cover the side peripheral surface SW of the spacer 4.

[0121] The embodiments of the present invention have been described above, but the present invention is not limited to these embodiments and can be implemented in various ways without departing from the spirit of the present invention. The present invention includes the following combinations.

[0122] <1>

[0123] A stacked ceramic electronic component, comprising:

[0124] A laminate includes an inner layer in which dielectric layers and internal electrode layers are alternately stacked, and has two main faces opposite each other in the stacking direction, two end faces opposite each other in the length direction intersecting the stacking direction, and two side faces opposite each other in the width direction intersecting the stacking direction and the length direction.

[0125] Two external electrodes are respectively connected to the internal electrode layer at the two end faces, and cover a portion of the end faces and two main surfaces connected to and opposite to the end faces; and

[0126] Two spacers, on one of the two main surfaces of the laminate, are configured to sandwich the external electrode between them.

[0127] When, among the two opposing surfaces of the spacer formed in the stacking direction, the surface that sandwiches the external electrode is designated as the first main surface, and the surface that does not sandwich the external electrode is designated as the second main surface,

[0128] The angle between the second main surface of the spacer and the main surface of the laminate on which the spacer is disposed, when viewed from the width direction, is less than 5 degrees.

[0129] <2>

[0130] according to <1> The described laminated ceramic electronic components, among which,

[0131] When the spacer is viewed from the width direction, the length of the first main surface in the length direction is less than 95% or more than 105% of the length of the second main surface in the length direction.

[0132] <3>

[0133] according to <1> or <2> The described laminated ceramic electronic components, among which,

[0134] When the spacer is viewed from the width direction, the length of the central portion in the stacking direction is shorter than the length of the first main surface and the length of the second main surface in the length direction.

[0135] <4>

[0136] according to <1> to <3> Among the laminated ceramic electronic components described in any one of them,

[0137] The spacer contains resin.

[0138] <5>

[0139] according to <1> to <4> The ceramic capacitor described in any one of the following, among which,

[0140] The spacer contains copper and glass.

[0141] <6>

[0142] according to <1> to <5> Among the multilayer ceramic capacitors described in any one of the following,

[0143] The spacer contains phenolic resin.

[0144] <7>

[0145] according to <1> to <6> The described multilayer ceramic capacitors, among which,

[0146] The spacer contains epoxy resin.

[0147] <8>

[0148] according to <1> to <7> The described multilayer ceramic capacitors, among which,

[0149] The spacer contains rosin.

[0150] <9>

[0151] according to <1> to <8> Among the laminated ceramic electronic components described in any one of them,

[0152] A reinforcing member is disposed between the two spacers, the reinforcing member covering at least a portion of the two spacers and at least a portion of the main surface of the laminate.

[0153] <10>

[0154] according to <9> The described laminated ceramic electronic components, among which,

[0155] The reinforcing member covers the side circumferential surfaces of the two spacers.

[0156] <11>

[0157] A stacked ceramic electronic component, comprising:

[0158] A laminate includes an inner layer in which dielectric layers and internal electrode layers are alternately stacked, and has two main faces opposite each other in the stacking direction, two end faces opposite each other in the length direction intersecting the stacking direction, and two side faces opposite each other in the width direction intersecting the stacking direction and the length direction.

[0159] Two external electrodes are respectively connected to the internal electrode layer at the two end faces, and cover a portion of the end faces and two opposing side faces connected to the end faces; and

[0160] Two spacers, on one of the two sides of the laminate, are configured to sandwich the external electrode between them.

[0161] When the surface that clamps the external electrode is designated as the first side surface and the surface that does not clamp the external electrode is designated as the second side surface among the two opposing surfaces formed on the spacer in the width direction,

[0162] The angle between the second side of the spacer and the side of the laminate on which the spacer is disposed is less than 5 degrees when viewed from the width direction.

[0163] <12>

[0164] according to <11> The described laminated ceramic electronic components, among which,

[0165] When the spacer is viewed from the stacking direction, the length of the first side in the length direction is less than 95% or more than 105% of the length of the second side in the length direction.

[0166] <13>

[0167] according to <11> or <12> The described laminated ceramic electronic components, among which,

[0168] When the spacer is viewed from the stacking direction, the length of the central portion in the width direction is shorter than the length of the first side and the length of the second side.

[0169] <14>

[0170] according to <11> to <13> Among the laminated ceramic electronic components described in any one of them,

[0171] The spacer contains resin.

[0172] <15>

[0173] according to <11> to <14> The ceramic capacitor described in any one of the following, among which,

[0174] The spacer contains copper and glass.

[0175] <16>

[0176] according to <11> to <15> Among the multilayer ceramic capacitors described in any one of the following,

[0177] The spacer contains phenolic resin.

[0178] <17>

[0179] according to <11> to <16> The described multilayer ceramic capacitors, among which,

[0180] The spacer contains epoxy resin.

[0181] <18>

[0182] according to <11> to <17> The described multilayer ceramic capacitors, among which,

[0183] The spacer contains rosin.

[0184] <19>

[0185] according to <11> to <18> Among the laminated ceramic electronic components described in any one of them,

[0186] A reinforcement is disposed between the two spacers, the reinforcement covering at least a portion of the two spacers and at least a portion of the side surface of the laminate.

[0187] <20>

[0188] according to <19> The described laminated ceramic electronic components, among which,

[0189] The reinforcing member covers the side circumferential surfaces of the two spacers.

[0190] Explanation of reference numerals in the attached figures

[0191] A main surface

[0192] A1 1st main side

[0193] A2 Second Main Side

[0194] B Side

[0195] C end face

[0196] MF metal powder

[0197] MP Metal Area

[0198] P gap

[0199] RP resin area

[0200] SA1 1st main side

[0201] SA2 2nd main side

[0202] SW side surface

[0203] 1. Multilayer ceramic capacitor

[0204] 1A capacitor body

[0205] 2-layered body

[0206] 3 External Electrodes

[0207] 4 spacers

[0208] 11 Inner layer

[0209] 12 Outer layer

[0210] 14 Dielectric layer

[0211] 15 Internal electrode layer

[0212] 30 Substrate electrode layer

[0213] 31 First plating layer

[0214] 32 Second plating layer

[0215] 40 Holding substrate

[0216] 41 Spare Part Manufacturing Paste

[0217] 50 Reinforcing Components

[0218] 51. Central Department.

Claims

1. A laminated ceramic electronic component, comprising: A laminate includes an inner layer in which dielectric layers and internal electrode layers are alternately stacked, and has two main faces opposite each other in the stacking direction, two end faces opposite each other in the length direction intersecting the stacking direction, and two side faces opposite each other in the width direction intersecting the stacking direction and the length direction. Two external electrodes are respectively connected to the internal electrode layer at the two end faces, and cover a portion of the end faces and two main surfaces connected to and opposite to the end faces; and Two spacers, on one of the two main surfaces of the laminate, are configured to sandwich the external electrode between them. When, among the two opposing surfaces of the spacer formed in the stacking direction, the surface that sandwiches the external electrode is designated as the first main surface, and the surface that does not sandwich the external electrode is designated as the second main surface, The angle between the second main surface of the spacer and the main surface of the laminate on which the spacer is disposed, when viewed from the width direction, is less than 5 degrees.

2. The laminated ceramic electronic component according to claim 1, wherein, When the spacer is viewed from the width direction, the length of the first main surface in the length direction is less than 95% or more than 105% of the length of the second main surface in the length direction.

3. The laminated ceramic electronic component according to claim 1 or 2, wherein, When the spacer is viewed from the width direction, the length of the central portion in the stacking direction is shorter than the length of the first main surface and the length of the second main surface in the length direction.

4. The laminated ceramic electronic component according to any one of claims 1 to 3, wherein, The spacer contains resin.

5. The laminated ceramic electronic component according to any one of claims 1 to 4, wherein, The spacer contains copper and glass.

6. The laminated ceramic electronic component according to any one of claims 1 to 5, wherein, The spacer contains phenolic resin.

7. The laminated ceramic electronic component according to any one of claims 1 to 6, wherein, The spacer contains epoxy resin.

8. The laminated ceramic electronic component according to any one of claims 1 to 7, wherein, The spacer contains rosin.

9. The laminated ceramic electronic component according to any one of claims 1 to 8, wherein, A reinforcing member is disposed between the two spacers, the reinforcing member covering at least a portion of the two spacers and at least a portion of the main surface of the laminate.

10. The laminated ceramic electronic component according to claim 9, wherein, The reinforcing member covers the side circumferential surfaces of the two spacers.

11. A laminated ceramic electronic component, comprising: A laminate includes an inner layer in which dielectric layers and internal electrode layers are alternately stacked, and has two main faces opposite each other in the stacking direction, two end faces opposite each other in the length direction intersecting the stacking direction, and two side faces opposite each other in the width direction intersecting the stacking direction and the length direction. Two external electrodes are respectively connected to the internal electrode layer at the two end faces, and cover a portion of the end faces and two opposing side faces connected to the end faces; and Two spacers, on one of the two sides of the laminate, are configured to sandwich the external electrode between them. When the surface that clamps the external electrode is designated as the first side surface and the surface that does not clamp the external electrode is designated as the second side surface among the two opposing surfaces formed on the spacer in the width direction, The angle between the second side of the spacer and the side of the stack on which the spacer is disposed is less than 5 degrees when viewed from the stacking direction.

12. The laminated ceramic electronic component according to claim 11, wherein, When the spacer is viewed from the stacking direction, the length of the first side in the length direction is less than 95% or more than 105% of the length of the second side in the length direction.

13. The laminated ceramic electronic component according to claim 11 or 12, wherein, When the spacer is viewed from the stacking direction, the length of the central portion in the width direction is shorter than the length of the first side and the length of the second side.

14. The laminated ceramic electronic component according to any one of claims 11 to 13, wherein, The spacer contains resin.

15. The laminated ceramic electronic component according to any one of claims 11 to 14, wherein, The spacer contains copper and glass.

16. The laminated ceramic electronic component according to any one of claims 11 to 15, wherein, The spacer contains phenolic resin.

17. The laminated ceramic electronic component according to any one of claims 11 to 16, wherein, The spacer contains epoxy resin.

18. The laminated ceramic electronic component according to any one of claims 11 to 17, wherein, The spacer contains rosin.

19. The laminated ceramic electronic component according to any one of claims 11 to 18, wherein, A reinforcement is disposed between the two spacers, the reinforcement covering at least a portion of the two spacers and at least a portion of the side surface of the laminate.

20. The laminated ceramic electronic component according to claim 19, wherein, The reinforcing member covers the side circumferential surfaces of the two spacers.

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