Hard disk access method of hard disk backboard, substrate management controller, server and storage medium

Abstract

The invention discloses a hard disk access method of a hard disk backboard, a substrate management controller, a server and a storage medium, and relates to the technical field of server hardware management, and the method comprises the following steps: accessing a register of a programmable logic device with a first preset fixed address in a target hard disk backboard, and obtaining topological information of the target hard disk backboard; determining a target hard disk adaptation type of the target hard disk backboard from a plurality of hard disk adaptation types based on the NVME support state of each port contained in the topological information; and accessing the in-place target hard disk based on the access strategy information matched with the target hard disk adaptation type. The problem of high coupling of the BMC code and the hard disk backboard adaptation type is effectively solved, and the flexibility and expandability of server hardware adaptation are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of server hardware management, and particularly relates to a hard disk access method of a hard disk backboard, a baseboard management controller, a server and a storage medium. BACKGROUND

[0002] In a server system, a BMC (Baseboard Management Controller) is used for monitoring, managing and maintaining various hardware devices inside the server. Among them, the hard disk backboard as a key hardware device connecting the server mainboard and the hard disk directly affects the stability of the server in accessing the hard disk.

[0003] In the related art, the adaptation of the BMC and the hard disk backboard mainly adopts a code coupling method. The BMC describes the topology information of the hard disk backboard through a data structure defined in the internal code, which specifically includes the number of hard disks, the interface type, the connection mode and other parameters. However, when a new hard disk backboard needs to be added or replaced, since different models or specifications of hard disk backboards have differences in topology structure, the static content contained in the data structure defined in the internal code of the BMC does not match the topology information of the new hard disk backboard, and the internal code of the BMC must be modified to adapt to the topology information of the new hard disk backboard. Therefore, the traditional code coupling method has low compatibility and scalability for hardware adaptation. SUMMARY

[0004] The present application provides a hard disk access method of a hard disk backboard to at least solve the problem of low compatibility and scalability of the hard disk backboard in the related art.

[0005] In a first aspect, an embodiment of the present application provides a hard disk access method of a hard disk backboard. A baseboard management controller pre-stores a first preset fixed address, a plurality of hard disk adaptation types and access strategy information matched with each hard disk adaptation type. Each hard disk adaptation type includes an NVME hard disk adaptation type, a serial interface hard disk adaptation type and a hybrid hard disk adaptation type. The hard disk access method of a hard disk backboard includes: accessing a register of a programmable logic device with the first preset fixed address in a target hard disk backboard to obtain topology information of the target hard disk backboard. The topology information includes the number of ports of the target hard disk backboard, the NVME support state of each port and the hard disk in-place information of each port; based on the NVME support state of each port contained in the topology information, determining a target hard disk adaptation type of the target hard disk backboard from the plurality of hard disk adaptation types; based on the access strategy information matched with the target hard disk adaptation type, accessing the target hard disk in place.

[0006] In a second aspect, embodiments of the present application provide a baseboard management controller configured to implement the hard disk access method of the hard disk backplane according to any of the embodiments of the first aspect.

[0007] In a third aspect, embodiments of the present application provide a server comprising at least one hard disk backplane and a baseboard management controller; The at least one hard disk backplane is provided with a programmable logic device having a first preset fixed address, at least one I2C switch having a second preset fixed address, and an electrically erasable programmable read-only memory having a third preset fixed address. The baseboard management controller is configured to implement the hard disk access method of the hard disk backplane according to any of the embodiments of the first aspect.

[0008] In a fourth aspect, embodiments of the present application provide a computer readable storage medium having a computer program stored thereon, the computer program being configured to implement the steps of the hard disk access method of the hard disk backplane according to any of the embodiments of the first aspect when executed by a processor.

[0009] The present application also provides a computer program product comprising a computer program configured to implement the steps of the hard disk access method of the hard disk backplane according to any of the embodiments of the first aspect when executed by a processor.

[0010] By unifying the addresses of the programmable logic devices of the hard disk backplanes of different hard disk adaptation types, and pre-storing the addresses in the code of the BMC, the BMC can parse the topology information of the hard disk backplanes of all hard disk adaptation types based on the fixed addresses. In the case of replacing or adding a hard disk backplane, the BMC can identify the hard disk backplanes of NVME hard disk adaptation type, SATA / SAS hard disk adaptation type and mixed hard disk adaptation type without modifying the BMC code, effectively solving the problem of high coupling between the BMC code and the hard disk backplane adaptation type, and improving the flexibility and scalability of server hardware adaptation. BRIEF DESCRIPTION OF DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present application, the drawings required in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0012] Figure 1 A hard disk access method of a hard disk backplane according to an embodiment of the present application is provided. Figure 2 A flowchart of a hard disk access method of a hard disk backplane according to an embodiment of the present application is provided. Figure 3 Flowchart for configuration information involving I2C switch in some embodiments; Figure 4 Flowchart for temperature information in some embodiments; Figure 5 Logic diagram for BMC connecting with multiple hard disk backplanes through multiple I2C buses in some embodiments; Figure 6 Logic diagram for BMC connecting with multiple hard disk backplanes indirectly through bus I2C switch connected with I2C bus in some embodiments. DETAILED DESCRIPTION

[0013] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0014] It should be noted that, in the description of the present application, the terms "comprise", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. The terms "first", "second" and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0015] In order for those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0016] In conjunction with the specific application environment architecture or specific hardware architecture on which the hard disk access method of the hard disk backplane of the embodiments of the present application depends, the specific application environment architecture or specific hardware architecture is described here.

[0017] In a first aspect, the embodiments of the present application provide a hard disk access method of a hard disk backplane. The method can be applied to, for example Figure 1The application environment shown. Among them, the server 100 includes a BMC 110 and a hard disk backboard 120, wherein the hard disk backboard 120 has a first preset fixed address. The BMC 110 can communicate with the hard disk backboard 120 through the I2C bus to access the hard disk connected on the hard disk backboard 120. The first preset fixed address, a plurality of hard disk adaptation types and the access strategy information matched with each hard disk adaptation type are pre-stored in the BMC 110; each hard disk adaptation type includes an NVME hard disk adaptation type, a serial interface hard disk adaptation type and a hybrid hard disk adaptation type. The programmable logic device with the first preset fixed address is arranged on the hard disk backboard 120, and the BMC 110 can identify the hard disk adaptation type of the hard disk backboard 120 by accessing the topology information of the hard disk backboard 120 stored in the register in the programmable logic device, and access different types of hard disks connected on the hard disk backboard 120.

[0018] Of course, the container image cleaning method provided by the embodiments of the present disclosure can also be applied to more unillustrated scenarios.

[0019] The hard disk access method based on the hard disk backboard is applied to Figure 1 The BMC 110 in the server 100 is taken as an example for illustration. In some embodiments, as shown in Figure 2 The hard disk access method based on the hard disk backboard includes steps S210 to S230 that can be executed by the BMC 110. Each step is described below.

[0020] Step S210: Access the register of the programmable logic device with the first preset fixed address in the target hard disk backboard to obtain the topology information of the target hard disk backboard.

[0021] Among them, the topology information includes the number of ports of the target hard disk backboard, the NVME support state of each port and the hard disk in-place information of each port.

[0022] The first preset fixed address is the address corresponding to the programmable logic device, and the address offset of the register relative to the programmable logic device is 0, so the addresses of the programmable logic device and the register can be considered the same, i.e. the register in the programmable logic device can be directly accessed according to the first preset fixed address. In some optional embodiments, the first preset fixed address stored in the BMC code can be unique, i.e. only one specific address is saved as the first preset fixed address in the data structure of the BMC code. In some optional embodiments, any one of a plurality of candidate addresses can be saved as the first preset fixed address in the data structure of the BMC code.

[0023] NVME (Non-Volatile Memory Express) is a non-volatile memory host controller interface specification, which has the advantages of low delay, high throughput, multi-queue parallel and high scalability. The hard disk supporting NVME is NVME hard disk, and the hard disk backplane port capable of connecting NVME hard disk is NVME port.

[0024] One BMC can be connected to multiple hard disk backplanes, and each hard disk backplane is installed with a programmable logic device. The target hard disk backplane is any one of the multiple hard disk backplanes. Among them, the programmable logic device can be a CPLD (Complex Programmable Logic Device), an FPGA (Field Programmable Gate Array), or an MCU (Microcontroller Unit), etc. The present application does not limit this (hereinafter, the programmable logic device is taken as an example of CPLD).

[0025] In the hardware design stage, the address of the CPLD on each hard disk backplane is fixed as a first preset fixed address, for example, 0x80 (hexadecimal number). The first preset fixed address is pre-written into the code of the BMC, and the BMC can access the CPLD of each hard disk backplane through the pre-stored first preset fixed address, so as to obtain the topology information about the hard disk backplane.

[0026] In some optional embodiments, the first preset fixed address can be arbitrarily selected according to actual conditions, and the present application does not limit this.

[0027] Step S220: Based on the NVME support state of each port contained in the topology information, the target hard disk adaptation type of the target hard disk backplane is determined from multiple hard disk adaptation types.

[0028] The support state of NVME can be obtained by analyzing the specific storage information in the register, for example, the 7th bit of a certain byte of the register is 1, which indicates that the corresponding port supports NVME, and if the bit is 0, it indicates that the corresponding port does not support NVME.

[0029] Optionally, the storage bit of the NVME support state and the 0 / 1 signal and the corresponding relationship of the NVME support state are only used as an example for illustration, and other possible ways can be used in actual application, and the present application does not limit this.

[0030] Each port supports the NVME hard disk backboard for the NVME hard disk adaptation type, and can be connected to the NVME hard disk; each port does not support NVME, and only supports the hard disk backboard of the SATA (Serial ATA) or SAS (Serial Attached SCSI) standard for the serial interface hard disk adaptation type, and can only be connected to the SATA / SAS hard disk; part of the ports support NVME, and part of the ports only support the hard disk backboard of the SATA / SAS for the mixed hard disk adaptation type, and can be connected to the NVME hard disk and the SATA / SAS hard disk at the same time.

[0031] In addition, the port supporting the NVME hard disk usually has good downward compatibility and can also be connected to the SATA / SAS hard disk.

[0032] Step S230: Access the target hard disk in place based on the access policy information matched with the target hard disk adaptation type.

[0033] The pre-stored code in the BMC contains access policy information of different hard disk adaptation types, which corresponds to the hardware design rules of the hard disk backboard, and the access policy information specifically includes the access address of the CPLD and the like.

[0034] By unifying the CPLD addresses of the hard disk backboards of different hard disk adaptation types and pre-storing the addresses in the code of the BMC, the BMC can parse the topology information of the hard disk backboards of all hard disk adaptation types based on the fixed address in the fixed code. In the case of replacing or adding the hard disk backboard, the BMC code does not need to be modified to identify the hard disk backboard of the NVME hard disk adaptation type, the SATA / SAS hard disk adaptation type and the mixed hard disk adaptation type, effectively solving the problem of high coupling between the BMC code and the hard disk backboard adaptation type, and improving the flexibility and scalability of the server hardware adaptation.

[0035] In some embodiments, as shown in Figure 3 When the BMC 110 performs step S230, it can also include steps S231 to S232.

[0036] Step S231: If the target hard disk adaptation type is the NVME hard disk adaptation type or the mixed hard disk adaptation type, the configuration information of the I2C switch is determined based on the number of NVME hard disks in place.

[0037] The configuration information at least includes the number of I2C switches, the model of I2C switch and the address of I2C switch.

[0038] I2C (Inter-Integrated Circuit) is a simple, flexible and widely supported serial communication protocol, suitable for short-distance data transmission between electronic devices. I2C switch is an integrated circuit used to expand the number of I2C bus connected devices, which realizes communication between the host controller and multiple devices through multi-channel switching.

[0039] The number of NVME ports supported by the hard disk backplane represents the number of NVME hard disks that the hard disk backplane can dock.

[0040] In the hardware design stage of the hard disk backplane, according to the number of NVME hard disks that the hard disk backplane can dock, the configuration information of the I2C switch is determined, and the I2C configuration information is written into the BMC code. After the BMC identifies the NVME hard disk adaptation type and the hybrid hard disk adaptation type, the configuration information of the I2C switch is parsed, and according to the number of NVME hard disks currently in place, one or more different models of I2C switch access channels are switched to access each NVME hard disk.

[0041] Step S232: Determine the access channel corresponding to each NVME hard disk according to the configuration information of the I2C switch, and access the NVME hard disk based on the access channel.

[0042] In some specific embodiments, an I2C switch can include multiple access channels, and each access channel can communicate with a port of the hard disk backplane. BMC can control the opening and closing state of multiple access channels of I2C switch by accessing the address of I2C switch, and access the port of the hard disk backplane through the opened access channel, so as to access the NVME hard disk in place.

[0043] Generally, multiple access channels of I2C switch follow a serial working mode, that is, only one access channel of I2C switch can be in an open state at the same time, and other access channels must be in a closed state. Although this serial working mode limits the parallel communication capability, it can guarantee the uniqueness and accuracy of I2C bus data transmission, and effectively avoid system abnormalities caused by signal confusion.

[0044] In some embodiments, when BMC 110 performs step S231, it can also include steps S231-A to S231-C (not shown).

[0045] Step S231-A: If the number of NVME hard disks in place is not greater than the first preset number threshold, determine the number of I2C switches to be one and the model of I2C switch to be the first model.

[0046] The number of channels corresponding to the first model is the first preset number threshold.

[0047] In some specific embodiments, there are various models of I2C switches, typically including CA9545 (4 channels), CA9548 (8 channels), and PCA9546APW (4 channels) with reset function and TCA9548APWR (8 channels) with reset function. Each I2C channel can communicate with a port of a hard disk backplane, and the number of NVME hard disks can determine one or more different models of I2C switches to achieve various channel combinations to interface with multiple ports of the hard disk backplane.

[0048] For example, if the number of in-place NVME hard disks is not greater than 4 (the first preset number threshold), it can be determined that one I2C switch needs to be enabled, and the I2C switch model is 4-channel CA9545 or PCA9546APW. Using one 4-channel I2C switch can meet the access requirements of NVME hard disks with a number not greater than 4.

[0049] Step S231-B: If the number of in-place NVME hard disks is greater than the first preset number threshold and not greater than the second preset number threshold, it is determined that the number of I2C switches is one, and the I2C switch model is the second model.

[0050] Among them, the channel number corresponding to the second model is the second preset number threshold.

[0051] For example, if the number of in-place NVME hard disks is greater than 4 (the first preset threshold) and not greater than 8 (the second preset threshold), it can be determined that one I2C switch needs to be enabled, and the I2C switch model is 8-channel CA9548 or TCA9548APWR. Using one 8-channel I2C switch can meet the access requirements of NVME hard disks with a number greater than 4 and less than 8.

[0052] Step S231-C: If the number of in-place NVME hard disks is greater than the second preset number threshold, it is determined that the number of I2C switches is the number of NVME hard disks divided by the second preset number, and the I2C switch model is the second model.

[0053] For example, if the number of in-place NVME hard disks is greater than 8 (the second preset number threshold), it can be determined that the number of I2C switches that need to be enabled is the number of NVME hard disks divided by 8, and the model of the I2C switch is the model contained in the 8-channel I2C switch.

[0054] For example, assuming that the number of in-place NVME hard disks is 10, it can be determined that the number of I2C switches that need to be enabled is ⌈10 / 8⌉=2, and using two 8-channel I2C switches can meet the access requirements of NVME hard disks with a number greater than 8.

[0055] In some optional embodiments, when the number of in-place NVME hard disks is greater than 8, a plurality of 4-channel I2C switches can also be combined to realize access channels of more than 8 channels, and the present application does not limit this.

[0056] Notably, in order to facilitate the management and maintenance of hardware devices by developers or maintenance personnel, when the number of in-place NVME hard disks is greater than 8, a 4-channel I2C switch is usually not combined with an 8-channel I2C switch, but a I2C switch with the same number of basic channels is preferred.

[0057] Specifically, as the core communication hub between the BMC and the hard disk backplane ports, the number of channels and the combination mode of the I2C switch directly affect the complexity of overall hardware management. If a 4-channel I2C switch is combined with an 8-channel I2C switch, the difference in channel capacity between the two types of I2C switches will cause the mapping logic of the ports and channels to be fragmented, bringing multiple inconveniences to hardware management.

[0058] For example, when 12 NVME ports need to be managed, if one 8-channel I2C switch and one 4-channel I2C switch are used, the developer needs to separately design different channel calculation methods for the two types of I2C switches when writing BMC code, and a large number of conditional judgment statements need to be added to the code to distinguish between the two types of I2C switches, which not only increases code redundancy, but also may cause channel matching errors due to logical omissions. Moreover, the mixed combination will increase the difficulty of troubleshooting for maintenance personnel. When a NVME port communication is abnormal, the maintenance personnel need to first determine whether the port corresponds to a 4-channel I2C switch or an 8-channel I2C switch, and then consult the hardware manuals and channel test procedures of the two types of I2C switches respectively, which cannot form a unified troubleshooting standard, especially when multiple groups of mixed I2C switches are deployed in a server, the troubleshooting efficiency will decrease significantly.

[0059] However, by combining I2C switches with the same number of basic channels, there is no need to design differential logic in the BMC code, and only a unified calculation module needs to be called to achieve accurate matching of ports and channels, and the code structure is more concise. In addition, the combination of I2C switches with the same number of channels also provides convenience for subsequent hardware expansion. If the number of NVME hard disks increases to 24 in the future, only the same number of I2C switches need to be added, and the original mapping logic can be used, without the need to restructure the hardware connection and software code, further reducing long-term operation and maintenance costs.

[0060] In some embodiments, when the BMC 110 performs step S231, it can also include steps S231-D to S231-E (not shown).

[0061] Step S231-D: If the number of I2C switches is one, determine that the I2C switch address is a second preset fixed address.

[0062] Specifically, in the hardware design stage of the hard disk backplane, when it is determined that the number of I2C switches is one, the address of the I2C switch is fixed as a second preset fixed address, for example, 0xE2, and the second preset fixed address is written into the code of the BMC.

[0063] In the process of communication between the BMC and the target hard disk backplane, when the BMC identifies the number of NVMEs on the target hard disk backplane, the number of I2C switches to be enabled is determined, and then the I2C switches can be accessed according to the second preset fixed address pre-stored in the code, so as to control each channel of the I2C switches.

[0064] Step S231-E: If the number of I2C switches is greater than one, the second preset fixed address is taken as a starting address, and each I2C switch address is incremented by a preset interval.

[0065] Specifically, in the hardware design stage of the hard disk backplane, when it is determined that the number of I2C switches is greater than one, the address of the first I2C switch is fixed as a second preset fixed address (for example, 0xE2), and the second preset fixed address is taken as a reference address of the entire I2C switch group, and the addresses of the subsequent I2C switches are allocated in turn according to the rule of incrementing by an interval of 2 bytes.

[0066] For example, the next address (for example, 0xE4) spaced by 2 bytes from the second preset fixed address is taken as the fixed address of the second I2C switch, and the next address (for example, 0xE6) spaced by 4 bytes from the second preset fixed address is taken as the fixed address of the third I2C switch, and so on, and the second preset fixed address and the preset interval are written into the code of the BMC. The preset interval is 2 bytes.

[0067] In the process of communication between the BMC and the target hard disk backplane, when the BMC identifies the number of NVMEs on the target hard disk backplane, the number of I2C switches to be enabled is determined, and then each I2C switch can be accessed according to the pre-stored second preset fixed address and the preset interval in the code, so as to control each channel of each I2C switch.

[0068] Through the fixed-interval address allocation, address conflicts of multiple I2C switches on the same I2C bus can be avoided, and it is ensured that the control instructions sent by the BMC can be received by a unique I2C switch. At the same time, the standardized address increment rule makes the BMC code not need to store a complex address mapping table, but only needs to directly calculate the target address through the I2C switch serial number, which greatly simplifies the logic of address calling in the code and reduces the development difficulty.

[0069] In addition, the interval unit of 2 bytes is selected based on the address characteristics of the I2C protocol: the I2C device address is usually 7 bits or 10 bits. Taking the common 7-bit address as an example, the 2-byte interval (i.e., the binary address increment of 10) can not only ensure efficient use of the address space, but also reserve sufficient address offset for each switch to avoid exhausting the available address resources due to subsequent expansion of more switches.

[0070] In some optional embodiments, the second preset fixed address can be arbitrarily selected according to actual conditions, and the present application does not limit this.

[0071] By determining the model and number of I2C switches according to the number of NVME hard disks in the hardware design stage, unifying the addresses of I2C switches in different hard disk backplanes to a fixed address, and pre-storing the configuration information of I2C switches to the code of BMC, the BMC can access the I2C switch based on the fixed address, thereby realizing the access of each NVME port in the hard disk backplane of different hard disk adaptation types.

[0072] In some embodiments, when performing step S232, the BMC 110 can further include step S232-A (not shown).

[0073] Step S232-A: calculating the remainder of the port number of the target port divided by the number of channels corresponding to the I2C switch model; and taking the target channel with the channel number as the remainder as the access channel of the target port.

[0074] Wherein, the target port is any one of the ports.

[0075] Under normal circumstances, the multiple channels of an I2C switch are sequentially corresponding to the multiple ports of the hard disk backplane according to the serial number, for example, the channels 1 to 8 of an 8-channel I2C switch are respectively corresponding to the ports 1 to 8 of the hard disk backplane. When the number of ports of the hard disk backplane exceeds the channel capacity of a single I2C switch, a second I2C switch is introduced for channel expansion. For example, the channels 1 to 8 of the second 8-channel I2C switch are respectively corresponding to the ports 9 to 16 of the hard disk backplane. Multiple I2C switches are combined until the number of channels is greater than or equal to the number of ports of the hard disk backplane.

[0076] Specifically, when determining the access channel corresponding to the target port, the numbering method of the access channel is x=Port ID mod M, where x is the channel number of the access channel corresponding to the target port, Port ID is the port number of the target port, and M is the number of channels corresponding to the I2C switch (usually 4 or 8).

[0077] It should be noted that when determining the access channel corresponding to the target port, the BMC also determines the I2C switch to which the access channel corresponding to the target port belongs, including determining the address of the I2C switch.

[0078] According to the content described in the foregoing step S231-E, the addressing formula of the I2C switch can be Addr = 0xE2 + 2 x (Port ID / M), where Addr is the address of each I2C switch.

[0079] Exemplarily, assuming that the number of channels corresponding to the I2C switch designed on the target hard disk backplane is 4, and the port number of the target port is 3, then the channel number of the access channel corresponding to the target port is 3 mod 4 = 3, and the address of the I2C switch to which the access channel belongs is 0xE2 + 2 x (3 / 4) = 0xE2, that is, the access channel corresponding to the target port is Channel 3 of the first I2C switch.

[0080] For another example, assuming that the number of channels corresponding to the I2C switch designed on the target hard disk backplane is 8, and the port number of the target port is 17, then the channel number of the access channel corresponding to the target port is 17 mod 8 = 3, and the address of the I2C switch to which the access channel belongs is 0xE2 + 2 x (17 / 8) = 0xE6, that is, the access channel corresponding to the target port is Channel 3 of the third I2C switch.

[0081] The combination determination mode of the I2C switch address and the channel number can accurately locate any port, effectively avoiding the problem of channel and port mapping confusion that may occur when multiple switches are used in parallel, and at the same time, leaving clear serial number expansion space for subsequent hardware expansion.

[0082] By recording the calculation mode of the access channel corresponding to each port in the BMC code, the BMC code structure is simple and clear, and the difficulty of later maintenance and upgrading is significantly reduced, thereby reducing the maintenance cost of the server.

[0083] In some optional embodiments, the BMC 110 can further perform step S240: accessing an electrically erasable programmable read-only memory with a third preset fixed address in the target hard disk backplane to obtain temperature information of the target hard disk backplane, so as to monitor the temperature of the target hard disk backplane.

[0084] In some specific embodiments, as shown in Figure 4 Step S240 further includes steps S241 to S242.

[0085] Step S241: determining a sensor address of a temperature sensor from the electrically erasable programmable read-only memory according to the third preset fixed address and a preset temperature address offset.

[0086] The third preset fixed address, along with the first and second preset fixed addresses mentioned above, are all physical addresses of hardware components, sharing the same format but differing in content.

[0087] Specifically, an electrically erasable programmable read-only memory (EEPROM) is installed on the hard drive backplane. During the hardware design phase of the hard drive backplane, the address of the EEPROM is fixed to a third preset fixed address, such as 0x0A, and the third fixed address is written into the code of the BMC. The BMC can directly read the EEPROM according to the pre-stored code.

[0088] The EEPROM stores the sensor address of the temperature sensor.

[0089] In some optional embodiments, temperature sensors, as core components for monitoring the temperature of the hard drive backplane, may increase in number as the number of hard drive backplanes increases. To ensure that the BMC can accurately identify each temperature sensor and avoid monitoring failures due to sensor address confusion, dedicated storage space can be allocated in the EEPROM. For example, starting at an address offset of 0x1000 from the EEPROM start address 0x0A, 1KB of storage space can be allocated to centrally store the address information of all temperature sensors. Compared to distributing the address information across different hardware modules, this facilitates unified reading and management by the BMC and provides a clear address lookup basis for future sensor maintenance or replacement.

[0090] Step S242: Access the temperature sensor according to the sensor address to obtain the temperature information of the target hard disk backplane.

[0091] BMC obtains the sensor address of the temperature sensor by reading the EEPROM, and can then access the temperature sensor and read its temperature parameters to obtain the temperature information of the target hard drive backplane.

[0092] In some optional embodiments, multiple temperature sensors may be provided. The sensor addresses of each temperature sensor can be stored in the EEPROM, or the sensor addresses of each temperature sensor can be set at fixed intervals, and the sensor address of the first temperature sensor and the fixed interval can be stored in the EEPROM. In addition, the type of temperature sensor and the number of hard disk backplanes whose temperature needs to be monitored can also be stored in the EEPROM, which is not limited in this application.

[0093] By saving the address of the temperature sensor to the EEPROM and setting the EEPROM address to a fixed address, the BMC can parse the code to obtain the sensor address stored in the EEPROM, and then obtain the temperature information of the hard drive backplane, thus realizing temperature monitoring of hard drive backplanes of different hard drive adapter types.

[0094] In some embodiments, the BMC 110 may also perform step S250: according to a preset access cycle, read the register, determine the hard disk presence status of each NVME port based on the hard disk presence information of each port stored in the register, and update the open / closed state of the access channel of the I2C switch corresponding to each NVME port based on the hard disk presence status of each NVME port.

[0095] In some specific embodiments, step S250 includes step S251: if the current hard disk presence status of the target NVME port is opposite to the previous historical hard disk presence status of the target NVME port, then update the open / closed status of the access channel corresponding to the target NVME port to be opposite to the previous historical open / closed status.

[0096] The target NVME port can be any one of the various NVME ports.

[0097] For example, the BMC reads the CPLD registers every second to obtain the current hard drive presence status of each NVME port, and compares it with the previously obtained historical hard drive presence status. If the current hard drive status is not present, but the previous historical hard drive presence status was present, it means that the NVME hard drive of that NVME port has been removed, and the BMC closes the access channel of the I2C switch corresponding to that NVME port to save communication resource overhead. Conversely, if the current hard drive presence status is present, but the previous historical hard drive presence status was not present, it means that the NVME hard drive of that NVME port has been inserted, and the BMC reopens the access channel of the I2C switch corresponding to that NVME port to enable normal hard drive access.

[0098] In some embodiments, BMC 110 may also perform step S260: saving a log of hard disk presence status changes of the NVME port for maintenance of the NVME port.

[0099] The hard drive presence status change log includes at least: the NVME port number and the hard drive presence status change type.

[0100] For example, when the BMC detects that the hard drive in NVME port 6 has been removed, the BMC generates a hard drive presence status change log: "Port 6: NVME hard drive removed". Similarly, when the BMC detects that a hard drive in NVME port 6 has been inserted, it also generates a corresponding hard drive presence status change log: "Port 6: NVME hard drive inserted".

[0101] Optionally, the hard disk presence status change log may also include information such as the NVME support status of the port, and the BMC may also detect the presence status of serial interface hard disks; this application does not impose any restrictions on this.

[0102] By periodically monitoring the presence status of NVMe ports, hot-swapping of NVMe hard drives can be monitored, allowing for adaptive adjustments to the opening and closing of access channels. This balances communication resource overhead with hard drive access demands. Especially in high-density NVMe storage servers, when some ports have no hard drives connected, closing their access channels can free up significant bus resources, allowing ports with hard drives to obtain more communication bandwidth and improving data read / write efficiency. Simultaneously, a hard drive presence status change log is generated for each port. This allows maintenance personnel to quickly locate related events when port anomalies occur by reviewing the logs. Furthermore, by analyzing long-term logs, if the frequency of hard drive presence status changes on a particular NVMe port is significantly higher than on other ports, it can be predicted in advance that the port may have potential issues such as physical interface wear or poor signal contact, allowing for timely port repair or replacement and preventing hard drive offline and data access interruptions due to sudden failures.

[0103] In some embodiments, BMC 110 may also perform step S270: if the target adapter type is a serial interface hard disk adapter type or a hybrid hard disk adapter type, then based on the number of serial interface hard disks in place, directly access the serial interface hard disks corresponding to each port of the target hard disk.

[0104] Specifically, none of the ports of the serial interface hard drive adapter type support NVMe, so there is no need to access them for NVMe. Access to the serial interface hard drive does not need to go through the I2C switch access channel. The conventional access method corresponding to the serial interface hard drive can be used, such as access through the traditional AHCI protocol. This application will not elaborate on this.

[0105] Accessing serial interface hard drives is independent of the I2C communication system, which simplifies the access link and avoids the delays that may be caused by I2C bus bandwidth occupation.

[0106] It's important to note that NVMe ports are not limited to connecting NVMe protocol hard drives. Through hardware compatibility optimization and protocol adaptation, they also offer backward compatibility with serial interface hard drives (such as SATA and SAS drives). When a serial interface hard drive is plugged into an NVMe-enabled port, the system does not need to replace the hardware interface or redeploy the communication link; it can still use the existing I2C switch access channel for data interaction and device management.

[0107] In a server's hardware management architecture, the Base Management Console (BMC), as the core unit for hardware monitoring and control, typically needs to connect to multiple hard drive backplanes, such as two, four, or even more, depending on the server's storage expansion requirements. Therefore, before accessing the hard drives on a target hard drive backplane, the BMC determines the target backplane from among the multiple backplanes based on the connection methods between the BMC and the backplanes.

[0108] In one alternative embodiment, the BMC can directly connect to multiple hard disk backplanes via multiple I2C buses, wherein one I2C bus connects to one hard disk backplane. In this case, the BMC can scan multiple I2C buses and determine the target hard disk from the multiple hard disk backplanes connected by the multiple I2C buses.

[0109] The I2C bus is a simple, bidirectional, two-wire synchronous serial bus that allows devices connected to the I2C bus to transmit information.

[0110] For example, such as Figure 5 As shown, the BMC is directly connected to the hard drive backplane via the I2C bus. Specifically, the BMC is directly connected to the hard drive backplane 1 via I2C bus 1, the BMC is directly connected to the hard drive backplane 2 via I2C bus 2, the BMC is directly connected to the hard drive backplane 3 via I2C bus 3, and so on.

[0111] Because each hard drive backplane is independently connected to a different I2C bus, meaning each I2C bus is responsible for carrying communication data for only a single hard drive backplane, this "one-to-one" bus allocation mode provides the hardware foundation for parallel access. For example, at the same time, the BMC can obtain hard drive health information of hard drive backplane 1 through I2C bus 1, and also send fan speed adjustment commands to hard drive backplane 2 through I2C bus 2; in addition, it can also conduct other communication or command sending to hard drive backplane 3 through I2C bus 3. This parallel access capability not only avoids the response latency caused by the single-bus bottleneck, but also significantly improves the centralized management efficiency of the BMC for multiple hard drive backplanes, especially in scenarios where servers are equipped with a large number of hard drive backplanes, effectively ensuring the real-time performance and stability of hardware monitoring and control.

[0112] In another alternative embodiment, the BMC can be indirectly connected to multiple hard disk backplanes through the channels of a bus I2C switch connected to the I2C bus, wherein the bus I2C switch has multiple bus channels, and one hard disk backplane can be connected to one bus channel.

[0113] For example, such as Figure 6As shown, the BMC is indirectly connected to multiple hard disk backplanes through a 4-channel bus I2C switch connected to the I2C bus. Specifically, access channel 1 of the I2C switch is connected to hard disk backplane 1, access channel 2 of the I2C switch is connected to hard disk backplane 2, access channel 3 of the I2C switch is connected to hard disk backplane 3, and access channel 4 of the I2C switch is connected to hard disk backplane 4.

[0114] The bus I2C switch can be any of the types of I2C switches described above. When a 4-channel I2C switch is used as the bus I2C switch, the BMC can connect up to 4 hard drive backplanes through one I2C bus. When an 8-channel I2C switch is used as the bus I2C switch, the BMC can connect up to 8 hard drive backplanes through one I2C bus.

[0115] Since different hard drive backplanes are connected to the same I2C bus, the BMC can only access different hard drive backplanes serially by switching the I2C bus switch channels.

[0116] For example, when the BMC needs to interact with hard drive backplane A, it must first send a control command to the bus I2C switch to switch the communication channel of the bus I2C switch to Channel 1 corresponding to hard drive backplane A. Data interaction can only begin after the channel switch is completed and a stable communication is established. If access to hard drive backplane B is required subsequently, the connection of the current Channel 1 must be disconnected first, and a command must be sent to the bus I2C switch again to switch to Channel 2. Throughout this process, there is a clear sequence of access operations for different hard drive backplanes. The next hard drive backplane cannot establish communication with the BMC until the access task of the previous hard drive backplane is completed and the channel is switched. This serial access mode simplifies bus wiring and reduces hardware costs.

[0117] It should be noted that the addresses of the bus I2C switches connecting multiple hard drive backplanes must not be the same as the addresses of the multiple I2C switches corresponding to the target hard drive backplane described above. This is to avoid the problem of different I2C switches being unable to be accessed and controlled individually, which could lead to communication chaos and data corruption.

[0118] When the BMC connects to multiple hard drive backplanes, since each hard drive backplane has a CPLD with a first preset fixed address, at least one I2C switch with a second preset fixed address, and an EEPROM with a third preset fixed address, the BMC only needs to parse the fixed code to identify and access different hard drive backplanes. When adding or replacing a hard drive backplane, there is no need to modify the BMC code.

[0119] The following specific examples will be used to further explain the method for accessing the hard drive backplane.

[0120] Example 1: The target hard drive backplane is an NVMe hard drive adapter type, with 2 ports and 2 NVMe hard drives already inserted.

[0121] (1) The BMC sends a read command to the CPLD with a fixed address of 0x80 on the target hard disk backplane via the I2C bus. The CPLD responds to the read command and returns the topology information stored in the register to the BMC. After parsing, the BMC determines that each Port supports NVME, and two of the ports have been plugged into NVME hard disks.

[0122] (2) Based on the number of NVME hard drives in place, the BMC determines the corresponding I2C switch model as PCA9546APW (4 channels) and the corresponding I2C switch address as 0xE2. The BMC controls the I2C switch to switch to Channel 1 and Channel 2 respectively to access the NVME hard drives on Port 1 and Port 2, thereby realizing data interaction for monitoring the status of these two NVME hard drives.

[0123] (3) The BMC accesses the EEPROM at address 0x0A via the I2C bus, reads that there is one temperature sensor in the EEPROM, the sensor type is EMC1413, and the sensor address of the temperature sensor is 0x98. The BMC sends a temperature read command to address 0x98 to obtain temperature data and completes the temperature monitoring of the target hard disk backplane.

[0124] (4) The BMC reads the CPLD register every second. When it detects that the NVME hard drive in Port 2 has been removed, it generates a hard drive presence status change log: "Port 2: NVME hard drive removed, NVME supported". At the same time, the BMC stops accessing Port 2 through Channel 2 of the I2C switch. After a period of time, when the BMC detects that a new NVME hard drive has been inserted into Port 2, the BMC generates a new hard drive presence status change log: "Port 2: NVME hard drive inserted, NVME supported", and resumes accessing the new hard drive in Port 2 through Channel 2 of the I2C switch.

[0125] Example 2: The target hard drive backplane is a serial interface hard drive adapter type, with a total of 6 ports and 6 SATA / SAS hard drives already inserted.

[0126] (1) The BMC sends a read command to the CPLD with a fixed address of 0x80 on the target hard disk backplane via the I2C bus. The CPLD responds to the read command and returns the topology information stored in the register to the BMC. After parsing, the BMC determines that none of the Ports support NVME, and six of the ports have been plugged into SATA / SAS hard disks.

[0127] (2) Since none of the ports support NVMe, the BMC does not need to perform channel switching and access operations for NVMe-related I2C switches, and manages them according to the conventional access methods of SATA / SAS. The conventional access methods of SATA / SAS can be found in existing related technologies, which will not be elaborated here.

[0128] (3) The BMC accesses the EEPROM at address 0x0A via the I2C bus, reads the number of temperature sensors stored in the EEPROM as 1, the sensor type as EMC1413, and the sensor address as 0x98. The BMC sends a temperature read command to address 0x98 to obtain temperature data and completes the temperature monitoring of the target hard disk backplane.

[0129] (4) The BMC reads the CPLD register every second. When it detects that the SATA hard drive in Port 5 has been removed, it generates a hard drive presence status change log: "Port 5: SATA / SAS hard drive removed, NVME not supported". At the same time, the BMC stops regular access to Port 5. After a period of time, when the BMC detects that a new SAS hard drive has been inserted into Port 5, the BMC generates a new hard drive presence status change log: "Port 2: SATA / SAS hard drive inserted, NVME not supported", and resumes regular access to the new hard drive in Port 5.

[0130] Example 3: The target hard drive backplane is an NVMe hard drive adapter type, with 10 ports and 10 NVMe hard drives already inserted.

[0131] (1) The BMC sends a read command to the CPLD with a fixed address of 0x80 on the target hard disk backplane via the I2C bus. The CPLD responds to the read command and returns the topology information stored in the register to the BMC. After parsing, the BMC determines that each Port supports NVME, and 10 ports have been plugged into NVME hard disks.

[0132] (2) Based on the number of NVMe hard drives in place, the BMC determines that two I2C switches of model TCA9548APWR (8 channels) are needed, with corresponding I2C switch addresses of 0xE2 and 0xE4, respectively. For Port 1 to Port 8, the I2C switch with BMC control address 0xE2 switches to Channel 1 and Channel 8 for access, respectively. For Port 9 to Port 10, the I2C switch with BMC control address 0xE4 switches to Channel 1 and Channel 2 for access, thereby achieving full access to all 10 NVMe hard drives.

[0133] (3) The BMC accesses the EEPROM at address 0x0A via the I2C bus, reads the number of temperature sensors stored in the EEPROM as 1, the sensor type as EMC1413, and the sensor address as 0x98. The BMC sends a temperature read command to address 0x98 to obtain temperature data and completes the temperature monitoring of the target hard disk backplane.

[0134] (4) The BMC reads the CPLD register every second. When it detects that the NVME hard drive in Port 2 has been removed, it generates a hard drive presence status change log: "Port 2: NVME hard drive removed, NVME supported". At the same time, the BMC stops accessing Port 2 through Channel 2 of the I2C switch. After a period of time, when the BMC detects that a new NVME hard drive has been inserted into Port 2, the BMC generates a new hard drive presence status change log: "Port 2: NVME hard drive inserted, NVME supported", and resumes accessing the new hard drive in Port 2 through Channel 2 of the I2C switch.

[0135] Example 4: The target hard drive backplane is a hybrid hard drive adapter type with a total of 8 ports, which can be used to insert 4 NVMe hard drives and 4 SATA hard drives respectively.

[0136] (1) The BMC sends a read command to the CPLD with a fixed address of 0x80 on the target hard disk backplane via the I2C bus. The CPLD responds to the read command and returns the topology information stored in the register to the BMC. After parsing, the BMC determines that Port 1 to Port 4 support NVME and that an NVME hard disk has been inserted, while Port 5 to Port 8 do not support NVME.

[0137] (2) Based on the number of NVMe hard drives in place (4), the BMC determines to use a PCA9546APW (4-channel) I2C switch with the corresponding I2C switch address 0xE2. For Port 1 to Port 4, the BMC controls the I2C switch with address 0xE2 to switch to Channel 1 and Channel 4 respectively to access the NVMe hard drives. For Port 5 to Port 8, since NVMe is not supported, no NVMe-related access is performed, and the SATA hard drives are managed in the conventional access mode.

[0138] (3) The BMC accesses the EEPROM at address 0x0A via the I2C bus, reads the number of temperature sensors stored in the EEPROM as 1, the sensor type as EMC1413, and the sensor address as 0x98. The BMC sends a temperature read command to address 0x98 to obtain temperature data and completes the temperature monitoring of the target hard disk backplane.

[0139] (4) The BMC reads the CPLD register every second. When it detects that the NVME hard drive in Port 3 has been removed, it generates a hard drive presence status change log: "Port 3: NVME hard drive removed, NVME supported". At the same time, the BMC stops accessing Port 3 through Channel 3 of the I2C switch. When the BMC detects that the SATA hard drive in Port 6 has been removed, the BMC generates a hard drive presence status change log: "Port 6: SATA hard drive removed, NVME not supported", and stops regular access to it.

[0140] This application standardizes the information storage specifications of CPLD (fixed address 0x80) and EEPROM (fixed address 0x0A), and clarifies the dynamic matching rules between I2C switch model, address, and the number of NVMe hard drives. This provides a hardware foundation for automatic BMC resolution. When a hard drive backplane is replaced or added, the BMC reads the CPLD and EEPROM information according to the fixed address, and can automatically identify the I2C switch model and address according to the rules, and adjust the control logic of the access channel. The entire process does not require manual modification of the BMC code, breaking through the limitations of traditional code coupling, greatly improving the compatibility of the BMC with different hard drive backplanes, and reducing the cost of later hardware upgrades and maintenance.

[0141] It should be understood that, although Figures 2 to 4 The steps in the flowchart are shown sequentially according to the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Figures 2 to 4 Unless otherwise expressly stated herein, the steps illustrated and other steps involved in the embodiments are not subject to strict order restrictions and may be performed in other orders. Furthermore, at least some steps in the foregoing embodiments may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but may be performed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0142] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0143] In a second aspect, embodiments of this application provide a baseboard management controller for implementing the hard disk access method for the hard disk backplane provided in any embodiment of the first aspect of this application.

[0144] In a third aspect, embodiments of this application provide a server including at least one hard disk backplane and a baseboard management controller; At least one hard disk backplane is provided with a programmable logic device with a first preset fixed address, at least one I2C switch with a second preset fixed address, and an electrically erasable programmable read-only memory with a third preset fixed address. The baseboard management controller is used to implement the hard disk access method for the hard disk backplane provided in any embodiment of the first aspect of this application.

[0145] In some embodiments, the server further includes: an electrically erasable programmable read-only memory storing the sensor address of a temperature sensor, the temperature sensor being used to detect temperature information of at least one hard disk backplane.

[0146] In some embodiments, the server further includes: at least one hard disk backplane directly connected to the baseboard management controller via at least one I2C bus, wherein one I2C bus is connected to one hard disk backplane.

[0147] In some embodiments, the server further includes: at least one hard disk backplane is indirectly connected to the baseboard management controller via a channel of a bus I2C switch connected to the I2C bus; wherein the bus I2C switch has multiple bus channels, and one bus channel is connected to one hard disk backplane.

[0148] In a fourth aspect, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the hard disk access method for a hard disk backplane provided in any embodiment of the first aspect of this application.

[0149] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0150] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The aforementioned computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments of this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0151] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0152] The above embodiments merely illustrate several implementation methods of this application, and their descriptions are quite specific and detailed, but they should not be construed as limiting the scope of protection of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the scope of protection of this application.

Claims

1. A hard disk access method for a hard disk backplane, applied to a baseboard management controller, characterized in that, The baseboard management controller pre-stores a first preset fixed address, multiple hard disk adapter types, and access policy information matching each hard disk adapter type; each hard disk adapter type includes NVME hard disk adapter type, serial interface hard disk adapter type, and hybrid hard disk adapter type; the method includes: Access the register of the programmable logic device with the first preset fixed address in the target hard disk backplane to obtain the topology information of the target hard disk backplane; the topology information includes the number of ports of the target hard disk backplane, the NVME support status of each port, and the hard disk presence information of each port; Based on the NVME support status of each port contained in the topology information, the target hard drive adapter type of the target hard drive backplane is determined from the multiple hard drive adapter types. Access the in-place target hard drive based on the access policy information that matches the target hard drive adaptation type.

2. The method as described in claim 1, characterized in that, The access to the in-place target hard drive based on the access policy information matching the target hard drive adaptation type includes: If the target hard drive adapter type is the NVME hard drive adapter type or the hybrid hard drive adapter type, then the configuration information of the I2C switch is determined based on the number of NVME hard drives in place; the configuration information includes at least the number of I2C switches, the I2C switch model, and the I2C switch address; The access channel corresponding to each NVMe hard drive is determined based on the configuration information of the I2C switch, and the NVMe hard drive is accessed based on the access channel.

3. The method as described in claim 2, characterized in that, The determination of I2C switch configuration information based on the number of in-situ NVMe hard drives includes: If the number of NVMe hard drives in place is not greater than the first preset number threshold, then the number of I2C switches is determined to be one, and the I2C switch model is the first model; the number of channels corresponding to the first model is the first preset number threshold. If the number of NVMe hard drives in place is greater than the first preset number threshold and not greater than the second preset number threshold, then the number of I2C switches is determined to be one, and the I2C switch model is the second model; wherein, the number of channels corresponding to the second model is the second preset number threshold. If the number of NVMe hard drives in place is greater than the second preset number threshold, then the number of I2C switches is determined to be the number of NVMe hard drives divided by the second preset number, rounded up, and the I2C switch model is the second model.

4. The method as described in claim 3, characterized in that, The method of determining the I2C switch configuration information based on the number of in-situ NVMe hard drives also includes: If the number of I2C switches is one, then the address of the I2C switch is determined to be the second preset fixed address; If the number of I2C switches is greater than one, then the second preset fixed address is used as the starting address, and the address of each I2C switch is incremented at a preset interval.

5. The method as described in claim 2, characterized in that, The step of determining the access channel corresponding to each NVMe hard drive based on the configuration information of the I2C switch includes: Calculate the remainder when the port number of the target port is divided by the number of channels corresponding to the I2C switch model; The target channel whose channel number is the remainder is used as the access channel of the target port; wherein, the target port is any one of the ports.

6. The method as described in claim 1, characterized in that, The method further includes: The target hard disk backplane is determined based on multiple hard disk backplanes connected by multiple I2C buses; wherein, one I2C bus connects to one hard disk backplane.

7. The method as described in claim 1, characterized in that, The method further includes: The target hard disk backplane is determined based on the bus I2C switch connected to the I2C bus; wherein, the bus I2C switch corresponds to multiple bus channels, and one bus channel is connected to one hard disk backplane.

8. The method as described in claim 1, characterized in that, The method further includes: Access the electrically erasable programmable read-only memory with a third preset fixed address in the target hard disk backplane to obtain the temperature information of the target hard disk backplane, so as to monitor the temperature of the target hard disk backplane.

9. The method as described in claim 8, characterized in that, The step of accessing the electrically erasable programmable read-only memory with a third preset fixed address in the backplane of the target hard disk to obtain the temperature information of the backplane of the target hard disk includes: The sensor address of the temperature sensor is determined from the electrically erasable programmable read-only memory based on the third preset fixed address and the preset temperature address offset. Access the temperature sensor based on the sensor address to obtain the temperature information of the target hard disk backplane.

10. The method as described in claim 1, characterized in that, The method further includes: According to the preset access cycle, the register is read, and the hard disk presence status of each NVME port is determined based on the hard disk presence information of each port stored in the register. Based on the hard drive presence status of each NVME port, update the open / closed status of the access channel of the I2C switch corresponding to each NVME port.

11. The method as described in claim 10, characterized in that, The step of updating the open / closed state of the access channel corresponding to each NVMe port based on the hard drive presence status of each NVMe port includes: If the current hard drive presence status of the target NVME port is the opposite of the previous historical hard drive presence status of the target NVME port, then the open / closed status of the access channel corresponding to the target NVME port is updated to be the opposite of the previous historical open / closed status; wherein, the target NVME port is any one of the various NVME ports.

12. The method as described in claim 10, characterized in that, The method further includes: Save the hard drive presence status change log of the NVME port for maintenance of the NVME port; wherein the hard drive presence status change log includes at least: the port number of the NVME port and the hard drive presence status change type.

13. The method as described in claim 1, characterized in that, The access to the in-place target hard drive based on the access policy information matching the target hard drive adaptation type includes: If the target hard disk adapter type is the serial interface hard disk adapter type or the hybrid hard disk adapter type, then based on the number of serial interface hard disks in place, the serial interface hard disks corresponding to each port of the target hard disk are directly accessed.

14. A baseboard management controller, characterized in that, The substrate management controller is used to perform the steps of the method as described in any one of claims 1 to 13.

15. A server, characterized in that, The server includes: at least one hard disk backplane and a baseboard management controller; The at least one hard disk backplane is provided with a programmable logic device with a first preset fixed address, at least one I2C switch with a second preset fixed address, and an electrically erasable programmable read-only memory with a third preset fixed address. The baseboard management controller is used to perform the steps of the method as described in any one of claims 1 to 13 for the at least one hard disk backplane.

16. The server as described in claim 15, characterized in that, Also includes: The electrically erasable programmable read-only memory stores the sensor address of the temperature sensor, which is used to detect the temperature information of the at least one hard disk backplane.

17. The server as described in claim 15, characterized in that, Also includes: The at least one hard drive backplane is directly connected to the baseboard management controller via at least one I2C bus, wherein one I2C bus is connected to one hard drive backplane.

18. The server as described in claim 15, characterized in that, Also includes: The at least one hard disk backplane is indirectly connected to the baseboard management controller via a channel of a bus I2C switch connected to the I2C bus; wherein, the bus I2C switch has multiple bus channels, and one bus channel is connected to one hard disk backplane.

19. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method as described in any one of claims 1 to 13.

20. A computer program product, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1 to 13.

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