Low-noise operational amplifier based on current multiplexing

Abstract

The invention discloses a low-noise operational amplifier based on current multiplexing, relates to the technical field of radio frequency integrated circuits, and solves the technical problems of limited gain bandwidth product and conversion rate, high static power consumption and lack of dynamic power consumption adjustment capability. According to the technical scheme, the circuit is characterized by comprising a first adaptive biasing circuit, a first amplifying circuit, a second amplifying circuit, a multiplexing current adaptive circuit, a current multiplexing circuit and the like, wherein an active buffer circuit is arranged between the first amplifying circuit and the second amplifying circuit. The first adaptive bias circuit adjusts bias voltage by using signal strength, and the second adaptive bias circuit is provided with an analog control and power detection circuit. And the current multiplexing circuit cooperates with each part and comprises a self-adaptive adjustment mechanism. According to the invention, the gain bandwidth product and the conversion rate are improved through current multiplexing and active buffering, and the noise is reduced; power consumption is reduced through self-adaptive bias; the bias monitoring and current detection feedback control circuit ensures the stability; and the method has flexibility and adaptability, and can efficiently process signals and save energy.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of radio frequency integrated circuits, and particularly relates to a low-noise operational amplifier based on current multiplexing. BACKGROUND

[0002] With the rapid development of technologies such as the Internet of Things and mobile terminals, people have higher requirements for the endurance of portable devices, so reducing the power consumption of circuits has become one of the key challenges in chip design. Under the premise of not sacrificing performance, how to reduce power consumption by optimizing circuit structure and control method has become a research hotspot. In the fields of modern communication, audio processing, sensor signal processing, etc., the processing precision of signals such as amplification and filtering is increasingly required, and circuits need to have higher gain-bandwidth product, lower noise and other performance indicators. Traditional circuit structures often cannot meet these requirements at the same time.

[0003] When improving the gain-bandwidth product and the conversion rate, the traditional circuit design method often needs to increase the power consumption or sacrifice other performance indicators. Some simple amplifier circuit structures cannot meet the requirements of high gain and large bandwidth at the same time when processing high-frequency signals, resulting in increased distortion of the amplified signals, which limits their application in the fields of high-speed communication, high-frequency signal processing, etc.

[0004] The prior art lacks adjustability of circuit parameters, and cannot dynamically adjust the power consumption according to the changes of input signals. And some circuits use fixed biasing, which may cause the transistors to be in an over-conduction or cut-off state when working, thereby generating a large static power consumption.

[0005] Therefore, the prior art still has the problems of limited gain-bandwidth product and conversion rate, high static power consumption, and lack of dynamic power consumption adjustment capability. SUMMARY

[0006] The present application provides a low-noise operational amplifier based on current multiplexing, which aims to improve the gain-bandwidth product and the conversion rate, reduce the static power consumption, and improve the dynamic power consumption adjustment capability.

[0007] The above technical purpose of the present application is achieved by the following technical scheme:

[0008] The application discloses a low-noise operational amplifier based on current multiplexing, which comprises a first adaptive bias circuit, a first amplification circuit, a second adaptive bias circuit, a second amplification circuit, a variable voltage dividing network, a multiplexing current adaptive circuit, a current multiplexing circuit and an active buffer circuit, an input matching circuit is connected with the first amplification circuit through the first adaptive bias circuit, the active buffer circuit is connected between the first amplification circuit and the second amplification circuit, the first amplification circuit and the second amplification circuit are connected with the current multiplexing circuit, the second amplification circuit is connected with the second adaptive bias circuit, the current multiplexing circuit is connected with the multiplexing current adaptive circuit, and the variable voltage dividing network is connected with the second adaptive bias circuit and the second amplification circuit.

[0009] Preferably, the first amplification circuit comprises a first enhancement transistor M1, the drain of the first enhancement transistor M1 is connected with a capacitor C1, the gate of the first enhancement transistor M1 is connected with a resistor R1 and the first adaptive bias circuit respectively, the resistor R1 and the capacitor C1 are connected in series, and a variable resistor R0 is connected in parallel with the resistor R1; one end of a resistor R2 is grounded, the other end of the resistor R2 is connected with the first adaptive bias circuit and one end of a capacitor C8; the other end of the capacitor C8, one end of a resistor R3 and the non-inverting input terminal of an operational amplifier U1 are all connected; the other end of the resistor R3 is connected with the current multiplexing circuit, the source of the first enhancement transistor M1 is connected with one end of an inductor L1, and the other end of the inductor L1 is grounded.

[0010] Preferably, the second amplification circuit comprises a second enhancement transistor M2, the gate of the second enhancement transistor M2 is connected with the multiplexing current adaptive circuit (Ri0 and Ri1) and one end of a resistor R4 respectively, the other end of the resistor R4 is connected with a capacitor C2 in series and then connected with the drain of the second enhancement transistor M2, the drain of the second enhancement transistor M2 is also connected with a matching circuit output end and a resistor R6, the resistor R6 and a resistor R5 are connected in series, the other end of the resistor R5 is grounded, the resistor R5 and the resistor R6 are connected with the variable voltage dividing network, the connecting point between the resistor R5 and the resistor R6 is connected with the second adaptive bias circuit, the source of the second enhancement transistor M2 is connected with one end of a resistor R7, the other end of the resistor R7 and one end of a resistor R8 are connected in series, the other end of the resistor R8 is grounded, and the resistor R8 is connected with a capacitor C3 and a capacitor C6 in parallel respectively.

[0011] Preferably, the first adaptive bias circuit comprises a DSP, the input terminals of the DSP are connected with a signal detection circuit and a digital potentiometer respectively, the digital potentiometer is connected with the connecting point between the resistor R2 and the capacitor C8 and the output terminal of the operational amplifier U1, the non-inverting input terminal of the operational amplifier U1 is connected with the connecting point between the resistor R3 and the capacitor C8, the inverting input terminal of the operational amplifier U1 is connected with a reference voltage source V1 through a voltage dividing network composed of a resistor R11 and a resistor R12, and the other end of the resistor R11 and the other end of the reference voltage source V1 are both grounded.

[0012] The signal detection circuit comprises a rectifier diode D1, a positive pole of the rectifier diode D1 is connected with an input end of the DSP, a negative pole of the rectifier diode D1 is connected with one end of a capacitor C7 and one end of a resistor R10 respectively, the other ends of the capacitor C7 and the resistor R10 are grounded.

[0013] Preferably, the second adaptive bias circuit comprises an analog control circuit and a power detection circuit, wherein the analog control circuit comprises an operational amplifier U3, an inverting input end of the operational amplifier U3 is connected with a bias network voltage monitoring circuit, a non-inverting input end of the operational amplifier U3 is connected with a connecting point of the resistor R5 and the resistor R6, an output end of the operational amplifier U3 is connected with one input end of a multiplication analog, the other input end of the multiplication analog is connected with the power detection circuit; the bias network voltage monitoring circuit comprises the resistor R16 and the resistor R17 connected in series, a connecting point of the resistor R16 and the resistor R17 connected in series is connected with the inverting input end of the operational amplifier U3, the other end of the resistor R16 is grounded through a reference voltage source V3, the other end of the resistor R17 is grounded.

[0014] Preferably, the power detection circuit comprises a diode D2, a capacitor C9 and a resistor R15, one end of the capacitor C9 and the resistor R15 is connected with the other input end of the multiplication analog, and the other end of the capacitor C9 and the resistor R15 is grounded, the other input end of the multiplication analog is also connected with a connecting point between the output end of the matching circuit and the drain of the second enhancement mode transistor M2 through the diode D2.

[0015] Preferably, the variable voltage dividing network comprises an operational amplifier U5, an inverting input end of the operational amplifier U5 is grounded through an input resistor R14, an output end is connected to the inverting input end through a variable resistor R13, the resistor R5 and the resistor R6 together with the variable resistor R13 constitute a voltage dividing network, a non-inverting input end of the operational amplifier U5 is connected with an output end of the multiplication analog.

[0016] Preferably, the current multiplexing circuit comprises a resistor R9, one end of the resistor R9 is connected with one end of a capacitor C4 in series, the other end of the resistor R9 is connected with a gate of the second enhancement mode transistor M2 through the multiplexing current adaptive circuit, the other end of the capacitor C4 is grounded; a connecting point between the resistor R9 and the capacitor C4 is connected with an inductor L4, the inductor L4 is connected with an inductor L2 and an inductor L3 in parallel, the inductor L2 is connected with a connecting point between the first enhancement mode transistor M1 and the active buffer circuit, the inductor L3 is connected with the other end of the resistor R3.

[0017] Preferably, the multiplexing current adaptive circuit comprises a current detection resistor Ri0, a voltage signal across the current detection resistor Ri0 is connected to the non-inverting input of an operational amplifier U4 through an input resistor Ri1, the inverting input of the operational amplifier U4 is connected to one end of a reference voltage source V2 through a resistor Ri2, the other end of the reference voltage source V2 is grounded, the output of the operational amplifier U4 is connected to one end of a feedback resistor Rf, the other end of the feedback resistor Rf is connected to the inverting input of the operational amplifier U4 through a control circuit.

[0018] Preferably, the active buffer circuit comprises an operational amplifier U2, the non-inverting input of the operational amplifier U2 is connected to the source of the first enhancement-mode transistor M1, the output of the operational amplifier U2 is connected to the gate of the second enhancement-mode transistor M2, and the inverting input of the operational amplifier U2 is connected to its own output.

[0019] The application has the following advantages:

[0020] (1) The application uses current multiplexing technology and adds an active buffer circuit, which can achieve higher equivalent transconductance without increasing power consumption, thereby improving the gain-bandwidth product and conversion rate and other performance indicators, making the amplification and processing of signals more efficient, and being suitable for applications with high requirements for signal processing speed and accuracy.

[0021] (2) The first and second adaptive bias circuits in the application can automatically adjust the bias voltage according to the input signal strength and power, etc., so that the transistors work in a more suitable state, avoiding excessive conduction or cutoff of the transistors caused by fixed bias, thereby reducing static power consumption and improving the energy efficiency ratio of the circuit.

[0022] (3) The presence of the adaptive bias circuit and the multiplexing current adaptive circuit in the application allows the circuit to automatically adjust parameters such as bias voltage and multiplexing current according to different working conditions and signal characteristics, thereby better adapting to changes in various input signals, maintaining stable performance, and improving the reliability and versatility of the circuit.

[0023] (4) The bias network voltage monitoring circuit in the second adaptive bias circuit in the application can monitor the bias voltage in real time and adjust it through the analog control circuit to ensure the stability of the bias voltage and prevent bias point drift caused by power supply fluctuations, temperature changes, etc., thereby improving the stability and reliability of the circuit operation.

[0024] (5) The feedback control circuit composed of the current sensing resistor and the operational amplifier in the multiplexing current adaptive circuit of this application can monitor the magnitude of the multiplexing current in real time and automatically adjust it according to the reference voltage source, which ensures the accuracy and stability of current multiplexing and avoids the impact of current overload or insufficient current on circuit performance. Attached Figure Description

[0025] Fig. 1 This is a schematic diagram of the structure of a low-noise operational amplifier based on current multiplexing in an embodiment of this application;

[0026] Fig. 2 This is a circuit diagram of a low-noise operational amplifier based on current multiplexing in an embodiment of this application. Detailed Implementation

[0027] The technical solution of this application will be described in detail below with reference to the accompanying drawings.

[0028] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0029] Example

[0030] like Figs. 1-2 As shown, this application provides a low-noise operational amplifier based on current multiplexing, including a first adaptive bias circuit, a first amplification circuit, a second adaptive bias circuit, a second amplification circuit, a variable voltage divider network, a multiplexed current adaptive circuit, a current multiplexing circuit, and an active buffer circuit. The input matching circuit is connected to the first amplification circuit through the first adaptive bias circuit. An active buffer circuit is connected between the first amplification circuit and the second amplification circuit. The first amplification circuit and the second amplification circuit are connected to the current multiplexing circuit. The second amplification circuit is connected to the second adaptive bias circuit. The current multiplexing circuit is connected to the multiplexed current adaptive circuit. The variable voltage divider network is connected to both the second adaptive bias circuit and the second amplification circuit.

[0031] The first amplification circuit comprises a first enhancement transistor M1, the drain of the first enhancement transistor M1 is connected with a capacitor C1, the gate of the first enhancement transistor M1 is connected with a resistor R1 and a first adaptive bias circuit respectively, the resistor R1 and the capacitor C1 are connected in series, and a variable resistor R0 is connected in parallel with the resistor R1; one end of a resistor R2 is grounded, and the other end is connected with the first adaptive bias circuit and one end of a capacitor C8; the other end of the capacitor C8, one end of a resistor R3 and the non-inverting input terminal of an operational amplifier U1 are all connected; the other end of the resistor R3 is connected with a current multiplexing circuit, the source of the first enhancement transistor M1 is connected with one end of an inductor L1, and the other end of the inductor L1 is grounded.

[0032] The second amplification circuit comprises a second enhancement transistor M2, the gate of the second enhancement transistor M2 is connected with a multiplexing current adaptive circuit (Ri0 and Ri1) and one end of a resistor R4 respectively, the other end of the resistor R4 is connected with a capacitor C2 in series and then connected with the drain of the second enhancement transistor M2, the drain of the second enhancement transistor M2 is also connected with a matching circuit output end and a resistor R6, the resistor R6 and a resistor R5 are connected in series, the other end of the resistor R5 is grounded, and the resistor R5 and the resistor R6 are connected with a variable voltage dividing network, the connection point between the resistor R5 and the resistor R6 is connected with a second adaptive bias circuit, the source of the second enhancement transistor M2 is connected with one end of a resistor R7, the other end of the resistor R7 is connected with one end of a resistor R8 in series, the other end of the resistor R8 is grounded, and the resistor R8 is connected with a capacitor C3 and a capacitor C6 in parallel respectively.

[0033] The first adaptive bias circuit comprises a DSP, the input terminals of the DSP are connected with a signal detection circuit and a digital potentiometer respectively, the digital potentiometer is connected with the connection point between the resistor R2 and the capacitor C8 and the output terminal of the operational amplifier U1, the non-inverting input terminal of the operational amplifier U1 is connected with the connection point between the resistor R3 and the capacitor C8, the inverting input terminal of the operational amplifier U1 is connected with a reference voltage source V1 through a voltage dividing network composed of a resistor R11 and a resistor R12, and the other end of the resistor R11 and the other end of the reference voltage source V1 are both grounded.

[0034] The signal detection circuit comprises a rectifier diode D1, the positive electrode of the rectifier diode D1 is connected with the input terminal of the DSP, the negative electrode of the rectifier diode D1 is connected with one end of a capacitor C7 and one end of a resistor R10 respectively, and the other ends of the capacitor C7 and the resistor R10 are both grounded.

[0035] The second adaptive bias circuit comprises an analog control circuit and a power detection circuit, wherein the analog control circuit comprises an operational amplifier U3, the inverting input terminal of the operational amplifier U3 is connected with a bias network voltage monitoring circuit, the non-inverting input terminal of the operational amplifier U3 is connected with the connecting point of a resistor R5 and a resistor R6, the output terminal of the operational amplifier U3 is connected with one input terminal of a multiplication simulator, the other input terminal of the multiplication simulator is connected with the power detection circuit; the bias network voltage monitoring circuit comprises a resistor R16 and a resistor R17 connected in series, the connecting point of the resistor R16 and the resistor R17 connected in series is connected with the inverting input terminal of the operational amplifier U3, the other end of the resistor R16 is grounded through a reference voltage source V3, and the other end of the resistor R17 is grounded.

[0036] The power detection circuit comprises a diode D2, a capacitor C9 and a resistor R15, one end of the capacitor C9 and the resistor R15 is connected with the other input terminal of the multiplication simulator, and the other end of the capacitor C9 and the resistor R15 is grounded, and the other input terminal of the multiplication simulator is also connected with the connecting point between the output terminal of the matching circuit and the drain of the second enhancement mode transistor M2 through the diode D2.

[0037] The variable voltage dividing network comprises an operational amplifier U5, the inverting input terminal of the operational amplifier U5 is grounded through an input resistor R14, the output terminal is connected to the inverting input terminal through a variable resistor R13, the resistor R5 and the resistor R6 constitute a voltage dividing network together with the variable resistor R13, and the non-inverting input terminal of the operational amplifier U5 is connected with the output terminal of the multiplication simulator.

[0038] The current multiplexing circuit comprises a resistor R9, one end of the resistor R9 is connected with one end of a capacitor C4 in series, the other end of the resistor R9 is connected with the gate of the second enhancement mode transistor M2 through the multiplexing current adaptive circuit, and the other end of the capacitor C4 is grounded; the connecting point between the resistor R9 and the capacitor C4 is connected with an inductor L4, the inductor L4 is connected with an inductor L2 and an inductor L3 in parallel, the inductor L2 is connected with the connecting point between the first enhancement mode transistor M1 and the active buffer circuit, and the inductor L3 is connected with the other end of the resistor R3.

[0039] The multiplexing current adaptive circuit comprises a current detection resistor Ri0, a voltage signal between the current detection resistor Ri0 is connected to the non-inverting input terminal of the operational amplifier U4 through an input resistor Ri1, the inverting input terminal of the operational amplifier U4 is connected to one end of the reference voltage source V2 through a resistor Ri2, the other end of the reference voltage source V2 is grounded, and the output terminal of the operational amplifier U4 is connected to one end of the feedback resistor Rf, and the other end of the feedback resistor Rf is connected to the inverting input terminal of the operational amplifier U4 through the control circuit. The feedback control circuit composed of the current detection resistor Ri0 and the operational amplifier U4 in the multiplexing current adaptive circuit can monitor the size of the multiplexing current in real time, and automatically adjust according to the reference voltage source V2, thereby ensuring the accuracy and stability of the current multiplexing and avoiding the influence of current overload or insufficient on the circuit performance.

[0040] The active buffer circuit comprises the operational amplifier U2, the non-inverting input terminal of the operational amplifier U2 is connected to the source of the first enhancement transistor M1, the output terminal of the operational amplifier U2 is connected to the gate of the second enhancement transistor M2, and the inverting input terminal of the operational amplifier U2 is connected to its own output terminal. The active buffer circuit adopts the form of the voltage follower composed of the operational amplifier, has the characteristics of high input impedance and low output impedance, can effectively isolate the mutual influence between the front and rear circuits, reduce the distortion and noise interference in the signal transmission process, and improve the signal quality of the entire circuit.

[0041] The small bypass capacitor C8 between the connection point of the resistor R2 and the resistor R3 and the ground can filter the high-frequency noise in the power supply, reduce the influence of the power supply noise on the bias point of the first enhancement transistor M1, and further improve the noise performance of the amplifier. The variable resistor R0 connected in parallel with the resistor R1 can dynamically change the feedback coefficient of the gate-drain negative feedback network by adjusting the resistance value of the variable resistor R0, thereby realizing the accurate control of the gain of the first-stage amplification circuit. This gain control can optimize the linearity and dynamic range of the amplifier in the case of different input signal intensities. The small variable capacitor C6 connected in parallel across the capacitor C3 can more finely control the stability of the source voltage of the second enhancement transistor M2 by adjusting the value of the variable capacitor C6, and further optimize the linearity and gain flatness of the amplifier.

[0042] The working principle of the first adaptive bias circuit is as follows:

[0043] The connection point of resistor R2 and resistor R3 is connected to the non-inverting input of the operational amplifier. The reference voltage source is connected to the inverting input of the operational amplifier U1 through a voltage divider network (consisting of two resistors R11 and R12). The output of the operational amplifier U1 is connected to the control terminal of the digital potentiometer. One terminal of the digital potentiometer is connected to the terminal of resistor R3 originally connected to the current multiplexing circuit, so that the bias voltage of the first enhancement mode transistor M1 is adjusted by changing the resistance of the digital potentiometer.

[0044] The signal strength detection circuit is connected between the input matching circuit and the gate of the first enhancement mode transistor M1. Its output is connected to an input pin of the DSP. The DSP controls the resistance of the digital potentiometer according to the received signal strength information and the error signal output by the operational amplifier U1, according to a pre-programmed algorithm.

[0045] The anode of the rectifier diode D1 of the signal detection circuit is connected to the output of the input matching circuit, i.e. the node where the signal enters the first stage of the amplifier. The cathode of the rectifier diode D1 is connected to one terminal of the filter capacitor C7 and one terminal of the load resistor R10. The other terminal of the filter capacitor C7 and the other terminal of the load resistor R10 are grounded.

[0046] From the connection position, the signal detection circuit is connected in parallel between the input matching circuit and the gate of the first enhancement mode transistor M1. Its input (anode of rectifier diode D1) is connected to the output of the input matching circuit, which is directly connected to the gate of the first enhancement mode transistor M1, so that the signal detection circuit can detect the amplitude of the input signal without interfering with the normal transmission of the input signal to the gate of the first enhancement mode transistor M1. The detected signal can be used for subsequent adaptive bias control operations, such as outputting the DC voltage signal at the connection point of the filter capacitor C7 and the load resistor R10 to the input pin of the digital signal processor (DSP) as a reference signal for the input signal strength. The digital signal processor (DSP) is a commonly used technical device and means in the field, and its structure and overall layout are not described in detail here.

[0047] Second adaptive bias circuit:

[0048] The power detection circuit is used to detect the power of the output signal, the variable voltage divider network is used to adjust the voltage division ratio of the bias network, and the analog control circuit controls the variable voltage divider network according to the power detection result and the bias voltage monitoring result.

[0049] Analog control circuit: the principle is that the error signal output by the operational amplifier U3 can be combined with the power signal output by the power detection circuit to jointly adjust the bias voltage of the bias network.

[0050] Connection: The output of the operational amplifier U3 is connected to one input of the analog multiplier, and the signal outputted by the power detection circuit is connected to the other input of the analog multiplier. The output of the analog multiplier is connected to the input of another operational amplifier U5 (for signal amplification and driving), and the output of the operational amplifier U5 is connected to the control end of the variable resistor R13 (such as a resistor network controlled by an analog switch) in the variable voltage dividing network (for adjusting the voltage dividing ratio of the fifth resistor R5 and the sixth resistor R6 in the biasing network), so as to adjust the bias voltage according to the error signal and the power signal.

[0051] The output of the analog multiplier is connected to the non-inverting input of the operational amplifier U5, and the signal outputted by the analog multiplier represents the control signal after the bias voltage error and the power signal jointly act, which is connected to the non-inverting input of the operational amplifier, so that the signal amplification is facilitated, and the forward control is more easily realized when the variable resistor control end is connected subsequently.

[0052] Variable voltage dividing network (R5, R6, R13)

[0053] The inverting input of the operational amplifier U5 is connected to ground through an input resistor R14, and the output is connected to the inverting input through a variable resistor R13. The connection mode of the inverting input is used for signal amplification, so that the weak control signal outputted by the analog multiplier is enhanced to a suitable strength, so as to effectively drive the control end of the variable resistor R13. The resistor R5 and the resistor R6 together with the variable resistor R13 constitute a voltage dividing network. The variable resistor R13 is used to adjust the voltage dividing ratio and is the core device of the variable voltage dividing network, which is used to adjust the voltage dividing ratio. In the biasing network, the original fifth resistor R5 and the sixth resistor R6 still play a basic role in voltage dividing, and the change of the variable resistor R13 will change the overall voltage dividing ratio.

[0054] Biasing network voltage monitoring circuit

[0055] The operational amplifier U3 is used as a core comparison element to compare the actual bias voltage with the reference voltage and output an error signal. The reference voltage source V2 provides a stable reference voltage for comparison with the actual bias voltage. The voltage dividing resistors R17 and R16 are used to adjust the voltage of the reference voltage source to obtain a suitable reference voltage value. The positive electrode of the reference voltage source is connected to one end of R17, the other end of R17 is connected to one end of R16, the other end of R16 is connected to ground, and the reference voltage is taken from the connection point of R17 and R16 and sent to the inverting input of the operational amplifier. The non-inverting input of the operational amplifier U3 is connected to the connection point of the resistor R5 and the resistor R6 for obtaining the actual bias voltage. The inverting input is connected to the reference voltage obtained by the voltage dividing network composed of R17 and R16. The output end of the operational amplifier U3 outputs an error signal, which can be used for subsequent bias adjustment control.

[0056] power detection circuit

[0057] The detection circuit is composed of diode D2, capacitor C9 and resistor R15. The anode of diode D2 is connected to the signal path between the output matching circuit and the drain of the enhancement transistor M2, the cathode is connected to one end of the filter capacitor C9 and one end of the load resistor R15, the other end of the filter capacitor C9 and the other end of the load resistor R15 are grounded. The signal output from the connection point of the load resistor R15 and the filter capacitor C9 (representing power information) is sent to the subsequent control circuit for adjusting bias and other operations. Diode D2 is used for rectification to convert alternating current signal to direct current signal, capacitor C9 is used for filtering, and resistor R15 is used for voltage division and matching load. The load resistor R15 and the filter capacitor C9 filter and load match the detected signal to obtain a relatively smooth power-related signal.

[0058] Multiplexing current adaptive circuit:

[0059] In the current multiplexing circuit, the current detection resistor Ri0 is connected in series between the ninth resistor R9 and the source of the enhancement transistor M2. The voltage signal across the current detection resistor Ri0 is sent to a comparison circuit (composed of operational amplifier U4), and the other input of the comparison circuit is connected to a reference voltage (determined according to the signal amplitude and power detection result).

[0060] The output of the comparison circuit is connected to a control circuit, which is used to adjust the variable inductance or variable capacitance. For example, if it is a variable inductance, the control circuit can be a driving circuit that can change the position of the inductance magnetic core; if it is a variable capacitance, the control circuit can be a circuit that can change the reverse bias voltage of the varactor diode. By adjusting the variable inductance or variable capacitance, the parameters of the current multiplexing circuit are changed to achieve adaptive adjustment of the multiplexing current. The control circuit is prior art, so its structure and layout will not be described and shown again.

[0061] Comparison circuit (composed of operational amplifier U4)

[0062] The voltage signal across the current detection resistor Ri0 is connected to the non-inverting input of the operational amplifier U4 through an input resistor Ri1. The reference voltage source (determined according to the signal amplitude and power detection result) is connected to the inverting input of the operational amplifier U4 through another input resistor Ri2. The output of the operational amplifier U4 is connected to one end of the feedback resistor Rf, and the other end of the feedback resistor Rf is connected to the inverting input of the operational amplifier U4. In this way, a basic comparison amplification circuit is formed, which outputs an amplified signal related to the difference between the current detection signal and the reference voltage.

[0063] Active buffer circuit:

[0064] The non-inverting input of the operational amplifier U2 is connected to the output of the first stage amplification circuit, i.e., to the drain of the first enhancement-mode transistor M1. In this way, the signal output by the first stage amplification circuit can be directly input to the non-inverting input of the operational amplifier U2, allowing the operational amplifier U2 to perform buffering on this signal.

[0065] The output of the operational amplifier U2 is connected to the input of the stage amplification circuit, i.e., to the gate of the enhancement-mode transistor M2. In this way, the signal buffered by the operational amplifier U2 can effectively drive the stage amplification circuit, and the low output impedance of the operational amplifier U2 can be well matched with the input impedance of the stage amplification circuit, reducing signal attenuation and distortion. The inverting input of the operational amplifier U2 is connected to its own output. This connection forms a voltage follower circuit. According to the virtual short (the potentials at the non-inverting input and the inverting input are approximately equal) and virtual open (the current flowing into and out of the input is approximately zero) characteristics of the operational amplifier, the voltage at the output will closely follow the voltage changes at the non-inverting input, thereby achieving the function of voltage following and effectively transmitting the output signal of the first stage amplification circuit to the stage amplification circuit. Here, the operational amplifier U2 mainly serves to isolate and buffer the first stage amplification circuit and the stage amplification circuit, achieving better signal transmission and matching.

[0066] Therefore, the low-noise operational amplifier based on current multiplexing described above has the following advantages. In terms of performance, the combination of current multiplexing and active buffering circuit improves the gain-bandwidth product and conversion rate, making signal processing more efficient. At the same time, the active buffering circuit effectively isolates the front and rear stages, reduces noise interference, and ensures signal quality. In terms of power consumption, current multiplexing reduces current waste, and the adaptive biasing circuit automatically adjusts according to signal strength and power, avoiding excessive work of the transistor, reducing static power consumption, and prolonging the endurance of the device. In terms of flexibility and adaptability, the adaptive biasing and multiplexing current adaptive circuit can automatically adjust parameters according to working conditions and signal characteristics, and the variable resistor also increases the parameter adjustment, which can adapt to various application scenarios. The stability of the circuit is also enhanced, and the bias voltage monitoring and current detection feedback control circuit ensure the stability of the bias voltage and the accuracy of the current multiplexing, respectively, reducing the adverse effects caused by power supply fluctuations, temperature changes, and other factors, making the circuit work more reliably.

[0067] Finally, it should be noted that the above examples are only used to illustrate the technical solutions of the present application and not to limit them. Although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can still be modified or equivalently replaced, and these modifications or equivalent replacements cannot make the modified technical solutions deviate from the spirit and scope of the technical solutions of the present application.

Claims

1. A low noise operational amplifier based on current multiplexing, characterized by, It includes a first adaptive bias circuit, a first amplifier circuit, a second adaptive bias circuit, a second amplifier circuit, a variable voltage divider network, a multiplexed current adaptive circuit, a current multiplexing circuit, and an active buffer circuit. The input matching circuit is connected to the first amplifier circuit through the first adaptive bias circuit. An active buffer circuit is connected between the first amplifier circuit and the second amplifier circuit. Both the first amplifier circuit and the second amplifier circuit are connected to the current multiplexing circuit. The second amplifier circuit is connected to the second adaptive bias circuit. The current multiplexing circuit is connected to the multiplexed current adaptive circuit. The variable voltage divider network is connected to both the second adaptive bias circuit and the second amplifier circuit.

2. The low noise operational amplifier of claim 1, wherein, The first amplifier circuit includes a first enhancement-mode transistor M1. The drain of the first enhancement-mode transistor M1 is connected to a capacitor C1. The gate of the first enhancement-mode transistor M1 is connected to a resistor R1 and a first adaptive bias circuit. The resistor R1 and the capacitor C1 are connected in series. A variable resistor R0 is also connected in parallel with the resistor R1. One end of the resistor R2 is grounded, and the other end is connected to the first adaptive bias circuit and one end of the capacitor C8. The other end of the capacitor C8, one end of the resistor R3, and the non-inverting input of the operational amplifier U1 are all connected. The other end of the resistor R3 is connected to a current multiplexing circuit. The source of the first enhancement-mode transistor M1 is connected to one end of the inductor L1, and the other end of the inductor L1 is grounded.

3. The low noise operational amplifier of claim 1, wherein, The second amplifier circuit includes a second enhancement-mode transistor M2. The gate of the second enhancement-mode transistor M2 is connected to the multiplexed current adaptive circuit and one end of resistor R4. The other end of resistor R4 is connected in series with capacitor C2 and then connected to the drain of the second enhancement-mode transistor M2. The drain of the second enhancement-mode transistor M2 is also connected to the output of the matching circuit and resistor R6. Resistors R6 and R5 are connected in series. The other end of resistor R5 is grounded. Resistors R5 and R6 are connected to a variable voltage divider network. The connection point between resistors R5 and R6 is connected to the second adaptive bias circuit. The source of the second enhancement-mode transistor M2 is connected to one end of resistor R7. The other end of resistor R7 is connected in series with one end of resistor R8. The other end of resistor R8 is grounded. Resistors R8 are connected in parallel with capacitors C3 and C6.

4. The low noise operational amplifier of claim 1, wherein, The first adaptive bias circuit includes a DSP. The input terminal of the DSP is connected to the signal detection circuit and the digital potentiometer, respectively. The connection point between the digital potentiometer and the resistor R2 and the capacitor C8, as well as the output terminal of the operational amplifier U1, are all connected. The non-inverting input terminal of the operational amplifier U1 is connected to the connection point between the resistor R3 and the capacitor C8. The inverting input terminal of the operational amplifier U1 is connected to the reference voltage source V1 through a voltage divider network composed of resistors R11 and R12. The other end of resistor R11 and the other end of the reference voltage source V1 are both grounded. The signal detection circuit includes a rectifier diode D1. The positive terminal of the rectifier diode D1 is connected to the input terminal of the DSP, and the negative terminal of the rectifier diode D1 is connected to one end of the capacitor C7 and one end of the resistor R10. The other ends of the capacitor C7 and the resistor R10 are both grounded.

5. The low noise operational amplifier of claim 1, wherein, The second adaptive bias circuit includes an analog control circuit and a power detection circuit. The analog control circuit includes an operational amplifier U3. The inverting input of the operational amplifier U3 is connected to the bias network voltage monitoring circuit, and the non-inverting input of the operational amplifier U3 is connected to the connection point of resistors R5 and R6. The output of the operational amplifier U3 is connected to one input of the multiplication simulator, and the other input of the multiplication simulator is connected to the power detection circuit. The bias network voltage monitoring circuit includes resistors R16 and R17 connected in series. The connection point of resistors R16 and R17 connected in series is connected to the inverting input of the operational amplifier U3. The other end of resistor R16 is grounded through a reference voltage source V3, and the other end of resistor R17 is grounded.

6. The low noise operational amplifier of claim 1, wherein, The power detection circuit includes diode D2, capacitor C9 and resistor R15. One end of resistor C9 and resistor R15 are connected to the other input terminal of the multiplication simulator, and the other end of resistor C9 and resistor R15 are grounded. The other input terminal of the multiplication simulator is also connected to the connection point between the output terminal of the matching circuit and the drain of the second enhancement transistor M2 through diode D2.

7. The low noise operational amplifier of claim 1, wherein, The variable voltage divider network includes operational amplifier U5. The inverting input of operational amplifier U5 is grounded through an input resistor R14, and the output is connected to the inverting input through a variable resistor R13. Resistors R5 and R6 together with the variable resistor R13 form a voltage divider network. The non-inverting input of operational amplifier U5 is connected to the output of the multiplication simulator.

8. The low noise operational amplifier of claim 1, wherein, The current multiplexing circuit includes a resistor R9, one end of which is connected in series with one end of a capacitor C4. The other end of the resistor R9 is connected to the gate of the second enhancement-mode transistor M2 through a multiplexing current adaptive circuit. The other end of the capacitor C4 is grounded. The connection point between the resistor R9 and the capacitor C4 is connected to the inductor L4. The inductor L4 is connected in parallel with the inductors L2 and L3 respectively. The inductor L2 is connected to the connection point between the first enhancement-mode transistor M1 and the active buffer circuit. The other end of the inductor L3 is connected to the resistor R3.

9. The low noise operational amplifier of claim 1, wherein, The multiplexed current adaptive circuit includes a current sensing resistor Ri0. The voltage signal across the current sensing resistor Ri0 is connected to the non-inverting input of operational amplifier U4 through an input resistor Ri1. The inverting input of operational amplifier U4 is connected to one end of a reference voltage source V2 through a resistor Ri2. The other end of the reference voltage source V2 is grounded. The output of operational amplifier U4 is connected to one end of a feedback resistor Rf. The other end of the feedback resistor Rf is connected to the inverting input of operational amplifier U4 through a control circuit.

10. The low noise operational amplifier of claim 1, wherein, The active buffer circuit includes an operational amplifier U2, the non-inverting input of which is connected to the source of the first enhancement-mode transistor M1, the output of which is connected to the gate of the second enhancement-mode transistor M2, and the inverting input of which is connected to its own output.

Images