Driving circuit, fast charging protocol chip and electronic equipment

Abstract

The invention provides a driving circuit, a fast charge protocol chip and electronic equipment, and relates to the technical field of power management chips, the circuit comprises a ramp voltage generation circuit and a class AB operational amplifier circuit, the ramp voltage generation circuit comprises a controllable current source circuit, a first capacitor and a clamping circuit, and the controllable current source circuit comprises a current branch; the controllable current source circuit obtains a first current and a second current according to the first digital signal, and the magnitude of the first current and the magnitude of the second current are in positive correlation with the number of the current branches; the first capacitor charges itself according to the first current and discharges itself according to the second current to obtain a ramp voltage signal; the clamping circuit clamps the ramp voltage signal according to the first digital signal and the reference voltage to enable the ramp voltage signal to be lower than the reference voltage; the class AB operational amplifier circuit amplifies the ramp voltage signal to obtain a second digital signal. Therefore, the circuit is suitable for wide-range load capacitance, and has a high power supply rejection ratio.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power management chips, in particular to a driving circuit, a fast charging protocol chip and an electronic device. BACKGROUND

[0002] Fast charging technology has been widely applied in electronic devices such as smart phones, tablet computers and even notebook computers. In order to improve user experience, major manufacturers have launched their own fast charging protocols. Fast charging protocols not only greatly improve charging speed, but also bring more intelligent and safer charging experience. With the rapid development of fast charging protocols, the application of TypeC charging interface is becoming more and more popular. Apple system, as one of the most widely used mobile phones in the world, also has its PD (Power Delivery) protocol rapidly developing. PD protocol is a fast charging protocol based on TypeC interface.

[0003] PD protocol uses the bidirectional communication function of TypeC interface to achieve fast charging by negotiating voltage and current. In the application of PD protocol, communication handshake is required, and there are often many scenarios of receiving and transmitting data packets. It is required that the waveform of the signal received and transmitted on the CC pin of the fast charging protocol chip meets certain shape requirements, for example, the rising edge, falling edge, high level or low level of the signal data meet the requirements, which is collectively referred to as eye diagram (i.e. eye diagram).

[0004] Referring to Figure 1 , Figure 1 is a schematic diagram of the application of PD protocol, as Figure 1 shown, in the application of PD protocol, the transmitting end circuit (i.e. TX) of the fast charging protocol chip needs to convert digital signals into eye diagram waveforms that meet the requirements. For example, referring to Figure 1 , the input signal PD_DATA_IN is converted into the output signal PD_DATA_OUT in the application of PD protocol, wherein PD_DATA_IN can be a digital signal of 0-3.3V (0V corresponds to a low-level digital signal 0, and 3.3V corresponds to a high-level digital signal 1), and PD_DATA_OUT is a ramp signal of 0-1.125V that meets the eye diagram requirements. The high level of the ramp signal is 1.125V, and the low level is 0V.

[0005] Referring to Figure 2 , Figure 2 is an eye diagram generating circuit provided by the prior art, as Figure 2As shown, the circuit is realized by controlling the turn-on or turn-off of the second transistor M2 and the third transistor M3 to realize the charging or discharging of the capacitor CC1, and the output signal DATA_OUT is obtained. In this scheme, for different capacitor values of the capacitor CC1, the turn-on impedance of the second transistor M2 and the third transistor M3 needs to be adjusted correspondingly, and at the same time a large number of registers are needed to control the turn-on impedance of the second transistor M2 and the third transistor M3, which will cause the application to be not flexible enough. In the scene where the capacitance value of the capacitor CC1 needs to be changed in a large range, this scheme has obvious disadvantages and cannot adapt to the scene where the capacitance value changes in a large range. In the prior art, CLASSAB amplification circuit can adapt to the scene where the capacitance value changes in a large range, but the power supply rejection ratio of the traditional CLASSAB amplification circuit is often not high. Therefore, how the eye diagram generation circuit adapts to the wide range of load capacitance and has a high power supply rejection ratio is a technical problem to be solved. SUMMARY

[0006] The present application provides a driving circuit, a fast charging protocol chip and an electronic device to adapt to a wide range of load capacitance and have a high power supply rejection ratio, thereby greatly improving the performance of the eye diagram.

[0007] In a first aspect, the present application provides a driving circuit, which comprises a slope voltage generation circuit and a CLASSAB operational amplifier circuit, the slope voltage generation circuit comprising a controllable current source circuit, a first capacitor and a clamping circuit, wherein the controllable current source circuit comprises a current branch.

[0008] The controllable current source circuit is configured to obtain a first current and a second current according to a first digital signal, and the current sizes of the first current and the second current are positively correlated with the number of the current branches.

[0009] The first capacitor is configured to charge itself according to the first current and discharge itself according to the second current to obtain a slope voltage signal.

[0010] The clamping circuit is configured to clamp the slope voltage signal according to the first digital signal and a reference voltage, so that the voltage value of the slope voltage signal is lower than the reference voltage.

[0011] The CLASSAB operational amplifier circuit is configured to amplify the slope voltage signal to obtain a second digital signal.

[0012] In a possible design, the controllable current source circuit comprises an inverter, a first controllable current circuit and a second controllable current circuit, wherein the first controllable current circuit comprises at least one current branch, and the second controllable current circuit comprises at least one current branch.

[0013] The inverter is configured to perform level conversion on the first digital signal to obtain a third digital signal, and transmit the third digital signal to the first controllable current circuit and the second controllable current circuit.

[0014] The first controllable current circuit is configured to obtain the first current according to the third digital signal.

[0015] The second controllable current circuit is configured to obtain the second current according to the third digital signal.

[0016] In a possible design, the first controllable current circuit further includes a first switch tube and a pull-up current source; the current branch includes a current source and a switch, an input end of the current source is electrically connected with a first end of the current branch, an output end of the current source is electrically connected with a first end of the switch, and a second end of the switch is electrically connected with a second end of the current branch.

[0017] A first end of the pull-up current source is electrically connected with the first end of the current branch, and is configured to access a power supply voltage.

[0018] A control end of the first switch tube is electrically connected with an output end of the inverter, and a first end of the first switch tube is electrically connected with a second end of the pull-up current source and a second end of the current branch respectively.

[0019] A second end of the first switch tube is electrically connected with a first end of the first capacitor.

[0020] In a possible design, the second controllable current circuit further includes a second switch tube and a pull-down current source.

[0021] A control end of the second switch tube is electrically connected with the output end of the inverter, and a first end of the second switch tube is electrically connected with a first end of the pull-down current source and a first end of the current branch respectively.

[0022] A second end of the second switch tube is electrically connected with the first end of the first capacitor.

[0023] A second end of the pull-down current source and a second end of the current branch are grounded.

[0024] A second end of the first capacitor is grounded.

[0025] In a possible design, the clamping circuit includes a comparator, a third switch tube and a fourth switch tube.

[0026] The non-inverting input terminal of the comparator is connected to the first end of the first capacitor and the second end of the third switch tube, and serves as an output terminal of the slope voltage generating circuit, for outputting the slope voltage signal; the inverting input terminal of the comparator is connected to the reference voltage; and the output terminal of the comparator is connected to the control terminal of the third switch tube and the second end of the fourth switch tube.

[0027] The control terminal of the fourth switch tube is connected to the third digital signal.

[0028] The first end of the third switch tube and the first end of the fourth switch tube are grounded.

[0029] In a possible design, the class AB operational amplifier circuit includes a fully differential operational amplifier, a first bias current source, a second bias current source, a fifth switch tube, a sixth switch tube, a seventh switch tube, an eighth switch tube, a ninth switch tube, a tenth switch tube, an eleventh switch tube, and a twelfth switch tube.

[0030] The non-inverting input terminal of the fully differential operational amplifier is connected to the slope voltage signal; the inverting input terminal of the fully differential operational amplifier is connected to the second digital signal; and the inverting output terminal of the fully differential operational amplifier is connected to the first end of the seventh switch tube, the second end of the tenth switch tube, and the control terminal of the eleventh switch tube.

[0031] The non-inverting output terminal of the fully differential operational amplifier is connected to the second end of the seventh switch tube, the first end of the tenth switch tube, and the control terminal of the twelfth switch tube.

[0032] The first end of the first bias current source is connected to the first end of the fifth switch tube and the first end of the eleventh switch tube, and is connected to a power supply voltage; the control terminal of the fifth switch tube is connected to the second end of the fifth switch tube and the first end of the sixth switch tube.

[0033] The control terminal of the sixth switch tube is connected to the second end of the sixth switch tube, the control terminal of the seventh switch tube, and the first end of the second bias current source.

[0034] The second end of the first bias current source is connected to the control terminal of the eighth switch tube, the second end of the eighth switch tube, and the control terminal of the tenth switch tube.

[0035] The first end of the eighth switch tube is connected to the control terminal of the ninth switch tube and the second end of the ninth switch tube.

[0036] The second end of the eleventh switch tube is electrically connected with the second end of the twelfth switch tube as an output end of the class AB operational amplifier circuit, and is configured to output the second digital signal.

[0037] The first end of the ninth switch tube, the second end of the second bias current source and the first end of the twelfth switch tube are grounded.

[0038] In a possible design, the fifth switch tube, the sixth switch tube, the seventh switch tube and the eleventh switch tube are P-type MOS tubes, and the eighth switch tube, the ninth switch tube, the tenth switch tube and the twelfth switch tube are N-type MOS tubes.

[0039] In a possible design, the class AB operational amplifier circuit further includes a second capacitor and a third capacitor.

[0040] The first end of the second capacitor is electrically connected with the control end of the eleventh switch tube, and the second end of the second capacitor is electrically connected with the second end of the eleventh switch tube.

[0041] The first end of the third capacitor is electrically connected with the control end of the twelfth switch tube, and the second end of the third capacitor is electrically connected with the second end of the twelfth switch tube.

[0042] In a possible design, when the driving circuit is applied to a fast charging protocol chip supporting a PD protocol, the high level of the first digital signal is the power supply voltage, and the low level of the first digital signal is zero; the rising time and the falling time of the second digital signal are both not less than 300 ns, the high level of the second digital signal is 1.125 V±100 mV, and the low level of the second digital signal is ±100 mV.

[0043] In a second aspect, the present application provides a fast charging protocol chip, which includes the driving circuit as described in the first aspect.

[0044] In a third aspect, the present application provides an electronic device, which includes the fast charging protocol chip as described in the second aspect.

[0045] The beneficial effects of the embodiments of the present application are as follows:

[0046] The driving circuit in the application comprises a slope voltage generating circuit and a class AB operational amplifier circuit, wherein the slope voltage generating circuit comprises a controllable current source circuit, a first capacitor and a clamping circuit, the controllable current source circuit comprises a current branch. The controllable current source circuit obtains a first current and a second current according to a first digital signal, the current sizes of the first current and the second current are positively correlated with the number of the current branches, therefore, the current sizes of the first current and the second current can be controlled by setting the number of the current branches, so that the first capacitor charges itself according to the first current and discharges itself according to the second current to obtain a slope voltage signal, the waveform slope of the slope voltage signal can be flexibly adjusted by controlling the number of the current branches, then the waveform of the slope voltage signal is only related to the current size of the first current, the current size of the second current and the capacitance value of the first capacitor, and is irrelevant to the capacitance value of the load capacitor, therefore, the slope voltage signal can adapt to the scene with a wide range of load capacitors; the slope voltage signal is amplified by the class AB operational amplifier circuit to obtain a second digital signal, which increases the driving capability of the slope voltage signal and has a high power supply rejection ratio, and then a waveform meeting the eye diagram requirement is obtained. BRIEF DESCRIPTION OF DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other embodiments can also be obtained by those skilled in the art according to these drawings.

[0048] Figure 1 Application diagram of the PD protocol;

[0049] Figure 2 An eye diagram generating circuit provided by the prior art;

[0050] Figure 3 A traditional class AB amplifier circuit provided by the prior art;

[0051] Figure 4 Application diagram of a driving circuit provided by the embodiments of the present application;

[0052] Figure 5 Structural diagram of a slope voltage generating circuit provided by the embodiments of the present application;

[0053] Figure 6 Structural diagram of a class AB operational amplifier circuit provided by the embodiments of the present application;

[0054] Figure 7 Structural diagram of another class AB operational amplifier circuit provided by the embodiments of the present application. DETAILED DESCRIPTION

[0055] In the present application, "at least one" means one or more, and "multiple" means two or more. The "and / or" describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or similar expressions means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, or c alone can represent: a alone, b alone, c alone, combination of a and b, combination of a and c, combination of b and c, or combination of a, b and c, where a, b, c can be single or multiple. In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0056] The terms "center", "longitudinal", "lateral", "upper", "lower", "left", "right", "front", "back", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0057] The terms "connected" and "connected" should be broadly understood, for example, the "connected" or "connected" of the circuit structure can mean not only physical connection, but also electrical connection or signal connection, for example, it can be directly connected, that is, physically connected, or indirectly connected through at least one element in the middle, as long as the circuit is connected, it can also be the internal connection of two elements; In addition to signal connection through circuit, signal connection through media medium, such as radio wave, can also be referred to. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0058] For the standard PD protocol, the corresponding eye diagram requirements in the application of the PD protocol are: in the range of 0-600pF load capacitance, the rise time and fall time of the waveform of the output signal PD_DATA_OUT are not less than 300ns, the high level is 1.125V±100mV, and the low level is ±100mV. In order to generate the required eye diagram waveform, most of the solutions adopted by the prior art are to generate a voltage of 1.125V through an LDO (Low Dropout Regulator, low dropout linear regulator), and then control the switching state of the pull-up switch or the pull-down switch to obtain the output signal.

[0059] Referring to Figure 2 , the circuit first generates a voltage of 1.125V through the LDO, obtains a voltage of 1.125V with driving capability through the operational amplifier A, the first transistor M1 and the resistor R0, controls the switching state of the second transistor M2 through the first input signal DATA, and controls the switching state of the third transistor M3 through the second input signal DATA_Z, wherein the second input signal DATA_Z is a signal obtained by level conversion of the first input signal DATA, and the level of the second input signal DATA_Z is opposite to that of the first input signal DATA, for example, when the first input signal DATA is high, the second input signal DATA_Z is low; when the first input signal DATA is low, the second input signal DATA_Z is high.

[0060] Through the first input signal DATA and the second input signal DATA_Z, the conduction or non-conduction of the second transistor M2 and the third transistor M3 is controlled, so that the voltage of 1.125V is used to charge the capacitor CC1 through the second transistor M2 or discharge the capacitor CC1 through the third transistor M3, and the output signal DATA_OUT is obtained, which meets the eye diagram requirement corresponding to the PD protocol.

[0061] Referring to Figure 2 , in the prior art, the conduction or non-conduction of the second transistor M2 and the third transistor M3 is controlled to realize the charging or discharging of the capacitor CC1, and the output signal DATA_OUT is obtained. The rising time (or rising edge time) of the waveform of the output signal DATA_OUT depends on the conduction impedance of the second transistor M2 and the capacitance value of the capacitor CC, and similarly, the falling time (or falling edge time) depends on the conduction impedance of the third transistor M3 and the capacitance value of the capacitor CC. The capacitor CC1 can be regarded as the load of the eye diagram generation circuit, and the value range of the capacitance value of the capacitor CC1 is often wide, which can be 0-600pF.

[0062] In the application of the PD protocol, the output signal DATA_OUT needs to meet the eye diagram requirements of the PD protocol when the capacitance value of the capacitor CC1 is any value in the range of 0-600 pF. For the capacitor CC1 with different capacitance values, the rising edge time and the falling edge time of the corresponding output signal DATA_OUT will also be different. In order to make the output signal DATA_OUT meet the eye diagram requirements of the PD protocol in the above wide range of capacitance values, the on-resistance of the second transistor M2 and the third transistor M3 needs to be adjusted corresponding to the capacitor CC1 with different capacitance values, and a large number of registers are also needed to control the on-resistance of the second transistor M2 and the third transistor M3, which will lead to inflexible application. In the scenario where the capacitance value of the capacitor CC1 needs to be changed in a large range, i.e., in the scenario where the load range is wide, the above scheme has obvious disadvantages and cannot adapt to the scenario where the capacitance value changes in a large range.

[0063] In the prior art, a CLASS AB amplification circuit can adapt to the scenario where the capacitance value changes in a large range, as shown in Figure 3 , Figure 3 A traditional CLASS AB amplification circuit provided by the prior art is shown in Figure 3 . The working principle of the circuit is as follows: the on or off of the fourth transistor M4 and the fifth transistor M5 is controlled by the first input signal DATA, so as to realize charging or discharging of the capacitor CC2, and obtain the output signal DATA_OUT.

[0064] As shown in Figure 3 , in an example, the fourth transistor M4 is a P-type MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) tube, and the fifth transistor M5 is an N-type MOS tube. When the first input signal DATA is at a low level, the fourth transistor M4 is turned on, and the fifth transistor M5 is turned off. The supply voltage VCC charges the capacitor CC2 through the fourth transistor M4. After the charging is completed, the output signal DATA_OUT is VCC. When the first input signal DATA is at a high level, the fifth transistor M5 is turned on, and the fourth transistor M4 is turned off. At this time, the capacitor CC2 discharges to the ground GND through the fifth transistor M5. After the discharging is completed, the output signal DATA_OUT is 0.

[0065] As shown in Figure 3, the traditional Class AB amplifier circuit is essentially an inverter, and the driving current is directly determined by the gate-source voltage VGS of the fourth transistor M4 and the fifth transistor M5 (i.e. the voltage difference between the transistor gate and the source). Based on the influence of the parasitic capacitance of the fourth transistor M4 and the fifth transistor M5, the ripple of the supply voltage VCC and the ground GND will be directly transmitted to the waveform of the output signal DATA_OUT, and the influence on the output signal DATA_OUT is large. Therefore, the power supply rejection ratio of the traditional Class AB amplifier circuit is not very high.

[0066] In order to adapt to the scene with a wide range of loads and have a high power supply rejection ratio, the application provides a driving circuit 1000, as shown in Figure 4 , Figure 4 The application provides an application schematic diagram of the driving circuit, as shown in Figure 4 The driving circuit 1000 can include a slope voltage generating circuit 100 and a Class AB operational amplifier circuit 200.

[0067] As shown in Figure 5 , Figure 5 The application provides a structure schematic diagram of the slope voltage generating circuit, as shown in Figure 5 The slope voltage generating circuit 100 can include a controllable current source circuit 101, a first capacitor Cramp and a clamping circuit 102, wherein the controllable current source circuit 101 includes a current branch 111.

[0068] The controllable current source circuit 101 is configured to obtain a first current I1 and a second current I2 according to a first digital signal PD_DATA_IN, and the current sizes of the first current I1 and the second current I2 are positively correlated with the number of the current branch 111.

[0069] The first capacitor Cramp is configured to charge itself according to the first current I1 and discharge itself according to the second current I2, and obtain a slope voltage signal RAMP_OUT.

[0070] The clamping circuit 102 is configured to clamp the slope voltage signal RAMP_OUT according to the first digital signal PD_DATA_IN and a reference voltage, so that the voltage value of the slope voltage signal RAMP_OUT is lower than the reference voltage.

[0071] The Class AB operational amplifier circuit 200 is configured to amplify the slope voltage signal RAMP_OUT and obtain a second digital signal PD_DATA_OUT.

[0072] As shown in Figure 4The driving circuit 1000 in the application is applied to a fast charging protocol chip supporting a PD protocol. In a PD protocol application, the digital signal needs to be converted into an eye pattern waveform meeting the requirements for a transmitting end circuit (i.e., TX) in the fast charging protocol chip. The driving circuit 1000 in the application takes a first digital signal PD_DATA_IN as an input signal and takes a second digital signal PD_DATA_OUT as an output signal. The fast charging protocol chip supporting the PD protocol can realize bidirectional data exchange between an electronic device and a charging device through a Type-C interface, automatically negotiate an optimal charging power, identify a device type and dynamically adjust parameters, for example, match the charging requirements of a mobile phone or a notebook computer.

[0073] In the fast charging protocol chip supporting the PD protocol, the first digital signal PD_DATA_IN can be a digital signal data packet obtained by the fast charging protocol chip from a previous stage circuit, for example, a digital signal data packet including 0 and 1 signals. The previous stage circuit can be a digital logic circuit implementing a state machine. In actual applications, the fast charging protocol chip is used to manage the conversion of protocol states, and the state machine is used to implement the conversion of protocol states and deliver the conversion results to the fast charging protocol chip. For example, when charging an electronic device, the fast charging protocol chip is used to manage trickle charging, pre-charging, constant current charging or constant voltage charging of the electronic device according to the current power of the electronic device; and the state machine is used to implement the state switching between trickle charging, pre-charging, constant current charging or constant voltage charging.

[0074] The voltage range of the first digital signal PD_DATA_IN is 0-VDD, and VDD is the power supply voltage of the fast charging protocol chip. In general, the power supply voltage VDD can be 3.3V or 5V, and the specific voltage value of the power supply voltage is not limited in the application. The first digital signal PD_DATA_IN is a digital signal, which can be 5V, 3.3V or 0V. It can be understood that, in the digital signal, the first digital signal PD_DATA_IN is 5V or 3.3V, which corresponds to a logic level 1, and the first digital signal PD_DATA_IN is 0V, which corresponds to a logic level 0. In the PD protocol application, the voltage range of the second digital signal PD_DATA_OUT is 0-1.125V, and the second digital signal PD_DATA_OUT can be 1.125V or 0V, but needs to meet the eye pattern requirements. The eye pattern requirements in the PD protocol application are that, in the range of 0-600pF of the load capacitance, the rising time and the falling time of the waveform of the second digital signal PD_DATA_OUT are both not less than 300ns, the high level of the second digital signal is 1.125V±100mV, and the low level of the second digital signal is ±100mV.

[0075] In the application of PD protocol, the reference voltage can be 1.125V. In one example, when the power voltage VDD is 3.3V, the first digital signal PD_DATA_IN of 0-3.3V can be converted into the second digital signal PD_DATA_OUT of 0-1.125V meeting the eye diagram requirement by the driving circuit 1000.

[0076] Referring to Figure 4 The driving circuit 1000 in the application can include a ramp voltage generating circuit 100 and an operational amplifier circuit 200. The ramp voltage generating circuit 100 is configured to convert the first digital signal PD_DATA_IN into a ramp voltage signal RAMP_OUT. The ramp voltage signal RAMP_OUT generated by the ramp voltage generating circuit in the application only realizes the conversion of the level and does not have the driving capability. Since the driving capability of the ramp voltage signal RAMP_OUT is poor, the ramp voltage signal RAMP_OUT cannot drive the load capacitance CP with the capacitance range of 0-600pF.

[0077] Therefore, the ramp voltage signal RAMP_OUT needs to be amplified by the operational amplifier circuit 200 to obtain the second digital signal PD_DATA_OUT, so that the driving capability of the ramp voltage signal RAMP_OUT is increased, and the second digital signal PD_DATA_OUT voltage follows the ramp voltage signal RAMP_OUT. The operational amplifier circuit 200 is equivalent to a voltage follower, which can increase the driving capability of the ramp voltage signal RAMP_OUT and make the voltage of the second digital signal PD_DATA_OUT follow the voltage of the ramp voltage signal RAMP_OUT.

[0078] Referring to Figure 5 The ramp voltage generating circuit 100 can include a controllable current source circuit 101, a first capacitor Cramp and a clamping circuit 102. The controllable current source circuit 101 can include a current branch 111.

[0079] Specifically, the controllable current source circuit 101 obtains the first current I1 and the second current I2 according to the first digital signal PD_DATA_IN. The current values of the first current I1 and the second current I2 are positively correlated with the number of the current branch 111. Therefore, the current values of the first current I1 and the second current I2 can be controlled by setting the number of the current branch 111. For example, when the number of the current branch 111 is 1, the current value of the first current I1 is 1A and the current value of the second current I2 is 1A. When the number of the current branch 111 is 2, the current value of the first current I1 is 2A and the current value of the second current I2 is 2A.

[0080] The first capacitor Cramp in the application charges itself according to the first current I1 and discharges itself according to the second current I2 to obtain the ramp voltage signal RAMP OUT. In the process of charging the first capacitor Cramp according to the first current I1, the number of current branches 111 can be controlled to control the size of the first current I1, and then control the charging speed of the first capacitor Cramp, so that the rising edge time of the ramp voltage signal RAMP OUT is controllable; similarly, in the process of discharging the first capacitor Cramp according to the second current I2, the number of current branches 111 can be controlled to control the size of the second current I2, and then control the discharging speed of the first capacitor Cramp, so that the falling edge time of the ramp voltage signal RAMP OUT is controllable; and then the ramp voltage signal RAMP OUT with controllable waveform slope is obtained. The number of current branches 111 can be flexibly adjusted to adjust the waveform slope of the ramp voltage signal RAMP OUT.

[0081] The rising edge time of the waveform of the ramp voltage signal RAMP OUT is equivalent to the current value of the first current I1 divided by the capacitance value of the first capacitor Cramp, and the falling edge time is equivalent to the current value of the second current I2 divided by the capacitance value of the first capacitor Cramp. Referring to Figure 4 Therefore, the waveform of the ramp voltage signal RAMP OUT is only related to the capacitance value of the first capacitor Cramp, the current value of the first current I1 and the current value of the second current I2, and is independent of the capacitance value of the load capacitor CP, which can adapt to the scene with a wide range of load capacitance. For example, the capacitance value of the load capacitor CP can range from 0 to 600pF.

[0082] In addition, the clamping circuit 102 clamps the ramp voltage signal RAMP OUT according to the first digital signal PD DATA IN and the reference voltage, so that the voltage value of the ramp voltage signal RAMP OUT is lower than the reference voltage. In the application of PD protocol, the reference voltage in the application can be 1.125V. The reference voltage can be generated by LDO or obtained by a reference chip, and the generation method of the reference voltage is not limited in the application. The clamping circuit 102 can clamp the voltage value of the ramp voltage signal RAMP OUT to 1.125V to prevent the voltage of the ramp voltage signal RAMP OUT from being too high, and the high level of the ramp voltage signal RAMP OUT is 1.125V.

[0083] Referring to Figure 4Since the driving capability of the ramp voltage signal RAMP_OUT in the present application is poor, the class AB operational amplifier circuit 200 is needed to amplify the ramp voltage signal RAMP_OUT to obtain the second digital signal PD_DATA_OUT, so as to increase the driving capability of the ramp voltage signal RAMP_OUT to drive the load capacitor with a wide range of capacitance values; in order to make the waveform of the second digital signal PD_DATA_OUT meet the eye diagram requirement, and at the same time make the voltage of the second digital signal PD_DATA_OUT follow the voltage of the ramp voltage signal RAMP_OUT. The present application amplifies the ramp voltage signal RAMP_OUT through the class AB operational amplifier circuit 200 to obtain the second digital signal PD_DATA_OUT which has driving capability and meets the eye diagram requirement.

[0084] In the embodiment of the present application, the driving circuit includes a ramp voltage generating circuit and a class AB operational amplifier circuit, and the ramp voltage generating circuit includes a controllable current source circuit, a first capacitor and a clamping circuit, wherein the controllable current source circuit includes a current branch. The controllable current source circuit obtains a first current and a second current according to the first digital signal, and the current sizes of the first current and the second current are positively correlated with the number of the current branches. Therefore, by setting the number of the current branches, the current sizes of the first current and the second current can be controlled, so that the first capacitor charges itself according to the first current and discharges itself according to the second current to obtain a ramp voltage signal. The waveform slope of the ramp voltage signal can be flexibly adjusted by controlling the number of the current branches, and then the waveform of the ramp voltage signal is only related to the current size of the first current, the current size of the second current and the capacitance value of the first capacitor, and is independent of the capacitance value of the load capacitor. Therefore, the scenario with a wide range of load capacitors can be adapted. The ramp voltage signal is amplified by the class AB operational amplifier circuit to obtain a second digital signal, which increases the driving capability of the ramp voltage signal and has a high power supply rejection ratio, and then a waveform meeting the eye diagram requirement is obtained.

[0085] In a possible embodiment, referring to Figure 5 The controllable current source circuit 101 can include an inverter 10, a first controllable current circuit 11 and a second controllable current circuit 12, wherein the first controllable current circuit 11 includes at least one current branch 111, and the second controllable current circuit 12 includes at least one current branch 111.

[0086] The inverter 10 is configured to perform level conversion on the first digital signal PD_DATA_IN to obtain a third digital signal PD_DATA_Z, and transmit the third digital signal PD_DATA_Z to the first controllable current circuit 11 and the second controllable current circuit 12.

[0087] The first controllable current circuit 11 is used to obtain the first current I1 according to the third digital signal PD_DATA_Z.

[0088] The second controllable current circuit 12 is used to obtain the second current I2 according to the third digital signal PD_DATA_Z.

[0089] In the embodiment, the inverter 10 is used to perform level conversion on the first digital signal PD_DATA_IN to obtain the third digital signal PD_DATA_Z, and the voltage of the third digital signal PD_DATA_Z is opposite to the voltage of the first digital signal PD_DATA_IN, for example, when the voltage of the first digital signal PD_DATA_IN is high, the voltage of the third digital signal PD_DATA_Z is low; when the voltage of the first digital signal PD_DATA_IN is low, the voltage of the third digital signal PD_DATA_Z is high.

[0090] The third digital signal PD_DATA_Z is used as a switch control signal of the first controllable current circuit 11 and the second controllable current circuit 12, and is used to control the first controllable current circuit 11 to output the first current I1 and control the second controllable current circuit 12 to output the second current I2.

[0091] In addition, the first controllable current circuit 11 includes at least one current branch 111, and the second controllable current circuit 12 includes at least one current branch 111, and the current value of the first current I1 and the second current I2 can be controlled by controlling the number of the current branch 111. Referring to Figure 5 In order to make the drawings clear, Figure 5 In the embodiment, the first controllable current circuit 11 and the second controllable current circuit 12 are both drawn with two current branches, and are taken as examples for description, and the number of the current branch 111 is not limited in actual application.

[0092] In the embodiment, the number of the current branch in the controllable current source circuit is controlled to control the current value of the first current and the second current, and then the charging speed and the discharging speed of the first capacitor are controlled, so that the rising edge time and the falling edge time of the slope voltage signal are controllable, and then the slope voltage signal with controllable waveform slope is obtained. In addition, the number of the current branch can also be used to flexibly adjust the waveform slope of the slope voltage signal.

[0093] In a possible embodiment, referring to Figure 5The first controllable current circuit 11 further comprises a first switch tube Q1 and a pull-up current source Isource.

[0094] A first end of the pull-up current source Isource is electrically connected to a first end of the current branch 111, and is used to access a power supply voltage VDD.

[0095] A control end of the first switch tube Q1 is electrically connected to an output end of the inverter 10, and a first end of the first switch tube Q1 is electrically connected to a second end of the pull-up current source Isource and a second end of the current branch 111 respectively.

[0096] A second end of the first switch tube Q1 is electrically connected to a first end of the first capacitor Cramp.

[0097] In the present application, the first switch tube Q1 can be a bipolar transistor or a field effect transistor, etc. For example, when the first switch tube Q1 is a bipolar transistor, the control end refers to the base of the bipolar transistor, and the first end can be the collector or the emitter of the bipolar transistor, and the corresponding second end can be the emitter or the collector of the bipolar transistor; when the first switch tube Q1 is a field effect transistor, the control end refers to the gate of the field effect transistor, and the first end can be the drain or the source of the field effect transistor, and the corresponding second end can be the source or the drain of the field effect transistor.

[0098] In the case where the first switch tube Q1 is a P-type MOS tube, the control end of the first switch tube Q1 refers to the gate of the P-type MOS tube, the first end of the first switch tube Q1 is the source of the P-type MOS tube, and the corresponding second end of the first switch tube Q1 is the drain of the P-type MOS tube.

[0099] In a possible embodiment, referring to Figure 5 The second controllable current circuit 12 further comprises a second switch tube Q2 and a pull-down current source Isink.

[0100] A control end of the second switch tube Q2 is electrically connected to the output end of the inverter 10, and a first end of the second switch tube Q2 is electrically connected to a first end of the pull-down current source Isink and a first end of the current branch 111 respectively.

[0101] A second end of the second switch tube Q2 is electrically connected to the first end of the first capacitor Cramp.

[0102] A second end of the pull-down current source Isink and the second end of the current branch 111 are both grounded.

[0103] The second end of the first capacitor Cramp is grounded.

[0104] In the application, the second switch Q2 can be a bipolar transistor or a field effect transistor, etc. For example, when the second switch Q2 is a bipolar transistor, the control end is the base of the bipolar transistor, the first end can be the collector or the emitter of the bipolar transistor, and the corresponding second end can be the emitter or the collector of the bipolar transistor; when the second switch Q2 is a field effect transistor, the control end is the gate of the field effect transistor, the first end can be the drain or the source of the field effect transistor, and the corresponding second end can be the source or the drain of the field effect transistor.

[0105] In the case where the second switch Q2 is an N-type MOS tube, the control end of the second switch Q2 is the gate of the N-type MOS tube, the first end of the second switch Q2 is the source of the N-type MOS tube, and the corresponding second end of the second switch Q2 is the drain of the N-type MOS tube.

[0106] In one possible embodiment, referring to Figure 5 The clamping circuit 102 comprises a comparator CMP, a third switch Q3, and a fourth switch Q4.

[0107] The non-inverting input end of the comparator CMP is electrically connected with the first end of the first capacitor Cramp and the second end of the third switch Q3 respectively, and serves as the output end of the ramp voltage generating circuit 100, for outputting a ramp voltage signal RAMP_OUT, the inverting input end of the comparator CMP is used for inputting a reference voltage (i.e. 1.125V), and the output end of the comparator CMP is electrically connected with the control end of the third switch Q3 and the second end of the fourth switch Q4 respectively.

[0108] The control end of the fourth switch Q4 is used for inputting a third digital signal PD_DATA_Z.

[0109] The first end of the third switch Q3 and the first end of the fourth switch Q4 are both grounded.

[0110] In the application, the third switch Q3 and the fourth switch Q4 can be a bipolar transistor or a field effect transistor, etc. For example, when the third switch Q3 and the fourth switch Q4 are bipolar transistors, the control end is the base of the bipolar transistor, the first end can be the collector or the emitter of the bipolar transistor, and the corresponding second end can be the emitter or the collector of the bipolar transistor; when the third switch Q3 and the fourth switch Q4 are field effect transistors, the control end is the gate of the field effect transistor, the first end can be the drain or the source of the field effect transistor, and the corresponding second end can be the source or the drain of the field effect transistor.

[0111] In the case that the third switch Q3 and the fourth switch Q4 are N-type MOS tubes, the control end of the third switch Q3 and the fourth switch Q4 refers to the gate of the N-type MOS tube, the first end of the third switch Q3 and the fourth switch Q4 is the source of the N-type MOS tube, and the second end of the third switch Q3 and the fourth switch Q4 is the drain of the N-type MOS tube.

[0112] Referring to Figure 6 The first current I1 is the sum of the current of the pull-up current source Isource and the current of each current branch 111, and the second current I2 is the sum of the current of the pull-down current source Isink and the current of each current branch 111. By controlling the switching state of the switch K0 in the current branch 111, the current output of the current source Is in the current branch 111 can be controlled, so that by setting the number of current branches and controlling the state of the switch in the current branch, the purpose of controlling the current size of the first current I1 and the second current I2 can be achieved.

[0113] In one example, when the number of current branches 111 in the first controllable current circuit 11 is set to 1 and the switch K0 is turned on, the first current I1 is 1A; when the number of current branches 111 in the first controllable current circuit 11 is set to 2 and the switches K0 are all turned on, the first current I1 is 2A. When the number of current branches 111 in the second controllable current circuit 12 is set to 1 and the switch K0 is turned on, the second current I2 is 1A; when the number of current branches 111 in the second controllable current circuit 12 is set to 2 and the switches K0 are all turned on, the second current I2 is 2A.

[0114] In one example, when the number of current branches 111 in the first controllable current circuit 11 is set to 2 and the switch K0 in one of the current branches 111 is turned on and the switch K0 in the other current branch 111 is turned off, the first current I1 is 1A; when the number of current branches 111 in the first controllable current circuit 11 is set to 2 and the switches K0 in both current branches 111 are turned on, the first current I1 is 2A. When the number of current branches 111 in the second controllable current circuit 12 is set to 2 and the switch K0 in one of the current branches 111 is turned on and the switch K0 in the other current branch 111 is turned off, the second current I2 is 1A; when the number of current branches 111 in the second controllable current circuit 12 is set to 2 and the switches K0 in both current branches 111 are turned on, the second current I2 is 2A.

[0115] Based on the above examples, the application can control the current size of the first current I1 and the second current I2 by setting the number of current branches, and also can control the current size of the first current I1 and the second current I2 by controlling the state of the switch in the current branch after setting the number of current branches. The application does not limit the specific way to control the current size of the first current I1 and the second current I2.

[0116] In actual project applications, the current size ratio relationship of the pull-up current source Isource and the current source Is in each current branch 111 can be set according to the design needs of the user. For example, the pull-up current source Isource: current source Is can be 1:1 or 1:2, and the current size of the current source Is in each current branch 111 can be equal or not equal, which is not limited by the application. Similarly, the current size ratio relationship of the pull-down current source Isink and the current source Is in each current branch 111 can also be set according to the design needs of the user, for example, the pull-down current source Isink: current source Is can be 1:1 or 1:2.

[0117] In actual project applications, the current mirror circuit can be used to set the current size ratio relationship of the pull-up current source Isource and the current source Is in each current branch 111. Similarly, the current mirror circuit can also be used to set the current size ratio relationship of the pull-down current source Isink and the current source Is in each current branch 111. In this way, the current size of the first current I1 and the second current I2 can be equal or not equal. The current mirror circuit is a prior art, which can realize the function of copying current and can adjust the copying ratio of current according to actual needs. The specific circuit structure of the current mirror circuit is not described again.

[0118] The first switch tube Q1 and the second switch tube Q2 are controlled by the third digital signal PD_DATA_Z to be turned on or turned off, so that the first capacitor Cramp is charged according to the first current I1 and is discharged according to the second current I2. By charging and discharging the first capacitor Cramp at different times, the ramp voltage signal RAMP_OUT is obtained.

[0119] Referring to Figure 6, the ramp voltage generating circuit 100 generates the ramp voltage signal in the following process: when the first digital signal PD_DATA_IN is high, the third digital signal PD_DATA_Z is low, at this time, the first switch Q1 is turned on, the second switch Q2 is turned off, the power supply voltage VDD charges the first capacitor Cramp with the first current I1, the charging rate is the current value of the first current I1 divided by the capacitance value of the first capacitor Cramp, until the voltage of the first capacitor Cramp is charged to 1.125V, when the voltage of the first capacitor Cramp is higher than 1.125V, the output end of the comparator CMP is high, the third switch Q3 is turned on, since the third digital signal PD_DATA_Z is low, the fourth switch Q4 is turned off, the first capacitor Cramp discharges to ground through the third switch Q3, and the voltage of the first capacitor Cramp is clamped at 1.125V. When the voltage of the first capacitor Cramp has not been charged to 1.125V, the output end of the comparator CMP is low, the third switch Q3 is turned off, and the discharge path is turned off. The power supply voltage VDD continues to charge the first capacitor Cramp with the first current I1 until the voltage of the first capacitor Cramp is charged to 1.125V.

[0120] When the first digital signal PD_DATA_IN is low, the third digital signal PD_DATA_Z is high, at this time, the second switch Q2 is turned on, the first switch Q1 is turned off, and the first capacitor Cramp discharges to ground with the second current I2, the discharging rate is the current value of the second current I2 divided by the capacitance value of the first capacitor Cramp, until the voltage of the first capacitor Cramp is discharged to 0V. During the discharging process, when the voltage of the first capacitor Cramp is lower than 1.125V, the output end of the comparator CMP is low, the third switch Q3 is turned off, and since the third digital signal PD_DATA_Z is high, the fourth switch Q4 is turned on.

[0121] Based on the above process of generating the ramp voltage signal RAMP_OUT by the ramp voltage generating circuit 100, the first digital signal PD_DATA_IN of 0-3.3V can be converted into the ramp voltage signal RAMP_OUT of 0-1.125V, and the waveform slope of the ramp voltage signal RAMP_OUT can be flexibly adjusted by setting the number of current branches 111 and the state of the switch K0 in the current branch 111. However, the driving ability of the ramp voltage signal RAMP_OUT is poor, and the class A / B operational amplifier circuit 200 is needed to increase the driving ability of the ramp voltage signal RAMP_OUT.

[0122] In a possible embodiment, referring to Figure 6 , Figure 6 A class A / B operational amplifier circuit structure schematic diagram provided by the embodiment of the application is as follows:Figure 6 As shown, the Class AB operational amplifier circuit 200 can include: a fully differential operational amplifier OP, a first bias current source Ibias1, a second bias current source Ibias2, a fifth switch tube Q5, a sixth switch tube Q6, a seventh switch tube Q7, an eighth switch tube Q8, a ninth switch tube Q9, a tenth switch tube Q10, an eleventh switch tube Q11, and a twelfth switch tube Q12.

[0123] The non-inverting input terminal of the fully differential operational amplifier OP is used to access the ramp voltage signal RAMP_OUT, the inverting input terminal of the fully differential operational amplifier OP is used to access the second digital signal PD_DATA_OUT, and the inverting output terminal Vp of the fully differential operational amplifier OP is electrically connected to the first terminal of the seventh switch tube Q7, the second terminal of the tenth switch tube Q10, and the control terminal of the eleventh switch tube Q11, respectively.

[0124] The non-inverting output terminal Vn of the fully differential operational amplifier OP is electrically connected to the second terminal of the seventh switch tube Q7, the first terminal of the tenth switch tube Q10, and the control terminal of the twelfth switch tube Q12, respectively.

[0125] The first terminal of the first bias current source Ibias1 is electrically connected to the first terminal of the fifth switch tube Q5 and the first terminal of the eleventh switch tube Q11, respectively, for accessing the power supply voltage VDD, and the control terminal of the fifth switch tube Q5 is electrically connected to the second terminal of the fifth switch tube Q5 and the first terminal of the sixth switch tube Q6, respectively.

[0126] The control terminal of the sixth switch tube Q6 is electrically connected to the second terminal of the sixth switch tube Q6, the control terminal of the seventh switch tube Q7, and the first terminal of the second bias current source Ibias2, respectively.

[0127] The second terminal of the first bias current source Ibias1 is electrically connected to the control terminal of the eighth switch tube Q8, the second terminal of the eighth switch tube Q8, and the control terminal of the tenth switch tube Q10, respectively.

[0128] The first terminal of the eighth switch tube Q8 is electrically connected to the control terminal of the ninth switch tube Q9 and the second terminal of the ninth switch tube Q9, respectively.

[0129] The second terminal of the eleventh switch tube Q11 is electrically connected to the second terminal of the twelfth switch tube Q12, serving as the output terminal of the Class AB operational amplifier circuit 200, for outputting the second digital signal PD_DATA_OUT.

[0130] The first terminal of the ninth switch tube Q9, the second terminal of the second bias current source Ibias2, and the first terminal of the twelfth switch tube Q12 are all grounded.

[0131] In a possible embodiment, the fifth switch tube Q5, the sixth switch tube Q6, the seventh switch tube Q7, and the eleventh switch tube Q11 are P-type MOS tubes, and the eighth switch tube Q8, the ninth switch tube Q9, the tenth switch tube Q10, and the twelfth switch tube Q12 are N-type MOS tubes.

[0132] The control end of the fifth switch tube Q5, the sixth switch tube Q6, the seventh switch tube Q7, and the eleventh switch tube Q11 is the gate of the P-type MOS tube, the first end of the fifth switch tube Q5, the sixth switch tube Q6, the seventh switch tube Q7, and the eleventh switch tube Q11 is the source of the P-type MOS tube, and the second end of the fifth switch tube Q5, the sixth switch tube Q6, the seventh switch tube Q7, and the eleventh switch tube Q11 is the drain of the P-type MOS tube.

[0133] The control end of the eighth switch tube Q8, the ninth switch tube Q9, the tenth switch tube Q10, and the twelfth switch tube Q12 is the gate of the N-type MOS tube, the first end of the eighth switch tube Q8, the ninth switch tube Q9, the tenth switch tube Q10, and the twelfth switch tube Q12 is the source of the N-type MOS tube, and the second end of the eighth switch tube Q8, the ninth switch tube Q9, the tenth switch tube Q10, and the twelfth switch tube Q12 is the drain of the N-type MOS tube.

[0134] Referring to Figure 6 The ramp voltage signal RAMP_OUT generated by the driving capability poor ramp voltage generating circuit 100 is input to the class AB operational amplifier circuit 200 in the application as an input signal of the class AB operational amplifier circuit 200, and is transmitted to the class AB operational amplifier circuit 200 in the application to enhance the driving capability of the ramp voltage signal RAMP_OUT. The class AB operational amplifier circuit in the application is essentially a class AB operational amplifier using a translinear loop. Specifically, the ramp voltage signal RAMP_OUT is first transmitted through the fully differential operational amplifier OP, and then the translinear loop structure is used to amplify the ramp voltage signal RAMP_OUT to obtain the second digital signal PD_DATA_OUT. The second digital signal PD_DATA_OUT is also electrically connected to the inverting input end of the fully differential operational amplifier OP as the output feedback of the driving circuit 1000, so that the voltage of the second digital signal PD_DATA_OUT can well follow the voltage of the ramp voltage signal RAMP_OUT.

[0135] Referring to Figure 6, the transconductance linearity loop structure in the class AB operational amplifier circuit 200 includes: a first bias current source Ibias1, a second bias current source Ibias2, a fifth switch tube Q5, a sixth switch tube Q6, a seventh switch tube Q7, an eighth switch tube Q8, a ninth switch tube Q9, a tenth switch tube Q10, an eleventh switch tube Q11, and a twelfth switch tube Q12. According to the topology of the transconductance linearity loop, in the case that the bias currents of the first bias current source Ibias1 and the second bias current source Ibias2 are constant values, VgsQ5+VgsQ6 is also a constant value, wherein VgsQ5 is the voltage difference between the gate and the source of the fifth switch tube Q5 (i.e., the gate-source voltage of the fifth switch tube Q5), and VgsQ6 is the voltage difference between the gate and the source of the sixth switch tube Q6 (i.e., the gate-source voltage of the sixth switch tube Q6).

[0136] The topology of the transconductance linearity loop includes the relationship: VgsQ5+VgsQ6=VgsQ11+VgsQ7, wherein VgsQ5 is the voltage difference between the gate and the source of the fifth switch tube Q5 (i.e., the gate-source voltage of the fifth switch tube Q5), VgsQ6 is the voltage difference between the gate and the source of the sixth switch tube Q6 (i.e., the gate-source voltage of the sixth switch tube Q6), VgsQ11 is the voltage difference between the gate and the source of the eleventh switch tube Q11 (i.e., the gate-source voltage of the eleventh switch tube Q11), and VgsQ7 is the voltage difference between the gate and the source of the seventh switch tube Q7 (i.e., the gate-source voltage of the seventh switch tube Q7).

[0137] Thus, the following relationship can be obtained: VgsQ11=VgsQ5+VgsQ6-VgsQ7, since VgsQ5+VgsQ6 is a constant value, VgsQ11=constant-VgsQ7 can be obtained, as shown in Figure 2 The source of the seventh switch tube Q7 is electrically connected to the inverting output terminal of the fully differential operational amplifier OP, so that the source current of the eleventh switch tube Q11 (i.e., the source current of the second digital signal PD_DATA_OUT output by the class AB operational amplifier circuit 200) is only related to the bias current of the fully differential operational amplifier OP and is not affected by the power supply voltage VDD ripple, thereby greatly improving the power supply rejection ratio of the driving circuit. Similarly, the source of the twelfth switch tube Q12 is electrically connected to the non-inverting output terminal of the fully differential operational amplifier OP, so that the sink current of the twelfth switch tube Q12 (i.e., the sink current of the second digital signal PD_DATA_OUT output by the class AB operational amplifier circuit) is only related to the bias current of the fully differential operational amplifier OP and is not affected by the ground GND ripple, thereby improving the power supply rejection ratio of the driving circuit.

[0138] As shown in Figure 7 The class AB operational amplifier circuit 200 in the present application is different from the conventional class AB operational amplifier circuit (as shown in Figure 7The optimization is carried out, including two-stage amplification structure, that is, full differential operational amplifier and transconductance linear loop topology structure are adopted, so that the driving capability of the slope voltage signal RAMP_OUT is increased, and the power supply rejection ratio of the driving circuit 1000 is effectively improved.

[0139] Therefore, the driving capability and bandwidth of the Class AB operational amplifier circuit 200 can be set according to design requirements, for example, the driving capability and bandwidth of the Class AB operational amplifier circuit can be increased, so that the voltage of the second digital signal PD_DATA_OUT follows the voltage of the slope voltage signal RAMP_OUT, and in this process, the second digital signal PD_DATA_OUT is not affected by the load capacitance CP, so as to drive the load capacitance CP with a wide range of capacitance values.

[0140] In order to adapt to a wide range of load scenarios and have a high power supply rejection ratio, the driving circuit 1000 in the application first obtains the first current I1 and the second current I2 according to the first digital signal PD_DATA_IN through the controllable current source circuit 101. The current sizes of the first current I1 and the second current I2 are positively correlated with the number of current branches 111. Therefore, by setting the number of current branches 111 and controlling the state of the switch K0 in the current branch 111, the current sizes of the first current I1 and the second current I2 can be controlled, so that the first capacitance Cramp is charged according to the first current I1 and discharged according to the second current I2 to obtain the slope voltage signal RAMP_OUT. In this way, the waveform slope of the slope voltage signal RAMP_OUT can be flexibly adjusted by controlling the number of current branches 111. The waveform of the slope voltage signal RAMP_OUT is only related to the current sizes of the first current I1 and the second current I2 and the capacitance value of the first capacitance Cramp, and is independent of the capacitance value of the load capacitance CP. Therefore, the driving circuit 1000 can adapt to a wide range of load capacitance scenarios.

[0141] Furthermore, this application amplifies the ramp voltage signal RAMP_OUT using a Class AB operational amplifier circuit 200 to obtain a second digital signal PD_DATA_OUT. The Class AB operational amplifier circuit 200 in this application is a Class AB operational amplifier using a transconductance linear loop, comprising a two-stage amplification structure, namely a first-stage amplification structure and a second-stage amplification structure. The first-stage amplification structure is a fully differential operational amplifier OP, which is a dual-input dual-output operational amplifier. The ramp voltage signal RAMP_OUT is first input to the non-inverting input terminal of the fully differential operational amplifier OP, and the inverting input terminal of the fully differential operational amplifier OP is electrically connected to the output terminal of the Class AB operational amplifier circuit 200, forming a feedback loop. The non-inverting output Vn and inverting output Vp of the fully differential operational amplifier OP are connected to the second-stage amplification structure, namely the transconducting linear loop. Through the topology of the transconducting linear loop and the included relationships, the current of the second digital signal PD_DATA_OUT output from the output terminal of the Class AB operational amplifier circuit 200 is only related to the bias current of the fully differential operational amplifier OP, and is not affected by the power supply voltage VDD ripple and ground GND ripple, which greatly improves the power supply rejection ratio of the drive circuit.

[0142] Therefore, the driving circuit 1000 in this application obtains a ramp voltage signal with controllable waveform slope through the ramp voltage generation circuit 100 to adapt to scenarios with a wide range of load capacitance. The driving capability of the ramp voltage signal is increased by the class AB operational amplifier circuit 200, and it has a high power supply rejection ratio.

[0143] In this embodiment of the application, the driving circuit obtains a waveform with driving capability and meeting the eye diagram requirements by using a ramp voltage generation circuit to generate a ramp voltage signal with a controllable waveform slope to adapt to scenarios with a wide range of load capacitance. Then, a class AB operational amplifier circuit is used to amplify the ramp voltage signal to obtain a second digital signal with stronger driving capability and a higher power supply rejection ratio to drive a load capacitor with a wide range of capacitance values. This significantly improves the performance of the eye diagram and thus obtains a waveform that meets the eye diagram requirements.

[0144] In addition, based on the driving circuit 1000 in this application, in order to further improve the stability of the driving circuit, this application introduces an additional capacitor for Miller compensation.

[0145] See Figure 7 , ​ A schematic diagram of another Class AB operational amplifier circuit provided in an embodiment of this application is shown below. ​ As shown, the Class AB operational amplifier circuit 200 may further include: a second capacitor C2 and a third capacitor C3.

[0146] The first end of the second capacitor C2 is electrically connected with the control end of the eleventh switch tube Q11, and the second end of the second capacitor C2 is electrically connected with the second end of the eleventh switch tube Q11.

[0147] The first end of the third capacitor C3 is electrically connected with the control end of the twelfth switch tube Q12, and the second end of the third capacitor C3 is electrically connected with the second end of the twelfth switch tube Q12.

[0148] Miller compensation is achieved by inserting a capacitor in the signal path of the amplifier by using the Miller Effect, and the principle of Miller compensation is to offset the zero point in the frequency response of the operational amplifier by introducing an additional capacitor, to improve the phase margin, so that the Class A and Class B operational amplifier circuit is more stable.

[0149] In the embodiment of the application, the second capacitor C2 is introduced between the control end of the eleventh switch tube Q11 and the second end of the eleventh switch tube Q11, and the third capacitor C3 is introduced between the control end of the twelfth switch tube Q12 and the second end of the twelfth switch tube Q12, and Miller compensation is achieved by introducing an additional capacitor, which can effectively enhance the stability of the Class A and Class B operational amplifier circuit.

[0150] The embodiment of the application further provides a fast charging protocol chip, which comprises the driving circuit as described above.

[0151] The fast charging protocol chip in the embodiment of the application can realize communication between the electronic device and the charging device through the PD protocol, so as to adapt the charging current of the charging device to the electronic device.

[0152] The embodiment of the application further provides an electronic device, which comprises the fast charging protocol chip as described above.

[0153] The electronic device in the embodiment of the application can include but is not limited to an adapter, a charger, a tablet computer, a smart home device, a vehicle and a wearable device.

[0154] Finally, it should be noted that the above embodiments are merely specific embodiments of the application, but the protection scope of the application is not limited thereto, and any changes or replacements within the technical scope disclosed in the application should be covered in the protection scope of the application. Therefore, the protection scope of the application should be subject to the protection scope of the claims.

Claims

1. A driving circuit, characterized in that, The driving circuit includes: a ramp voltage generating circuit and a class AB operational amplifier circuit. The ramp voltage generating circuit includes: a controllable current source circuit, a first capacitor, and a clamping circuit. The controllable current source circuit includes a current branch. The controllable current source circuit is used to obtain a first current and a second current based on a first digital signal, wherein the magnitudes of the first current and the second current are both positively correlated with the number of current branches. The first capacitor is used to charge itself according to the first current and discharge itself according to the second current to obtain a ramp voltage signal. The clamping circuit is used to clamp the ramp voltage signal according to the first digital signal and the reference voltage, so that the voltage value of the ramp voltage signal is lower than the reference voltage. The Class AB operational amplifier circuit is used to amplify the ramp voltage signal to obtain a second digital signal.

2. The driving circuit according to claim 1, characterized in that, The controllable current source circuit includes: an inverter, a first controllable current circuit, and a second controllable current circuit, wherein the first controllable current circuit includes at least one of the current branches, and the second controllable current circuit includes at least one of the current branches. The inverter is used to perform level conversion on the first digital signal to obtain a third digital signal, and transmit the third digital signal to the first controllable current circuit and the second controllable current circuit. The first controllable current circuit is used to obtain the first current based on the third digital signal; The second controllable current circuit is used to obtain the second current based on the third digital signal.

3. The driving circuit according to claim 2, characterized in that, The first controllable current circuit further includes: a first switching transistor and a pull-up current source; wherein, the current branch includes: a current source and a switch, the input terminal of the current source is electrically connected to the first terminal of the current branch, the output terminal of the current source is electrically connected to the first terminal of the switch, and the second terminal of the switch is electrically connected to the second terminal of the current branch; The first end of the pull-up current source is electrically connected to the first end of the current branch, and is used to connect to the power supply voltage; The control terminal of the first switching transistor is electrically connected to the output terminal of the inverter, and the first terminal of the first switching transistor is electrically connected to the second terminal of the pull-up current source and the second terminal of the current branch, respectively. The second terminal of the first switching transistor is electrically connected to the first terminal of the first capacitor.

4. The driving circuit according to claim 3, characterized in that, The second controllable current circuit also includes: a second switching transistor and a pull-down current source; The control terminal of the second switch is electrically connected to the output terminal of the inverter, and the first terminal of the second switch is electrically connected to the first terminal of the pull-down current source and the first terminal of the current branch, respectively. The second terminal of the second switching transistor is electrically connected to the first terminal of the first capacitor; The second terminal of the pull-down current source and the second terminal of the current branch are both grounded; The second terminal of the first capacitor is grounded.

5. The driving circuit according to claim 2, characterized in that, The clamping circuit includes: a comparator, a third switch, and a fourth switch; The non-inverting input of the comparator is electrically connected to the first terminal of the first capacitor and the second terminal of the third switch, and serves as the output terminal of the ramp voltage generating circuit for outputting the ramp voltage signal. The inverting input of the comparator is used to connect to the reference voltage. The output of the comparator is electrically connected to the control terminal of the third switch and the second terminal of the fourth switch. The control terminal of the fourth switch is used to connect to the third digital signal; The first terminal of the third switch and the first terminal of the fourth switch are both grounded.

6. The driving circuit according to claim 1, characterized in that, The Class AB operational amplifier circuit includes: a fully differential operational amplifier, a first bias current source, a second bias current source, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a ninth switch, a tenth switch, an eleventh switch, and a twelfth switch. The non-inverting input of the fully differential operational amplifier is used to receive the ramp voltage signal, the inverting input of the fully differential operational amplifier is used to receive the second digital signal, and the inverting output of the fully differential operational amplifier is electrically connected to the first terminal of the seventh switch, the second terminal of the tenth switch, and the control terminal of the eleventh switch, respectively. The non-inverting output terminal of the fully differential operational amplifier is electrically connected to the second terminal of the seventh switch, the first terminal of the tenth switch, and the control terminal of the twelfth switch, respectively. The first terminal of the first bias current source is electrically connected to the first terminal of the fifth switch and the first terminal of the eleventh switch, respectively, for connecting to the power supply voltage. The control terminal of the fifth switch is electrically connected to the second terminal of the fifth switch and the first terminal of the sixth switch, respectively. The control terminal of the sixth switch is electrically connected to the second terminal of the sixth switch, the control terminal of the seventh switch, and the first terminal of the second bias current source, respectively. The second terminal of the first bias current source is electrically connected to the control terminal of the eighth switch, the second terminal of the eighth switch, and the control terminal of the tenth switch, respectively. The first terminal of the eighth switch is electrically connected to the control terminal of the ninth switch and the second terminal of the ninth switch, respectively. The second terminal of the eleventh switch is electrically connected to the second terminal of the twelfth switch, serving as the output terminal of the Class AB operational amplifier circuit for outputting the second digital signal; The first terminal of the ninth switch, the second terminal of the second bias current source, and the first terminal of the twelfth switch are all grounded.

7. The driving circuit according to claim 6, characterized in that, The fifth, sixth, seventh, and eleventh switching transistors are all P-type MOSFETs, while the eighth, ninth, tenth, and twelfth switching transistors are all N-type MOSFETs.

8. The driving circuit according to claim 6, characterized in that, The Class AB operational amplifier circuit further includes: a second capacitor and a third capacitor; The first terminal of the second capacitor is electrically connected to the control terminal of the eleventh switch, and the second terminal of the second capacitor is electrically connected to the second terminal of the eleventh switch. The first terminal of the third capacitor is electrically connected to the control terminal of the twelfth switch, and the second terminal of the third capacitor is electrically connected to the second terminal of the twelfth switch.

9. The driving circuit according to claim 3, characterized in that, When the driving circuit is applied to a fast charging protocol chip that supports the PD protocol, the high level of the first digital signal is the power supply voltage, and the low level of the first digital signal is zero; the rise time and fall time of the second digital signal are both not less than 300ns, the high level of the second digital signal is 1.125V±100mV, and the low level of the second digital signal is ±100mV.

10. A fast charging protocol chip, characterized in that, include: The driving circuit as described in any one of claims 1-9.

11. An electronic device, characterized in that, include: The fast charging protocol chip as described in claim 10.

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