Solar cell, manufacturing method thereof and photovoltaic module

Abstract

The invention discloses a solar cell and a manufacturing method thereof, and a photovoltaic module, and relates to the field of photovoltaic technology. The solar cell includes: a semiconductor substrate having a first surface including a first region and a second region adjacent to a first cut side; the second region comprises a step structure, an included angle is formed between the side wall of the step structure and the thickness direction of the semiconductor substrate, the first region is provided with a first pyramid structure, and the bottom wall of the step structure is provided with a first texture structure or a second pyramid structure; the first doping layer is arranged on the first region, and the height of the bottom wall of the step structure is lower than that of the first doping layer; the first passivation layer is arranged on one side, deviating from the semiconductor substrate, of the first doping layer and is arranged on the second region; the second passivation layer is arranged on the edge, close to the second area, of the first area, part of the second area and the first cutting side face. The passivation effect near the cutting side face is improved, carrier recombination is reduced, and the photoelectric conversion efficiency is improved.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202510792152.8, filed on June 12, 2025, entitled “A Solar Cell and a Method for Manufacturing the Same Thereof, and a Photovoltaic Module”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of photovoltaic technology, and in particular to a solar cell and its manufacturing method, and a photovoltaic module. Background Technology

[0004] A solar cell is a device that converts sunlight into electrical energy. Specifically, when a solar cell is in operation, sunlight shines on the semiconductor pn junction of the solar cell, forming new electron-hole pairs. Under the influence of the built-in electric field of the pn junction, photogenerated holes flow to the p-region, and photogenerated electrons flow to the n-region. When the circuit is connected, an electric current is generated.

[0005] Half-cell solar cells offer better power output and efficiency compared to full-cell solar cells. Therefore, they are commonly used in the fabrication of photovoltaic modules. However, the process of cutting full-cell solar cells into half-cells can create defects such as dangling bonds near the cut side, increasing carrier recombination and reducing photoelectric conversion efficiency. Summary of the Invention

[0006] The purpose of this application is to provide a solar cell and its manufacturing method, as well as a photovoltaic module, to improve the passivation effect near the cut side, reduce carrier recombination, and improve photoelectric conversion efficiency.

[0007] To achieve the above objectives, this application provides the following technical solution:

[0008] A solar cell, comprising:

[0009] A semiconductor substrate includes a first surface and a second surface opposite to each other, and a first cut side surface connecting the first surface and the second surface. The first surface includes a first region and a second region adjacent to the first cut side surface. The second region includes a stepped structure recessed into the second surface. The first region is provided with a first type of pyramid structure. The bottom wall of the stepped structure is provided with a first texture structure or a second type of pyramid structure. The side wall of the stepped structure has an angle with the thickness direction of the semiconductor substrate.

[0010] A first doped layer is disposed on the first region; along the thickness direction of the semiconductor substrate, the height of the bottom wall of the stepped structure is lower than the height of the first doped layer;

[0011] a first passivation layer disposed on a side of the first doped layer facing away from the semiconductor substrate and on part of the second region;

[0012] a second passivation layer disposed on an edge of the first region close to the second region, the second region and the first cutting side, and the second passivation layer is disposed on a side of the first passivation layer facing away from the semiconductor substrate.

[0013] In the solar cell provided by the application, the height of the bottom wall of the step structure is lower than the height of the first doped layer. Thus, in the cutting process, the position of the laser cutting is farther from the first doped layer, which reduces the damage of the laser to the first doped layer and reduces the damage to the passivation performance of the first doped layer. On the other hand, the probability of the recombination of the carrier in the first doped layer with the dangling bond formed in the cutting process is reduced, and thus the influence of the cutting on the transmission performance of the first doped layer is reduced. Then, the first passivation layer is disposed on the second region, and the second passivation layer disposed on the first cutting side is wrapped to the second region. Thus, the double-layer passivation of the first passivation layer and the second passivation layer on the second region further improves the passivation effect of the second region. In addition, the second passivation layer also wraps the edges of the first cutting side to the second region and the edges of the second region to the first region, thereby improving the passivation effect of the edges between the first region and the second region. That is, the embodiments of the application can compensate for various passivation defects caused by cutting and improve the overall passivation effect of the cell piece. In addition, the first passivation layer is disposed on the part of the second region provided with the first texture structure or the second type of pyramid structure and the inclined step side wall, which can improve the light trapping effect and provide a larger surface area, thereby providing a larger deposition area for the subsequent deposition of the passivation layer, so as to balance the passivation and light trapping effects.

[0014] In an implementation manner, along the extension direction of the second region, the second region includes an edge region and a middle region, the middle region and the edge region include the first step structure recessed to the second surface in communication, the height of the bottom wall of the first step structure is lower than the first doped layer, and the step bottom wall of the first step structure of the edge region is provided with a second step structure, and the first passivation layer is disposed on the step side wall and the step bottom wall of the first step structure.

[0015] The first passivation layer is arranged on the step bottom wall and the step side wall of the first step structure. In this way, the first passivation layer is arranged on the bottom wall of the first step structure, which can protect the edge portion of the first step structure bottom wall close to the second step structure. Especially in the case where the second step structure is made by a lossy laser, the first passivation layer of the first step bottom wall has a significant passivation effect. In the embodiment, the edge region of the second region includes the first step structure and the second step structure, so that the second passivation layer can protect the first step structure and the second step structure of the battery piece and the first cutting side, especially can bypass the edge of the first cutting side to the bottom wall of the second step, the edge of the second step structure side wall to the bottom wall of the first step structure, and the edge of the inclined side wall of the first step structure to the first region, which can fully passivate the edge region, reduce the recombination site, and improve the photoelectric conversion efficiency of the battery piece.

[0016] In an implementation manner, along the extension direction of the second region, the second region includes an edge region and a middle region, the middle region is recessed to the second surface to form a first step structure, the edge region is recessed to the second surface to form a second step structure, a step depth of the second step structure is greater than a step depth of the first step structure, a width of the first step structure is greater than a width of the second step structure, a height of a bottom wall of the first step structure is lower than the first doped layer, the first passivation layer is arranged on a step side wall and a step bottom wall of the first step structure, and a width of the first region covered by the second passivation layer is to an edge of the middle region of the second region corresponding to the first region.

[0017] In the embodiment, the thickness of the battery piece in the partial region along the cutting direction of the battery piece is thinned, which reduces the difficulty of splitting from the deep groove of the edge region. In addition, the second passivation layer passivating the first cutting side needs to wrap around the first region of the front surface, and the width of the first region wrapped around needs to cover the edge recessed to the non-cutting edge due to the step structure of the middle region. In this way, the second passivation layer wraps around two edges of the bottom wall of the first step structure and the second step structure from the first cutting side, and two edges from the side wall of the first step structure and the second step structure to the first region, thereby improving the passivation effect of the battery piece as a whole. Therefore, the embodiment can reduce the difficulty of splitting while improving the passivation effect of the battery piece.

[0018] In an implementation manner, a width of the first region covered by the second passivation layer is greater than a width of the second step structure.

[0019] In an implementation manner, the second surface is provided with a third passivation layer, and the second passivation layer extends to the edge of the second surface and is located on the side of the third passivation layer away from the semiconductor substrate.

[0020] In an implementation, the first step structure has a step depth of 2-10 um along the thickness direction of the semiconductor substrate; and / or

[0021] The second step structure has a step depth of 30% H-100% H, H being the thickness of the solar cell; and / or

[0022] The included angle is 15-60°.

[0023] In an implementation, the first step structure is provided with a prismatic structure on the sidewall thereof.

[0024] In an implementation, the first region is provided with a first type of pyramid structure, the bottom wall of the first step structure of the second region is provided with a first texture structure, the second surface is provided with a second texture structure, and the one-dimensional size of the first texture structure is greater than that of the second texture structure.

[0025] In an implementation, the one-dimensional size of the first texture structure is 15-50 um; and / or, the one-dimensional size of the second texture structure is 2-20 um.

[0026] In an implementation, the solar cell further comprises a second doped layer provided on the second surface, the second doped layer has a conductivity type opposite to that of the first doped layer, and the second surface is entirely provided with the second texture structure; or

[0027] The solar cell further comprises second doped layers provided at intervals on the second surface, the second doped layers have a conductivity type opposite to that of the first doped layer, and the second surface is provided with the second texture structure in the interval region between two adjacent second doped layers.

[0028] In an implementation, the solar cell further comprises second doped layers provided at intervals on the second surface, the second doped layers have a conductivity type opposite to that of the first doped layer, the first region is provided with a first type of pyramid structure, and the bottom wall of the first step structure of the second region is provided with a second type of pyramid structure.

[0029] In an implementation, the one-dimensional size of the first type of pyramid structure is greater than that of the second type of pyramid structure; and / or

[0030] The second surface is provided with the third type of pyramid structure in the interval region between two adjacent second doped layers, and the one-dimensional size of the third type of pyramid structure is smaller than that of the second type of pyramid structure; and / or

[0031] a depth range of a spacing region between two adjacent second doping layers of the second surface is the same as a step depth range of the first step structure;

[0032] a range of an included angle between a sidewall of a spacing region between two adjacent second doping layers of the second surface and a thickness direction of the semiconductor substrate is the same as a range of an included angle between a sidewall of the step structure and the thickness direction of the semiconductor substrate.

[0033] In an implementation manner, the first step structure is in a wave shape or a meander shape along an extension direction of the first step structure; and / or,

[0034] the first step structure continuously extends or discontinuously extends along an extension direction of the first step structure; and / or,

[0035] a width of the first step structure along a direction perpendicular to the first cutting side surface is 20 μm to 500 μm.

[0036] In an implementation manner, a thickness of the second passivation layer at the first cutting side surface is greater than a thickness of the second passivation layer at the second region.

[0037] In an implementation manner, a thickness of the second passivation layer is greater than a thickness of the first passivation layer.

[0038] In an implementation manner, the semiconductor substrate further comprises a second cutting side surface, the second cutting side surface is oppositely arranged with the first cutting side surface, the first surface further comprises a third region adjacent to the second cutting side surface, the first region is located on a side of the third region away from the second cutting side surface, the third region comprises a step structure recessed to the second surface, a bottom wall of the step structure of the third region is provided with a texture structure or a pyramid-like structure, a sidewall of the step structure of the third region has an included angle with a thickness direction of the semiconductor substrate, along the thickness direction of the semiconductor substrate, a height of the bottom wall of the step structure of the third region is lower than a height of the first doping layer; a fourth passivation layer, the fourth passivation layer is arranged at an edge of the first region close to the third region, the third region and the second cutting side surface, and the fourth passivation layer is located on a side of the first passivation layer away from the semiconductor substrate.

[0039] In an implementation manner, a step depth of the step structure of a middle region of the second region is the same as a step depth of the step structure of a middle region of the third region; and / or

[0040] a step depth of the step structure of an edge region of the second region is the same as a step depth of the step structure of an edge region of the third region; and / or,

[0041] a step width of the step structure of the edge region of the second region is the same as a step width of the step structure of the edge region of the third region.

[0042] a step width of the step structure of the edge region of the second region is the same as a step width of the step structure of the edge region of the third region.

[0043] A photovoltaic module comprising a plurality of cell strings connected in parallel and / or in series, the cell strings comprising a plurality of solar cells according to any one of the preceding solar cells connected in series.

[0044] Compared with the prior art, the photovoltaic module provided by the application has the same advantages as the above-mentioned solar cells, which will not be described here again.

[0045] A solar cell, the solar cell comprising a groove, and the solar cell according to any one of the preceding solar cells is obtained by dicing at the groove.

[0046] In an implementation manner, the groove is arranged at a middle region of the second region along a second region extension direction.

[0047] In an implementation manner, an edge region of the second region is provided with a groove structure; and the groove structure is a Y-shaped groove.

[0048] In an implementation manner, a depth of the groove structure is greater than a depth of the groove.

[0049] A manufacturing method of a solar cell, comprising:

[0050] providing a semiconductor substrate comprising opposite first and second surfaces, the first surface comprising a first region and a second region;

[0051] forming a first doped layer and a first doped silicon glass layer on the first surface;

[0052] reducing the density of the first doped silicon glass layer of the second region by laser irradiation;

[0053] trough polishing the second surface and removing part of the first doped silicon glass layer of the second region, and forming a groove recessed towards the second surface in the second region;

[0054] forming a second doped layer on the second surface, the second doped layer being opposite in conductivity type to the first doped layer;

[0055] removing the second doped silicon glass layer of the second surface and forming a first texture structure or a second pyramidal structure in the groove, and making the side wall of the groove have an included angle with the thickness direction of the semiconductor substrate, and along the thickness direction of the semiconductor substrate, the height of the bottom wall of the groove is lower than the height of the first doped layer;

[0056] forming a first passivation layer on the first surface, the first passivation layer being located on the side of the first doped layer away from the semiconductor substrate;

[0057] forming a first electrode on the first doped layer and a second electrode on the second doped layer;

[0058] cutting the semiconductor substrate along the groove to obtain a plurality of solar cells;

[0059] forming a second passivation layer on the edge of the first region close to the second region, the second region and the first cutting side, the second passivation layer being located on the side of the first passivation layer away from the semiconductor substrate.

[0060] In an implementation, after forming a first electrode on the first doped layer and a second electrode on the second doped layer, before cutting the semiconductor substrate along the groove to obtain a plurality of solar cells, the method for manufacturing a solar cell further comprises the steps of:

[0061] forming a trench structure in the edge region of the second region by using a laser;

[0062] cutting along the groove and the trench structure to obtain a plurality of solar cells.

[0063] A method for manufacturing a solar cell, comprising:

[0064] providing a semiconductor substrate, the semiconductor substrate comprising opposite first and second surfaces, the first surface comprising a first region and a second region;

[0065] forming a first doped layer and a first doped silicon glass layer on the first surface;

[0066] forming a second doped layer and a second doped silicon glass layer on the second surface, the second doped layer being opposite in conductive type to the first doped layer;

[0067] reducing the density of the first doped silicon glass layer of the second region and the interval by using a laser;

[0068] removing the first doped silicon glass layer and the second doped silicon glass layer, and forming a groove in the groove, so that the groove has an included angle between the sidewall of the groove and the thickness direction of the semiconductor substrate, and the height of the bottom wall of the groove is lower than the height of the first doped layer along the thickness direction of the semiconductor substrate;

[0069] forming a first passivation layer on the first surface, the first passivation layer being located on the side of the first doped layer away from the semiconductor substrate;

[0070] forming a first electrode on the first doped layer and a second electrode on the second doped layer;

[0071] cutting the semiconductor substrate along the groove to obtain a plurality of solar cells;

[0072] forming a second passivation layer on the edge of the first region close to the second region, the second region, and the first cutting side, the second passivation layer being located on the side of the first passivation layer away from the semiconductor substrate.

[0073] In an implementation, after forming a first electrode on the first doped layer and a second electrode on the second doped layer, before cutting the semiconductor substrate along the groove to obtain a plurality of solar cells, the method for manufacturing the solar cell further comprises the steps of:

[0074] forming a groove structure in the edge region of the second region by using a laser;

[0075] cutting along the groove and the groove structure to obtain a plurality of solar cells.

[0076] Compared with the prior art, the method for manufacturing the solar cell provided by the application is used to form any one of the above-mentioned solar cells, so the beneficial effects of the method for manufacturing the solar cell are the same as those of the above-mentioned solar cell, which will not be described here again.

[0077] A photovoltaic module is provided, comprising: a plurality of cell strings connected in series and / or parallel, the cell string comprising: an electrical connector and a first solar cell and a second solar cell, the first solar cell being the solar cell of the first aspect, or the solar cell obtained by the manufacturing method of the second aspect, the first solar cell and the second solar cell being connected by the electrical connector, the distance between the starting end of the electrical connector and the edge of the first region being greater than the width of the step structure of the middle region, and the electrical connector passing through the first surface and the second side surface of the first solar cell, and passing through the second surface of the second solar cell, the second side surface being the side surface opposite to the first cutting surface in the first solar cell, and the edge of the first region being the boundary between the first region and the second region.

[0078] In some possible implementation manners, a distance between the starting end of the electric connecting piece and the edge of the first area is greater than or equal to 1 mm.

[0079] In some possible implementation manners, the second side is a non-cutting side. BRIEF DESCRIPTION OF DRAWINGS

[0080] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0081] Figure 1 A schematic view of a photovoltaic module according to an embodiment of the application;

[0082] Figure 2 A micro view of a solar cell according to an embodiment of the application;

[0083] Figure 3 A partial sectional view of a solar cell according to an embodiment of the application;

[0084] Figure 4 A partial sectional view of a solar cell according to another embodiment of the application;

[0085] Figure 5 A top view of a first surface of a whole cell before cutting according to an embodiment of the application

[0086] Figure 6 A top view of a first surface of a half cell according to an embodiment of the application;

[0087] Figure 7 A top view of a first surface of a whole cell before cutting according to another embodiment of the application;

[0088] Figure 8 A partial structural sectional view of a whole cell before cutting according to an embodiment of the application;

[0089] Figure 9 A partial sectional view of a solar cell according to another embodiment of the application;

[0090] Figure 10 A partial sectional view of a solar cell according to another embodiment of the application;

[0091] Figure 11 A partial sectional view of a solar cell according to another embodiment of the application;

[0092] Figure 12 A partial sectional view of a solar cell according to another embodiment of the application;

[0093] Figure 13 A plan view of a solar cell according to another embodiment of the application is provided.

[0094] Figure 14 A schematic view of a photovoltaic module according to an embodiment of the application is provided.

[0095] Reference signs:

[0096] 1 - first region, 2 - second region, 3 - step sidewall, 10 - semiconductor substrate, 11 - first interface layer, 12 - first doped layer, 13 - first passivation layer, 14 - first electrode, 15 - second interface layer, 16 - second doped layer, 17 - third passivation layer, 18 - second electrode, 19 - second passivation layer; 30 - groove structure, 31 - groove, 32 - trench, 21 - intermediate region, 22 - edge region;

[0097] A - solar cell, a - sub-piece, C - cutting line. DETAILED DESCRIPTION

[0098] In order to make the technical problems to be solved, technical solutions and beneficial effects of the present application clearer, further detailed description of the present application will be given below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application.

[0099] It should be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0100] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly and specifically limited. The meaning of "several" is one or more, unless otherwise explicitly and specifically limited.

[0101] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0102] In the description of the present application, it should be noted that unless specifically defined and limited otherwise, the terms "mount", "connect", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0103] It should be noted that the various embodiments of the present application can be implemented as separate embodiments, and can also be combined without logical conflict, which is not limited in the present application.

[0104] The present application provides a kind of photovoltaic module, the photovoltaic module includes multiple parallel and / or series cell strings, each cell string includes electrical connector and multiple series solar cells, electrical connector is electrically connected at least two solar cells.Exemplarily, Figure 1 A schematic diagram of multiple solar cells electrically connected together is provided.As shown in Figure 1 Multiple solar cells are arranged in sequence along direction A to form a cell string, and multiple solar cells in the cell string are connected in series.Two or more cell strings are arranged in sequence along direction A to form a group of cell strings, and multiple groups of cell strings are arranged in sequence along direction B.

[0105] Compared with whole piece of cell piece, half piece of cell piece has better power output and efficiency. Therefore, half piece of cell piece is currently often used to prepare photovoltaic module. However, in the process of cutting whole piece of cell piece to form half piece of cell piece, defects such as dangling bond are formed near the cutting side surface due to laser loss, which increases carrier recombination and reduces photoelectric conversion efficiency.

[0106] In view of the above, in order to improve the passivation effect near the cutting side surface, reduce carrier recombination and improve photoelectric conversion efficiency, the present application also provides a solar cell and a preparation method thereof, which can be applied to the above-mentioned photovoltaic module.

[0107] The solar cell provided by the embodiments of the present application includes a semiconductor substrate 10, which includes opposite first and second surfaces, i.e. the two surfaces opposite along the thickness direction of the semiconductor substrate 10 are the first and second surfaces respectively. The first surface can correspond to the light-receiving surface of the solar cell, and the second surface corresponds to the back surface of the solar cell; or, the first surface can correspond to the back surface of the solar cell, and the second surface corresponds to the light-receiving surface of the solar cell. In the present application, the first surface corresponds to the light-receiving surface of the solar cell, and the second surface corresponds to the back surface of the solar cell.

[0108] The semiconductor substrate 10 includes a first cutting side, i.e., the solar cell is a cut cell, and at least one side of the semiconductor substrate 10 is a cutting surface after cutting, and the first cutting side is the cutting surface after cutting. The following embodiments are described by taking the cut cell as an example. As shown in Figure 2 the first surface includes a first region 1 and a second region 2, the second region 2 is adjacent to the first cutting side, and the first region 1 is located on a side of the second region 2 away from the first cutting side. That is, the second region 2 is adjacent to the first cutting side compared to the first region 1, and the second region 2 is located between the first region 1 and the first cutting side. As shown in Figure 2 the second region 2 includes a step structure recessed toward the second surface, and the second region 2 can be recessed as a whole to form the step structure, or part of the second region 2 is recessed to form the step structure. The step structure and the first region 1 form a step side wall 3, and the step structure includes the step side wall 3 and a step bottom wall.

[0109] In some possible embodiments, the first region 1 is provided with a first type of pyramid structure, and the step bottom wall of the second region 2 is provided with a first texture structure or a second type of pyramid structure. For example Figure 10 , the step bottom wall is provided with the second type of pyramid structure; or, for example Figure 11 , the step bottom wall is provided with the first texture structure. The first type of pyramid structure and / or the second type of pyramid structure can include pyramids with sharp corners, pyramids with rounded corners, or pyramids with flattened corners. With this technical solution, the first type of pyramid structure of the first region 1, the first texture structure or the second type of pyramid structure of the second region 2 can improve the light trapping effect of the light surface, reduce the reflectivity of light, and help more light to be reflected into the semiconductor substrate 10 and utilized by the semiconductor substrate 10, thereby improving the light absorption utilization rate. The first texture structure or the second type of pyramid structure of the second region 2 can increase the specific surface area and roughness of the second region 2, play a certain anchoring role, help to improve the adhesion of the second region 2 after lamination, prevent the second region 2 of the cell from delaminating or peeling off, and prolong the service life of the solar cell.

[0110] In some embodiments, referring to Figure 3 , the side wall of the step structure is parallel to the thickness direction of the semiconductor substrate 10. The side wall of the step structure can be arranged perpendicular to the first surface of the semiconductor substrate 10, which simplifies the processing process and improves the processing efficiency.

[0111] In some embodiments, referring to Figure 4, the step side wall 3 and the thickness direction of the semiconductor substrate 10 have an included angle. Specifically, the step side wall 3 gradually inclines from the bottom to the top to the direction close to the first region 1, forming a slope. In this way, the stress concentration near the step side wall 3 during the lamination process can be avoided, and the stress concentration caused by the hidden cracks of the battery piece can be avoided, thereby improving the product yield.

[0112] As shown in Figure 4 , the first doped layer 12 is arranged on the first region 1. Specifically, the first doped layer 12 can cover all or part of the first region 1. The first doped layer 12 can be additionally formed on the semiconductor substrate 10 by deposition technology, or can be formed in the semiconductor substrate 10 by diffusion, ion implantation and the like. Along the thickness direction of the semiconductor substrate 10, the height of the step bottom wall is lower than the height of the first doped layer 12. That is, when the first surface is upward, the step bottom wall is arranged lower than the bottom side of the first doped layer 12, and the step bottom wall has a height difference with the first doped layer 12. The side wall of the step structure and the thickness direction of the semiconductor substrate 10 have an included angle. Specifically, the side wall of the first step structure gradually inclines from the bottom to the top to the direction close to the first region 1, forming a slope. In this way, the stress concentration near the side wall of the step structure during the lamination process can be avoided, and the stress concentration caused by the hidden cracks of the battery piece can be avoided, thereby improving the product yield. In addition, the inclined step side wall can form a larger deposition area for the subsequent passivation layer, and form a uniform passivation layer.

[0113] As shown in Figure 4 , the first passivation layer 13 is arranged on the side of the first doped layer 12 away from the semiconductor substrate 10, and on part of the second region. The first passivation layer 13 can protect the surface of the battery piece, prevent water vapor or oxygen from penetrating into the battery piece, thereby avoiding the performance degradation of the battery piece caused by oxidation or hydrolysis; and the arrangement of the first passivation layer 13 can reduce the surface recombination rate of the battery piece and reduce the reflectivity of light, thereby improving the photoelectric conversion efficiency of the battery. It can be understood that the first passivation layer 13 can be a single-layer structure; or the first passivation layer 13 can also be a multi-layer structure. Specifically, the first passivation layer 13 is at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, an aluminum oxide layer or a composite film stacked by them. For example, the first passivation layer 13 can be a double-layer structure, which includes an aluminum oxide layer and a silicon nitride layer, and the aluminum oxide layer is located on the side of the silicon nitride layer close to the semiconductor substrate 10.

[0114] Referring to Figure 4In some embodiments, the solar cell further comprises a second passivation layer 19 disposed on the edge of the first region 1 close to the second region 2, the second region 2 and the first cutting side, and the second passivation layer 19 is located on the side of the first passivation layer 13 away from the semiconductor substrate 10. In some embodiments, the solar cell further comprises a second passivation layer 19 disposed on the edge of the first region 1 close to the second region 2, the second region 2 and the first cutting side, and the second passivation layer 19 is located on the side of the first passivation layer 13 away from the semiconductor substrate 10. The second passivation layer 19 can protect the second region 2 and the first cutting side of the cell sheet, especially the edge of the second region 2 around the first cutting side and the edge of the second region 2 to the first region, which can be fully passivated to reduce the recombination sites and improve the photoelectric conversion efficiency of the cell sheet. The number of layers and the material of the second passivation layer 19 can refer to the description of the first passivation layer 13, for example, the second passivation layer 19 can be a single layer structure, and the single layer structure is an aluminum oxide layer.

[0115] Therefore, in the solar cell provided by the present application, the height of the bottom wall of the step structure is lower than the height of the first doped layer 12, so that the position of the laser cutting is farther away from the first doped layer 12 during the cutting process, which reduces the damage of the laser to the first doped layer 12 and reduces the damage to the passivation performance of the first doped layer 12, and reduces the probability of the recombination of the suspended bonds of the carriers in the first doped layer 12 during the cutting process, thereby reducing the influence of the cutting on the transmission performance of the first doped layer 12. Then, the first passivation layer is arranged on the second region, and the second passivation layer arranged on the first cutting side is wrapped around the second region, so that the second region is further passivated by the double-layer passivation of the first passivation layer and the second passivation layer, and the passivation effect of the second region is further improved. In addition, the second passivation layer also wraps the edge of the second region from the first cutting side and the edge of the second region to the first region, thereby improving the passivation effect of the edge between the first region and the second region. That is, the embodiments of the present application can compensate for various passivation defects caused by cutting and improve the overall passivation effect of the cell sheet. In addition, the first passivation layer arranged on the part of the second region with the first texture structure or the second type of pyramid structure and the inclined step side can improve the light trapping effect while providing a larger surface area, thereby providing a larger deposition area for the subsequent deposition of the passivation layer, so as to balance the passivation and light trapping effects.

[0116] It can be understood that the first doped layer 12 can be a P-type doped layer or an N-type doped layer. The P-type doped layer can contain one or more of the group IIIA elements (for example, it can be boron). The N-type doped layer can contain one or more of the group VA elements (for example, it can be phosphorus). The materials of the N-type doped layer and the P-type doped layer can include any one of semiconductor materials such as silicon, silicon germanium, germanium, or gallium arsenide. In terms of the arrangement of the materials, the crystal phase of the doped layer can be amorphous, microcrystalline, nanocrystalline, single crystal, or polycrystalline. Among them, the materials of the N-type doped layer and the P-type doped layer can be the same or different. For example, the materials of the N-type doped layer and the P-type doped layer can both include doped polysilicon. For another example, the material of the P-type doped layer can include doped polysilicon, and the material of the N-type doped layer can include at least one of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon. The P-type doped layer can be obtained by in-situ doping on the surface of the silicon substrate or deposited on the surface of the silicon substrate. The N-type doped layer can also be obtained by in-situ doping on the surface of the silicon substrate or deposited on the surface of the silicon substrate. The silicon substrate 1 can be N-type single crystal silicon or P-type single crystal silicon, which can provide long-lived carriers.

[0117] In some possible embodiments, when the semiconductor substrate and the first doped layer 12 form a PN junction, for example, the semiconductor substrate 10 is an N-type substrate, and the first doped layer 12 is a P-type doped layer, the semiconductor substrate 10 and the first doped layer 12 form a PN junction. The height of the bottom wall of the step structure is lower than the height of the first doped layer 12, which can be understood as removing the PN junction in the edge region of the cell piece close to the cutting surface, that is, removing the P-type doped layer (that is, removing the highly doped B atoms), which can effectively suppress the probability of carrier recombination in the second region, reduce the influence on the field passivation effect of the passivation layer on the subsequent cutting surface, and make the subsequent passivation effect better, thereby helping to reduce the power loss caused by laser cutting.

[0118] In some possible embodiments, with reference to Figure 5As shown, the half battery piece on the side after cutting. Along the extension direction of the second region 2, the second region 2 includes an edge region 22 and a middle region 21, the middle region 21 is recessed to the second surface to form a first step structure, the edge region 22 is recessed to the second surface to form a second step structure, the step depth of the second step structure is greater than the step depth of the first step structure, and the width of the first step structure is greater than the width of the second step structure. In this way, the shallow groove (groove 31) of the whole battery piece does not penetrate the whole battery piece, only the middle region 21 of the battery piece is provided, and the deep groove (trench 32) is provided in the edge region 22. The thickness of the battery piece in the partial region along the cutting direction of the battery piece is thinned, and the difficulty of splitting from the deep groove of the edge region is reduced. Among them, the first passivation layer can be arranged on the side wall and bottom wall of the first step structure. The width of the second passivation layer in the first region is covered to the edge of the middle region of the second region corresponding to the first region. For example, referring to Figure 6 , the width of the second passivation layer 19 in the first region is covered to the edge of the middle region of the second region corresponding to the first region. That is, the width of the second passivation layer 19 in the first region covers not only the edge of the shallow groove (groove 31) corresponding to the first surface, but also the edge (dashed line in Figure 6 ) corresponding to the deep groove (trench 32). That is, the second passivation layer of the first cutting side in this embodiment needs to wrap around the first region of the front surface, and the width of the wrapped first region needs to be able to cover the edge of the step structure recessed to the non-cutting edge due to the arrangement of the middle region. In this way, the second passivation layer wraps around the two edges of the bottom wall of the first step structure and the second step structure from the first cutting side, and the two edges from the side wall of the first step structure and the second step structure to the first region, thereby improving the passivation effect of the battery piece as a whole. In addition, in this embodiment, the height of the bottom wall of the first step structure is lower than the first doped layer, and the step depth of the second step structure is greater than the step depth of the first step structure, so the bottom wall of the second step structure is also higher than the first doped layer. That is, there is no first doped layer (for example, no high-doped B atoms) on the bottom wall of the first step structure and the second step structure, so that passivation is easier, and the probability of recombination of dangling bonds formed by carriers in the first doped layer during the cutting process is reduced, further improving the passivation effect of the second region. Therefore, this embodiment can reduce the difficulty of splitting while improving the passivation effect of the battery piece.

[0119] It can be understood that the boundary of the second passivation layer 19 in the first region can be wavy or other irregular shapes, which are not limited in the present application.

[0120] It can be understood that the edge region of the battery piece can be the two ends along the cutting direction (i.e. Figure 5The edge region 22 on the upper side, the middle side or the lower side, which is not limited in the present application. Figure 3 The edge region 22 on the upper side, the middle side or the lower side, which is not limited in the present application.

[0121] It should be noted that in the embodiments of the present application, the width of the deep groove and the shallow groove can be the same, or the width of the deep groove can be smaller than the width of the shallow groove. For the convenience of description, the following embodiments are described by taking the width of the deep groove as an example, but the present application is not limited thereto. In addition, the deep groove can be obtained by laser, for example, it can be a lossy laser.

[0122] It should also be noted that in the present embodiment, the first texture structure or the second type of pyramid structure can be arranged on the bottom wall of the first step structure. That is, only on the bottom wall of the shallow groove in the middle region.

[0123] It can also be understood that in the present embodiment, the second step structure and the first step structure can be connected or not connected, that is, the present application does not limit the connection or non-connection of the deep groove and the shallow groove of the whole wafer cell piece.

[0124] It can also be understood that in the present embodiment, the middle region 21 can be obtained by laser and wet method together, which can be specifically referred to the preparation method described below.

[0125] In some embodiments, the angle between the side wall of the step structure and the thickness direction of the semiconductor substrate 10 can be 15°, 30°, 45°, 60°, etc., for example, as shown in the inclination of the step structure. Figure 4 Such an angle inclined step side wall is more conducive to the subsequent deposition of a uniform thickness passivation layer, alleviates the stress concentration degree during film deposition, and reduces the risk of film cracking or peeling.

[0126] In some possible embodiments, referring to Figure 7 , Figure 7 shows a top view of the first surface of the whole wafer cell piece before cutting, along the extension direction of the second region 2, the second region 2 includes an edge region 22 and a middle region 21. After cutting along the cutting line C, the middle region 21 and the edge region 22 include a first step structure recessed to the second surface in communication, and a second step structure is arranged on the step bottom wall of the first step structure of the edge region, and the first passivation layer 13 is arranged on the step side wall and the step bottom wall of the first step structure.

[0127] That is, for the whole wafer cell piece, the shallow groove is a through groove along the cutting direction, and the deep groove is arranged in the shallow groove. Further referring to Figure 8 , Figure 8A partial structure cross-sectional view of a whole cell piece before cutting is shown, and the recess depth H2 of the edge region 22 of the second region after cutting is greater than the recess depth H1 of the middle region 21 of the second region. In this way, when the whole cell piece is cut along the cutting line C, a deeper groove 32 is opened in the edge region 22 on the basis of the shallower groove 31 in the middle region 21, so that the cell piece is thinned as a whole in the cutting direction, thereby further reducing the difficulty of splitting, and the requirement for laser alignment can be reduced with respect to the non-through groove, thereby reducing the requirement for process complexity. In addition, the depth of the laser in the shallow through groove is less than the depth of the laser in the edge region, thereby reducing the requirement for laser intensity and reducing the cost of the laser, that is, reducing the overall process cost. In addition, in the scheme applied to the negative spacing (that is, the edge regions of adjacent cell pieces are arranged in an overlapping manner) arrangement of adjacent cell pieces, the first step structure can also be used for negative spacing lapping to improve the flatness of the entire surface of the adjacent cell pieces. The first passivation layer is arranged on the step bottom wall and the step side wall of the first step structure. In this way, the first passivation layer arranged on the bottom wall of the first step structure can protect the edge portion of the first step structure bottom wall close to the second step structure. Especially in the case where the second step structure is made by lossy laser, the first passivation layer of the first step bottom wall has a significant passivation effect. In the embodiment, as shown in Figure 9 the edge region of the second region 2 includes a first step structure and a second step structure, wherein the side wall of the first step structure can be inclined, and in some embodiments, the side wall of the second step structure can also be an inclined side wall. The second passivation layer can protect the first step structure and the second step structure of the cell piece and the first cutting side, especially the edges around the first cutting side to the bottom wall of the second step 2, the edges around the second step structure side wall to the bottom wall of the first step structure, and the edges around the inclined side wall of the first step structure to the first region, which can fully passivate the edge region, reduce the recombination sites, and improve the photoelectric conversion efficiency of the cell piece. In addition, in the embodiment, the height of the bottom wall of the first step structure is lower than the first doped layer, and the step bottom wall of the first step structure of the edge region is provided with the second step structure, so that the bottom wall of the second step structure is also higher than the first doped layer. That is, there is no first doped layer (for example, no high-doped B atoms) on the bottom wall of the first step structure and the second step structure, which can make passivation easier and reduce the probability of recombination of carriers in the first doped layer with the dangling bonds formed during the cutting process, thereby further improving the passivation effect of the second region.

[0128] It should be noted that the first texture structure or the second type of pyramid structure can be arranged on the bottom wall of the first step structure. That is, it is arranged on the bottom wall of the through shallow groove.

[0129] For example, a single solar cell can be cut into multiple solar cells, such as 2, 3, 4, 6... solar cells. On the first surface of the solar cell, grooves 30 (i.e., shallow grooves) can be arranged along the extension direction of the cutting line C. Subsequent cutting based on these grooves 30 makes the cutting operation easier, improves cutting efficiency, and enhances the quality of the finished product. In other words, the grooves 30 can reduce the overall structural thickness of the solar cell in the cutting extension direction, thereby further reducing the difficulty of dicing. Figure 3 , 4 As shown in the example in Figure 5, after the entire solar cell is cut, two solar cells (i.e., half solar cells) can be obtained. Specifically, along the cutting line C, two edge regions 22 and a middle region 21 can be divided on the first surface of the entire solar cell. The groove 30 can include a shallow groove 31 located mostly in the middle region 21 and a deep groove 32 located in the edge region 22.

[0130] In some possible implementations, the thickness of the second passivation layer on the first cut side is greater than the thickness of the second passivation layer in the second region. For example... Figure 4 As shown, the second passivation layer can wrap around the bottom and side walls of the stepped structure from the first cut side, and then wrap around the first region from the side walls of the stepped structure. The thickness of the second passivation layer on the first cut side is greater than the thickness of the second passivation layer in the second region. This results in a thicker second passivation layer on the first cut side, while the bottom and side walls of the stepped structure have a first passivation layer and a thinner second passivation layer. This minimizes the difference in passivation effect between the first cut side and the stepped structure, preventing the battery performance from degrading too quickly due to poor passivation at one point, thereby improving the battery cell's lifespan.

[0131] It is understandable that the second passivation layer can gradually thin from the first cut side to the stepped structure and then to the first region.

[0132] In some possible embodiments, the thickness of the second passivation layer is greater than the thickness of the first passivation layer. For example, when the first passivation layer comprises aluminum oxide and silicon nitride, and the second passivation layer is aluminum oxide, the first passivation layer combines various properties of both aluminum oxide and silicon nitride (e.g., hydrogen passivation, field passivation, chemical passivation, etc.), while the second passivation layer only possesses the passivation properties of aluminum oxide (e.g., a small amount of hydrogen passivation, field passivation, and chemical passivation, etc.). Therefore, the thickness of the second passivation layer needs to be much greater than the thickness of the aluminum oxide in the first passivation layer to improve the hydrogen passivation of the cut side. Furthermore, the thickness of the second passivation layer can also be greater than the thickness of the first passivation layer, which includes both aluminum oxide and silicon nitride, thereby further enhancing the hydrogen passivation of the cut side.

[0133] It can be understood that the passivation thickness of the second passivation layer of the first step structure and the second step structure in the second region is consistent.

[0134] In some possible embodiments, referring to Figure 5 and Figure 8 , the step width W2 of the edge region 22 is smaller than the step width W1 of the middle region 21. The step structure of the edge region is used for splitting, and the depth is deeper, so the step width of the edge region is smaller than the step width of the middle region, which can avoid causing more damage to the solar cell piece.

[0135] In some possible embodiments, the width of the second passivation layer covering the first region is greater than the width of the second step structure. The second passivation layer covering the first region is the second passivation layer, and the thickness of the second passivation layer gradually decreases from the edge to the center of the first region. Therefore, the second passivation layer needs to have sufficient width to wrap around the edge from the second region to the first region, so that the passivation effect near the cutting region is better.

[0136] It should be noted that the texture structure of the present application can be the surface topography of the polished surface, or a tower base structure (for example, it can be a convex structure, or a concave structure, etc.), which is not limited in the present application. For example, the above-mentioned first texture structure, and the following second texture structure, third texture structure, but each texture structure can be the same or different, which is not limited in the present application.

[0137] In some possible embodiments, the one-dimensional size of the first type of pyramid structure and the one-dimensional size of the second type of pyramid structure are different, or in other words, the size range is different. The second type of pyramid structure provided in the second region is smaller than the one-dimensional size of the first type of pyramid structure in the first region, so that the pyramid structure in the second region is smaller in height, which is more conducive to the deposition of a passivation layer with uniform thickness, thereby further improving the passivation effect of the second region.

[0138] It can be understood that the pyramid structure involved in the embodiments of the present application can be a pyramid structure with a tower top, or a pyramid structure without a tower top, which is not limited in the present application.

[0139] In some possible embodiments, the second region is provided with a plurality of second texture structures, and the second texture structure close to the side wall is more dense, and the second texture structure away from the side wall is more sparse. For example, the number of tower base structures close to the side wall is greater than the number of second texture structures away from the side wall.

[0140] In some embodiments, the depth of the first step structure is arranged along the thickness direction of the semiconductor substrate 10. If the depth of the first step structure is too large, the mechanical strength of the semiconductor substrate 10 will be reduced. If the depth of the first step structure is too small, the first doped layer cannot be completely removed, and the first doped layer 12 will be greatly affected during the laser cutting process, which will affect the passivation effect. In the technical solution, in order to balance the above two aspects, the depth of the middle region of the first step structure is 2um-10um along the thickness direction of the semiconductor substrate, so as to ensure the mechanical strength of the semiconductor substrate 10, reduce the influence of cutting on the passivation effect of the edge of the cell sheet close to the cutting surface, improve the passivation effect of the cell sheet after cutting, and further reduce the carrier recombination. The depth of the edge region of the first step structure is 30% H-100% H, and H is the thickness of the solar cell. Such a depth range can ensure that the cutting guide region formed effectively divides the whole solar cell into two split solar cells. Further, when the ratio is less than 100%, the damage of the lossy laser to the solar cell can be reduced.

[0141] For example, the depth of the first step structure is 2um, 3um, 4um, 5um, 6um, 7um, 8um, 9um or 10um.

[0142] It should be noted that for the scheme of arranging the through shallow groove, the deep groove is in the shallow groove, and the depth of the deep groove can be understood as from the first surface of the cell sheet.

[0143] The embodiments of the present application can be applied to bifacial cells (for example, TOPCon (passivated contact) cells) and back contact cells (for example, BC cells).

[0144] In some embodiments, the solar cell further comprises a second doped layer arranged on the second surface, the second doped layer is opposite in conductivity type to the first doped layer, and the second surface is entirely provided with a second texture structure. That is, the embodiments of the present application can be applied to the scheme of arranging the second doped layer on the entire back surface. The first texture structure and the second texture structure can be the same or different. The first texture structure can include a tower base structure, which is beneficial to forming a better passivation layer in the second region 2, improving the passivation effect of the second region 2, further reducing the carrier recombination on the surface of the solar cell, and improving the photoelectric conversion efficiency. By using the technical solution, the second texture structure is beneficial to further improving the light trapping effect of the second surface, reducing the reflectivity of light, and being beneficial to reflecting more light into the semiconductor substrate 10 and being utilized by the semiconductor substrate 10, thereby improving the light absorption utilization rate.

[0145] It can be understood that the entire back surface does not necessarily mean that the entire back surface is provided with the second doped layer. It is only used to distinguish the product with the doped layer arranged at intervals on the back surface. It can be understood that the entire back surface does not necessarily mean that the entire back surface is provided with the second doped layer. It is only used to distinguish the product with the doped layer arranged at intervals on the back surface.

[0146] In some embodiments, refer to Figure 11 The solar cell further includes second doped layers spaced apart on the second surface. The second doped layers have an opposite conductivity type to the first doped layers. A second texture structure is disposed in the spacer region between two adjacent second doped layers on the second surface. When a first texture structure is disposed in the second region, a second texture structure is disposed in the spacer region between two adjacent second doped layers on the second surface. The one-dimensional dimension of the first texture structure is larger than the one-dimensional dimension of the second texture structure. The larger one-dimensional dimension of the first texture structure indicates a smaller degree of undulation in the first texture structure, which helps to cover the passivation layer in the cut area, thereby further improving the passivation effect near the cut area. In addition, the second surface is provided with a second texture structure, which can be applied to a battery structure in which the entire back surface is provided with a tunneling oxide layer and a doped polycrystalline silicon layer (i.e., a second doped layer). That is, a tunneling oxide layer and a doped polycrystalline silicon layer are deposited on a semiconductor substrate with a second texture structure. Since the tunneling oxide layer is difficult to grow, a smaller second texture structure is required. The bottom wall of the step in the second area on the front side is only used to deposit a passivation layer (e.g., aluminum oxide) and is not affected by the tunneling oxide layer. Therefore, a larger tower base structure can be set here, which helps to deposit a passivation layer better.

[0147] The solar cell also includes a second doped layer 16 disposed on the second surface. The second doped layer 16 can be disposed entirely or partially on the second surface. The second doped layer 16 can be additionally formed on the semiconductor substrate 10 by deposition technology, or it can be formed within the semiconductor substrate 10 by diffusion, ion implantation, or other methods. The second doped layer 16 has the opposite conductivity type to the first doped layer 12, so as to collect and export electrons and holes respectively, which is beneficial to the formation of photocurrent. When the second doped layer 16 is partially disposed on the second surface, the second doped layer 16 can be distributed at intervals along the first direction on the second surface; when the second doped layer 16 extends along the second direction, the second doped layer 16 can be distributed in strip, shaped like a character, or similar. The first direction and the second direction intersect, and the angle between the first direction and the second direction can be an acute angle or a right angle. The first direction can be the length direction of the semiconductor substrate 10 or the width direction of the semiconductor substrate 10. When the first direction is the length direction of the semiconductor substrate 10, the second direction is the width direction of the semiconductor substrate 10; when the first direction is the width direction of the semiconductor substrate 10, the second direction is the length direction of the semiconductor substrate 10.

[0148] It can be understood that the one-dimensional size can be a one-dimensional parameter of the height, width, pitch, etc. of the first or second texture structure; for example, the height of the first texture structure is greater than the height of the second texture structure, or the width of the first texture structure is greater than the width of the second texture structure, etc.

[0149] In some embodiments, the one-dimensional size of the first texture structure is set in a reasonable range of 15um-50um, so as to improve the light trapping effect and light absorption utilization of the second region 2, while avoiding the one-dimensional size of the first texture structure being too large to affect the formation quality of the passivation layer in the second region 2, and avoiding the case that the formation quality of the passivation layer is reduced to cause poor passivation effect. For example, the one-dimensional size of the first texture structure is 15um, 18um, 20um, 22um, 25um, 26um, 27um, 28um, 29um, 30um, 31um, 32um, 33um, 34um, 35um, 38um, 40um, 42um, 45um, 48um or 50um, etc.

[0150] In some embodiments, the one-dimensional size of the second texture structure is set in a reasonable range of 2um-20um, so as to prevent the size of the second texture structure in the interval region between the two adjacent second doped layers 16 on the second surface from being too large, so that the etching in the interval region between the two adjacent second doped layers 16 is serious, the number of dangling bonds is too large, the carrier recombination is serious, and the power generation efficiency is not improved, and the mechanical properties of the silicon wafer are affected. For example, the one-dimensional size of the second texture structure is 2um, 3um, 4um, 5um, 6um, 7um, 8um, 9um, 10um, 11um, 12um, 13um, 14um, 15um, 18um or 20um, etc.

[0151] In some embodiments, the first step structure is formed between the first region and the first step structure, and the prismatic structure is arranged on the first step structure. The prismatic structure is arranged on the sidewall of the first step structure, and in addition to the complete texture structure formed on the sidewall of the first step structure, other structures can also be formed on the sidewall of the first step structure, such as a convex strip structure, or a prismatic structure extending along the direction from the bottom to the top of the first step structure. The prismatic structure can increase the surface area of the sidewall of the first step structure, thereby increasing the adhesion of the sidewall of the first step structure after lamination, preventing delamination and peeling of the battery edge. Since the prismatic structure can further increase the surface area, it provides a larger deposition area for the subsequent passivation layer, thereby further improving the passivation effect of the first step structure region.

[0152] In some possible embodiments, the solar cell further comprises a second doped layer arranged at intervals on the second surface, the second doped layer being opposite in conductive type to the first doped layer; and in the case where the second region is provided with the second type of pyramid structure, the interval region between two adjacent second doped layers on the second surface is provided with a third type of pyramid structure. Figure 3 As shown in FIG. 16, the second doped layer 16 is arranged at intervals in the first direction on the second surface, and in the case where the second region 2 is provided with the second type of pyramid structure, the interval region between two adjacent second doped layers 16 on the second surface is provided with a third type of pyramid structure. Optionally, the one-dimensional size of the third type of pyramid structure is smaller than the one-dimensional size of the second type of pyramid structure. The base portion of the second type of pyramid has a larger volume and a larger surface area, so that the top of the pyramid has a better light reflection and scattering effect, and can deposit more passivation layers, and has a better passivation effect.

[0153] In some possible embodiments, the depth range of the interval region between two adjacent second doped layers is the same as the step depth range of the first step structure. The depth of the interval region can be the thickness of the back passivation layer, the tunneling oxygen layer, the second doped layer, and the inner diffusion layer. That is, the step depth range is the sum of the thicknesses of the back passivation layer, the tunneling oxygen layer, the second doped layer, and the inner diffusion layer. In this way, the recess depths of the front surface and the back surface can be substantially consistent, so that the front surface and the back surface can withstand a relatively consistent pressure, and the mechanical performance of the solar cell can be ensured.

[0154] In some possible embodiments, the included angle range between the sidewall of the interval region between two adjacent second doped layers and the thickness direction of the semiconductor substrate is the same as the included angle range between the sidewall of the step structure and the thickness direction of the semiconductor substrate. In this way, the passivation effects of the sidewall of the step structure and the sidewall of the interval region can be balanced, that is, the passivation effects of the front surface and the back surface are consistent.

[0155] In some embodiments, the sidewall of the first step structure is provided with a fourth type of pyramid structure, and the size range of the fourth type of pyramid structure can be the same as or different from the size range of the third type of pyramid structure. With this technical solution, the sidewall of the first step structure has a good light trapping effect, and the utilization rate of light by the solar cell is further improved. It can be understood that, in addition to the complete pyramid structure and the incomplete pyramid structure, other structures can also be formed on the sidewall of the first step structure, such as a convex strip structure or a prismatic structure extending from the bottom to the top of the first step structure.

[0156] The shapes of the third type of pyramid structure and the fourth type of pyramid structure can refer to the shape of the first type of pyramid structure, which will not be described herein again.

[0157] Optionally, the size range of the fourth type of pyramid structure can be the same as the size range of the first type of pyramid structure.

[0158] In some embodiments, the step sidewall 3 of the first step structure is wavy or zigzag-shaped along the extension direction of the step sidewall 3 (for example, as shown in Figure 2 The extension direction of the step sidewall 3 can be the same as the extension direction of the first doped layer 12, that is, the step sidewall 3 extends along the second direction. With this technical solution, the overall extension length of the step sidewall 3 can be increased, which is beneficial to improving the adhesion of the step sidewall 3 after lamination, thereby improving the stability of the solar energy. Of course, along the extension direction of the step sidewall 3, the step sidewall 3 can also extend along a straight line, which is not limited here.

[0159] In some embodiments, the first step structure is wavy or zigzag-shaped along the extension direction of the first step structure;

[0160] In some embodiments, the first step structure continuously extends or discontinuously extends along the extension direction of the first step structure;

[0161] In some embodiments, the width of the first step structure along the direction perpendicular to the first cut side is 20 μm to 500 μm.

[0162] If the first step structure is too wide, the area of the first doped layer 12 will be reduced, which will affect the current collection efficiency of the first doped layer 12. If the first step structure is too narrow, it cannot effectively cut off the transmission of the doped layer during the laser cutting process, and the passivation effect will be greatly affected and significantly reduced. In order to take into account the above two aspects, in this technical solution, the width of the first step structure along the direction perpendicular to the first cut side is 20 μm to 500 μm. Or, the width of the first step structure along the second direction is 20 μm to 500 μm. In this technical solution, the width of the first step structure is set to a reasonable range of 20 μm to 500 μm, so as to prevent the area of the first doped layer 12 from being reduced, ensure the current collection efficiency of the first doped layer 12, and at the same time avoid the passivation effect of the first doped layer 12 during the laser cutting process being significantly reduced, thereby ensuring a high power generation efficiency.

[0163] For example, the width of the first step structure is 20 μm, 50 μm, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 550 μm, 400 μm, 450 μm, or 500 μm, etc.

[0164] It can be understood that the width of the first step structure is 20 μm to 500 μm, and accordingly, the width of the second region as a whole is 40 μm to 1000 μm.

[0165] In some embodiments, the first step structure can continuously extend, in particular, the first step structure can continuously extend along the first direction. With this technical solution, the first doped layer 12 at any position of the first region 1 is far away from the cutting position, which ensures that the passivation effect of the first doped layer 12 close to the edge of the second region 2 is reduced, and further reduces the carrier recombination.

[0166] In other embodiments, the first step structure discontinuously extends, in particular, the first step structure can discontinuously extend along the first direction, i.e., the first step structure is discontinuously arranged.

[0167] In some embodiments, the sidewall of the first step structure is parallel to the thickness direction of the semiconductor substrate 10, in particular, the sidewall of the first step structure can be arranged perpendicular to the first surface of the semiconductor substrate 10, which facilitates to simplify the processing technology and improve the processing efficiency.

[0168] In some embodiments, the semiconductor substrate further comprises a second cutting side surface, the second cutting side surface is arranged opposite to the first cutting side surface, the first surface further comprises a third region close to the second cutting side surface, the first region is located on the side of the third region away from the second cutting side surface; along the extension direction of the third region, the third region comprises an edge region and a middle region, the edge region and the middle region both comprise step structures, the step depth of the step structure of the edge region of the third region is greater than the step depth of the step structure of the middle region of the third region, the height of the bottom wall of the step structure of the middle region of the third region is lower than the height of the first doped layer; a fourth passivation layer, the fourth passivation layer is arranged close to the edge of the third region, the third region and the second cutting side surface of the first region, and the fourth passivation layer is located on the side of the first passivation layer away from the semiconductor substrate.

[0169] The plurality of surfaces of the semiconductor substrate 10 are all cutting surfaces, for example, two cutting surfaces of two battery pieces in the middle after the whole battery piece is quartered. In the technical solution, the semiconductor substrate 10 further includes a second cutting surface opposite to the first cutting surface, and the first surface further includes a third region adjacent to the second cutting surface, and the first region 1 is located on a side of the third region away from the second cutting surface; that is, the third region is adjacent to the first cutting surface compared with the first region 1, and the third region is located between the first region 1 and the second cutting surface. Along the extension direction of the third region, the third region includes an edge region and a middle region, and the edge region and the middle region of the third region both include a step structure, the step depth of the step structure of the edge region of the third region is greater than the step depth of the step structure of the middle region of the third region, and the height of the bottom wall of the step structure of the middle region of the third region is lower than the height of the first doped layer. In the process of cutting to form the second cutting surface, the position of laser cutting is farther away from the first doped layer 12, so that the loss of the first doped layer 12 caused by the laser is smaller, and the formation of more dangling bonds and carrier recombination is avoided, and the influence of the passivation effect of the passivation layer on the cutting region after the etching of the step structure to the first doped layer is reduced. That is, the embodiments of the present application can improve the passivation effect of the half battery piece with two cutting surfaces on both sides and improve the photoelectric conversion efficiency. In addition, the embodiments of the present application can also achieve the balance of the passivation effect of the two cutting surfaces in the scheme of two cutting surfaces on both sides.

[0170] It should be noted that the third region can have the same embodiments as the second region described above, and for the convenience of description, details are not described here.

[0171] In some embodiments, the step depth of the step structure of the middle region of the second region is the same as the step depth of the step structure of the middle region of the third region. In other embodiments, the step depth of the step structure of the edge region of the second region is the same as the step depth of the step structure of the edge region of the third region. In this way, the structures at the two cutting surfaces of the battery piece can be consistent, the mechanical properties of the two sides of the battery piece are balanced, and the passivation effects at the two cutting surfaces are also consistent.

[0172] In some embodiments, the step width of the stepped structure in the middle region of the second region is the same as the step width of the stepped structure in the middle region of the third region. The width of the stepped structure in the second region refers to the dimension of the stepped structure along the direction perpendicular to the first cut side; the width of the stepped structure in the third region refers to the dimension of the stepped structure along the direction perpendicular to the second cut side. This configuration allows the width of the stepped structure to be set according to the laser energy forming the first cut side and the laser energy forming the second cut side, respectively, which helps to make the passivation effect of the cut regions on both sides more consistent. Furthermore, if the first or second stepped structure is too wide, it will lead to a reduction in the area of ​​the first doped layer 12, a decrease in carrier collection efficiency, and a reduction in the mechanical properties of the solar cell.

[0173] In other embodiments, the step width of the step structure in the edge region of the second region is the same as the step width of the step structure in the edge region of the third region.

[0174] In some embodiments, the extended shape of the stepped sidewall 3 in the second region is the same as the extended shape of the stepped sidewall in the third region. The stepped structures on both sides can be completed in the same process flow, which improves processing efficiency and helps to ensure consistent passivation effect at the cut surfaces on both sides.

[0175] In some embodiments, the edge area can be chamfered. This design can prevent the corners of the battery cells from cracking when the edge area is cut, thus improving product yield.

[0176] In practical applications, the semiconductor substrate 10 can be made of materials such as silicon (Si), germanium (Ge), or gallium arsenide (GaAs). Obviously, in terms of conductivity type, the semiconductor substrate 10 can be an intrinsically conductive substrate, an n-type conductive substrate, or a p-type conductive substrate. Optionally, the semiconductor substrate 10 can be a p-type conductive substrate or an n-type conductive substrate. Compared to an intrinsically conductive substrate, a p-type conductive substrate or an n-type conductive substrate has better conductivity, resulting in a lower bulk resistivity in the final solar cell, thereby improving the efficiency of the solar cell.

[0177] For example, the semiconductor substrate 10 can be a p-type substrate or an n-type substrate. The n-type substrate has advantages such as high minority carrier lifetime, no light decay, and good performance in weak light.

[0178] The first doped layer 12 may include doped polycrystalline silicon. Doped polycrystalline silicon layers have higher carrier transport characteristics; therefore, when the first doped layer 12 is a doped polycrystalline silicon layer, the carrier transport efficiency is higher, which is beneficial for improving the photoelectric conversion efficiency of the solar cell. Of course, the first doped layer 12 may also be one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon.

[0179] The second doped layer 16 may include doped polycrystalline silicon, or the second doped layer 16 may be one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon.

[0180] In some embodiments, a first interface layer 11 is disposed between the first doped layer 12 and the semiconductor substrate 10, and a second interface layer 15 is disposed between the second doped layer 16 and the semiconductor substrate 10. The passivated contact structure composed of the interface layer and the doped layer has excellent interface passivation effect and can achieve selective collection of charge carriers, reducing the carrier recombination rate in the region where the doped layer is formed on the surface of the semiconductor substrate 10, thereby further improving the photoelectric conversion efficiency of the solar cell. The material and thickness of the first interface layer 11 can be set according to the material of the first doped layer 12 and actual requirements, and the material and thickness of the second interface layer 15 can be set according to the material of the second doped layer 16 and actual requirements; no specific limitations are made here.

[0181] For example, the first doped layer 12 can be a doped polysilicon layer, and the first interface layer 11 can be a tunneling oxide layer. The second doped layer 16 can be a doped polysilicon layer, and the second interface layer 15 can be a tunneling oxide layer.

[0182] It should be noted that, referring to Figure 4 , Figure 10 , Figure 11 , Figure 12 In this embodiment of the application, the solar cell may also omit the first interface layer.

[0183] The materials of the first doped layer 12 and the second doped layer 16 can be silicon (Si), germanium (Ge), silicon carbide (SiCx), or gallium arsenide (GaAs), etc. In terms of conductivity type, the first doped layer 12 can be an n-type doped layer and the second doped layer 16 can be a p-type doped layer; or, the first doped layer 12 can be a p-type doped layer and the second doped layer 16 can be an n-type doped layer.

[0184] This application also provides another type of solar cell, such as... Figure 13 As shown, in some embodiments, the shallow groove (groove 31) at the edge of the second region can also be configured as a Y-shaped groove. This configuration can prevent the battery cell from cracking at the corners when cutting the edge region, thus improving product yield.

[0185] It should be noted that the shallow groove and the trench 32 structure can be formed in the same process or in different process steps, and this application does not limit this.

[0186] In other embodiments, such as Figure 3 or Figure 4As shown, the second surface is provided with a third passivation layer 17, the first cutting side is provided with a second passivation layer 19, and the second passivation layer 19 extends to the edge of the second surface and is located on the side of the third passivation layer 17 away from the semiconductor substrate 10. The third passivation layer 17 not only can protect the second surface of the battery piece, avoid water vapor or oxygen from penetrating into the battery piece, and prolong the service life of the solar cell; but also can play a role in reducing reflection, and improve the light absorption utilization rate. The number of layers and the material of the third passivation layer 17 can refer to the description of the first passivation layer 13, for example, the third passivation layer 17 can be a single-layer structure, and the single-layer structure is a silicon nitride layer. The second passivation layer can passivate the first cutting side and the back surface in the same step, thereby further improving the passivation effect and saving the process flow. Alternatively, the second passivation layer can wrap the edge of the first region of the first surface and the edge of the second surface in the same step, thereby further improving the passivation effect and saving the process flow.

[0187] Figure 14 A schematic diagram of an assembly in an embodiment of the present application is shown. As shown in the figure, Figure 14 An electrical connecting piece is arranged between the adjacent first solar cell 141 and second solar cell 142. The first solar cell 141 is the solar cell involved in the foregoing embodiments. The connection mode of the electrical connecting piece is as shown in the figure, Figure 14 from the first surface and the second side of the first solar cell 141, and then through the second surface of the second solar cell, and the second side is the side opposite to the first cutting surface. Among them, the distance (such as d in the figure) Figure 14 ) between the starting end of the electrical connecting piece and the edge of the first region (i.e. the boundary between the first region and the second region) is greater than the width of the stepped structure of the middle region. Considering that the starting end of the electrical connecting piece can have burrs and other protrusions, the starting end of the electrical connecting piece is arranged at a certain distance from the edge, so as not to damage the passivation layer of the cutting region and ensure the passivation effect at the cutting region.

[0188] Optionally, the second side is a non-cutting side. That is, as shown in the figure, Figure 12 the side of the first solar cell 121 is a cutting surface, and the opposite side is a non-cutting surface. In this way, the starting end of the electrical connecting piece starts from the front surface close to the cutting surface side and extends to the non-cutting surface to cause extrusion to the non-cutting side. Compared with the electrical connecting piece extending from the cutting side with a stepped structure to extrude the cutting side, the embodiment of the present application can avoid affecting the mechanical properties of the solar cell.

[0189] It can be understood that the second side can also be a cutting surface, for example, it can be the aforementioned second cutting side.

[0190] It can also be understood that the electrical connecting piece can be a solder strip.

[0191] It can also be understood that the edge of the first region can be the joint edge between the first region and the intermediate region between the first region and the second region, or the joint edge between the first region and the edge region of the second region, and the present application does not limit this.

[0192] In some possible embodiments, the distance between the starting end of the electrical connector and the edge of the first region (i.e., the joint edge between the first region and the second region) is greater than or equal to 1 mm.

[0193] The embodiments of the present application also provide a manufacturing method of a first solar cell, which can manufacture the solar cell described in any of the above embodiments, and the manufacturing method of the solar cell comprises the following steps:

[0194] S1: providing a semiconductor substrate 10, the semiconductor substrate 10 comprising opposite first and second surfaces, and the first surface comprising a first region 1 and a second region 2.

[0195] The first region 1 is used to form a first type of pyramid structure.

[0196] Before this step, in some embodiments, the semiconductor substrate 10 can also be put into a polishing cleaning machine to remove the cutting damage layer of the semiconductor substrate 10 by using a polishing liquid. In addition, the morphology of the first and second surfaces of the semiconductor substrate 10 after polishing and cleaning can also be adjusted by adjusting parameters such as temperature, time, type of cleaning liquid, and concentration of cleaning liquid. It should be noted that in some examples, the step of polishing and cleaning can be omitted.

[0197] S2: forming a first type of pyramid structure on the first surface;

[0198] In this step, the first type of pyramid structure can be formed on the first surface by a texturing method.

[0199] S3: forming a first doped layer 12 and a first doped silicon glass layer on the first surface with the first type of pyramid structure.

[0200] The first doped layer 12 can be additionally formed on the first surface of the semiconductor substrate 10 by a deposition technique, or can be formed in the semiconductor substrate 10 by diffusion, ion implantation, or the like. A first doped silicon glass layer is formed at the same time in the process of forming the first doped layer 12.

[0201] It should be noted that in the case where the solar cell also comprises a first interface layer 11, the first interface layer 11 can be formed by using a deposition and etching process before the first doped layer is formed in this step.

[0202] S4: reducing the density of the first doped silicon glass layer of the second region 2 by laser irradiation.

[0203] In this step, the first doped silicon glass layer in the second region 2 is irradiated with a laser to reduce the density of the first doped silicon glass layer in the second region 2, which makes it easier to remove the first doped silicon glass layer in the second region 2 in the subsequent process.

[0204] S5: The second surface is polished in a groove and part of the first doped silicon glass layer in the second region is removed, and a groove is formed in the second region 2 that is recessed into the second surface.

[0205] In this step, the first doped silicon glass layer in the second region 2 can be removed by etching with an etchant. With the first doped silicon glass layer formed on both the second surface and side surfaces, it is first removed from both surfaces using a chain conveyor. Then, the cell is polished using a trough-type machine to polish the second surface and remove the first doped silicon glass layer in the second region 2, thus forming a groove in the second region 2. In this way, polishing and groove formation are achieved in a single process step, reusing the polishing step during groove formation, saving process steps.

[0206] Understandably, the first doped silicon glass layer (e.g., BSG) is typically quite thick, around 100 nm.

[0207] S6: A second doped layer 16 is formed on the second surface, the second doped layer 16 having the opposite conductivity type to the first doped layer 12.

[0208] The second doped layer 16 can be additionally formed on the second surface of the semiconductor substrate 10 by deposition technology, or it can be formed within the semiconductor substrate 10 by diffusion, ion implantation, or other methods. The second doped layer 16 can be disposed entirely or partially on the second surface. When the second doped layer 16 is partially disposed on the second surface, the second doped layer 16 can be spaced apart along the first direction on the second surface; when the second doped layer 16 extends along the second direction, the second doped layer 16 can be distributed in the shape of strips, a shaped pattern, or the like.

[0209] It should be noted that, in the case where the solar cell also includes a second interface layer 15, the second interface layer 15 can be formed by deposition and etching processes before forming the second doped layer.

[0210] When the second doped layer 16 is a doped polycrystalline silicon layer and the second interface layer 15 is a tunneling oxide layer, a tunneling oxide layer and an intrinsic polycrystalline silicon layer can be formed sequentially on the second surface first, and then the intrinsic polycrystalline silicon layer can be diffused to obtain a doped polycrystalline silicon layer. During the formation of the doped polycrystalline silicon layer, a second doped glass silicon layer can be formed simultaneously.

[0211] Understandably, the second doped glass silicon layer is typically around 30nm.

[0212] S7: removing the second doped silicon glass layer of the second surface, and forming a first texture structure or a second pyramidal structure in the groove, and making the side wall of the groove have an included angle with the thickness direction of the semiconductor substrate, and along the thickness direction of the semiconductor substrate, the height of the bottom wall of the groove is lower than the height of the first doped layer. After this step, the remaining first doped glass silicon layer on the first surface and the entire second doped glass silicon layer can be removed synchronously.

[0213] In step S7, the first doped silicon glass layer in the groove and the first doped layer are completely removed by chain partial front doped silicon glass layer and then by groove type equipment for overall etching. That is, through multiple cleaning, the thicker first doped glass silicon layer in the groove can be removed.

[0214] S8: forming a first passivation layer on the first surface, the first passivation layer being located on the side of the first doped layer away from the semiconductor substrate;

[0215] S9: forming a first electrode 14 on the first doped layer 12 and forming a second electrode 18 on the second doped layer 16.

[0216] The first electrode 14 and / or the second electrode 18 can be formed by screen printing, electroplating, sputtering or evaporation, etc. The first electrode 14 is electrically connected to the first doped layer 12 to lead out the current collected by the first doped layer 12, and the second electrode 18 is electrically connected to the second doped layer 16 to lead out the current collected by the second doped layer 16. The first electrode 14 and the second electrode 18 can be silver, copper, aluminum and alloys thereof. The first electrode 14 and the second electrode 18 can be the same or different.

[0217] S10: cutting the semiconductor substrate along the groove to obtain a plurality of solar cells.

[0218] S11: forming a second passivation layer on the edge of the first region close to the second region, the second region and the first cutting side, the second passivation layer being located on the side of the first passivation layer away from the semiconductor substrate.

[0219] It can be understood that the second passivation layer can protect the second region and the first cutting side of the cell piece, especially the edge of the second region around the first cutting side and the side wall edge of the second region to the first region, which can be fully passivated to reduce the recombination sites and improve the photoelectric conversion efficiency of the cell piece. The number of layers and the material of the second passivation layer can be referred to the description of the first passivation layer, for example, the second passivation layer can be a single layer structure, and the single layer structure is an aluminum oxide layer.

[0220] In some embodiments, before S9, the method for manufacturing the solar cell further comprises: forming a third passivation layer on the second surface, the third passivation layer being on the side of the second doped layer facing away from the semiconductor substrate. It can be understood that this step can be completed at the same time as S11, and the present application does not limit this.

[0221] In some embodiments, after S9 and before S10, the method for manufacturing the solar cell further comprises: forming a groove structure in the edge region of the second region by using a laser; and cutting along the groove and the groove structure to obtain a plurality of solar cells.

[0222] The second region comprises a middle region along the extension direction of the second region and the edge region. In this step, before cutting the solar cell, a groove can be formed in the edge region of the second region of the whole solar cell, the groove having a depth greater than that of the groove, so that the structure of the solar cell is thinned to a certain extent along the cutting direction, and the subsequent automatic disconnection of the cutting line position can be achieved by using a non-destructive laser and water spraying, thereby completing the cutting. This cutting method has high cutting efficiency and cutting accuracy, and can ensure the quality of the finished product after cutting.

[0223] In some embodiments, forming the groove in the edge region of the second region by using a laser comprises: forming the groove in the edge region inside the groove.

[0224] In this case, the groove can be a through groove. When the through groove is opened, the requirement for the alignment of the laser can be reduced, thereby reducing the process complexity.

[0225] In some embodiments, S6 forms the second doped layer 16 on the second surface includes: S61 forms the second doped layer 16 and a second doped glass-silicon layer on the second surface; S62 reduces the density of the second doped glass-silicon layer in the interval region between two adjacent second doped layers 16 by laser irradiation; and S63 removes the second doped glass-silicon layer and forms a second texture structure in the interval region between two adjacent second doped layers 16. Specifically, in this technical solution, the second doped layer 16 and the second doped glass-silicon layer are formed at the same time, and the second doped layer 16 is distributed on the second surface in the first direction. The interval region is between two adjacent second doped layers 16. The second doped glass-silicon layer in the interval region is irradiated by laser to reduce the density of the second doped glass-silicon layer in the interval region, which is beneficial to subsequent removal. The second doped glass-silicon layer is removed by etching with an etching solution, and a second texture structure is formed in the interval region between two adjacent second doped layers 16. The second doped glass-silicon layer is removed synchronously, and the remaining first doped glass-silicon layer on the first surface can also be removed. Specifically, chain cleaning and tank cleaning methods can be used. By using this technical solution, a second texture structure is formed in the interval region on the second surface, which is beneficial to improve the light trapping effect of the light-receiving surface, reduce the reflectivity of light, and also reduce the lateral recombination of carriers. The second texture structure can be a tower base structure, and the size of the tower base structure formed in the interval region can be different from the size of the tower base structure formed on the second surface, the side surface, and the groove structure of the semiconductor substrate 10.

[0226] In some embodiments, S6 forms the second doped layer 16 on the second surface includes: S61 forms the second doped layer 16 and a second doped glass-silicon layer on the second surface; S62 reduces the density of the second doped glass-silicon layer in the interval region between two adjacent second doped layers 16 by laser irradiation; and S63 removes the second doped glass-silicon layer and forms a second texture structure in the interval region between two adjacent second doped layers 16. Specifically, in this technical solution, the second doped layer 16 and the second doped glass-silicon layer are formed at the same time, and the second doped layer 16 is distributed on the second surface in the first direction. The interval region is between two adjacent second doped layers 16. The second doped glass-silicon layer in the interval region is irradiated by laser to reduce the density of the second doped glass-silicon layer in the interval region, which is beneficial to subsequent removal. The second doped glass-silicon layer is removed by etching with an etching solution, and a second texture structure is formed in the interval region between two adjacent second doped layers 16. The second doped glass-silicon layer is removed synchronously, and the remaining first doped glass-silicon layer on the first surface can also be removed. Specifically, chain cleaning and tank cleaning methods can be used. By using this technical solution, a second texture structure is formed in the interval region on the second surface, which is beneficial to improve the light trapping effect of the light-receiving surface, reduce the reflectivity of light, and also reduce the lateral recombination of carriers. The second texture structure can be a tower base structure, and the size of the tower base structure formed in the interval region can be different from the size of the tower base structure formed on the second surface, the side surface, and the groove structure of the semiconductor substrate 10.

[0227] The embodiments of the present application also provide a second method for manufacturing a solar cell. The solar cell can be manufactured by any of the above embodiments. The method for manufacturing the solar cell includes the following steps:

[0228] S1’ provides a semiconductor substrate 10, which includes a first surface and a second surface opposite to each other. The first surface includes a first region 1 and a second region 2.

[0229] The step S1’ can refer to the description of the step S1 in the foregoing, and will not be described here.

[0230] S2’ forms a first pyramid structure on the first surface.

[0231] Step S2' can be referred to the description of step S2 above, and will not be repeated here.

[0232] S3': A first doped layer 12 and a first doped silicon glass layer are formed on the first surface having the first type of pyramid structure.

[0233] This step S3' can be referred to the description of step S3 above, and will not be repeated here.

[0234] S4': A second doped layer 16 and a second doped silicon glass layer are formed on the second surface. The second doped layer 16 has the opposite conductivity type to the first doped layer 12.

[0235] The second doped layer 16 can be additionally formed on the second surface of the semiconductor substrate 10 by deposition technology, or it can be formed within the semiconductor substrate 10 by diffusion, ion implantation, or other methods. A second doped silicon glass layer is formed simultaneously with the formation of the second doped layer 16. The second doped layer 16 can be locally disposed on the second surface, or it can be spaced apart along a first direction on the second surface; the second doped layer 16 can extend along a second direction, or it can be distributed in strip, U-shape, or similar shapes.

[0236] It should be noted that, in the case where the solar cell also includes a second interface layer 15, the second interface layer 15 can be formed by deposition and etching processes before forming the second doped layer.

[0237] When the second doped layer 16 is a doped polycrystalline silicon layer and the second interface layer 15 is a tunneling oxide layer, a tunneling oxide layer and an intrinsic polycrystalline silicon layer can be formed sequentially on the second surface first, and then the intrinsic polycrystalline silicon layer can be diffused to obtain a doped polycrystalline silicon layer. During the formation of the doped polycrystalline silicon layer, a second doped glass silicon layer can be formed simultaneously.

[0238] S5': Using a laser, the density of the first doped silicon glass layer and the spacer of the second doped silicon glass layer in the second region 2 is reduced.

[0239] In the same step, laser irradiation reduces the density of the second doped silicon glass layer in the spacer region between the first doped silicon glass layer and the adjacent second doped layer 16 in the second region 2.

[0240] S6': Remove the first doped silicon glass layer and the second doped silicon glass layer, and form a groove that is recessed toward the second surface in the groove, and form a first texture structure or a second type of pyramid structure in the second region 2, and make the sidewall of the groove have an angle with the thickness direction of the semiconductor substrate, and the height of the bottom wall of the groove is lower than the height of the first doped layer along the thickness direction of the semiconductor substrate.

[0241] The first doped silicon glass layer and the second doped silicon glass layer can be removed by etching with an etching solution, and a groove (shallow trench) is formed in the second region 2 by etching, and the first textured structure or the second pyramidal structure is formed in the second region 2.

[0242] S7': forming a first passivation layer on the first surface, the first passivation layer being on the side of the first doped layer away from the semiconductor substrate;

[0243] S8': forming a first electrode 14 on the first doped layer 12 and a second electrode 18 on the second doped layer 16.

[0244] The step S8' can refer to the description of the step S8 above, and will not be described here again.

[0245] S9': cutting the semiconductor substrate along the groove to obtain a plurality of solar cells.

[0246] The step S9' can refer to the description of the step S9 above, and will not be described here again.

[0247] S10': forming a second passivation layer on the edge of the first region close to the second region, the second region, and the first cutting side, the second passivation layer being on the side of the first passivation layer away from the semiconductor substrate.

[0248] The main difference between the second method and the first method is that the second doped silicon glass layer in the interval between the first doped silicon glass layer and the adjacent second doped layer 16 in the second region 2 is irradiated by laser in the same step, which is beneficial to the removal of the second doped silicon glass layer in the second region 2 and the interval and the formation of the second textured structure.

[0249] In some embodiments, a second textured structure is formed in the interval between two adjacent second doped layers 16 during the removal of the second doped silicon glass layer. Specifically, the second doped silicon glass layer can be removed by wet etching, and a part of the semiconductor substrate 10 is etched to form the second textured structure in the interval, which is beneficial to improve the light trapping effect of the light receiving surface and reduce the reflectivity of light.

[0250] In some embodiments, the third type of pyramid structure is formed in the spacing area between two adjacent second doped layers 16 during the process of removing the second doped glass silicon layer. The second doped glass silicon layer can be removed by wet etching, and a part of the semiconductor substrate 10 is etched to form the third type of pyramid structure in the spacing area, which is conducive to improving the light trapping effect of the light surface and reducing the reflectivity of light. The base of the pyramid has a large volume and a large surface area, which is conducive to ensuring the passivation effect of the passivation layer covering the base of the pyramid, and the top of the pyramid has a better reflection and scattering effect on light. In this technical solution, S61-S62 are the same as the above technical solution, and the descriptions of S61 and S62 are the same as the above technical solution.

[0251] In the above two methods of manufacturing solar cells, the first passivation layer 13 is located on the side of the first doped layer 12 away from the semiconductor substrate 10. The third passivation layer 17 is formed on the second surface, and the third passivation layer 17 is located on the side of the second doped layer 16 away from the semiconductor substrate 10. In this technical solution, the first electrode 14 is electrically connected to the first doped layer 12 through the first passivation layer 13, and the second electrode 18 is electrically connected to the second doped layer 16 through the third passivation layer 17.

[0252] The method of manufacturing solar cells further includes forming a second passivation layer 19 on the edge of the first region 1 close to the second region 2, the second region 2, and the first cutting side, and the second passivation layer 19 is located on the side of the first passivation layer 13 away from the semiconductor substrate 10.

[0253] The structure, material and function of the first passivation layer 13, the second passivation layer 19 and the third passivation layer 17 can be referred to the above description.

[0254] In some embodiments, the laser can use a green skin laser, and the spot diameter or spot width of the laser is 105 μm-410 μm. For example, the spot diameter or spot width of the laser is 105 μm, 120 μm, 150 μm, 200 μm, 220 μm, 250 μm, 280 μm, 300 μm, 320 μm, 350 μm, 380 μm, 400 μm or 410 μm.

[0255] The frequency of the laser is 200 KHz-800 KHz. For example, the frequency of the laser is 200 KHz, 250 KHz, 300 KHz, 350 KHz, 400 KHz, 450 KHz, 500 KHz, 550 KHz, 600 KHz, 650 KHz, 700 KHz or 8000 KHz.

[0256] The power of the laser can be 50w-150w, and for example, the power of the laser can be 50w, 55w, 60w, 65w, 70w, 75w, 80w, 85w, 90w, 95w, 100w, 105w, 110w, 115w, 120w, 125w, 130w, 140w, or 1500w, etc.

[0257] The capacity density of the laser can be 100m / cm2-800m / cm2, and for example, the capacity density of the laser can be 100m / cm2, 200m / cm2, 300m / cm2, 400m / cm2, 500m / cm2, 600m / cm2, 700m / cm2, or 800m / cm2, etc.

[0258] During the laser irradiation process, the overlap rate of adjacent laser spots can be 30%-50%. For example, the overlap rate of adjacent laser spots can be 30%, 35%, 40%, 45%, or 50%, etc.

[0259] The engraving speed of the laser can be 20000mm / s-40000mm / s. For example, the engraving speed of the laser can be 20000mm / s, 22000mm / s, 25000mm / s, 27000mm / s, 29000mm / s, 30000mm / s, 32000mm / s, 35000mm / s, 38000mm / s, or 40000mm / s.

[0260] Of course, the laser used in the first method for manufacturing solar cells can be different from the laser used in the second method for manufacturing solar cells, or they can be the same, which is not limited herein.

[0261] In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0262] The above only describes specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A solar cell, characterized in that, include: A semiconductor substrate includes a first surface and a second surface opposite to each other, and a first cut side surface connecting the first surface and the second surface. The first surface includes a first region and a second region adjacent to the first cut side surface. The second region includes a stepped structure recessed into the second surface. The first region is provided with a first type of pyramid structure. The bottom wall of the stepped structure is provided with a first texture structure or a second type of pyramid structure. The side wall of the stepped structure has an angle with the thickness direction of the semiconductor substrate. A first doped layer is disposed on the first region; along the thickness direction of the semiconductor substrate, the height of the bottom wall of the stepped structure is lower than the height of the first doped layer; A first passivation layer is disposed on the side of the first doped layer away from the semiconductor substrate and on a portion of the second region; The second passivation layer is disposed on the edge of the first region near the second region, the second region and the first cut side, and the second passivation layer is located on the side of the first passivation layer away from the semiconductor substrate.

2. The solar cell according to claim 1, characterized in that, Along the extension direction of the second region, the second region includes an edge region and a middle region. The middle region and the edge region include a first step structure that is connected and recessed into the second surface. The height of the bottom wall of the first step structure is lower than the first doped layer. The bottom wall of the first step structure in the edge region is provided with a second step structure. The first passivation layer is provided on the step sidewall and the step bottom wall of the first step structure.

3. The solar cell according to claim 1, characterized in that, Along the extension direction of the second region, the second region includes an edge region and a middle region. The middle region is recessed into the second surface to form a first step structure, and the edge region is recessed into the second surface to form a second step structure. The step depth of the second step structure is greater than the step depth of the first step structure, and the width of the first step structure is greater than the width of the second step structure. The height of the bottom wall of the first step structure is lower than the first doped layer. The first passivation layer is disposed on the step sidewall and the step bottom wall of the first step structure. The width of the second passivation layer in the first region is such that it covers the edge of the middle region corresponding to the second region of the first region.

4. The solar cell according to claim 2 or 3, characterized in that, The width of the second passivation layer covering the first region is greater than the width of the second step structure.

5. The solar cell according to any one of claims 2 to 4, characterized in that, The first stepped structure has a prismatic structure on its sidewall.

6. The solar cell according to any one of claims 2 to 4, characterized in that, The first region is provided with a first type of pyramid structure, the bottom wall of the first step structure of the second region is provided with a first texture structure, and the second surface is provided with a second texture structure. The one-dimensional dimension of the first texture structure is larger than the one-dimensional dimension of the second texture structure.

7. The solar cell according to claim 7, characterized in that, The first texture structure has a one-dimensional size of 15um to 50um; and / or the second texture structure has a one-dimensional size of 2um to 20um.

8. The solar cell according to claim 6 or 7, characterized in that, The solar cell further includes a second doped layer disposed on the second surface, the second doped layer having an opposite conductivity type to the first doped layer, and the entire second surface being provided with a second textured structure; or The solar cell further includes a second doped layer disposed at intervals on the second surface, the second doped layer having the opposite conductivity type to the first doped layer, and the second texture structure being disposed in the interval region between two adjacent second doped layers on the second surface.

9. The solar cell according to any one of claims 2 to 4, characterized in that, The solar cell further includes a second doped layer disposed at intervals on the second surface. The second doped layer has the opposite conductivity type to the first doped layer. The first region is provided with a first type of pyramid structure, and the bottom wall of the first step structure in the second region is provided with a second type of pyramid structure.

10. The solar cell according to claim 9, characterized in that, The one-dimensional dimension of the first type of pyramid structure is larger than the one-dimensional dimension of the second type of pyramid structure; and / or The third type of pyramid structure is disposed in the spacer region between two adjacent second doped layers on the second surface, and the one-dimensional dimension of the third type of pyramid structure is smaller than the one-dimensional dimension of the second type of pyramid structure; and / or The depth range of the spacing region between two adjacent second doped layers on the second surface is the same as the step depth range of the first stepped structure. The angle range between the sidewall of the spacer region between two adjacent second doped layers on the second surface and the thickness direction of the semiconductor substrate is the same as the angle range between the sidewall of the stepped structure and the thickness direction of the semiconductor substrate.

11. The solar cell according to claim 2 or 3, characterized in that, Along the extending direction of the first step structure, the first step structure is wavy or bent; and / or, Along the extending direction of the first step structure, the first step structure extends continuously or intermittently; and / or, Along the direction perpendicular to the first cut side, the width of the first step structure is 20μm to 500μm.

12. The solar cell according to any one of claims 2 to 4, characterized in that, Along the thickness direction of the semiconductor substrate, the step depth of the first step structure is 2µm to 10µm; and / or The step depth of the second step structure is 30%H to 100%H, where H is the thickness of the solar cell; and / or The included angle is 15° to 60°.

13. The solar cell according to any one of claims 1 to 12, characterized in that, The thickness of the second passivation layer on the first cut side is greater than the thickness of the second passivation layer in the second region. Preferably, the thickness of the second passivation layer is greater than the thickness of the first passivation layer.

14. The solar cell according to any one of claims 1 to 13, characterized in that, The second surface is provided with a third passivation layer, and the second passivation layer extends to the edge of the second surface and is located on the side of the third passivation layer away from the semiconductor substrate.

15. The solar cell according to any one of claims 1 to 14, characterized in that, The semiconductor substrate further includes a second diced side surface, which is disposed opposite to the first diced side surface. The first surface also includes a third region adjacent to the second diced side surface. The first region is located on the side of the third region away from the second diced side surface. The third region includes a stepped structure recessed into the second surface. The bottom wall of the stepped structure in the third region is provided with a textured structure or a pyramid-like structure. The side wall of the stepped structure in the third region has an angle with the thickness direction of the semiconductor substrate. Along the thickness direction of the semiconductor substrate, the height of the bottom wall of the stepped structure in the third region is lower than the height of the first doped layer. A fourth passivation layer is disposed on the edge of the first region near the third region, the third region and the second cut side, and the fourth passivation layer is located on the side of the first passivation layer away from the semiconductor substrate.

16. The solar cell according to claim 15, characterized in that, The step depth of the stepped structure in the middle region of the second region is the same as the step depth of the stepped structure in the middle region of the third region; and / or The step depth of the step structure at the edge of the second region is the same as the step depth of the step structure at the edge of the third region; and / or, The step width of the stepped structure in the middle area of ​​the second region is the same as the step width of the stepped structure in the middle area of ​​the third region; and / or The step width of the step structure in the edge region of the second region is the same as the step width of the step structure in the edge region of the third region.

17. A method for manufacturing a solar cell, characterized in that, include:: A semiconductor substrate is provided, the semiconductor substrate including opposing first and second surfaces, the first surface including a first region and a second region; A first type of pyramid structure is formed on the first surface; A first doped layer and a first doped silicon glass layer are formed on the first surface having the first type of pyramid structure; Laser irradiation is used to reduce the density of the first doped silicon glass layer in the second region. The second surface is polished in a groove and a portion of the first doped silicon glass layer in the second region is removed, and a groove is formed in the second region that is recessed into the second surface; A second doped layer is formed on the second surface, the second doped layer having an opposite conductivity type to the first doped layer; The second doped silicon glass layer on the second surface is removed, and a first texture structure or a second type of pyramid structure is formed in the groove, such that the sidewall of the groove has an angle with the thickness direction of the semiconductor substrate, and the height of the bottom wall of the groove is lower than the height of the first doped layer along the thickness direction of the semiconductor substrate. A first passivation layer is formed on the first surface, the first passivation layer being located on the side of the first doped layer away from the semiconductor substrate; A first electrode is formed on the first doped layer, and a second electrode is formed on the second doped layer; Cut the semiconductor substrate along the groove to obtain multiple solar cells; A second passivation layer is formed in the first region near the edge of the second region, the second region and the first cut side, the second passivation layer being located on the side of the first passivation layer away from the semiconductor substrate.

18. A method for manufacturing a solar cell, characterized in that, include:: A semiconductor substrate is provided, the semiconductor substrate including opposing first and second surfaces, the first surface including a first region and a second region; A first type of pyramid structure is formed on the first surface; A first doped layer and a first doped silicon glass layer are formed on the first surface having the first type of pyramid structure; A second doped layer and a second doped silicon glass layer are formed on the second surface, wherein the second doped layer has the opposite conductivity type to the first doped layer. Using a laser, the density of the first doped silicon glass layer and the spacer in the second region is reduced; Remove the first doped silicon glass layer and the second doped silicon glass layer, and form a groove that is recessed toward the second surface in the groove, and form a first texture structure or a second type of pyramid structure in the groove, such that there is an angle between the sidewall of the groove and the thickness direction of the semiconductor substrate, and the height of the bottom wall of the groove is lower than the height of the first doped layer along the thickness direction of the semiconductor substrate. A first passivation layer is formed on the first surface, the first passivation layer being located on the side of the first doped layer away from the semiconductor substrate; A first electrode is formed on the first doped layer, and a second electrode is formed on the second doped layer; Cut the semiconductor substrate along the groove to obtain multiple solar cells; A second passivation layer is formed in the first region near the edge of the second region, the second region and the first cut side, the second passivation layer being located on the side of the first passivation layer away from the semiconductor substrate.

19. A photovoltaic module, characterized in that, include: Multiple battery strings connected in series and / or in parallel, each battery string comprising: an electrical connector and a first solar cell and a second solar cell, wherein the first solar cell is a solar cell according to any one of claims 1 to 17, or a solar cell obtained by the manufacturing method according to claim 18 or 19, the first solar cell and the second solar cell are connected by the electrical connector, the distance between the starting end of the electrical connector and the edge of the first region is greater than the width of the stepped structure of the intermediate region, and the conductive element passes through the first surface and the second side surface of the first solar cell, and through the second surface of the second solar cell, wherein the second side surface is the side surface opposite to the first cut surface in the first solar cell, and the edge of the first region is the boundary edge between the first region and the second region, preferably, the distance between the starting end of the electrical connector and the edge of the first region is greater than or equal to 1 mm.

20. The solar cell according to claim 19, characterized in that, The second side is the non-cut side.

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