Method and system for positioning and optimizing gate oxide process fault of MOSFET (Metal Oxide Semiconductor Field Effect Transistor)

Abstract

The invention relates to the related technical field of semiconductor chips, in particular to a gate-oxide process fault positioning optimization method and system for an MOSFET, and the method comprises the steps: determining gate-oxide process key parameters, constructing a defect type digital feature matrix, carrying out the correlation analysis, setting a first defect recognition vector, carrying out the correlation analysis of a positioning fault source and sensitive parameters, and setting a second vector, and generating a non-dominated solution set, screening an optimal process parameter combination, and sending a compensation instruction. The technical problems that the quality of silicon carbide MOSFET gate oxidation cannot be comprehensively and deeply reflected, a fault process point is difficult to accurately position, and the performance stability of a silicon carbide MOSFET device is low are solved, and a gate oxide defect type digital characteristic matrix is constructed according to key parameters such as the thickness of an equivalent oxide layer and the density of an interface state. Correlation analysis is carried out on the isolation oxide layer and the gate oxide test structure, the gate oxide quality of the silicon carbide MOSFET is monitored and improved, and the performance and reliability of the silicon carbide MOSFET device are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor chips, in particular to a MOSFET gate oxide process fault positioning optimization method and system. BACKGROUND

[0002] In new energy vehicle, smart grid and other high-voltage high-frequency power electronic scenarios, silicon carbide (SiC) MOSFET is widely used due to its high breakdown field strength, low conduction loss and other advantages. The quality of the silicon carbide MOSFET gate oxide layer, which is a key structure for SiC MOSFET to realize current control, directly affects the threshold voltage stability, breakdown reliability and long-term working life of the device.

[0003] However, higher critical electric field strength means that the silicon carbide MOSFET gate oxide layer of the silicon carbide MOSFET device bears a higher electric field strength than the silicon MOSFET gate oxide layer of the silicon device. In addition, fixed charges and interface trap charges further increase the electric field strength of the silicon carbide MOSFET gate oxide layer, resulting in more complex and difficult-to-detect gate oxide defect types. Conventional detection methods cannot comprehensively and deeply reflect the quality of the silicon carbide MOSFET gate oxide, resulting in frequent occurrence of hidden faults such as N-epitaxial layer defect induction and P-well / N+ source region interface recombination anomalies.

[0004] In summary, the prior art has the technical problems of being unable to comprehensively and deeply reflect the quality of the silicon carbide MOSFET gate oxide, being difficult to accurately locate the fault process point, and having low performance stability of the silicon carbide MOSFET device. SUMMARY

[0005] The present application provides a MOSFET gate oxide process fault positioning optimization method and system, which aims to solve the technical problems of being unable to comprehensively and deeply reflect the quality of the silicon carbide MOSFET gate oxide, being difficult to accurately locate the fault process point, and having low performance stability of the silicon carbide MOSFET device in the prior art.

[0006] In view of the above problems, the technical scheme of the present application is: In one aspect of the present application, a method for optimizing gate oxide process fault location of a MOSFET is provided, which comprises: obtaining C-V characteristic curve, I-V characteristic curve and trap charge relaxation characteristic data of a silicon carbide MOSFET gate oxide layer, and determining gate oxide process key parameters including equivalent oxide thickness, interface state density and threshold voltage drift; based on the gate oxide process key parameters, constructing a digital feature matrix of gate oxide defect types, performing correlation analysis with isolation oxide layer and gate oxide test structure, setting a first defect identification vector, and the gate oxide test structure comprises N-epitaxial layer, P-well and N+ source region; locating potential fault sources and key sensitive parameters affecting gate oxide quality, performing correlation analysis with isolation oxide layer process, gate oxide process and doping process, and setting a second defect identification vector; and according to the first defect identification vector and the second defect identification vector, taking improving breakdown voltage, reducing interface state density and reducing threshold voltage drift as optimization objectives, generating a non-dominated solution set, screening out a process parameter combination with the widest process window from the non-dominated solution set, and issuing a process compensation instruction.

[0007] Preferably, the silicon carbide MOSFET gate oxide layer is scanned to obtain flat-band voltage offset and equivalent oxide thickness of the C-V characteristic curve; a step pulse voltage is applied through a pulse I-V test system to capture subthreshold swing and threshold voltage drift of the I-V characteristic curve; the relaxation time constant and concentration of trap charge are obtained, and the interface state density is determined in combination with interface state charge and gate voltage.

[0008] Preferably, a mapping relationship between defect types and structure parameters is defined; core features are extracted according to the mapping relationship between defect types and structure parameters to construct a digital feature matrix of gate oxide defect types.

[0009] Preferably, isolation oxide layer breakdown in the defect types corresponds to high-frequency capacitance sudden drop in the C-V characteristic curve and high-concentration deep-level traps detected by DLTS.

[0010] Preferably, the gate oxide test structure comprises N-epitaxial layer, P-well and N+ source region, wherein N-epitaxial layer defect induction in the defect types is associated with abnormal subthreshold swing of the I-V characteristic curve and epitaxial layer resistivity fluctuation; P-well / N+ source region interface recombination anomaly in the defect types corresponds to sudden increase of interface state density and hysteresis loop in the C-V characteristic curve.

[0011] Preferably, a target function is established according to the optimization objectives, multi-objective optimization is performed to generate a non-dominated solution set, and based on the non-dominated solution set, a process parameter combination with a signal-to-noise ratio meeting a threshold value is screened out to generate the process compensation instruction.

[0012] Preferably, a process compensation decision model is constructed, with defect types and sensitive parameters as the state space, with parameter adjustment amplitude as the action space, and with yield improvement rate as the reward function; meanwhile, a digital twin model is called to verify the effectiveness of the process compensation instruction.

[0013] Preferably, if the simulated yield exceeds the preset lower limit of yield, the process compensation instruction is issued to the silicon carbide MOSFET device production line for execution, otherwise a secondary optimization iteration is triggered.

[0014] Preferably, if the model test result of the N+ source region is abnormal, and the model test results of the N- epitaxial layer and the P well are normal, it is determined that the N+ source region doping causes the gate oxide quality to decrease; if the model test results of the N- epitaxial layer, the P well and the N+ source region are normal, and the model test result of the P well / N+ source region is abnormal, it is determined that the N+ source region doping causes the gate oxide quality to decrease.

[0015] In another aspect of the present application, a MOSFET gate oxide process fault positioning optimization system is provided, wherein the system comprises: a data acquisition module configured to acquire, for a silicon carbide MOSFET device, C-V characteristic curve, I-V characteristic curve and trap charge relaxation characteristic data of a silicon carbide MOSFET gate oxide layer, and determine gate oxide process key parameters including equivalent oxide thickness, interface state density and threshold voltage drift amount; a first correlation analysis module configured to construct a digital feature matrix of gate oxide defect types based on the gate oxide process key parameters, perform correlation analysis with an isolation oxide layer and a gate oxide test structure, and set a first defect identification vector, wherein the gate oxide test structure comprises an N- epitaxial layer, a P well and an N+ source region; a second correlation analysis module configured to locate a potential fault source and a key sensitive parameter affecting gate oxide quality, perform correlation analysis with an isolation oxide process, a gate oxide process and a doping process, and set a second defect identification vector; and a process compensation module configured to generate a non-dominated solution set based on the first defect identification vector and the second defect identification vector, with the optimization objectives of improving breakdown voltage, reducing interface state density and reducing threshold voltage drift, filter out a process parameter combination with the widest process window from the non-dominated solution set, and issue a process compensation instruction.

[0016] In summary, one or more technical solutions provided in the present application achieve the technical effect of monitoring and improving the quality of silicon carbide MOSFET gate oxide and improving the performance and reliability of silicon carbide MOSFET devices by constructing a digital feature matrix of gate oxide defect types based on key parameters such as equivalent oxide thickness and interface state density, performing correlation analysis with an isolation oxide layer and a gate oxide test structure. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 A flowchart of a MOSFET gate oxide process fault positioning optimization method is provided in the present application; Figure 2This application provides a schematic diagram of a MOSFET gate oxide process fault location optimization system.

[0018] Explanation of reference numerals in the attached diagram: Data acquisition module M100, first correlation analysis module M200, second correlation analysis module M300, process compensation module M400. Detailed Implementation

[0019] Example 1 The present application will now be described in detail with reference to the accompanying drawings, such as... Figure 1 As shown, this application provides a method for optimizing gate oxide process fault location in MOSFETs, wherein the method includes: S1: For silicon carbide MOSFET devices, obtain the CV characteristic curve, IV characteristic curve, and trap charge relaxation characteristic data of the gate oxide layer of the silicon carbide MOSFET, and determine the key gate oxide process parameters including equivalent oxide layer thickness, interface state density, and threshold voltage drift; S2: Based on the key gate oxide process parameters, construct a digital feature matrix of gate oxide defect types, perform correlation analysis with the isolation oxide layer and the gate oxide test structure, and set a first defect identification vector. The gate oxide test structure includes an N-epitaxial layer, a P-well, and an N+ source region.

[0020] Specifically, obtaining the CV characteristic curves, IV characteristic curves, and trapped charge relaxation characteristic data of the gate oxide layer of a silicon carbide MOSFET is essential for a comprehensive evaluation of the quality and performance of the gate oxide layer. The CV characteristic curve reflects the relationship between capacitance and voltage, providing information about the gate oxide layer thickness and interface states of the silicon carbide MOSFET. The IV characteristic curve shows the relationship between current and voltage, helping to understand the device's conductivity and defect conditions. The trapped charge relaxation characteristic data involves the trapping and release behavior of trapped charges under the influence of an electric field, which is crucial for revealing the defect states in the gate oxide layer of the silicon carbide MOSFET.

[0021] Determining key gate oxide (GOX) process parameters, including equivalent oxide thickness, interface state density, and threshold voltage drift, is crucial for accurately identifying the core factors affecting GOX quality. Equivalent oxide thickness is a key indicator of the physical properties of the gate oxide layer in silicon carbide MOSFETs, interface state density reflects the degree of defects at the interface, and threshold voltage drift reflects the device's stability under different conditions. Constructing a digital feature matrix of GOX defect types allows for the digital characterization of these defect types, facilitating subsequent analysis and processing.

[0022] The correlation analysis with the isolation oxide layer and the gate oxide test structure is performed to find the internal relationship between the defects and the process structure. The isolation oxide layer is used to realize electrical isolation of the device, and the gate oxide test structure is a specific structure for evaluating the quality of the gate oxide, including an N-epitaxial layer, a P-well, and an N+ source region, which respectively play different functional roles in the device. The first defect identification vector is set to provide a quantitative basis for subsequent fault diagnosis and optimization, so as to more accurately locate the fault source.

[0023] The execution step: the characteristics of the silicon carbide MOSFET device are tested, and the C-V characteristic curve, I-V characteristic curve and trap charge relaxation characteristic data of the silicon carbide MOSFET gate oxide layer are obtained through professional test equipment and system. For example, when obtaining the C-V characteristic curve, the flat band voltage offset and equivalent oxide thickness parameters can be obtained by accurately controlling the test voltage and measuring the corresponding capacitance change; when obtaining the I-V characteristic curve, the subthreshold swing and threshold voltage drift information can be obtained by applying a step pulse voltage and capturing the current response; the trap charge relaxation characteristic data can be obtained by a specific test method to obtain the relaxation time constant and concentration of the trap charge.

[0024] Based on the key parameters of the gate oxide process, a digital feature matrix of the gate oxide defect type is constructed, the core features are extracted and the matrix is constructed by analyzing the mapping relationship between the defect type and the structure parameters. For example, when the isolation oxide layer breaks down, the high-frequency capacitance of the C-V characteristic curve drops sharply and the DLTS detects a high concentration of deep level traps. Correlation analysis is performed with the isolation oxide layer and the gate oxide test structure. For example, when the N-epitaxial layer defect is induced, the abnormal subthreshold swing of the I-V characteristic curve is associated with the fluctuation of the epitaxial layer resistivity; when the P-well / N+ source region interface recombination is abnormal, the interface state density increases sharply and the C-V characteristic curve appears hysteresis loop. The first defect identification vector is set to provide accurate quantitative basis for subsequent fault location.

[0025] Through accurate determination of the key parameters of the gate oxide process and construction of the digital feature matrix, key data support and quantitative basis are provided for subsequent fault diagnosis and process optimization.

[0026] S3: locating the potential fault source and the key sensitive parameters affecting the quality of the gate oxide, and performing correlation analysis with the isolation oxide layer process, the gate oxide process and the doping process, and setting the second defect identification vector; S4: according to the first defect identification vector and the second defect identification vector, taking improving the breakdown voltage, reducing the interface state density and reducing the threshold voltage drift as the optimization target, generating a non-dominated solution set, screening out the process parameter combination with the widest process window from the non-dominated solution set, and issuing a process compensation instruction.

[0027] Specifically, locating potential failure sources and key sensitive parameters affecting gate oxide quality refers to determining the root causes that may lead to gate oxide process failure and sensitive factors that have a significant impact on gate oxide quality through system analysis and diagnosis. These factors involve various aspects such as process conditions, material properties, or structure design. Correlation analysis with isolation oxide layer process, gate oxide process, and doping process refers to correlating the above potential failure sources and key sensitive parameters with isolation oxide layer process, gate oxide process, and doping process, respectively, and studying their mutual influence and action mechanism in order to more comprehensively understand the causes of failure.

[0028] Setting the second defect identification vector refers to constructing a vector based on the results of correlation analysis to quantify and identify the types and degrees of defects caused by these processes, with the optimization objectives of improving breakdown voltage, reducing interface state density, and reducing threshold voltage drift. Generating a non-dominated solution set refers to using multi-objective optimization algorithms to generate a series of process parameter combinations that are balanced in performance and cannot be simultaneously surpassed by other solutions, with the three key performance indicators as optimization directions. Selecting the process parameter combination with the widest process window from the non-dominated solution set and issuing process compensation instructions refers to selecting the parameter combination with the widest process window from the non-dominated solutions to ensure the stability and reliability of the process, and issuing instructions to compensate and adjust the existing process accordingly.

[0029] The execution steps are: locating potential failure sources and key sensitive parameters affecting gate oxide quality, and performing correlation analysis with isolation oxide layer process, gate oxide process, and doping process, setting the second defect identification vector process, which is specifically through analyzing a large amount of process data, using statistical analysis, machine learning, etc., combined with domain expert knowledge, to mine the internal relationship between potential failure sources and key sensitive parameters and process, for example, through the analysis of isolation oxide layer process parameters (such as oxidation temperature, time, etc.), the significant correlation with interface state density can be found; through the study of gate oxide process (such as gate oxide thickness, oxidation process, etc.), the influence law of breakdown voltage can be revealed; through the exploration of doping process (such as doping concentration, distribution, etc.), the correlation with threshold voltage drift can be determined.

[0030] Based on the correlation analysis with the isolation oxide layer process, gate oxide process, and doping process, a second defect recognition vector is set, which can further improve the accuracy of fault diagnosis, and the breakdown voltage, interface state density, and threshold voltage drift are optimized as the optimization objectives, a non-dominated solution set is generated, the reliability, stability, and performance of the silicon carbide MOSFET device can be considered at the same time, further, the multi-objective optimization algorithm (such as NSGA-II) can search for a non-dominated solution set that meets multiple optimization objectives in a complex process parameter space; the process parameter combination with the widest process window is screened out, which can ensure that the process parameters have a certain fluctuation range in the actual production process without affecting the final product quality, for example, in the screening process, the process parameter range of different solutions is evaluated, and the combination with the widest process window is selected, thereby improving the robustness and stability of the process, and issuing a process compensation instruction to guide the adjustment of the process parameters in the production process, realizing the continuous optimization of the gate oxide process.

[0031] Further, for the silicon carbide MOSFET device, the C-V characteristic curve, I-V characteristic curve, and trap charge relaxation characteristic data of the silicon carbide MOSFET gate oxide layer are obtained, and the method comprises: Scanning the silicon carbide MOSFET gate oxide layer to obtain the flat band voltage offset and equivalent oxide layer thickness of the C-V characteristic curve; applying a staircase pulse voltage through a pulse I-V test system to capture the subthreshold swing and threshold voltage drift of the I-V characteristic curve; obtaining the relaxation time constant and concentration of trap charge, and determining the interface state density in combination with the interface state charge and gate voltage.

[0032] Specifically, scanning the silicon carbide MOSFET gate oxide layer means using professional scanning equipment and technology to finely detect the silicon carbide MOSFET gate oxide layer to obtain information about its microstructure and electrical characteristics. Obtaining the flat band voltage offset and equivalent oxide layer thickness of the C-V characteristic curve is to measure the relationship curve between capacitance and voltage to determine the offset of the flat band voltage and calculate the actual thickness of the equivalent oxide layer, the flat band voltage offset reflects the influence of the interface state charge, and the equivalent oxide layer thickness is a key indicator for measuring the physical characteristics of the silicon carbide MOSFET gate oxide layer.

[0033] Applying a staircase pulse voltage through a pulse I-V test system means using a pulse current-voltage test system to apply a series of gradually increasing voltage pulses to stimulate the current response of the device under different voltages. Capturing the subthreshold swing and threshold voltage drift of the I-V characteristic curve means recording the relationship curve between current and voltage, analyzing the subtle changes in the curve to determine the subthreshold swing (an indicator of device switching performance) and the variation of threshold voltage under different conditions, and the threshold voltage drift reflects the stability and reliability of the device.

[0034] The relaxation time constant and concentration of trap charges are determined by a specific test method, measuring the process of trap charges capturing and releasing charges under the action of an electric field, to determine the relaxation time constant (a time parameter reflecting the dynamic characteristics of trap charges) and concentration (the number of trap charges per unit volume). The determination of the interface state density in combination with the interface state charge and the gate voltage refers to determining the interface state density by a physical model and mathematical calculation using the relationship between the measured interface state charge data and the gate voltage. The interface state density is an important parameter for characterizing the quality of the gate oxide layer and the semiconductor interface of the silicon carbide MOSFET.

[0035] The execution steps are as follows: scanning the gate oxide layer of the silicon carbide MOSFET, using a high-precision capacitance-voltage (C-V) tester, changing the test frequency and voltage to obtain the C-V characteristic curve. The flat-band voltage offset is obtained from the curve, and the equivalent oxide layer thickness is calculated according to the theoretical relationship between the flat-band voltage and the equivalent oxide layer thickness. Specifically, the deviation of the flat-band voltage offset from the theoretical value is ΔVfb, which is calculated by the formula ΔVfb = Vfb - Vfb0, where Vfb is the measured flat-band voltage, and Vfb0 is the theoretical flat-band voltage. The equivalent oxide layer thickness is calculated by the formula t = C0*Vfb0 / ε0, where C0 is the oxide capacitance, and ε0 is the vacuum permittivity. The equivalent oxide layer thickness is calculated by the formula t = C0*Vfb0 / ε0, where C0 is the oxide capacitance, and ε0 is the vacuum permittivity. , where is the oxide charge, is the oxide capacitance, and the deviation of the equivalent oxide layer thickness is calculated, and the equivalent oxide layer thickness is determined.

[0036] Using a pulse I-V test system, a step pulse voltage gradually increasing from low to high is applied to the device, each voltage pulse lasts for a certain time, the corresponding current response is captured, and the I-V characteristic curve is drawn. By analyzing the sub-threshold region of the curve, the sub-threshold swing is calculated, and the threshold voltage drift under different conditions is recorded, i.e. the threshold voltage drift.

[0037] The relaxation time constant and concentration of trap charges are obtained by deep level transient spectroscopy (DLTS) and other techniques. Preferably, the test is performed under different temperature and bias conditions, and the current or capacitance changes during the capture and release of trap charges are recorded. By analyzing the law of these changes over time, the relaxation time constant and concentration are determined.

[0038] In combination with the test data of the interface state charge and the relationship between the gate voltage, the interface state density is determined using a physical model (such as a Gaussian distribution model) and a mathematical calculation method. This provides a parameter basis for subsequent gate oxide defect analysis and process optimization, effectively reflects the quality of the gate oxide layer of the silicon carbide MOSFET, accurately locates the fault source, and provides strong support for subsequent process improvement.

[0039] Further, a digital feature matrix of the gate oxide defect type is constructed, and a correlation analysis is performed with the isolation oxide layer and the gate oxide test structure. The method of the present application includes: define a mapping relationship between defect types and structure parameters; extract core features according to the mapping relationship between defect types and structure parameters, and construct a digital feature matrix of gate oxide defect types.

[0040] Specifically, defining a mapping relationship between defect types and structure parameters means that according to professional knowledge and experimental data, the corresponding relationship between different defect types (such as isolation oxide breakdown, N-epitaxial layer defect induction, P-well / N+ source region interface recombination anomaly, etc.) and various structure parameters (including but not limited to layer thickness, doping concentration, interface state density, etc.) is clear. This is similar to establishing a control table from defects to structures, which provides a theoretical basis for subsequent analysis.

[0041] According to the mapping relationship between defect types and structure parameters, the core features are extracted, irrelevant or redundant information is removed, and the process is like picking out key evidence for solving a case from many clues; constructing a digital feature matrix of gate oxide defect types presents the extracted core features in a digital matrix form. This digital expression is convenient for computer processing and analysis, and lays a foundation for subsequent use of mathematical models or algorithms for defect analysis and identification.

[0042] Execution steps: combine past experimental experience to define the mapping relationship between defect types and structure parameters, for example, find that the isolation oxide breakdown defect type often corresponds to a sudden drop in high-frequency capacitance in the C-V characteristic curve, and high-concentration deep-level traps can be found when using DLTS (deep level transient spectroscopy) detection; based on such mapping relationship, further extract core features, such as for isolation oxide breakdown, focus on extracting two core features of high-frequency capacitance change rate and trap concentration; for N-epitaxial layer defect induction, focus on core features such as I-V characteristic curve sub-threshold swing change rate and epitaxial layer resistivity fluctuation amplitude.

[0043] After the extraction of core features, a digital feature matrix of gate oxide defect types is constructed. If there are three defect types, and each defect type extracts two core features, then the constructed digital feature matrix is a 3x2 matrix. Each element in the matrix is a feature value obtained by a large number of experimental data statistics and calculations. In the above steps, the feature matrix is converted into a digital world that can be processed, providing a precise data basis for subsequent use of machine learning algorithms or mathematical models for accurate identification and classification of defects.

[0044] Further, the method of the application further comprises: The isolation oxide breakdown in the defect type corresponds to a sudden drop in high-frequency capacitance in the C-V characteristic curve and a high-concentration deep-level trap detected by DLTS.

[0045] Specifically, the isolation oxide layer breakdown in the defect type refers to a specific gate oxide defect condition, that is, the isolation oxide layer has a breakdown phenomenon under the action of electric field or other factors, leading to a decrease in device performance or even failure. This defect can be caused by various factors, such as uneven oxide layer thickness, presence of impurities or crystal defects, etc. The sudden drop in high-frequency capacitance in the C-V characteristic curve refers to the phenomenon that when the isolation oxide layer breaks down, the capacitance value suddenly drops in the high-frequency segment of the C-V characteristic curve. This is because the breakdown causes the electrical properties of the oxide layer to change, and its capacitance characteristics no longer conform to the normal rules. The high concentration of deep level traps detected by DLTS refers to the use of deep level transient spectroscopy (DLTS) technology to detect a large number of deep level traps in the isolation oxide layer. These traps can capture and release charges, thereby affecting the electrical performance of the device. The presence of deep level traps is usually closely related to defects in the oxide layer, and a high concentration further indicates the severity of the isolation oxide layer breakdown defect.

[0046] Execution step: When the isolation oxide layer breaks down, the capacitance value will suddenly drop due to the change in dielectric properties of the oxide layer in the high-frequency segment of the C-V characteristic curve. For example, under normal circumstances, the high-frequency capacitance value changes with voltage in a certain pattern, but when the isolation oxide layer breaks down, the capacitance value may drop (20% to 50%) at a certain voltage point. This sudden drop is one of the important bases for judging the breakdown of the isolation oxide layer.

[0047] At the same time, through DLTS detection, it can be found that the concentration of deep level traps increases significantly. In DLTS testing, the energy level position and concentration of traps are obtained through data analysis by monitoring the current or capacitance transient signal during the capture and release of trap charges. Under normal circumstances, the concentration of deep level traps is 1x Below, and when the isolation oxide layer breaks down, the concentration of deep level traps may increase to 1x Even higher.

[0048] Through the above steps, the characteristics of the specific defect type of isolation oxide layer breakdown are described, providing clear judgment basis for subsequent defect identification and positioning. Combined with the C-V characteristic and DLTS detection results, the isolation oxide layer breakdown defect type can be accurately identified, thereby providing targeted guidance for subsequent process optimization and defect repair, which helps to improve the reliability and stability of silicon carbide MOSFET devices.

[0049] Further, the method of the present application further comprises: The gate oxide test structure includes an N-epitaxial layer, a P-well, and an N+ source region. Among the defect types, N-epitaxial layer defects induce a correlation between I-V characteristic curve sub-threshold swing anomalies and epitaxial layer resistivity fluctuations. The P-well / N+ source region interface recombination anomaly corresponds to a sudden increase in interface state density and a hysteresis loop in the C-V characteristic curve.

[0050] Specifically, the gate oxide test structure includes an N-epitaxial layer, a P-well, and an N+ source region, which means that in a silicon carbide MOSFET device, the specific structure used to evaluate the quality of the gate oxide is composed of these three layers. The N-epitaxial layer is a lightly doped N-type epitaxial layer used to form the drift region of the device. The P-well is a P-type doped region formed in the N-epitaxial layer, used to form the inversion layer and depletion layer. The N+ source region is a heavily doped N-type source region used to provide low resistance source contact.

[0051] Among the defect types, N-epitaxial layer defects induce a correlation between I-V characteristic curve sub-threshold swing anomalies and epitaxial layer resistivity fluctuations. The P-well / N+ source region interface recombination anomaly corresponds to a sudden increase in interface state density and a hysteresis loop in the C-V characteristic curve.

[0052] For N-epitaxial layer defect-induced cases, when the N-epitaxial layer has defects, it will cause the resistivity of the epitaxial layer to fluctuate, and at the same time, it will show sub-threshold swing anomalies in the I-V characteristic curve. For example, under normal circumstances, the sub-threshold swing is about 60-80 mV / decade, but if the N-epitaxial layer defects cause the resistivity to fluctuate more than ±10%, the sub-threshold swing may increase to 100-120 mV / decade, indicating that the switching performance of the device has deteriorated, which is an important indicator for identifying N-epitaxial layer defects.

[0053] For P-well / N+ source region interface recombination anomaly cases, interface recombination anomalies will cause a sudden increase in interface state density, for example, from the normal condition of 1× to 5× At the same time, hysteresis loop phenomenon appears in the C-V characteristic curve, that is, there is a significant difference in the capacitance value when the voltage is scanned forward and backward, and the width of the hysteresis loop can reach tens of millivolts or even more.

[0054] In the above steps, by analyzing the correlation between specific defect types and corresponding changes in electrical characteristics, a clear basis for fault diagnosis is provided; by monitoring these abnormal phenomena in the I-V and C-V characteristic curves, N-epitaxial layer defects and interface recombination abnormal problems can be quickly and accurately identified, thereby providing targeted direction for subsequent process optimization and improving the performance and reliability of silicon carbide MOSFET devices.

[0055] Further, a non-dominated solution set is generated, from which the process parameter combination with the widest process window is selected, and a process compensation instruction is issued. The method of the application comprises: According to the optimization target, a target function is established, multi-objective optimization is performed, a non-dominated solution set is generated, and based on the non-dominated solution set, a process parameter combination with a signal-to-noise ratio meeting a threshold value is selected, and the process compensation instruction is generated.

[0056] Specifically, according to the optimization target, a target function is established, multi-objective optimization is performed, a non-dominated solution set is generated, and based on the non-dominated solution set, a process parameter combination with a signal-to-noise ratio meeting a threshold value is selected, and the process compensation instruction is generated. Specifically, according to the optimization target, a target function is established, which means that according to the optimization direction to be achieved (such as increasing the breakdown voltage, reducing the interface state density, and reducing the threshold voltage drift), a corresponding mathematical model is constructed, and these optimization targets are converted into quantifiable function forms.

[0057] Multi-objective optimization means using a multi-objective optimization algorithm (such as NSGA-II) to find a balance between multiple mutually restrictive objectives and find the best process parameter combination that meets all optimization objectives. The generated non-dominated solution set means that it contains a series of process parameter combinations that are balanced in performance and cannot be simultaneously superior to other solutions. Based on the non-dominated solution set, a process parameter combination with a signal-to-noise ratio meeting a threshold value is selected from the non-dominated solution set, which means that the process parameter combination with a signal-to-noise ratio (an index measuring process stability and anti-interference ability) meeting the set standard is selected to ensure the reliability of the process. The process compensation instruction is generated according to the selected process parameter combination to form a specific process adjustment instruction, and the process compensation instruction is used to guide the process compensation and optimization in actual production.

[0058] The execution step is: taking the improvement of the breakdown voltage, the reduction of the interface state density and the reduction of the threshold voltage drift as the optimization targets, establishing a target function, performing multi-objective optimization in the process parameter space by using the NSGA-II algorithm, obtaining a solution set containing multiple non-dominated solutions, and further, through multiple rounds of iterative optimization, obtaining a solution set composed of multiple non-dominated solutions, each solution corresponding to different process parameter combinations and corresponding performance index values; selecting process parameter combinations with a signal-to-noise ratio meeting a threshold value (such as a signal-to-noise ratio greater than 20 dB) from the non-dominated solution set; selecting process parameter combinations meeting the conditions through signal-to-noise ratio analysis, which have high process stability and anti-interference ability while meeting the optimization targets; and generating specific process compensation instructions according to the selected process parameter combinations.

[0059] In the above steps, the multi-objective optimization and screening ensure the optimality and reliability of the process parameter combinations, and provide a strong guarantee for improving the performance and yield of the silicon carbide MOSFET device.

[0060] Further, after issuing the process compensation instructions, the method of the present application further comprises: A process compensation decision model is constructed, taking defect types and sensitive parameters as state spaces, taking parameter adjustment amplitudes as action spaces, and taking yield improvement rates as reward functions; at the same time, a digital twin model is called to verify the effectiveness of the process compensation instructions.

[0061] Specifically, constructing a process compensation decision model means using machine learning and reinforcement learning techniques to establish an intelligent decision model that can automatically determine the optimal process compensation parameters based on the current process state and defect information. In this model, defect types and sensitive parameters are used as state spaces, which means that various defect types (such as isolation oxide breakdown, N-epitaxial layer defect induction, P-well / N+ source region interface recombination anomaly, etc.) and sensitive parameters (such as equivalent oxide thickness, interface state density, threshold voltage drift, etc.) that have a significant impact on process quality are used as input state variables of the model to fully describe the current state of the process.

[0062] The parameter adjustment range as the action space refers to taking the change range of the adjustable process parameters (such as the gate oxide thickness adjustment range, the oxidation temperature adjustment range, the doping concentration adjustment range, etc.) as the output action variable of the model, providing the adjustment direction and range for the model decision; the yield improvement rate as the reward function refers to taking the improvement degree of the product yield after process adjustment as the objective function of model learning and optimization, encouraging the model to continuously learn and optimize the decision strategy to find the process parameter adjustment scheme that can maximize the yield improvement, and simultaneously, calling the digital twin model to verify the effectiveness of the process compensation instruction refers to using the digital twin technology to construct a virtual model highly consistent with the actual production process, simulating the execution of the process compensation instruction in the model to verify its effect in actual production in advance, and ensuring the reliability and effectiveness of the process adjustment.

[0063] Execution step: when constructing the process compensation decision model, a large amount of historical process data and defect data are first collected, including various defect types, sensitive parameter changes, and corresponding process parameter adjustment records and yield results; these data are used to train the model, and through reinforcement learning algorithms (such as DQN, PPO, etc.), the model learns to take what action (i.e., parameter adjustment range) under different states (i.e., different defect types and sensitive parameter combinations) to obtain the maximum reward (i.e., yield improvement rate), for example, during the training process, the model may learn that when N-epitaxial layer defects are induced and the interface state density is high, appropriately increasing the gate oxide thickness and improving the oxidation temperature can effectively improve the yield.

[0064] After completing the model training, whenever process compensation is needed, the current defect type and sensitive parameter are input into the decision model, the model will output the corresponding parameter adjustment range according to the learned strategy to form the process compensation instruction, and simultaneously, in order to verify the effectiveness of the instruction, it is input into the digital twin model for simulation; the digital twin model based on high-precision physical modeling and actual production data can accurately simulate the production process and results after executing the process compensation instruction, for example, the simulation result shows that the yield is improved from 85% to 92% after executing the instruction, which exceeds the preset lower limit of the yield (such as 90%), and it is considered that the process compensation instruction is effective and can be issued to the actual production line for execution; otherwise, if the simulation yield does not meet the requirements, a secondary optimization iteration is triggered to re-adjust the process parameters until the requirements are met.

[0065] In the above steps, through the intelligent decision model and digital verification means, the scientificity and accuracy of process compensation are greatly improved, ensuring the effectiveness and reliability of process adjustment, thereby realizing the efficient optimization and quality improvement of silicon carbide MOSFET device production.

[0066] Further, the method of the present application further comprises: If the simulated yield exceeds the preset yield lower limit, it is executed on the silicon carbide MOSFET device production line, otherwise a secondary optimization iteration is triggered.

[0067] Specifically, if the simulated yield exceeds the preset yield lower limit, it is executed on the silicon carbide MOSFET device production line, otherwise a secondary optimization iteration is triggered, that is, according to the verification result of the effectiveness of the process compensation instruction by the digital twin model to determine the next operation. Specifically, the preset yield lower limit is a threshold set according to production requirements, representing the acceptable minimum product yield. The simulated yield refers to the product yield obtained after executing the process compensation instruction by the digital twin model.

[0068] If the simulated yield is higher than or equal to the preset lower limit, it means that the current process compensation instruction can effectively improve the production quality and meet the production requirements. At this time, the instruction is issued to the actual silicon carbide MOSFET device production line to guide the process adjustment in the production process. On the contrary, if the simulated yield is lower than the preset lower limit, it means that the current process compensation instruction is not enough to effectively improve the production situation. At this time, a secondary optimization iteration is triggered, that is, the process parameters are optimized again, and a new process compensation instruction is generated and verified.

[0069] Execution step: After the digital twin model simulates the execution of the process compensation instruction, the simulated yield data is obtained. For example, if the preset yield lower limit is 90% and the simulation result shows that the yield is 92%, the process compensation instruction is issued to the production line for execution. The production line adjusts the process parameters according to the instruction, such as adjusting the gate oxide thickness, oxidation temperature, etc., so as to improve the performance and reliability of the silicon carbide MOSFET device. If the simulated yield is 88%, which is lower than the preset lower limit, a secondary optimization iteration is triggered.

[0070] At this time, the multi-objective optimization algorithm is combined with the process compensation decision model to re-optimize the process parameter combination, further adjust the process parameters, generate a new process compensation instruction, and verify its effectiveness through the digital twin model. This process will continue until the simulated yield reaches or exceeds the preset lower limit. Through the above steps, only the process compensation instruction that has been verified to be effective will be actually applied, avoiding ineffective or harmful process adjustments, ensuring the efficiency of silicon carbide MOSFET device production and the stability of product quality. At the same time, through the secondary optimization iteration, the optimal process scheme is continuously approached, improving the overall production yield and efficiency.

[0071] Further, the method of the present application further comprises: If the model test result of the N+ source region is abnormal, and the model test results of the N- epitaxial layer and the P well are normal, it is determined that the N+ source region doping causes the gate oxide quality to decrease.

[0072] Specifically, if the model test result of the N+ source region is abnormal, and the model test results of the N- epitaxial layer and the P well are normal, it is determined that the N+ source region doping causes the gate oxide quality to decrease, which refers to a process of locating the fault source through simulation simulation; when the N+ source region has abnormal results in the model test (such as the electrical characteristics not meeting the expectations), and the test results of other regions (the N- epitaxial layer and the P well) are normal, it can be determined that there is a problem in the N+ source region doping process, which causes the gate oxide quality to decrease.

[0073] Similarly, if the model test results of the N- epitaxial layer, the P well, and the N+ source region are normal, and the model test result of the P well / N+ source region is abnormal, it is determined that the N+ source region doping causes the gate oxide quality to decrease, which refers to that when the N- epitaxial layer, the P well, and the N+ source region are tested separately, the results are normal, but when the interface of the P well and the N+ source region is tested, an abnormality occurs, which indicates that the problem is at the interface of the P well and the N+ source region, and further analysis can trace back to the influence of the N+ source region doping process on the interface quality.

[0074] The execution step is: in the digital twin model, the N+ source region, the N- epitaxial layer, and the P well are respectively simulated and tested, for example, in the first case, if it is found in the test that the interface state density of the N+ source region is abnormally high, and the test results of the N- epitaxial layer and the P well are within the normal range, it indicates that the doping process of the N+ source region may cause the interface state density to increase, and then affect the gate oxide quality, at this time, the doping process of the N+ source region should be adjusted and optimized.

[0075] In the second case, if the test results of the N- epitaxial layer, the P well, and the N+ source region are all normal, but an abnormality is found when the interface of the P well and the N+ source region is tested, such as the existence of additional trap charge or the local increase of the interface state density, which indicates that there is a defect at the interface of the P well and the N+ source region, and further analysis finds that the lattice distortion or impurity accumulation at the interface is caused by the improper N+ source region doping process, thereby affecting the gate oxide quality.

[0076] In the above steps, through the comprehensive analysis of the simulation test results of different regions, the fault source can be accurately located, which provides a clear direction for subsequent process optimization, and ensures the quality and reliability of the silicon carbide MOSFET device.

[0077] In summary, the beneficial effects of the embodiments of the present application are: By employing data on silicon carbide MOSFET devices, the CV characteristic curves, IV characteristic curves, and trap charge relaxation characteristics of the gate oxide layer were obtained. Key gate oxide process parameters, including equivalent oxide thickness, interface state density, and threshold voltage drift, were determined. A digital feature matrix of gate oxide defect types was constructed, and correlation analysis was performed with the isolation oxide layer and the gate oxide test structure to establish a first defect identification vector. The gate oxide test structure includes an N-epitaxial layer, a P-well, and an N+ source region. Potential fault sources and key sensitive parameters affecting gate oxide quality were located, and correlation analysis was performed with the isolation oxide layer process, the gate oxide process, and the doping process to establish a second defect identification vector. The vector, combined with the first defect identification vector, aims to improve the breakdown voltage, reduce the interface state density, and reduce the threshold voltage drift. A non-dominated solution set is generated, from which the process parameter combination with the widest process window is selected, and a process compensation command is issued. This application provides a method and system for optimizing the gate oxide process of MOSFETs. It realizes the technical effect of constructing a digital feature matrix of gate oxide defect types based on key parameters such as equivalent oxide layer thickness and interface state density, performing correlation analysis with isolation oxide layer and gate oxide test structure, monitoring and improving the gate oxide quality of silicon carbide MOSFETs, and improving the performance and reliability of silicon carbide MOSFET devices.

[0078] Example 2 Based on the same inventive concept as the gate oxide process fault location optimization method for MOSFETs in the foregoing embodiments, such as Figure 2 As shown in the figure, this application embodiment provides a MOSFET gate oxide process fault location optimization system, wherein the system includes: The data acquisition module M100 is used to acquire the CV characteristic curve, IV characteristic curve and trap charge relaxation characteristic data of the gate oxide layer of silicon carbide MOSFET devices, and determine the key gate oxide process parameters including equivalent oxide layer thickness, interface state density and threshold voltage drift.

[0079] The first correlation analysis module M200 is used to construct a digital feature matrix of gate oxide defect types based on the key parameters of the gate oxide process, perform correlation analysis with the isolation oxide layer and the gate oxide test structure, and set a first defect identification vector. The gate oxide test structure includes an N-epitaxy layer, a P-well, and an N+ source region.

[0080] The second correlation analysis module M300 is used to locate potential fault sources and key sensitive parameters affecting gate oxide quality, perform correlation analysis with isolation oxide layer process, gate oxide process, and doping process, and set a second defect identification vector.

[0081] A process compensation module M400 is configured to generate a non-dominated solution set based on the first defect identification vector and the second defect identification vector, and to select a process parameter combination with the widest process window from the non-dominated solution set as an optimization target, and to issue a process compensation instruction.

[0082] Further, the data acquisition module M100 is configured to perform the following method: The gate oxide layer of the silicon carbide MOSFET is scanned to obtain the flat band voltage offset and the equivalent oxide thickness of the C-V characteristic curve; the subthreshold swing and the threshold voltage drift of the I-V characteristic curve are captured by applying a step pulse voltage through the pulse I-V test system; the trap charge relaxation time constant and the concentration are obtained, and the interface state density is determined in combination with the interface state charge and the gate voltage.

[0083] Further, the first correlation analysis module M200 is configured to perform the following method: A mapping relationship between the defect type and the structure parameter is defined; core features are extracted according to the mapping relationship between the defect type and the structure parameter, and a digital feature matrix of the gate oxide defect type is constructed.

[0084] Further, the first correlation analysis module M200 is further configured to perform the following method: The isolation oxide layer breakdown in the defect type corresponds to the high-frequency capacitance sudden drop in the C-V characteristic curve and the high-concentration deep-level trap detected by the DLTS.

[0085] Further, the first correlation analysis module M200 is further configured to perform the following method: The gate oxide test structure includes an N-epitaxial layer, a P-well, and an N+ source region, wherein the N-epitaxial layer defect induction in the defect type is associated with the abnormal subthreshold swing of the I-V characteristic curve and the epitaxial layer resistivity fluctuation; the P-well / N+ source region interface recombination anomaly in the defect type corresponds to the sudden increase of the interface state density and the hysteresis loop in the C-V characteristic curve.

[0086] Further, the process compensation module M400 is configured to perform the following method: A target function is established according to the optimization target, multi-objective optimization is performed to generate a non-dominated solution set, and a process parameter combination with a signal-to-noise ratio meeting a threshold value is selected based on the non-dominated solution set to generate the process compensation instruction.

[0087] Further, the process compensation module M400 is further configured to perform the following method: A process compensation decision model is constructed, with the defect type and the sensitive parameter as the state space, the parameter adjustment amplitude as the action space, and the yield improvement rate as the reward function; meanwhile, the effectiveness of the process compensation instruction is verified by calling the digital twin model.

[0088] Further, the process compensation module M400 is further configured to perform the following method: If the simulation yield exceeds the preset lower limit of yield, the method is executed on a silicon carbide MOSFET device production line, otherwise a secondary optimization iteration is triggered.

[0089] Further, the process compensation module M400 is further configured to perform the following method: If the model test result of the N+ source region is abnormal, and the model test results of the N- epitaxial layer and the P well are normal, it is determined that the N+ source region doping causes the gate oxide quality to decrease; if the model test results of the N- epitaxial layer, the P well and the N+ source region are normal, and the model test result of the P well / N+ source region is abnormal, it is determined that the N+ source region doping causes the gate oxide quality to decrease.

[0090] In summary, any step can be stored in a computer memory without limitation as computer instructions or programs, and can be called and recognized by a computer processor without limitation, and no further limitation is made herein.

[0091] Further, the above technical solutions only represent preferred technical solutions of the technical solutions of the embodiments of the present application, and some changes made by the person skilled in the art to some parts of the embodiments of the present application all represent the principles of the novel embodiments of the present application. Obviously, the person skilled in the art can make various modifications and changes to the present application without departing from the scope of the present application.

Claims

1. A method for gate oxide process failure location optimization of a MOSFET, comprising: The method comprises: For silicon carbide MOSFET devices, obtain the C-V characteristic curve, I-V characteristic curve and trap charge relaxation characteristic data of the silicon carbide MOSFET gate oxide layer, and determine the key parameters of the gate oxide process including the equivalent oxide thickness, interface state density and threshold voltage drift; Based on the key parameters of the gate oxide process, a digital feature matrix of the gate oxide defect type is constructed, and correlation analysis is performed with the isolation oxide layer and the gate oxide test structure, a first defect recognition vector is set, and the gate oxide test structure includes N-epitaxial layer, P-well and N+ source region; Locate the potential fault source and the key sensitive parameters affecting the quality of the gate oxide, and perform correlation analysis with the isolation oxide process, the gate oxide process and the doping process to set the second defect recognition vector; According to the first defect recognition vector and the second defect recognition vector, the non-dominated solution set is generated, the process parameter combination with the widest process window is selected from the non-dominated solution set, and the process compensation instruction is issued.

2. The method of claim 1, wherein the method further comprises: determining a location of a defect in the gate oxide of the MOSFET based on the measured current and the measured voltage. For silicon carbide MOSFET devices, obtain the C-V characteristic curve, I-V characteristic curve and trap charge relaxation characteristic data of the silicon carbide MOSFET gate oxide layer, and the method comprises: Scan the silicon carbide MOSFET gate oxide layer to obtain the flat-band voltage offset and the equivalent oxide thickness of the C-V characteristic curve; Capture the subthreshold swing and threshold voltage drift of the I-V characteristic curve by applying a step pulse voltage through a pulse I-V test system; Obtain the relaxation time constant and concentration of trap charge, and determine the interface state density in combination with the interface state charge and gate voltage.

3. The method of claim 1, wherein the method further comprises: determining a location of a defect in the gate oxide of the MOSFET based on the measured capacitance and the measured resistance. Construct a digital feature matrix of the gate oxide defect type, and perform correlation analysis with the isolation oxide layer and the gate oxide test structure, the method comprising: Define the mapping relationship between the defect type and the structure parameter; According to the mapping relationship between the defect type and the structure parameter, extract the core features to construct the digital feature matrix of the gate oxide defect type.

4. The method of claim 3, wherein the step of determining the location of the defect in the gate oxide of the MOSFET is performed by: determining a first location of the defect in the gate oxide of the MOSFET; and determining a second location of the defect in the gate oxide of the MOSFET. The isolation oxide layer breakdown in the defect type corresponds to the sudden drop of high-frequency capacitance in the C-V characteristic curve and the detection of high-concentration deep-level traps by DLTS.

5. The method of claim 4, wherein the step of determining the location of the defect in the gate oxide of the MOSFET is performed by: determining a first location of the defect in the gate oxide of the MOSFET; and determining a second location of the defect in the gate oxide of the MOSFET. The gate oxide test structure includes N-epitaxial layer, P-well and N+ source region, wherein the N-epitaxial layer defect induction in the defect type is associated with the abnormal subthreshold swing of the I-V characteristic curve and the fluctuation of the epitaxial layer resistivity; The P-well / N+ source region interface recombination anomaly in the defect type corresponds to the sudden increase of interface state density and the hysteresis loop in the C-V characteristic curve.

6. The method of claim 1, wherein: Generate a non-dominated solution set, select the process parameter combination with the widest process window from the non-dominated solution set, and issue a process compensation instruction, the method comprising: According to the optimization target, establish a target function, perform multi-objective optimization, and generate a non-dominated solution set; Based on the non-dominated solution set, filter out the process parameter combination with a signal-to-noise ratio meeting a threshold value, and generate the process compensation instruction.

7. The method of claim 6, wherein the step of determining the location of the defect in the gate oxide of the MOSFET is performed by: determining a location of the defect in the gate oxide of the MOSFET based on the measured capacitance and the measured resistance. And issue the process compensation instruction, after that, the method further comprises: Construct a process compensation decision model, taking the defect type and the sensitive parameter as the state space, the parameter adjustment amplitude as the action space, and the yield improvement rate as the reward function; At the same time, call the digital twin model to verify the effectiveness of the process compensation instruction.

8. The method of claim 7, wherein the step of determining the location of the defect in the gate oxide of the MOSFET is performed by: The method comprises the following steps of: ​ If the simulation yield exceeds the preset lower limit of yield, the method is executed on a silicon carbide MOSFET device production line, otherwise a secondary optimization iteration is triggered.

9. The method of claim 8, wherein the step of determining the location of the defect in the gate oxide of the MOSFET is performed by: determining a location of the defect in the gate oxide of the MOSFET based on the measured capacitance and the measured resistance. The method further comprises the following steps of: If the model test result of the N+ source region is abnormal, and the model test results of the N- epitaxial layer and the P well are normal, the N+ source region doping is locked as the cause of the gate oxide quality degradation. If the model test results of the N- epitaxial layer, the P well and the N+ source region are normal, and the model test result of the P well / N+ source region is abnormal, the N+ source region doping is locked as the cause of the gate oxide quality degradation.

10. A system for gate oxide process failure location optimization of a MOSFET, comprising: A MOSFET gate oxide process fault positioning optimization method for implementing any one of claims 1-9, the system comprises: A data acquisition module is configured to acquire C-V characteristic curves, I-V characteristic curves and trap charge relaxation characteristic data of a silicon carbide MOSFET gate oxide layer of a silicon carbide MOSFET device, and determine gate oxide process key parameters including equivalent oxide thickness, interface state density and threshold voltage drift amount; A first correlation analysis module is configured to construct a digital feature matrix of gate oxide defect types based on the gate oxide process key parameters, perform correlation analysis on an isolation oxide layer and a gate oxide test structure, and set a first defect identification vector, wherein the gate oxide test structure comprises an N- epitaxial layer, a P well and an N+ source region; A second correlation analysis module is configured to locate a potential fault source and a key sensitive parameter affecting gate oxide quality, perform correlation analysis on an isolation oxide process, a gate oxide process and a doping process, and set a second defect identification vector; A process compensation module is configured to generate a non-dominated solution set based on the first defect identification vector and the second defect identification vector, with the optimization objectives of improving breakdown voltage, reducing interface state density and reducing threshold voltage drift, filter out a process parameter combination with the widest process window from the non-dominated solution set, and issue a process compensation instruction.

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