Stacking packaging method and system for AI-DSP mixed audio processing chip

Abstract

The invention relates to a stacking packaging method and system for AI-DSP mixed audio processing chips, and the method comprises the following steps: employing a first bonding machine to carry out the flip-chip bonding of an AI chip and a DSP chip, and obtaining a flip-chip bonding chip; the flip-chip bonding chips are interconnected, and an interconnected chip structure is obtained; vertically stacking the interconnected chip structures to obtain a stacked chip structure; packaging the stacked chip structure by adopting a second bonding machine to obtain a packaging body; according to the AI-DSP mixed audio processing chip and the packaging method thereof, the packaging body is subjected to heat dissipation treatment through the preset heat dissipation substrate, the packaged AI-DSP mixed audio processing chip is obtained, and the technical problems that in a traditional packaging scheme, an AI chip and a DSP chip generally adopt different process nodes and manufacturing processes, and thermal expansion coefficients are not matched and stress distribution is uneven during direct integration are solved.

Description

TECHNICAL FIELD

[0001] The application relates to the chip technical field, in particular to a stacking packaging method and system of an AI-DSP hybrid audio processing chip. BACKGROUND

[0002] With the deep integration of artificial intelligence and digital signal processing technology, AI-DSP hybrid audio processing chips have shown broad application prospects in intelligent voice devices, wearable electronic products, and vehicle audio systems. Such chips need to have strong AI computing power to support complex algorithms such as voice recognition and semantic understanding, as well as efficient DSP capabilities to realize real-time audio signal acquisition, filtering, and encoding and decoding.

[0003] However, under the existing technical conditions, the stacking packaging of AI-DSP hybrid chips still faces many challenges. First, AI chips and DSP chips usually use different process nodes and manufacturing processes. Direct integration may cause problems such as mismatched thermal expansion coefficients, uneven stress distribution, and micro-bump breakage or solder joint failure, affecting the reliability and yield of the chips. SUMMARY

[0004] The main purpose of the application is to provide a stacking packaging method of an AI-DSP hybrid audio processing chip, which solves the technical problem of mismatched thermal expansion coefficients and uneven stress distribution when AI chips and DSP chips are directly integrated in the traditional packaging scheme.

[0005] To achieve the above purpose, the application provides a stacking packaging method of an AI-DSP hybrid audio processing chip, comprising the following steps: using a first bonder to flip chip AI chips and DSP chips to obtain flip chip chips; interconnecting the flip chip chips to obtain an interconnected chip structure, wherein the interconnected chip structure comprises AI chips and DSP chips interconnected by a micro-bump array; vertically stacking the interconnected chip structure to obtain a stacked chip structure, wherein the stacked chip structure comprises AI chips and DSP chips vertically stacked by a high-density three-dimensional wiring structure; using a second bonder to package the stacked chip structure to obtain a package; performing heat dissipation treatment on the package by a pre-set heat dissipation substrate to obtain a packaged AI-DSP hybrid audio processing chip.

[0006] Further, the interconnecting the flip chip chips to obtain an interconnected chip structure comprises: Bond the flip-chip with a first group of micro-bumps to obtain a first bonding structure, and press the first bonding structure based on a hot-press process to obtain a press structure; Construct an interconnection path based on the press structure to obtain a path structure, and bond the AI chip and the DSP chip in the path structure with a second group of micro-bumps to obtain a second bonding structure; Perform a signal integrity test based on the second bonding structure to obtain a test result, and when the test result shows that the signal attenuation exceeds a preset threshold, perform a compensation bonding process on the second bonding structure based on the test result to obtain an interconnected chip structure.

[0007] Further, the interconnected chip structure is vertically stacked to obtain a stacked chip structure, comprising: The interconnected chip structure is pre-aligned using a micro-gap positioning technology, and the pre-aligned interconnected chip structure is routed to obtain a routing path scheme; The pre-aligned interconnected chip structure is routed based on the routing path scheme to obtain a routed chip structure, and the routed chip structure is tested for vertical stacking to obtain stacking test data; The routed chip structure is vertically stacked based on the stacking test data to obtain an initial stacked chip structure, and the stacked chip structure is bonded and fixed to obtain a stacked chip structure.

[0008] Further, the pre-aligned interconnected chip structure is routed based on the routing path scheme to obtain a routed chip structure, comprising: Measure the interlayer distance of the pre-aligned interconnected chip structure to obtain chip spacing data, and route the pre-aligned interconnected chip structure based on the routing path scheme and the chip spacing data to obtain an initial routing grid; Calculate the density distribution of the initial routing grid to obtain a grid density distribution map, and optimize the routing channel based on the grid density distribution map to obtain an optimized routing grid; Verify the connectivity of the optimized routing grid to obtain a connectivity verification result, and when the connectivity verification result shows that there is an open circuit or a short circuit phenomenon, adjust the routing path of the pre-aligned interconnected chip structure based on the connectivity verification result to obtain a routed chip structure.

[0009] Further, the pre-aligned interconnected chip structure is routed based on the routing path scheme and the chip spacing data to obtain an initial routing grid, comprising: performing interlayer alignment marking on the pre-aligned interconnection chip structure to obtain alignment marking data, and performing wiring starting point planning on the alignment marking data based on the wiring path scheme and the chip spacing data to obtain wiring starting point data; performing vertical channel planning on the pre-aligned interconnection chip structure based on the wiring starting point data to obtain a vertical channel planning graph, and performing horizontal channel expansion in the vertical channel planning graph to obtain horizontal channel data; performing channel width distribution on the horizontal channel data to obtain a channel width distribution graph, and performing channel spacing optimization based on the channel width distribution graph to obtain optimized channel data; generating a wiring grid based on the optimized channel data on the pre-aligned interconnection chip structure to obtain an initial wiring grid.

[0010] Further, the second bonding machine is used to package the stacked chip structure to obtain a package, comprising: performing pin distribution scanning on the stacked chip structure to obtain a pin distribution graph, and performing lead frame positioning based on the pin distribution graph to obtain a positioned lead frame structure; performing partition bonding on the positioned lead frame structure by the second bonding machine to obtain a preliminary packaging structure, and injecting epoxy resin into the preliminary packaging structure to obtain a resin packaging structure; performing vacuum defoaming treatment on the resin packaging structure to obtain a defoamed package, and processing the surface conductive adhesive layer of the defoamed package by ion cleaning technology to obtain a package.

[0011] Further, the package is subjected to heat dissipation treatment by a preset heat dissipation substrate to obtain a packaged AI-DSP hybrid audio processing chip, comprising: adhering and fixing the heat dissipation substrate and the package to obtain a fixed package, and filling the fixed package by using a preset thermal interface material to obtain a filled package, wherein the thermal interface material comprises heat-conducting silicone grease and heat-conducting gel; performing thermal reliability testing based on the filled package to obtain thermal reliability testing results, and optimizing the performance of the heat dissipation substrate according to the thermal reliability testing results to obtain a packaged AI-DSP hybrid audio processing chip.

[0012] The application also provides an AI-DSP hybrid audio processing chip stacking packaging system, comprising: a flip-chip module configured to use a first bonding machine to flip-chip AI chips and DSP chips to obtain flip-chip chips; An interconnection module is configured to interconnect the flip-chip to obtain an interconnected chip structure, wherein the interconnected chip structure comprises the AI chip and the DSP chip interconnected by the micro-bump array; A stacking module is configured to vertically stack the interconnected chip structure to obtain a stacked chip structure, wherein the stacked chip structure comprises the AI chip and the DSP chip vertically stacked by the high-density three-dimensional wiring structure; A packaging module is configured to package the stacked chip structure by using a second bonding machine to obtain a package body; A heat dissipation module is configured to perform heat dissipation processing on the package body by using a preset heat dissipation substrate to obtain the packaged AI-DSP hybrid audio processing chip.

[0013] The application further provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method according to any one of the preceding embodiments when executing the computer program.

[0014] The application further provides a computer readable storage medium, which stores a computer program, and the computer program implements the steps of the method according to any one of the preceding embodiments when executed by a processor.

[0015] The application provides an AI-DSP hybrid audio processing chip stacking and packaging method, which comprises the following steps: using a first bonding machine to perform flip-chip on an AI chip and a DSP chip to obtain a flip-chip; interconnecting the flip-chip to obtain an interconnected chip structure; vertically stacking the interconnected chip structure to obtain a stacked chip structure; using a second bonding machine to package the stacked chip structure to obtain a package body; and performing heat dissipation processing on the package body by using a preset heat dissipation substrate to obtain a packaged AI-DSP hybrid audio processing chip. The technical problem of the traditional packaging scheme that the AI chip and the DSP chip usually use different process nodes and manufacturing processes, and direct integration causes the mismatch of the thermal expansion coefficient and the uneven stress distribution is solved, and the yield and long-term working reliability of the multi-chip stacked structure are improved. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a step schematic diagram of the AI-DSP hybrid audio processing chip stacking and packaging method in an embodiment of the application; Figure 2 is a structural block diagram of an AI-DSP hybrid audio processing chip stacking and packaging system in an embodiment of the application; Figure 3 is a structural schematic block diagram of a computer device in an embodiment of the application.

[0017] The application objectives, functional features and advantages will be further described with reference to the embodiments and the accompanying drawings. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0019] like Figure 1 As shown, Figure 1 This invention provides a stacking and packaging method for an AI-DSP hybrid audio processing chip, comprising the following steps: Step S1: The AI ​​chip and DSP chip are flip-chip bonded using a first bonding machine to obtain a flip-chip bonded chip.

[0020] Specifically, the AI ​​chip and DSP chip are flip-chip bonded using a first bonding machine to obtain flip-chip bonded chips. This process is a crucial initial step in achieving high-density integration, ensuring that the AI ​​chip and DSP chip initially form a stable connection in terms of physical structure and electrical connection. In practice, the active surfaces of the AI ​​chip and DSP chip are placed downwards, and the pads are precisely aligned using the precision alignment system of the first bonding machine. Then, appropriate heat and pressure are applied to the pre-prepared microbumps on the chip pads, causing plastic deformation and achieving metal-to-metal bonding, thus completing the flip-chip bond connection. Since the AI ​​chip is typically responsible for performing high-computing tasks such as deep learning inference, while the DSP chip focuses on real-time audio signal acquisition and preprocessing, efficient interconnection between the two is crucial in applications such as intelligent voice assistants. The flip-chip bonding completed by the first bonding machine not only reduces the parasitic inductance and resistance caused by traditional wire interconnects but also significantly improves signal transmission speed and reliability, making data interaction between the AI ​​and DSP modules faster and more stable, laying a solid foundation for subsequent interconnection and stacking processes. For example, in a high-end smart speaker, this flip-chip bonding process ensures that the voice wake-up command, after being input from the microphone array, can be transmitted to the DSP for noise reduction and feature extraction with extremely low latency, and then quickly handed over to the AI ​​chip to complete semantic recognition, thereby improving the user experience.

[0021] Step S2: Interconnect the flip-chip to obtain an interconnect chip structure, wherein the interconnect chip structure includes an AI chip and a DSP chip interconnected by a microbump array.

[0022] Specifically, the flip-chip is interconnected to obtain an interconnected chip structure, wherein the interconnected chip structure comprises an AI chip and a DSP chip interconnected by a micro-bump array. This process is a key extension after the completion of flip-chip, aiming to further strengthen the signal path between the AI chip and the DSP chip through high-density electrical connection. In actual operation, first, the chip assembly after flip-chip completed by the first bonder is detected and calibrated to ensure that the relative position accuracy between the AI chip and the DSP chip meets the micron-level requirement, and then the gap between the chips is filled with underfill adhesive to enhance the mechanical stability and thermal stress buffering capacity. Next, an advanced photolithography and electroplating process is used to build a micro-bump array between the chip pads. These micro-bumps, usually composed of copper pillars combined with solder caps, have excellent electrical conductivity and thermal fatigue resistance, and can realize parallel connection of hundreds of I / O channels between the AI chip and the DSP chip. Since the pitch of the micro-bump array can be controlled below 50 microns, extremely high interconnection density is achieved in limited space, significantly reducing signal transmission delay and power consumption. In the application scenario of intelligent voice assistants, this interconnected structure composed of a micro-bump array can ensure the high-speed transmission of audio data from the real-time processing module of the DSP chip to the neural network operation unit of the AI chip. For example, when the user issues a "play music" instruction, after the DSP completes the acoustic front-end processing, the feature data is quickly transmitted to the AI for semantic analysis through the micro-bump array. The whole process is smooth and responsive, thereby improving the real-time interaction of the device and the user experience.

[0023] Step S3, vertically stacking the interconnected chip structure to obtain a stacked chip structure, wherein the stacked chip structure comprises an AI chip and a DSP chip vertically stacked by a high-density three-dimensional wiring structure.

[0024] Specifically, the interconnection chip structure is vertically stacked to obtain a stacked chip structure, wherein the stacked chip structure comprises AI chips and DSP chips vertically stacked through a high-density three-dimensional wiring structure, and this step is a key link for further improving the integration density and system performance on the basis of completing the micro-bump array interconnection. In the specific implementation process, first, the AI chip and the DSP chip combined body of the interconnection chip structure are subjected to surface treatment and alignment mark preparation, and then a high-precision stacking device is used to vertically align the same or complementary function interconnection chip structure to ensure the accurate matching of the micro-bump and pad positions between the upper and lower layers, and then temperature and pressure are applied to complete the interlayer bonding, thereby realizing the vertical integration of multiple layers of chips. In this structure, the high-density three-dimensional wiring structure is constructed through through-silicon via (TSV) or thin-film redistribution layer (RDL) technology, which can form dense electrical paths in the vertical direction, so that the upper AI chip and the lower DSP chip not only maintain the original in-plane interconnection, but also increase the signal and power connection channels across the layers, greatly improving the data throughput capacity and system bandwidth. Since this structure effectively shortens the signal transmission path and reduces the parasitic effect, it has significant advantages in application scenarios such as intelligent voice assistants that have extremely high real-time requirements, for example, when the device is in a continuous voice listening state, the DSP chip can transmit the pre-processed audio stream to the AI chip stacked above through the high-density three-dimensional wiring structure with low delay for context understanding and intent recognition, avoiding the delay and power consumption problems caused by long-distance wiring in traditional planar layout, thereby realizing a faster and more accurate voice response experience.

[0025] Step S4, using a second bonding machine to package the stacked chip structure to obtain a package.

[0026] Specifically, a second bonder is used to package the stacked chip structure to obtain a package, which is an important link for realizing chip external protection and system-level electrical connection after vertical stacking. In actual operation, the formed stacked chip structure is first fixed on a packaging substrate, which is pre-designed with a pad array matching the high-density three-dimensional wiring structure in the stacked chip structure. Then, the I / O ports of the stacked chip structure are reliably connected to the corresponding lines on the packaging substrate by wire bonding or thermal compression bonding through the high-precision motion platform and visual alignment system of the second bonder. The second bonder focuses more on the multi-point and large-area connection capability in the packaging stage than the first bonder, and can adapt to the height difference and complex wiring requirements brought by the stacked structure. In this process, not only the signal ports of the AI chip and the DSP chip are led out to the packaging substrate, but also the power supply, ground wire and high-speed differential pair key network realize impedance matching and electromagnetic compatibility control through optimized wiring, thereby forming a complete electrical path system. The packaging material is usually encapsulated with epoxy molding compound to provide mechanical support, moisture and corrosion resistance, and stress buffering function, and finally form a complete functional package. In the application scenario of intelligent voice assistants, the packaging process completed by the second bonder ensures that the stacked chip structure can stably communicate with the external mainboard. For example, when the user issues a voice command in a far-field environment, the processing results generated by the AI chip and the DSP chip working together inside the package can be quickly transmitted to the device main control unit through the package pins to realize accurate voice response and device control. At the same time, the reliability of the package ensures the stability and durability of the product in long-term operation.

[0027] Step S5, the packaged AI-DSP hybrid audio processing chip is obtained by heat dissipation treatment of the package through a preset heat dissipation substrate.

[0028] Specifically, the encapsulated AI-DSP hybrid audio processing chip is obtained by performing heat dissipation treatment on the package body through a preset heat dissipation substrate. This step is a key guarantee for heat management and long-term reliable operation after the package body is completed. In specific implementation, first, the packaged chip body that has been completed is inverted or fixed on a preset heat dissipation substrate with high thermal conductivity. The heat dissipation substrate is usually made of metal alloy (such as copper or aluminum) or high-thermal-conductivity ceramic material, and can be integrated with micro-channel or fin structure to enhance the heat dissipation efficiency. Then, the package body and the heat dissipation substrate are closely attached through a thermal interface material (TIM) such as thermal silicone grease or solder, so as to ensure that heat can be conducted from the working area of the AI chip and the DSP chip to the heat dissipation substrate layer by layer through the high-density three-dimensional wiring structure, the interconnection chip structure and the micro-bump array of the flip-chip bonding, thereby realizing efficient heat diffusion. Since the AI chip generates significant power consumption when performing complex operations such as speech recognition and natural language understanding, and the DSP chip also generates heat continuously during the continuous sampling and filtering process, the heat is easy to accumulate in the vertical stacked structure. Therefore, the preset heat dissipation substrate not only provides physical support, but also builds a low-thermal-resistance heat dissipation path, effectively inhibiting the rise of chip junction temperature. In the application scenario of intelligent voice assistants, for example, when the device runs in a high-temperature environment for a long time or continuously responds to multiple rounds of voice interaction, the heat dissipation mechanism can ensure that the AI-DSP hybrid audio processing chip maintains stable performance, avoids frequency reduction or misjudgment due to overheating, and thus ensures that user instructions are accurately recognized and executed, ultimately realizing high-performance and high-reliability terminal experience.

[0029] In specific embodiments, the interconnection of the flip-chip bonded chips to obtain an interconnection chip structure comprises: The first group of micro-bumps is used to bond the flip-chip bonded chips to obtain a first bonding structure, and the first bonding structure is compressed based on a thermal compression process to obtain a compression structure. Based on the compression structure, an interconnection path is constructed to obtain a via structure, and the second group of micro-bumps is used to bond the unbonded regions of the AI chip and the DSP chip in the via structure to obtain a second bonding structure. Based on the second bonding structure, a signal integrity test is performed to obtain a test result. When the test result shows that the signal attenuation exceeds a preset threshold, a compensation bonding process is performed on the second bonding structure based on the test result to obtain an interconnection chip structure.

[0030] Specifically, the flip-chip is interconnected to obtain an interconnection chip structure. This process is a key step to achieve high-density and high-reliability electrical interconnection based on the completion of AI chip and DSP chip flip-chip connection. The specific implementation includes multiple fine steps, aiming to ensure the integrity and stability of signal transmission between chips. First, a first group of micro-bumps is used to bond the flip-chip to obtain a first bonding structure. In this step, the first group of micro-bumps is usually distributed in the pad area corresponding to the key signal path or power / ground network between the AI chip and the DSP chip. By accurately controlling the height, diameter and material composition (such as copper column tinning) of the micro-bump, the initial bonding is completed with the assistance of the first bonding machine or special interconnection equipment, forming the initial electrical and mechanical connection. Then, the first bonding structure is pressed based on the hot pressing process to obtain a pressed structure. The hot pressing process under the combined action of heating (usually in the range of 200-250°C) and vertical pressure (several to several tens of kilograms of force) promotes the plastic deformation of the micro-bump and forms a firm intermetallic bond with the corresponding pad, while eliminating the interface gap and improving the connection reliability and thermal conductivity. After the formation of the pressed structure, interconnection paths can be constructed based on it to obtain a path structure. This step involves advanced packaging processes such as deposition of dielectric layer on the chip surface, lithography window opening, and electroplating to form redistribution layer (RDL) to extend and optimize the interconnection path between the AI chip and the DSP chip. Especially for high-frequency audio signals or differential pair lines, impedance matching design is performed to construct low-loss and low-crosstalk interconnection paths. Then, a second group of micro-bumps is used to bond the un-bonded areas of the AI chip and the DSP chip in the path structure to obtain a second bonding structure. The second group of micro-bumps is mainly used to connect the I / O ports or auxiliary signal lines that are not covered in the first bonding, such as clock synchronization signals, interrupt request lines or debugging interfaces. Through supplementary bonding, full-function interconnection is realized, further improving system integration and communication bandwidth. After that, signal integrity testing is performed based on the second bonding structure to obtain test results. During the testing process, high-frequency probe station and vector network analyzer are used to scan the S parameters of the key signal path to evaluate its insertion loss, return loss and group delay. When the test results show that the signal attenuation exceeds the preset threshold, it indicates that there are problems such as impedance discontinuity, high contact resistance or micro-bump virtual welding in some paths. At this time, compensation bonding of the second bonding structure is needed based on the test results, that is, auxiliary bumps are added beside the original micro-bumps or the abnormal areas are re-pressed to enhance the electrical connection quality, finally obtaining a complete and reliable interconnection chip structure.In practical application scenarios of intelligent voice assistants, for example, when the device is in a continuous wake-up listening state, the DSP chip needs to process the raw audio stream of multi-channel microphone input in real time, and quickly transfer the feature data to the AI chip for semantic recognition through the high-density micro-bump array in the interconnection chip structure. If there is signal attenuation or time delay jitter in the interconnection path, it may cause voice recognition errors or response delays. Through the complete process of the above step-by-step bonding, pressing, path construction and compensation processing, the data link between the AI chip and the DSP chip can ensure excellent signal integrity, so as to ensure that the user's "play music" or "set alarm" instructions in a complex acoustic environment can be accurately captured and analyzed, significantly improving the product's interaction experience and running stability.

[0031] In specific embodiments, the vertically stacking the interconnection chip structure obtains a stacked chip structure, including: The micro-gap positioning technology is used to pre-align the interconnection chip structure, and the pre-aligned interconnection chip structure is subjected to wiring path planning to obtain a wiring path scheme; Based on the wiring path scheme, the pre-aligned interconnection chip structure is subjected to three-dimensional wiring to obtain a wired chip structure, and the wired chip structure is subjected to vertical stacking test to obtain stacking test data; Based on the stacking test data, the wired chip structure is subjected to vertical stacking to obtain an initial stacked chip structure, and the stacked chip structure is bonded and fixed to obtain a stacked chip structure.

[0032] Specifically, the interconnection chip structure is vertically stacked to obtain a stacked chip structure, which is a key process for three-dimensional integration based on high-density interconnection between the AI chip and the DSP chip, and aims to significantly improve system integration, shorten signal transmission path and enhance overall performance through vertical chip stacking. In the specific implementation process, first, the micro-gap positioning technology is used for pre-alignment of the interconnection chip structure. This technology uses a high-resolution optical alignment system and a micron-level motion control platform to perform preliminary position correction on the upper and lower interconnection chip structures in a vacuum or inert gas environment, ensuring that the deviation in X, Y and Z directions is within a few microns. Special attention is paid to the correspondence between the micro-bump arrays of the AI chip and the DSP chip to avoid misalignment leading to connection failure. After pre-alignment, the pre-aligned interconnection chip structure is then routed to obtain a routing path scheme, which includes a three-dimensional routing path for vertical stacking of the interconnection chip structure. This planning process relies on EDA tools to model and analyze the chip stacking configuration, considering power distribution, signal integrity, thermal stress distribution and process feasibility to design the optimal TSV position, RDL trace path and interlayer interconnection point layout, ensuring that the electrical paths in the vertical direction are dense and do not interfere with each other. Based on the routing path scheme, the pre-aligned interconnection chip structure is routed in three dimensions to obtain a routed chip structure. This process typically involves deep silicon etching, insulation layer deposition, TSV copper filling, chemical mechanical polishing (CMP) and multi-layer RDL construction, forming a high-density three-dimensional routing structure through the chip body, so that the output signal of the upper AI chip can be directly connected to the input port of the lower DSP chip through the vertical channel, greatly reducing interconnection delay and power consumption. Subsequently, the routed chip structure is tested for vertical stacking to obtain stacking test data, which includes mechanical stability evaluation, interlayer resistance measurement, capacitance coupling detection and preliminary on-off test to verify the quality of three-dimensional routing and stacking feasibility. If abnormal path impedance or short circuit risk is found, the process parameters can be corrected in advance. Based on the stacking test data, the structure is confirmed to be reliable, and the routed chip structure is vertically stacked to obtain an initial stacked chip structure. This process is completed by a high-precision chip mounter in a clean room environment, and the interconnection chip structure is stacked in the predetermined order layer by layer, and a heat-conducting adhesive is applied between each layer to assist heat dissipation. Finally, the stacked chip structure is bonded and fixed by thermal compression bonding or low-temperature solder bonding, forming a firm connection between the micro-bumps and pads of each layer, while ensuring the continuity of the three-dimensional routing path formed by the TSV and RDL, and finally forming a stable and reliable stacked chip structure.In the application scenario of intelligent voice assistants, for example, when the user successively issues multiple rounds of instructions such as "turn on the living room light" and "turn up the volume", the DSP chip needs to continuously collect and preprocess audio signals, and the AI chip needs to run a voice recognition model in real time. Both of them achieve millisecond-level data exchange through the high-density three-dimensional wiring path in the vertical stacking structure described above, avoiding the delay and noise interference caused by long-distance wiring in traditional planar packaging, thereby ensuring rapid response and accurate recognition of the device, and significantly improving user experience and overall system performance.

[0033] In specific embodiments, the three-dimensional wiring of the pre-aligned interconnection chip structure based on the wiring path scheme obtains a wired chip structure, including: Measuring the interlayer distance of the pre-aligned interconnection chip structure obtains chip spacing data, and based on the wiring path scheme and the chip spacing data, a wiring planning is performed on the pre-aligned interconnection chip structure to obtain an initial wiring grid; Calculating the density distribution of the initial wiring grid obtains a grid density distribution map, and based on the grid density distribution map, a wiring channel optimization is performed to obtain an optimized wiring grid; The optimized wiring grid is subjected to channel connectivity verification to obtain a connectivity verification result. When the connectivity verification result shows that there is an open circuit or a short circuit phenomenon, the pre-aligned interconnection chip structure is subjected to wiring path adjustment based on the connectivity verification result to obtain a wired chip structure, wherein the adjusted wiring structure includes a complete three-dimensional wire connection path.

[0034] Specifically, the pre-aligned interconnection chip structure is routed in three dimensions based on the routing path scheme to obtain a routed chip structure, which is a core process step for realizing high-density and high-reliability electrical connection of the AI chip and the DSP chip in the vertical direction. The purpose is to build a complete and optimized three-dimensional wire connection path to support subsequent vertical stacking and system-level function implementation. In the specific implementation process, first, the interlayer distance of the pre-aligned interconnection chip structure is measured to obtain chip spacing data. This step usually uses a non-contact optical interferometer or a confocal microscope to measure the physical gap between the upper and lower chips with high precision, ensuring that the obtained chip spacing data accurately reflects the actual pre-stacking space state. This data is crucial for subsequent routing design, because too small spacing may cause routing channel compression and insulation layer damage, while too large spacing may increase interconnection resistance and signal delay. Subsequently, routing planning is performed on the pre-aligned interconnection chip structure based on the routing path scheme and the chip spacing data to obtain an initial routing grid. The initial routing grid not only includes the layout of the horizontal wires, but more importantly, it includes three-dimensional coordinate information of the vertical interconnection channels, such as the position, depth, diameter of the through-silicon via (TSV), and its correspondence with the upper AI chip and lower DSP chip pads. These coordinate information is generated by EDA software modeling to form a preliminary three-dimensional interconnection topology, providing a geometric framework for subsequent fine routing. On this basis, the density distribution of the initial routing grid is further calculated to obtain a grid density distribution map. This map shows the routing density of different regions in the form of a heat map or a numerical matrix, identifying congested or sparse areas, and then optimizing the routing channel based on the grid density distribution map to obtain an optimized routing grid. The optimization process includes adjusting the TSV arrangement density, redistributing the RDL (redistribution layer) wire path, introducing multi-layer interposer or fan-out structure to relieve local congestion, thereby improving overall routing uniformity and signal transmission efficiency. After optimization, the optimized routing grid needs to be verified for channel connectivity to obtain a connectivity verification result. This verification usually simulates the current path through electrical test probes or simulation software to check for open circuits (i.e., a signal path that is not connected) or short circuits (i.e., unintended connection between adjacent lines). If the verification result shows defects, the pre-aligned interconnection chip structure must be adjusted based on the connectivity verification result, such as redesigning the TSV position in a certain area, adding redundant vias, or modifying the RDL layer stacking order to ensure complete connection of all signal, power, and ground paths. The finally formed routed chip structure not only has a complete three-dimensional wire connection path, but also achieves an optimal balance in electrical performance, thermal management, and mechanical stability.In the application scenario of intelligent voice assistants, for example, when the device is in a far-field voice recognition mode, the DSP chip needs to process audio signals from multiple microphones in real time and perform beamforming, and then transmit the processed data to the AI chip through an optimized three-dimensional wiring structure at high speed for wake-up word detection and natural language understanding. If there is a break in the wiring path or signal crosstalk in high-density areas, it will cause voice recognition failure or response delay. Through the above whole-process control based on chip distance measurement, wiring grid optimization and connectivity verification, the data channel between the AI chip and the DSP chip can be ensured to be stable and reliable, so as to ensure that the user's "Hey, little art" and other wake-up instructions in a noisy environment can be accurately captured and responded to, significantly improving the practicality and user experience of the product.

[0035] In specific embodiments, the wiring planning based on the wiring path scheme and the chip distance data is performed on the pre-aligned interconnection chip structure to obtain an initial wiring grid, including: Interlayer alignment marks are made on the pre-aligned interconnection chip structure to obtain alignment mark data, and wiring start point planning is performed on the alignment mark data based on the wiring path scheme and the chip distance data to obtain wiring start point data; Vertical channel planning is performed on the pre-aligned interconnection chip structure through the wiring start point data to obtain a vertical channel planning map, and horizontal channel expansion is performed in the vertical channel planning map to obtain horizontal channel data; Channel width distribution is performed on the horizontal channel data to obtain a channel width distribution map, and inter-channel distance optimization is performed based on the channel width distribution map to obtain optimized channel data; Based on the optimized channel data, a wiring grid is generated for the pre-aligned interconnection chip structure to obtain an initial wiring grid.

[0036] Specifically, the pre-aligned interconnection chip structure is routed and planned based on the routing path scheme and the chip spacing data to obtain an initial routing grid, which is a key design link to realize a high-density three-dimensional interconnection structure. This process ensures the electrical connection integrity between the AI chip and the DSP chip, while taking into account the process feasibility and signal transmission performance. In specific implementation, first, interlayer alignment marks are made on the pre-aligned interconnection chip structure, i.e., optical or electron beam recognizable alignment mark patterns are pre-made on the edges or non-functional areas of the AI chip and the DSP chip. The position information of these marks is collected by a high-precision imaging system to obtain alignment mark data, which reflects the relative offset and rotation angle of the upper and lower chips in the X, Y and Z directions, and provides a reference basis for the accurate positioning of the subsequent routing starting point. Subsequently, the routing starting point data is obtained by planning the routing starting point based on the interconnection topology defined in the routing path scheme and the chip spacing data obtained by the foregoing measurement, combined with the alignment mark data. This step maps the theoretically designed routing path to the actual chip physical position, determines the starting access point of each vertical interconnection channel on the bottom DSP chip pad, and ensures that the routing path can accurately connect the micro-bump array and the TSV entrance. On this basis, the vertical channel planning is performed on the pre-aligned interconnection chip structure based on the routing starting point data to generate a vertical channel planning graph, which details the positions, depths, diameters of all through-silicon vias (TSVs) and their corresponding relationships with the functional units of the upper and lower chips, forming a vertical electrical path skeleton from the DSP chip to the AI chip. Then, the horizontal channel extension is performed based on the vertical channel planning graph, i.e., a redistribution layer (RDL) is designed on the surface of each chip layer to extend the terminal of the vertical channel to the input / output ports of each functional module of the AI chip or the DSP chip, thereby obtaining horizontal channel data, which includes key information such as routing path, corner design, and interlayer via position. Subsequently, the channel width allocation is performed on the horizontal channel data, different wire widths are set according to the signal type (such as high-frequency clock, large-current power line or sensitive analog signal), and a channel width allocation graph is generated to meet the impedance matching, current carrying capacity and heat dissipation requirements. Based on the allocation graph, further channel spacing optimization is performed to avoid crosstalk or electromigration problems between adjacent wires due to too small spacing. Finally, the initial routing grid is obtained by generating a routing grid based on the optimized channel data on the pre-aligned interconnection chip structure. The grid not only contains the optimized vertical channel and horizontal channel layout, but also integrates the three-dimensional coordinate information of all connection points, forming a complete three-dimensional interconnection topology structure.In the application scenarios of intelligent voice assistants, for example, when the device performs a continuous speech recognition task, the DSP chip needs to quickly deliver multi-channel audio sampling data to the neural network acceleration unit of the AI chip through the vertical channels in the initial wiring grid. If the wiring starting point deviates or the channel spacing is unreasonable, it will cause data delay or error code. Through the above fine wiring planning process, efficient and stable transmission of signals between the AI chip and the DSP chip can be ensured, so as to ensure that the complex instructions such as "play Jay Chou's songs" issued by the user can be accurately analyzed and executed, and the response speed and recognition accuracy of the product can be significantly improved.

[0037] In specific embodiments, the vertical channel planning of the pre-aligned interconnection chip structure by the wiring starting point data includes: The wiring starting point data is identified for interlayer connection points to obtain a connection point distribution map, and the pre-aligned interconnection chip structure is determined for channel position based on the connection point distribution map to obtain channel position data; The pre-aligned interconnection chip structure is planned for a through-layer path based on the channel position data to obtain a through-layer path set, and the through-layer path set is analyzed for interconnection avoidance to obtain an avoidance area map; The avoidance area map is calculated for channel density to obtain a channel density distribution map, and the through-layer path set is adjusted for channel density based on the channel density distribution map to obtain an adjusted channel layout; The pre-aligned interconnection chip structure is drawn for vertical channels based on the adjusted channel layout to obtain a vertical channel planning map.

[0038] Specifically, the vertical channel planning of the pre-aligned interconnection chip structure is performed by the wiring starting point data to obtain a vertical channel planning map, which is a key design step in constructing a three-dimensional interconnection architecture of an AI-DSP hybrid audio processing chip. The purpose is to optimize the wiring layout in the vertical direction while ensuring the accuracy of electrical connection, so as to meet the system requirements of high density, high bandwidth and high reliability. In the specific implementation process, first, the interlayer connection point of the wiring starting point data is identified, that is, according to the wiring starting point data obtained in the early stage, the starting pad position corresponding to each functional signal needing to be connected from the lower DSP chip to the upper AI chip is identified, and visual labeling is performed in the three-dimensional modeling software, so as to obtain a connection point distribution map. This map clearly shows the spatial distribution of all input and output nodes of the vertical path to be established on the chip plane. Subsequently, based on the connection point distribution map, the channel position of the pre-aligned interconnection chip structure is determined, considering the layout of the micro-bump array, the TSV (through silicon via) process window and the sensitive area (such as analog circuit module or high-Q inductor) inside the chip, excluding the non-wirable area, and finally determining the specific coordinate position of each vertical channel in the X-Y plane to form accurate channel position data, providing a geometric reference for subsequent path planning. On this basis, based on the channel position data, the through-layer path planning of the pre-aligned interconnection chip structure is performed, and the EDA tool is used to automatically generate a complete set of through-layer paths from the functional unit of the DSP chip through the interlayer or redistribution layer to the corresponding input end of the AI chip. These paths not only include power lines, ground lines and high-speed differential pairs, but also cover control signals and clock lines, forming a complete electrical interconnection network. Then, the interconnection avoidance analysis of the through-layer path set is performed, the path area that may conflict with the existing metal layer, via, device structure or heat-sensitive area is identified, and an avoidance area map is generated to avoid short circuit, open circuit or thermal stress concentration in the subsequent manufacturing process. Then, the channel density calculation of the avoidance area map is performed to count the number of vertical channels in a unit area to obtain a channel density distribution map. This map reveals the congestion and sparseness of the wiring area, and then guides the designer to adjust the channel density of the through-layer path set, realizes the balanced allocation of wiring resources through local path offset, TSV reuse or adding redundant vias, and obtains the adjusted channel layout, which effectively reduces the signal crosstalk and electromigration risk. Finally, based on the adjusted channel layout, the vertical channel drawing of the pre-aligned interconnection chip structure is performed, and the optimized path is output in the standard GDS or ODB++ format to form the final vertical channel planning map. This map not only contains the three-dimensional coordinate information of all through-layer paths, but also marks the attributes (such as signal type, impedance requirement, current level) of each channel, providing accurate guidance for subsequent photolithography, etching and metal filling processes.In the application scenario of intelligent voice assistants, for example, when the device performs a far-field voice wake-up task, the DSP chip needs to quickly transmit the raw audio data collected by multiple microphones to the AI chip through a vertical channel for neural network inference. If the channel layout is unreasonable, it will cause delay or crosstalk, which will affect the recognition accuracy of commands such as "Hey, Xia Yi". Through the whole process planning method from the connection point identification to the channel drawing as described above, the data path between the AI chip and the DSP chip can have the optimal electrical performance and structural reliability, thereby ensuring the stable operation and high response speed of the voice interaction system in a complex acoustic environment.

[0039] In specific embodiments, the encapsulating the stacked chip structure by the second bonder to obtain an encapsulated body comprises: performing pin distribution scanning on the stacked chip structure to obtain a pin distribution map, and positioning a lead frame based on the pin distribution map to obtain a positioned lead frame structure; performing partition bonding on the positioned lead frame structure by the second bonder to obtain a preliminary encapsulated structure, and injecting epoxy resin into the preliminary encapsulated structure to obtain a resin encapsulated structure; performing vacuum debubbling treatment on the resin encapsulated structure to obtain a debubbled encapsulated body, and treating a surface conductive adhesive layer of the debubbled encapsulated body by ion cleaning technology to obtain an encapsulated body.

[0040] Specifically, the second bonding machine is used to package the stacked chip structure to obtain a package, which is a key process stage for realizing external electrical connection, mechanical protection and environmental isolation after the vertical stacking and bonding fixation of the AI chip and the DSP chip. The core goal is to convert the highly integrated stacked chip structure into an independent functional module that can be assembled, tested and stably operated for a long time. In the specific implementation process, first, the pin distribution of the stacked chip structure is scanned, and the position of all I / O pads to be extracted, the power ground network distribution and the signal type information in the stacked chip structure are accurately obtained by using high-resolution X-ray imaging or laser scanning confocal microscopy, so as to obtain a pin distribution map. The map not only reflects the electrical interface layout inside the chip, but also provides a physical basis for subsequent package structure design. Based on the pin distribution map, the lead frame is positioned, the lead frame with multiple metal lead layers and chip fixing area is selected, and the lead frame is matched with the stacked chip structure through a precision alignment system to ensure that the signal ports of each AI chip and DSP chip can be accurately corresponded to the metal traces on the lead frame. Finally, the positioned lead frame structure is obtained, which not only bears the mechanical support function, but also constitutes the primary electrical bridge between the external circuit and the internal chip. Subsequently, the positioned lead frame structure is partitioned and bonded by the second bonding machine. The second bonding machine has multi-axis motion control, automatic recognition and pressure regulation capabilities, and can complete lead bonding or flip-chip connection in sequence according to the preset program. Especially for high-frequency signal lines, low-arc gold or copper wires are used to reduce inductance, and for large current paths, thick wires or multiple parallel wires are used to improve current carrying capacity, thereby forming a preliminary package structure with complete electrical connection and high reliability. On this basis, epoxy resin is injected into the preliminary package structure, and a molding or dispensing process is used to fill the gap between the chip and the lead frame with resin. After curing, a resin package structure is formed, which includes multiple resin protection layers to resist moisture, dust and mechanical impact, while retaining the lead connection area for subsequent testing and welding. To further improve the packaging quality, the resin package structure is subjected to vacuum degassing treatment. By applying negative pressure in a sealed chamber, the internal bubbles of the resin are effectively removed, preventing local thermal resistance from rising or insulation performance from decreasing due to bubbles. A degassed package is obtained. Finally, the surface conductive adhesive layer of the degassed package is treated by ion cleaning technology. Argon ions or oxygen ions are used to bombard the surface to remove organic contaminants and oxides, enhance the adhesion of the outer layer material, and prepare for subsequent coating of the outer protective coating and stress release layer. Finally, a complete package is obtained, which not only has excellent electrical performance and environmental resistance, but also effectively relieves the mechanical stress caused by the mismatch of the thermal expansion coefficient.In the application scenario of intelligent voice assistants, for example, when the device is running for a long time in a high-temperature and high-humidity environment, the DSP chip continuously collects environmental sounds and hands them over to the AI chip for semantic analysis. If there are bubbles or interface pollution in the package, it may cause signal interruption or chip failure. However, through the above full-process packaging process of pin scanning, lead frame positioning, partition bonding, resin packaging and ion cleaning, the AI-DSP hybrid audio processing chip can still work stably under complex working conditions, thereby ensuring that user commands such as "wake me up at 7 am tomorrow morning" are accurately recognized and executed, and significantly improving product reliability and user experience.

[0041] In specific embodiments, the heat dissipation substrate is bonded and fixed to the package to obtain a fixed package, and a predetermined thermal interface material is used to fill the fixed package to obtain a filled package. The heat dissipation substrate is bonded and fixed to the package to obtain a fixed package, and a predetermined thermal interface material is used to fill the fixed package to obtain a filled package. The filled package is subjected to a thermal reliability test to obtain a thermal reliability test result, and the heat dissipation substrate is optimized in performance based on the thermal reliability test result to obtain the packaged AI-DSP hybrid audio processing chip.

[0042] Specifically, the encapsulated AI-DSP hybrid audio processing chip is obtained by heat dissipation treatment of the package body by a preset heat dissipation substrate. This step is a key thermal management link to ensure stable operation of the chip under high load working conditions after the package body is manufactured. The core is to build an efficient and low thermal resistance heat dissipation path to cope with the high power heat generated by the AI chip when executing complex speech recognition algorithms and the heat energy accumulated by the DSP chip in the continuous audio sampling and processing process. In the specific implementation process, first, the heat dissipation substrate is fixedly connected with the package body to obtain a fixed package body. The heat dissipation substrate is usually made of high thermal conductivity metal (such as copper or aluminum alloy) or advanced composite material (such as diamond-copper composite), has excellent heat diffusion capacity, and its surface is precisely processed to ensure the high flatness of the contact surface with the back of the package body, thereby improving the adhesion. The adhesion process adopts a structure glue or solder with high temperature resistance and low thermal resistance to realize firm combination under pressure and temperature control, and ensure mechanical stability and long-term reliability. Subsequently, the fixed package body is filled with a preset thermal interface material to obtain a filled package body. The thermal interface material includes thermal conductive silicone grease and thermal conductive gel, etc. Its role is to fill the air gap between the heat dissipation substrate and the package body caused by micro roughness. Because air is a poor conductor of heat, if it is not excluded, the interface thermal resistance will be significantly increased. The thermal conductive silicone grease has good filling property and moderate viscosity, and is suitable for large-area coating of flat contact surfaces. The thermal conductive gel has certain fluidity and elasticity, can maintain stable contact in temperature cycles, and effectively relieves stress fatigue caused by mismatch of thermal expansion coefficients. After filling is completed, the whole heat conduction path starts from the junction area of the AI chip and the DSP chip, passes through the high-density three-dimensional wiring structure inside the chip, the micro bump array in the interconnection chip structure, the package substrate, the epoxy resin layer, and finally conducts to the back of the package body, and is efficiently transferred to the heat dissipation substrate through the thermal interface material, realizing rapid lateral diffusion of heat and cooperative heat dissipation of the external heat sink. To further verify the effectiveness of the heat dissipation design, a thermal reliability test is performed based on the filled package body to obtain a thermal reliability test result. The test is usually performed for a long time in a high temperature working environment (such as 85°C or higher), and the infrared thermal imaging technology is used to monitor the temperature distribution of the chip surface in real time to evaluate the temperature rise and thermal stability of the chip under full load speech processing task. If the test result shows that the local hotspot temperature is too high or the thermal resistance is too large, the performance of the heat dissipation substrate is optimized according to the thermal reliability test result, for example, the fin structure is increased to increase the surface area, the micro flow channel is introduced to realize liquid cooling assistance, or the thickness and composition of the thermal interface material are adjusted to further reduce the interface thermal resistance, and finally the encapsulated AI-DSP hybrid audio processing chip is obtained. The chip not only includes the package body subjected to heat dissipation treatment by the heat dissipation substrate, but also realizes the best balance among performance, power consumption and reliability.In the application scenarios of intelligent voice assistants, for example, when the device continuously responds to multiple rounds of voice instructions or runs in a high-temperature vehicle environment, the AI chip frequently calls deep neural network models for semantic understanding, generating significant heat, which, if not promptly dissipated, will cause the chip to reduce frequency or even crash; and through the complete process of the above bonding and fixing, thermal interface material filling and thermal reliability testing optimization, the chip temperature can be ensured to be always within a safe range, thereby ensuring that the user's "navigate to the nearest gas station" and other key instructions are quickly responded to and executed, greatly improving the stability and user experience of the product in real use environment.

[0043] The above describes the packaging method of the AI-DSP hybrid audio processing chip in the embodiment of the application, and the packaging system of the AI-DSP hybrid audio processing chip in the embodiment of the application is described below. Please refer to Figure 2 The packaging system of the AI-DSP hybrid audio processing chip in the embodiment of the application includes one embodiment: The flip-chip module 21 is configured to flip-chip the AI chip and the DSP chip by using a first bonder to obtain a flip-chip structure. The interconnection module 22 is configured to interconnect the flip-chip structure to obtain an interconnected chip structure, wherein the interconnected chip structure includes the AI chip and the DSP chip interconnected by a micro-bump array. The stacking module 23 is configured to vertically stack the interconnected chip structure to obtain a stacked chip structure, wherein the stacked chip structure includes the AI chip and the DSP chip vertically stacked by a high-density three-dimensional wiring structure. The packaging module 24 is configured to package the stacked chip structure by using a second bonder to obtain a package. The heat dissipation module 25 is configured to perform heat dissipation treatment on the package by using a preset heat dissipation substrate to obtain a packaged AI-DSP hybrid audio processing chip.

[0044] In this embodiment, the specific implementation of each unit in the system embodiment described above can refer to the description in the method embodiment described above, and will not be repeated here.

[0045] Referring to Figure 3 In the embodiment of the application, a computer device is also provided, and the internal structure of the computer device can be as Figure 3The computer device includes a processor, a memory, a display screen, an input device, a network interface and a database connected through a system bus. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium. The database of the computer device is configured to store corresponding data in the embodiment. The network interface of the computer device is configured to communicate with an external terminal through a network connection. The computer program is executed by the processor to implement the above method.

[0046] Those skilled in the art can understand that, Figure 3 The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied.

[0047] The embodiment of the present application also provides a computer readable storage medium, which stores a computer program. The computer program is executed by the processor to implement the above method. It can be understood that the computer readable storage medium in the embodiment can be a volatile readable storage medium or a non-volatile readable storage medium.

[0048] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiment method. Any reference to the memory, storage, database or other medium provided by the present application and used in the embodiment can include non-volatile and / or volatile memory. The non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. The volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM) and memory bus dynamic RAM, etc.

[0049] It is to be understood that the terminology "including", "comprising", or any other variation thereof, is intended to cover a non-exclusive inclusion such that process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises a... " does not, without more constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0050] The preferred embodiments of the present application have been described above with the specific language and / or illustrative examples, but it should be understood that the patent protection is not limited to the specific embodiments and / or examples described herein, but it should be understood that all equivalents developed by one skilled in the art that are within the scope of the present application are to be included as further embodiments of the present application.

Claims

1. A stacked packaging method of an AI-DSP hybrid audio processing chip, characterized in that, The method comprises the following steps: adopting a first bonding machine to flip-chip AI chips and DSP chips to obtain flip-chip chips; interconnecting the flip-chip chips to obtain an interconnected chip structure, wherein the interconnected chip structure comprises AI chips and DSP chips interconnected by a micro-bump array; vertically stacking the interconnected chip structure to obtain a stacked chip structure, wherein the stacked chip structure comprises AI chips and DSP chips vertically stacked by a high-density three-dimensional wiring structure; adopting a second bonding machine to package the stacked chip structure to obtain a package; performing heat dissipation treatment on the package by a preset heat dissipation substrate to obtain a packaged AI-DSP hybrid audio processing chip.

2. The package-on-package method of an AI-DSP hybrid audio processing chip according to claim 1, wherein, The interconnecting the flip-chip chips to obtain an interconnected chip structure comprises: bonding the flip-chip chips by a first group of micro-bumps to obtain a first bonding structure, and pressing the first bonding structure based on a hot-pressing process to obtain a pressed structure; constructing an interconnection path based on the pressed structure to obtain a path structure, and bonding the un-bonded regions of AI chips and DSP chips in the path structure by a second group of micro-bumps to obtain a second bonding structure; performing a signal integrity test based on the second bonding structure to obtain a test result, and when the test result shows that the signal attenuation exceeds a preset threshold, performing a compensatory bonding process on the second bonding structure based on the test result to obtain an interconnected chip structure.

3. The package-on-package method of an AI-DSP hybrid audio processing chip according to claim 1, wherein, The vertically stacking the interconnected chip structure to obtain a stacked chip structure comprises: performing pre-alignment on the interconnected chip structure by a micro-gap positioning technology, and planning a wiring path for the pre-aligned interconnected chip structure to obtain a wiring path scheme; performing three-dimensional wiring on the pre-aligned interconnected chip structure based on the wiring path scheme to obtain a wired chip structure, and performing a vertical stacking test on the wired chip structure to obtain stacking test data; vertically stacking the wired chip structure based on the stacking test data to obtain an initial stacked chip structure, and bonding and fixing the stacked chip structure to obtain a stacked chip structure.

4. The package-on-package method of an AI-DSP hybrid audio processing chip according to claim 3, wherein, The performing three-dimensional wiring on the pre-aligned interconnected chip structure based on the wiring path scheme to obtain a wired chip structure comprises: measuring the interlayer distance of the pre-aligned interconnected chip structure to obtain chip spacing data, and planning a wiring for the pre-aligned interconnected chip structure based on the wiring path scheme and the chip spacing data to obtain an initial wiring grid; calculating the density distribution of the initial wiring grid to obtain a grid density distribution map, and optimizing the wiring channel based on the grid density distribution map to obtain an optimized wiring grid; verifying the channel connectivity of the optimized wiring grid to obtain a connectivity verification result, and when the connectivity verification result shows that there is an open circuit or a short circuit phenomenon, adjusting the wiring path of the pre-aligned interconnected chip structure based on the connectivity verification result to obtain a wired chip structure.

5. The package-on-package method of an AI-DSP hybrid audio processing chip according to claim 4, wherein, The pre-aligned interconnection chip structure is routed based on the routing path scheme and the chip spacing data to obtain an initial routing grid, including: The pre-aligned interconnection chip structure is marked with interlayer alignment marks to obtain alignment mark data, and the alignment mark data is routed based on the routing path scheme and the chip spacing data to obtain routing start point data; The pre-aligned interconnection chip structure is routed based on the routing path scheme and the chip spacing data to obtain an initial routing grid, including: The pre-aligned interconnection chip structure is marked with interlayer alignment marks to obtain alignment mark data, and the alignment mark data is routed based on the routing path scheme and the chip spacing data to obtain routing start point data; The pre-aligned interconnection chip structure is routed based on the routing path scheme and the chip spacing data to obtain an initial routing grid, including:

6. The package-on-package method of an AI-DSP hybrid audio processing chip according to claim 1, wherein, The pre-aligned interconnection chip structure is marked with interlayer alignment marks to obtain alignment mark data, and the alignment mark data is routed based on the routing path scheme and the chip spacing data to obtain routing start point data; The stack chip structure is encapsulated by the second bonder to obtain an encapsulated body, including: The pin distribution of the stack chip structure is scanned to obtain a pin distribution map, and the lead frame is positioned based on the pin distribution map to obtain a positioned lead frame structure; The positioned lead frame structure is bonded by the second bonder to obtain a preliminary encapsulated structure, and epoxy resin is injected into the preliminary encapsulated structure to obtain a resin encapsulated structure; 7. The package-on-package method of an AI-DSP hybrid audio processing chip according to claim 1, wherein, The resin encapsulated structure is subjected to vacuum degassing treatment to obtain a degassed encapsulated body, and the surface conductive adhesive layer of the degassed encapsulated body is treated by ion cleaning technology to obtain an encapsulated body. The encapsulated body is subjected to heat dissipation treatment by a preset heat dissipation substrate to obtain an encapsulated AI-DSP hybrid audio processing chip, including: The heat dissipation substrate is bonded and fixed with the encapsulated body to obtain a fixed encapsulated body, and the fixed encapsulated body is filled by using a preset thermal interface material to obtain a filled encapsulated body; 8. A stacked package system of an AI-DSP hybrid audio processing chip, characterized in that, The heat reliability of the filled encapsulated body is tested to obtain a heat reliability test result, and the performance of the heat dissipation substrate is optimized according to the heat reliability test result to obtain an encapsulated AI-DSP hybrid audio processing chip. It includes: The flip-chip module is used to flip-chip AI chips and DSP chips by using a first bonder to obtain flip-chip chips; The interconnection module is used to interconnect the flip-chip chips to obtain an interconnection chip structure, wherein the interconnection chip structure includes AI chips and DSP chips interconnected by a micro-bump array; The stacking module is used to vertically stack the interconnection chip structure to obtain a stacked chip structure, wherein the stacked chip structure includes AI chips and DSP chips vertically stacked by a high-density three-dimensional routing structure; The encapsulation module is used to encapsulate the stacked chip structure by using a second bonder to obtain an encapsulated body; The heat dissipation module is used to perform heat dissipation treatment on the encapsulated body by using a preset heat dissipation substrate to obtain an encapsulated AI-DSP hybrid audio processing chip. 9.A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the computer device is configured to perform the method according to any one of claims 1-8. The computer program is executed by the processor to implement the steps of the method of any one of claims 1 to 7.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method of any one of claims 1 to 7.

Images