Decoding verification method and device, storage medium and electronic device

Abstract

The embodiment of the invention provides a decoding verification method and device, a storage medium and an electronic device. The method comprises the following steps: determining the number of different sign bits of code word sign bits of an original code word after Mth decoding iteration and code word sign bits of the original code word after Nth decoding iteration as a first number; wherein M is an integer greater than or equal to 2, N is an integer greater than 2, and M is less than N; and under the condition that the first number is smaller than a preset verification threshold value, decoding verification is performed on the code word information of the Nth decoding iteration. Through the embodiment of the invention, the problem of high chip power consumption of a decoding algorithm of the quasi-cyclic LDPC code in the related technology can be solved, and the effect of saving the decoding power consumption of the quasi-cyclic LDPC code is achieved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of communication decoding, in particular to a decoding check method and device, a storage medium and an electronic device. BACKGROUND

[0002] Low Density Parity Check (LDPC) code is a kind of forward error check (FEC) code type with strong error correction capability. It is proved by experiments that the decoding performance tends to approach the Shannon limit, and it has a wide range of applications in optical communication, satellite, storage and other fields. However, the length of the code word is generally long, and the decoding algorithm has high computational complexity. Moreover, quasi-cyclic LDPC code often needs multiple iterations to correctly decode, especially when checking is needed at each iteration, which will increase the power consumption of the system on chips (SOC) chip. SUMMARY

[0003] Embodiments of the present application provide a decoding check method and device, a storage medium and an electronic device to at least solve the problem of large chip power consumption in the decoding algorithm of quasi-cyclic LDPC code in the related art.

[0004] According to an embodiment of the present application, a decoding check method is provided, comprising: determining the number of different symbol bits between the code symbol bits of an original code word after the Mth decoding iteration and the code symbol bits of the original code word after the Nth decoding iteration as a first number; wherein M is an integer greater than or equal to 2, N is an integer greater than 2, and M is less than N; and performing decoding check on the code word information of the Nth decoding iteration if the first number is less than a preset check threshold.

[0005] According to another embodiment of the present application, a decoding check device is provided, comprising: a determination module configured to determine the number of different symbol bits between the code symbol bits of an original code word after the Mth decoding iteration and the code symbol bits of the original code word after the Nth decoding iteration as a first number; wherein M is an integer greater than or equal to 2, N is an integer greater than 2, and M is less than N; and a check module configured to perform decoding check on the code word information of the Nth decoding iteration if the first number is less than a preset check threshold.

[0006] According to still another embodiment of the present application, a computer readable storage medium is also provided, which stores a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when running.

[0007] According to still another embodiment of the present application, there is also provided an electronic device comprising a memory having a computer program stored therein and a processor arranged to execute the computer program to perform the steps of any of the method embodiments described above.

[0008] According to still another embodiment of the present application, there is also provided a computer program product comprising computer programs, instructions, which when executed by a processor, implement the steps of any of the method embodiments described above.

[0009] According to the above embodiments of the present application, instead of performing decoding check after each decoding iteration in the decoding process, the position of decoding check is determined according to the number of different sign bits of code symbol bits after two adjacent decoding iterations and the preset check threshold, thus reducing the check power in the decoding iteration process of the quasi-cyclic LDPC code, and further reducing the chip power consumption of the decoding iteration of the quasi-cyclic LDPC code. Therefore, the problem of large chip power consumption of the decoding algorithm of the quasi-cyclic LDPC code in the related art can be solved, and the effect of saving the decoding power consumption of the quasi-cyclic LDPC code is achieved. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a hardware structure block diagram of an electronic device performing the decoding check method according to an embodiment of the present application;

[0011] Figure 2 is a flowchart of the decoding check method according to an embodiment of the present application;

[0012] Figure 3 is a flowchart of the check threshold table configuration method according to an embodiment of the present application;

[0013] Figure 4 is a flowchart of the flip statistic position table configuration method according to an embodiment of the present application;

[0014] Figure 5 is a flowchart of the decoding check method according to another embodiment of the present application;

[0015] Figure 6 is a structure block diagram of the decoding check device according to an embodiment of the present application. DETAILED DESCRIPTION

[0016] Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings and in conjunction with embodiments.

[0017] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and in the above-mentioned drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence.

[0018] The methods and embodiments provided in this application can be executed in a terminal, electronic device, or similar computing device. Taking running on an electronic device as an example, Figure 1 This is a hardware structure block diagram of an electronic device that implements the decoding and verification method according to an embodiment of the present invention. For example... Figure 1 As shown, an electronic device may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. The electronic device may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the electronic device described above. For example, the electronic device may also include components that are more... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0019] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the decoding and verification method in this embodiment of the invention. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thereby implementing the above-described method. The memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to electronic devices via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0020] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the electronic device. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0021] For the layered decoding of the quasi-cyclic LDPC, the decoder receives the LLR (Log-Likelihood Ratio) values from the channel and assigns them to the variable nodes Vn, assigns 0 to the check nodes Cn, and performs several iterations. In each iteration, the intermediate value Qn in each variable node is calculated using the expression Qn = Vn - Cn, and then the value of the check node Cn corresponding to the current iteration is calculated by the min-sum algorithm. The value of the variable node is updated by Vn = Qn + Cn. Finally, the sign bits of the updated Vn value after the current iteration are checked to determine whether the decoding is successful.

[0022] In the embodiment, a decoding check method running on the electronic device is provided, wherein the electronic device comprises a SOC chip, Figure 2 is a flowchart of the decoding check method according to an embodiment of the present application, as shown in Figure 2 , the flowchart comprises the following steps:

[0023] Step S202, determining the number of different sign bits between the code character sign bits of the original code word after the Mth decoding iteration and the code character sign bits of the original code word after the Nth decoding iteration as a first number; wherein M is an integer greater than or equal to 2, N is an integer greater than 2, and M is less than N;

[0024] In one embodiment, the decoding check method further comprises determining a preset check threshold, comprising: determining the number of different sign bits between the code character sign bits of the original code word after the first decoding iteration and the code character sign bits of the original code word after the second decoding iteration as a second number; and determining the preset check threshold corresponding to the second number by searching the pre-configured check threshold table according to the second number.

[0025] In one embodiment, the decoding check method further comprises pre-setting the check threshold table by simulation, comprising: for each channel condition, determining a plurality of initial check thresholds according to the length of the code character sign bits of the simulation code word; performing a plurality of first decoding simulations on the simulation code word according to the plurality of initial check thresholds; determining the first sum value corresponding to the iteration power and the check power of the plurality of first decoding simulations; and determining the initial check threshold corresponding to the minimum first sum value as the check threshold under the corresponding channel condition; and storing the corresponding relationship between the check threshold and the corresponding channel condition in the check threshold table, wherein the channel condition is represented by the number of different sign bits between the code character sign bits of the simulation code word after the first two decoding iterations of the corresponding first decoding simulation in the check threshold table.

[0026] Figure 3 is a flowchart of the check threshold table configuration method according to an embodiment of the present application, as shown in Figure 3 , the method comprises the following steps:

[0027] Step S301, according to the code symbol bit length of the simulation codeword, the check threshold is initialized and a plurality of initial check thresholds A (referred to as A values) are obtained, which can be set to 1 / 100 of the code symbol bit length. Among them, the simulation codeword is the codeword to be decoded in the decoding simulation process, which is functionally the same as the original codeword.

[0028] Specifically, the check threshold A is initialized to 1 / 100 of the code symbol bit length, that is, the A value is initialized to 1 / 100 of the code symbol bit length. The mathematical meaning of the A value is that under the current channel condition, the number of flipped codewords in the xth decoding iteration of the codeword decoded successfully and the number of flipped codewords in the x-1th decoding iteration of the codeword not decoded successfully are different (i.e. the number of different symbol bits after two decoding iterations), x is an integer greater than zero; "1 / 100" can be freely selected, for example: if the code symbol bit length is longer, it can be initialized to 1 / 200 or 1 / 300, and if the codeword is shorter, it can be initialized to 1 / 50. A value can also be selected according to the code symbol bit length; for example, when the total length of the code symbol bit is 10000, the A value can be initialized to 100, 95, 90, etc.

[0029] Step S302, decoding simulation is performed according to all A values (i.e. first decoding simulation), and the number of checks under different A values or the sum of iteration power and check power under different A values is counted.

[0030] In this embodiment, if the A value is too large, it will result in checking every time, which will increase the total power consumption; if it is too small, it will cause the check position to be delayed, increase the number of iterations, and also increase the total power consumption; wherein the total power consumption is the sum of the iteration power and the check power, i.e. the sum of the iteration power and the check power.

[0031] Step S303, select the A value with the least number of checks or the smallest sum of iteration power and check power as the check threshold of the code type (i.e. the code type corresponding to the simulation codeword in step S301).

[0032] For example, the initialized A values include: 100, 95, 90, 85; four decoding simulations are performed for 100, 95, 90, and 85, wherein each decoding simulation process includes multiple decoding iterations.

[0033] After simulation, the number of iterations or the total power consumption is the smallest when the A value is 85 under the current channel condition, so 85 is selected as the check threshold of the current channel condition.

[0034] Step S304, according to the step S301-S303 to determine the check threshold under different channel conditions, and the check threshold and the corresponding relationship of channel conditions are stored in the LUT table (i.e. check threshold table); wherein, the channel condition in the LUT table is represented by the number of different symbol bits of the code symbol bits after the first two decoding iterations (i.e. the first decoding iteration and the second decoding iteration) of each decoding simulation (i.e. the first decoding simulation).

[0035] In one embodiment, the A value configuration LUT table can also be a functional module, if the number of different symbol bits of the code symbol bits after the second decoding iteration and the first decoding iteration is less after the second decoding iteration, it indicates that the channel environment is better.

[0036] Step S204, in the case where the first number is less than the preset check threshold, the code symbol bits of the Nth decoding iteration are checked.

[0037] By configuring the check threshold table, the decoding check can be performed at a specific number of decoding iteration positions, the check number can be reduced under the condition of ensuring the performance of the quasi-cyclic LDPC decoding, and the decoding power consumption is reduced.

[0038] If the current code word can be decoded successfully under a certain number of iterations under the current channel condition, the number of code word flips of each iteration will certainly show a downward trend compared to the number of code word flips of the previous iteration. For example, the number of code word flips is 200 after the first iteration, and the number of code word flips will decrease in turn in the second, third and fourth decoding. Therefore, if the number of code word flips of each iteration can be counted, only a certain number of iterations are required for decoding, thereby saving the decoding power consumption of the previous iterations.

[0039] For example, if a code word needs 8 iterations to be decoded successfully, the most ideal case is that we count the code word flip information to be less than the set threshold at the 8th iteration, then we only need 1 decoding check and a certain number (less than or equal to 8 times) of code word flip information statistics. The power consumption is less than 8 decoding checks.

[0040] In this embodiment, the code word flip information does not need to be counted for the entire code word. For example, if the code word length is 10000, we can only take 1000 of them to count the flip information. The reason is that under the ideal Gaussian channel of wired transmission, the energy of each code word can be approximately equal, so the probability of error of each code word can also be approximately equal. Therefore, sampling can be used instead of the whole, which can greatly reduce the power consumption of code word flip information statistics.

[0041] Therefore, the decoding check method further comprises: determining the number of different symbol bits between the code symbol bits of the original code word after the first decoding iteration and the code symbol bits of the original code word after the second decoding iteration as a second number; and searching a pre-configured flipping statistical position table according to the second number to determine a flipping statistical position corresponding to the second number, wherein the flipping statistical position is used to indicate a target number of decoding iterations, the Mth decoding iteration and the Nth decoding iteration are both the flipping statistical position corresponding to the second number, and are adjacent flipping statistical positions.

[0042] After the corresponding flipping statistical position is determined, the number of flipped code words is only counted and it is determined whether to perform decoding check at each flipping statistical position, that is, the code symbol bits after iteration are obtained at each flipping statistical position, and the number of code symbol bits of the flipped code words in the code symbol bits is counted. After the decoding iteration at each flipping statistical position, the number of different symbol bits between the code symbol bits of the original code word after the current decoding iteration and the code symbol bits after the decoding iteration at the adjacent last flipping statistical position is determined, that is, the number of different symbol bits between the code symbol bits of the original code word after the Mth decoding iteration and the code symbol bits of the original code word after the Nth decoding iteration is determined as a first number. The check is performed only when the first number is less than a preset check threshold.

[0043] In one embodiment, determining the number of different symbol bits between the code symbol bits of the original code word after the Mth decoding iteration and the code symbol bits of the original code word after the Nth decoding iteration comprises: obtaining the code symbol bits when the original code word is iterated to the Mth decoding iteration and the Nth decoding iteration according to the flipping statistical position corresponding to the second number; and counting the number of different symbol bits according to the obtained code symbol bits after the Mth decoding iteration and the code symbol bits after the Nth decoding iteration.

[0044] In one embodiment, the flipping statistical position table is pre-set by simulation, and the pre-setting of the flipping statistical position table by simulation comprises: performing multiple second decoding simulations on the simulation code word according to a check threshold corresponding to each channel condition; setting an initial flipping statistical position corresponding to the multiple second decoding simulations; determining a second sum of iteration power and check power corresponding to the multiple second decoding simulations according to the initial flipping statistical position; determining the initial flipping statistical position corresponding to the minimum second sum as the flipping statistical position under the corresponding channel condition; and storing the corresponding relationship between the flipping statistical position and the corresponding channel condition in the flipping statistical position table, wherein the channel condition is represented by the number of different symbol bits between the code symbol bits of the simulation code word after the first two decoding iterations of each second decoding simulation in the flipping statistical position table.

[0045] The code word flip information statistics also increase power consumption after each iteration is completed, and the first several iterations are difficult to decode successfully when the signal-to-noise ratio is low, thus, the code word flip information statistics is not necessary to be performed each time. If the information statistics is too late, the check position is delayed, the iteration number is increased, and the power consumption is also increased. The appropriate flip information statistics position can be determined in advance to save the decoding power consumption to a certain extent, and the flip statistics position table is provided in the embodiment of the present application to determine the appropriate flip information statistics position and number. Figure 4 The flip statistics position table configuration method according to the embodiment of the present application is shown in the flow chart as shown in Figure 4 The method comprises the following steps:

[0046] In step S401, 1 / 10 or 1 / 20 of all code symbols of the simulation code word are sampled as the sample code word.

[0047] In the embodiment, the number of sample code words can also be flexibly configured, but should correspond to the A value, for example, if the A value is 100 under the simulation of 10000 code words, the A value can be configured as 10 when 1000 code words are taken.

[0048] Since the energy of each code word can be approximately equal under the ideal Gaussian channel of the wired transmission, the error code probability of each code word can also be approximately equal, thus, the sampling can be used instead of the integer, that is, the number of flip of all code words does not need to be counted, but only the sampling is needed.

[0049] In step S402, the check threshold under the current channel condition is determined based on the check threshold table, the decoding simulation is performed for multiple times (i.e., the second decoding simulation) according to the check threshold, and the number of flip information statistics positions is sequentially reduced from the first decoding simulation to the last decoding simulation, and the corresponding check number and iteration number are recorded.

[0050] For example, the check threshold of the current channel condition is 50, and three decoding simulations are initiated according to the check threshold.

[0051] In the first decoding simulation, the flip position statistics is performed after the 1st to 8th decoding iteration, that is, the code symbol after each decoding iteration is counted after the 1st to 8th decoding iteration.

[0052] In the second decoding simulation, the flip position statistics is performed after the 4th to 8th decoding iteration.

[0053] In the third decoding simulation, the flip position statistics is performed after the 1st, 2nd, 7th and 8th decoding iteration.

[0054] Step S403, determining the total power consumption of the multiple decoding simulations according to the check times and iteration times of each decoding simulation; wherein the power consumption of each check is a fixed constant x, and the power consumption of each iteration is a constant y, so the total power consumption of one decoding simulation = check times * x + iteration times * y.

[0055] Step S404, comparing the total power consumption of the multiple decoding simulations, and determining the flipping information statistical position corresponding to the code word of the decoding simulation with the minimum total power consumption as the flipping information statistical position under the current channel condition;

[0056] Step S405, storing the corresponding relationship between the flipping statistical position and the current channel condition in the flipping statistical position table, wherein the channel condition is represented by the number of different symbol bits of the code character symbol of the simulation code word after the first two decoding iterations of the corresponding decoding simulation (i.e. the second decoding simulation) in the flipping statistical position table.

[0057] In the embodiment, the number of different code character symbol bits of the to-be-decoded code word (original code word or simulation code word) after the first decoding iteration and the second decoding iteration is used as a bridge to establish the relationship between the check threshold and the flipping information statistical position of the code word. In actual decoding, only the corresponding flipping information statistical position and the check threshold need to be configured according to the flipping information of the code word after the first decoding iteration and the second decoding iteration, so that the decoding check can be performed at a specific position, and the decoding check does not need to be performed after each decoding iteration, thereby saving the decoding power consumption.

[0058] Through the above steps, the decoding check does not need to be performed after each decoding iteration in the decoding process, but the position of the decoding check is determined according to the number of different symbol bits of the code character symbol after the adjacent two decoding iterations and the preset check threshold. In this way, the check power in the decoding iteration process of the quasi-cyclic LDPC code is reduced, and the chip power consumption of the decoding iteration of the quasi-cyclic LDPC code is further reduced. Therefore, the problem that the decoding algorithm of the quasi-cyclic LDPC code has large chip power consumption in the related art can be solved, and the effect of saving the decoding power consumption of the quasi-cyclic LDPC code is achieved.

[0059] In combination with the above check threshold and flipping statistical position, the embodiment of the application further provides a decoding check method, Figure 5 which is a flowchart of the decoding check method according to another embodiment of the application, as shown in Figure 5 the method comprises the following steps:

[0060] Step S501, setting a check threshold A and a flipping statistical position (both of which are obtained by simulation);

[0061] Step S502, recording the symbol bit information of the initial code word (i.e. the original code word) after passing through the channel and before decoding, denoted as code word origin;

[0062] Step S503, the decoding iteration is to the target number of flipping statistics position indication decoding iteration, the Vn code character symbol bit after the target number of decoding iteration is counted, recorded as code word Temp;

[0063] Step S504, the number of different symbols between code word Temp and the last recorded code character symbol bit is counted (if the current position is the first time to be counted, it is compared with code word origin), recorded as x;

[0064] Step S505, x is compared with the check threshold A, if x is less than A, the current iteration is probably decoded successfully, and the check is directly performed; if x is greater than or equal to A, the current iteration is probably not decoded successfully, and the check is not necessary, and the next iteration is directly entered, and the decoding is circularly performed until the decoding is successful.

[0065] Through the embodiment of the present application, based on the statistical information of code word flipping in the quasi-cyclic LDPC decoding process, the number of flipped code words in the iteration process is recorded, and the change trend of the number of code word flipping is analyzed, so that the decoding check position is determined. Compared with the method that the quasi-cyclic LDPC performs check every time in a large iteration, the embodiment of the present application can reduce the check number to a certain extent, save the decoding power consumption, and will not reduce the decoding performance. Especially when the channel condition is very poor, 4-5 times of check power consumption can be saved through the above method.

[0066] In one embodiment, the determination of the check threshold and the flipping statistics position can also be directly given by the experience of those skilled in the art.

[0067] In one embodiment, the determination of the check threshold and the flipping statistics position is related to the code type or the code character symbol bit length to be decoded, and in the case that the code type or the code character symbol bit length of the current code to be decoded is different from that of the code corresponding to the current check threshold table or the flipping statistics position table, a new check threshold table and a flipping statistics position table need to be obtained by re-simulation.

[0068] Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and necessary general hardware platform, and of course it can also be realized by hardware, but in many cases the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disc, optical disc) and includes a plurality of instructions for making a terminal device (which can be a mobile phone, computer, server, or network device, etc.) execute the method described in each embodiment of the present application.

[0069] In the embodiment, a decoding and checking device is also provided, which is used to implement the above-mentioned embodiments and preferred embodiments, and will not be described herein. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, implementation in hardware or a combination of software and hardware is also possible and contemplated.

[0070] Figure 6 is a structural block diagram of a decoding and checking device according to an embodiment of the present application, as shown in the figure, the decoding and checking device 600 comprises a determining module 610 and a checking module 620. Figure 6

[0071] The determining module 610 is configured to determine the number of different symbol bits between the code symbol bits of the original code word after the Mth decoding iteration and the code symbol bits of the original code word after the Nth decoding iteration as a first number, wherein M is an integer greater than or equal to 2, N is an integer greater than 2, and M is less than N.

[0072] The checking module 620 is configured to perform decoding and checking on the code word information of the Nth decoding iteration when the first number is less than a preset checking threshold.

[0073] Under the condition of a low signal-to-noise ratio channel, the embodiment of the present application can effectively reduce the checking times to 2-3 times, and will not cause a decrease in decoding capability, thereby saving decoding power consumption.

[0074] It should be noted that the above-mentioned modules can be implemented by software or hardware, and for the latter, the implementation can be achieved by the following ways, but is not limited thereto: all the above-mentioned modules are located in the same processor; or the above-mentioned modules are located in different processors in any combination. In the actual implementation process, the module naming and function division in the above-mentioned decoding and checking device can be adjusted according to the actual situation, as long as the steps of the decoding and checking method in the above-mentioned embodiments can be implemented, which will not be described herein.

[0075] The embodiment of the present application also provides a computer readable storage medium, which stores a computer program, wherein the computer program is set to execute the steps in any one of the above-mentioned method embodiments when running.

[0076] In an exemplary embodiment, the above-mentioned computer readable storage medium can include but is not limited to: a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0077] ​The embodiment of the present application further provides an electronic device, comprising a memory and a processor, the memory stores a computer program, and the processor is configured to execute the computer program to perform the steps in any of the above method embodiments.

[0078] In an example embodiment, the electronic device further comprises a transmission device connected to the processor and an input / output device connected to the processor.

[0079] The embodiment of the present application further provides a computer program product, comprising a computer program and instructions, wherein the computer program and instructions are executed by a processor to implement the steps in any of the above method embodiments.

[0080] The specific examples in the embodiment can refer to the examples described in the above embodiments and example embodiments, and the embodiment will not be repeated here.

[0081] Obviously, those skilled in the art should understand that the modules or steps of the present application described above can be realized by general computing devices, which can be concentrated on a single computing device or distributed on a network composed of multiple computing devices, and they can be realized by program codes executable by the computing devices, so that they can be stored in storage devices and executed by the computing devices, and in some cases, the steps shown or described can be executed in different order, or they can be manufactured into individual integrated circuit modules, or multiple modules or steps can be manufactured into a single integrated circuit module. Thus, the present application is not limited to any particular combination of hardware and software.

[0082] The above only describes the preferred embodiments of the present application and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method of decoding a check, characterized by, The method comprises: determining the number of different symbol bits between the code symbol bits of the original code word after the Mth decoding iteration and the code symbol bits of the original code word after the Nth decoding iteration as a first number, wherein M is an integer greater than or equal to 2, N is an integer greater than 2, and M is less than N; in the case where the first number is less than a preset check threshold, performing a decoding check on the code symbol bits of the Nth decoding iteration.

2. The method of claim 1, wherein, The method further comprises: determining the number of different symbol bits between the code symbol bits of the original code word after the first decoding iteration and the code symbol bits of the original code word after the second decoding iteration as a second number; determining the preset check threshold corresponding to the second number by searching a preconfigured check threshold table according to the second number.

3. The method of claim 2, wherein, The method further comprises preconfiguring the check threshold table through simulation, and the preconfiguring the check threshold table through simulation comprises: determining a plurality of initial check thresholds according to the length of the code symbol bits of a simulation code word for each channel condition; performing a plurality of first decoding simulations on the simulation code word according to the plurality of initial check thresholds; determining the first sum of the iteration power and the check power corresponding to the plurality of first decoding simulations; and determining the initial check threshold corresponding to the minimum first sum as the check threshold under the corresponding channel condition; storing the correspondence between the check threshold and the corresponding channel condition in the check threshold table, wherein the channel condition is represented by the number of different symbol bits between the code symbol bits of the simulation code word after the first two decoding iterations of the corresponding first decoding simulation in the check threshold table.

4. The method of claim 1, wherein, The method further comprises: determining the number of different symbol bits between the code symbol bits of the original code word after the first decoding iteration and the code symbol bits of the original code word after the second decoding iteration as a second number; determining the flip statistical position corresponding to the second number by searching a preconfigured flip statistical position table according to the second number, wherein the flip statistical position is used to indicate the target number of decoding iterations, the Mth decoding iteration and the Nth decoding iteration are both the flip statistical position corresponding to the second number, and are adjacent flip statistical positions.

5. The method of claim 3, wherein, Determining the number of different symbol bits between the code symbol bits of the original code word after the Mth decoding iteration and the code symbol bits of the original code word after the Nth decoding iteration comprises: acquiring the code symbol bits when the original code word is iterated to the Mth decoding iteration and the Nth decoding iteration according to the flip statistical position corresponding to the second number; statistically determining the number of different symbol bits according to the acquired code symbol bits after the Mth decoding iteration and the Nth decoding iteration.

6. The method of claim 4, wherein, The method further comprises preconfiguring the flip statistical position table through simulation, and the preconfiguring the flip statistical position table through simulation comprises: performing a plurality of second decoding simulations on the simulation code word according to the check threshold corresponding to each channel condition; setting an initial flip statistical position for the plurality of second decoding simulations; determining a second sum of iteration power and check power corresponding to the multiple second decoding simulations according to the initial flipping statistic position; and determining the initial flipping statistic position corresponding to the minimum second sum as the flipping statistic position under the corresponding channel condition; storing the corresponding relationship between the flipping statistic position and the corresponding channel condition into a flipping statistic position table, wherein the channel condition is represented by the number of different symbol bits of the code symbol bits of the simulation codeword after the first two decoding iterations of the corresponding second decoding simulation in the flipping statistic position table.

7. A decoding check apparatus characterized by comprising: comprising: a determining module, configured to determine the number of different symbol bits between the code symbol bits of the original codeword after the Mth decoding iteration and the code symbol bits of the original codeword after the Nth decoding iteration as a first number; wherein M is an integer greater than or equal to 2, N is an integer greater than 2, and M is less than N; a checking module, configured to perform decoding check on the codeword information of the Nth decoding iteration if the first number is less than a preset check threshold.

8. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, wherein the computer program is executed by the processor to implement the steps of the method in any one of claims 1 to 6.

9. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the steps of the method in any one of claims 1 to 6.

10. A computer program product comprising a computer program, instructions, characterized in that, The computer program, instructions are executed by the processor to implement the steps of the method in any one of claims 1 to 6.

Images