Multi-platform hybrid power model simulation method and system and computer equipment

Abstract

The invention relates to a multi-platform hybrid power model simulation method and system and computer equipment. Comprising the following steps: determining a next time synchronization point of a power model, writing a state signal and the time synchronization point into a first shared memory, and providing a precise reference for discrete system simulation; the discrete system is triggered to advance and update a second shared memory according to a time synchronization point, and simulation time sequence and data synchronization is guaranteed; and the updated target analog signal in the second shared memory is read to continue power model simulation, so that the cyclic dynamic updating process of reference setting-simulation propulsion-data feedback is ensured, co-simulation under non-real-time multi-platform mixing is realized, and the overall simulation synchronism and accuracy are improved.

Description

Technical Field

[0001] This application relates to the field of power system analysis technology, and in particular to a multi-platform hybrid power model simulation method, system, and computer equipment. Background Technology

[0002] With the sweeping wave of digitalization and intelligentization, traditional power systems are accelerating their transformation into smart grids. A key characteristic of this transformation is the deep integration of power systems and network communication systems, which together form a complex cyber-physical system (CPS). To address the challenges arising from this integration in areas such as operation control and information interaction, new and stringent requirements are being placed on simulation technology. Building a joint simulation platform for power systems and network communication systems primarily requires solving the problem of time synchronization.

[0003] Currently, real-time hybrid digital simulation of power CPS is typically used to achieve synchronization on the same timeline. However, this places high demands on the computational performance of the simulation hardware, has high cost per node, limits the scale of systems that can be simulated, and the real-time nature of the simulation results in low efficiency when performing simulations on large time scales. In addition, when power systems connect to simulation platforms of network communication systems, they can usually only access them through IP routing or Ethernet frames, and the time consumed in these connections introduces inherent latency, causing serious interference to the power system simulation process. Summary of the Invention

[0004] Based on this, the purpose of this application is to find a way to build a non-real-time hybrid simulation system for power CPS by unifying time synchronization and simulation progress, so as to eliminate the inherent latency introduced by network communication equipment and break through the scale limitations of real-time simulation.

[0005] Firstly, this application provides a multi-platform hybrid power model simulation method. The multi-platform includes continuous systems and discrete systems, and the method is applied to continuous systems, including: Determine the next time synchronization point during the current simulation of the power model, and write the state signal associated with the power model and the time synchronization point into the first shared memory; The discrete system is triggered to perform simulation progress according to the time synchronization point, and the second shared memory is updated according to the target digital signal read from the first shared memory; The target analog signal is read from the second shared memory associated with the discrete system, and the simulation of the power model continues based on the target analog signal.

[0006] In one embodiment, the multi-platform further includes a coordination controller; the method further includes: sending a semaphore for communication between processes to the coordination controller; when the discrete system detects the occurrence of the semaphore, triggering the discrete system to perform simulation progress according to the time synchronization point, and sending an acknowledgment signal to the coordination controller; when the acknowledgment signal is received from the coordination controller, reading the target simulation signal from the second shared memory.

[0007] In one embodiment, after sending a semaphore for inter-process communication to the coordination controller, the execution process of the coordination controller includes: performing non-blocking detection through the semaphore; when the first shared memory is in an idle state, issuing a time advance instruction to the discrete system; and determining the acknowledgment signal fed back by the discrete system based on a preset waiting mechanism.

[0008] In one embodiment, determining the confirmation signal of discrete system feedback based on a preset waiting mechanism includes: starting a high-precision timer and determining an absolute time point; performing non-blocking polling monitoring based on the absolute time point to determine the average delay when discrete system feedback is obtained; and dynamically adjusting the waiting time based on the average delay to determine the confirmation signal of discrete system feedback based on the waiting time.

[0009] In one embodiment, triggering the discrete system to advance the simulation according to the time synchronization point and updating the second shared memory according to the target digital signal read from the first shared memory includes: pausing the current event processing of the discrete system and determining the target event corresponding to the time synchronization point; reading the target digital signal associated with the target event from the first shared memory and triggering the discrete system to execute the target event to obtain the execution result; and updating the second shared memory associated with the discrete system according to the execution result.

[0010] In one embodiment, the scheduling of the first shared memory and the second shared memory is implemented through a memory manager; the first shared memory represents the shared memory written according to the mapping file configuration after the analog signal is converted from analog to digital, realizing the writing of analog signals of continuous systems and the reading of digital signals of discrete systems; the second shared memory represents the shared memory written according to the mapping file configuration after the digital signal is converted from digital to analog, realizing the writing of digital signals of discrete systems and the reading of analog signals of continuous systems.

[0011] Secondly, this application also provides a multi-platform hybrid power model simulation system. The system includes a continuous system, a discrete system, a first shared memory, and a second shared memory, wherein: A continuous system is used to determine the next time synchronization point during the current simulation of the power model, and writes the state signal associated with the power model and the time synchronization point into the first shared memory; A discrete system for performing simulation progression according to the time synchronization point and updating the second shared memory based on the target digital signal read from the first shared memory; The continuous system is also used to read the target analog signal from the second shared memory associated with the discrete system and to continue the simulation of the power model based on the target analog signal.

[0012] In one embodiment, the system further includes a protocol application module, a protocol stack, a virtual network, a smart device, and a protocol processing module, wherein: the protocol application module and the protocol stack are used to convert the target analog signal into a dataset and a protocol message, respectively, and send them to the virtual network; the smart device is used to interact with the virtual network and complete data sampling and structure conversion; and the protocol processing module is used to parse the dataset and trigger the simulation process update of the power model.

[0013] Thirdly, this application also provides a computer device. The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the steps of the above-described multi-platform hybrid power model simulation method.

[0014] Fourthly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the above-described multi-platform hybrid power model simulation method.

[0015] The aforementioned multi-platform hybrid power model simulation method, system, computer equipment, and storage medium first determine the next time synchronization point of the power model and write the state signal and time synchronization point to the first shared memory, providing an accurate benchmark for discrete system simulation; then, it triggers the discrete system to advance according to the time synchronization point and update the second shared memory, ensuring simulation timing and data synchronization; finally, it reads the updated target simulation signal from the second shared memory to continue the power model simulation, ensuring the dynamic update process of "benchmark setting - simulation advancement - data feedback", realizing collaborative simulation under non-real-time multi-platform hybrid conditions, and improving the overall simulation synchronization and accuracy. Attached Figure Description

[0016] Figure 1 This is a flowchart illustrating the implementation method of a CPS non-real-time hybrid simulation system in one embodiment; Figure 2 This is a flowchart illustrating a multi-platform hybrid power model simulation method in one embodiment; Figure 3 This is a flowchart of the time and data synchronization process for a continuous system in one embodiment; Figure 4 This is a flowchart illustrating the execution process of the coordination controller in one embodiment; Figure 5 This is a flowchart illustrating the time and data synchronization process of a discrete system in one embodiment. Figure 6 This is a schematic diagram of a multi-platform hybrid power model simulation system in one embodiment; Figure 7 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0018] This application designs a multi-platform hybrid power model simulation system, including a continuous system, a discrete system, a first shared memory, and a second shared memory. The continuous system is used to determine the next time synchronization point in the current power model simulation and write the associated state signal and time synchronization point of the power model into the first shared memory. The discrete system is used to advance the simulation according to the time synchronization point and update the second shared memory based on the target digital signal read from the first shared memory. The continuous system is also used to read the target analog signal from the second shared memory associated with the discrete system and continue the power model simulation based on the target analog signal.

[0019] In power cyber-physical systems (CPS), the power system is typically a continuous system, described by a system of differential equations. During simulation, these equations are usually discretized into a system of difference equations, which are then solved using recursive formulas. The solver sequentially arranges the system states obtained at each time step to obtain a trajectory representing the dynamic changes of the system. Network communication systems within CPS are typically discrete systems. For discrete-time systems, the model is often described using logic equations, state machines, or other forms suitable for numerical computer solutions. Unlike the time axis of a continuous system, the time axis of a discrete-time system uses several events as coordinates, hence it is also called an event axis. Some of these events occur at fixed points in time and are predetermined, but many more are random events whose occurrence times cannot be determined before the simulation.

[0020] Specifically, such as Figure 1 As shown, Figure 1This is a flowchart illustrating the implementation method of a non-real-time hybrid simulation system for Cyber-Physical Systems (CPS). The power system (continuous system) is built using platforms such as Matlab's Simulink (a visual simulation platform), while the network communication system (discrete system) is built using platforms such as OMNet++ (a multi-protocol network simulation platform) and the INET standard protocol model library. The continuous system built on the visual simulation platform enables multi-domain simulation and model-based design; it supports system design, simulation, automatic code generation, and continuous testing and verification of embedded systems; and it provides a graphical editor, customizable module libraries, and solvers for dynamic system modeling and simulation. The discrete system built on the multi-protocol network simulation platform has a complete graphical interface and an embeddable simulation kernel, and can be used for simulation of distributed systems and communication networks.

[0021] In one embodiment, such as Figure 2 As shown, a multi-platform hybrid power model simulation method is provided, which can be applied to... Figure 1 Taking a continuous system as an example, the following steps are included: Step 202: Determine the next time synchronization point for the current simulation of the power model, and write the associated state signals and time synchronization point of the power model into the first shared memory.

[0022] Among them, the power model represents the simulation model constructed for purposes such as smart grid security attack and defense drills, new energy power station grid connection communication verification, and distribution network self-healing control strategy testing.

[0023] Specifically, such as Figure 3 As shown, Figure 3 This is a flowchart of the time and data synchronization process for a continuous system. In a continuous system, the Simulink S-Function (system function module) acquires the current time t before each simulation step and calculates the next time synchronization point. , among them This is the simulation step size for the power system. Next, the time synchronization point and the status signals to be collected and transmitted by the intelligent electronic devices will be written into the first shared memory.

[0024] In one embodiment, the scheduling of the first shared memory and the second shared memory is implemented through a memory manager; the first shared memory represents the shared memory written according to the mapping file configuration after the analog signal is converted from analog to digital, realizing the writing of analog signals of continuous systems and the reading of digital signals of discrete systems; the second shared memory represents the shared memory written according to the mapping file configuration after the digital signal is converted from digital to analog, realizing the writing of digital signals of discrete systems and the reading of analog signals of continuous systems.

[0025] Specifically, refer to Figure 1 As shown, the first shared memory, also known as analog-to-digital (ADC) shared memory, is implemented through an ADC module. The ADC module developed in Simulink performs sampling and quantization of analog signals in the power system. Since the differential equation model describing a continuous system is often discretized into difference equations for solution, and the system state is obtained by solving in step-size increments, this means that at the end of each step, the power system state has been discretized and sampled and quantized. The ADC module only needs to write the state signal to be transmitted into the named first shared memory according to the configuration of the mapping file. In other words, the first shared memory corresponding to the ADC module of the secondary-side intelligent electronic device of the power system is written to by the power system on the Simulink side and read by the network communication system on the OMNet++ side.

[0026] Similarly, the second shared memory, also known as a digital-to-analog converter (DAC) shared memory, is implemented through a DAC module. Since the network communication system itself is a discrete system, the signals received by the intelligent electronic device (IED) through the network communication system are discrete digital signals. These digital signals are written into the named second shared memory corresponding to the DAC module. Before each simulation step, the Simulink-simulated power system reads the value from the second shared memory corresponding to the DAC module, using it as the state signal to be input to the intelligent electronic device in the current simulation step. In other words, the second shared memory corresponding to the DAC module of the secondary-side intelligent electronic device in the power system is written to by the OMNet++-side network communication system and read from by the Simulink-side power system.

[0027] In one embodiment, shared memory is implemented through inter-process communication technology, achieving a latency of <1μs.

[0028] Step 204: Trigger the discrete system to perform simulation progress according to the time synchronization point, and update the second shared memory according to the target digital signal read from the first shared memory.

[0029] Specifically, refer to Figure 3 As shown, the continuous system triggers the discrete system's execution event jump by publishing inter-process communication semaphores. This allows the discrete system to advance and execute the simulation according to the time synchronization point and the target digital signal read from the first shared memory. Finally, the second shared memory is updated based on the execution result. At this time, the continuous system also synchronously advances the simulation process of the power model and blocks, waiting for the confirmation signal from the discrete system.

[0030] Step 206: Read the target analog signal from the second shared memory associated with the discrete system, and continue the simulation of the power model based on the target analog signal.

[0031] Specifically, refer to Figure 3 As shown, the discrete system has completed the update and writing of digital signals in the second shared memory. The system function module in the continuous system will continue to read the second shared memory maintained by the digital-to-analog conversion module of the intelligent electronic device, read the target analog signal converted from it, continuously maintain and update the first shared memory, and use it as a new input signal for the continuous system to realize the update of the power model and the continuation of the simulation.

[0032] In one embodiment, reference Figure 1 As shown, a multi-platform hybrid power model simulation method is also provided. The power system writes the current state signal of the power model simulation and the next time synchronization point into the analog-to-digital converter (ADC) shared memory, causing the ADC shared memory to publish a timestamp to the time synchronization engine. The time synchronization engine then issues a time advancement command to the network communication system. The network communication system advances the simulation according to the time synchronization point and encapsulates data based on the target digital signal read from the ADC shared memory. The encapsulated data packet is parsed by the INET protocol stack and used as a write-back control variable to update the ADC shared memory. When the target analog signal (ZMQ signal) is read from the ADC shared memory, the power system is triggered to continue the power model simulation based on the target analog signal.

[0033] In the aforementioned multi-platform hybrid power model simulation method, the next time synchronization point of the power model is first determined and the state signal and time synchronization point are written to the first shared memory to provide an accurate benchmark for discrete system simulation. Then, the discrete system is triggered to advance according to the time synchronization point and update the second shared memory to ensure the synchronization of simulation timing and data. Finally, the updated target simulation signal in the second shared memory is read to continue the power model simulation, ensuring the dynamic update process of "benchmark setting - simulation advancement - data feedback". This realizes collaborative simulation under non-real-time multi-platform hybrid conditions and improves the overall simulation synchronization and accuracy.

[0034] In one embodiment, the multi-platform system further includes a coordination controller. The method further includes: sending semaphores for inter-process communication to the coordination controller; when the discrete system detects the occurrence of a semaphore, triggering the discrete system to advance the simulation according to the time synchronization point and sending an acknowledgment signal to the coordination controller; and upon receiving the acknowledgment signal from the coordination controller, reading the target simulation signal from the second shared memory.

[0035] Specifically, refer to Figure 3As shown, after triggering the memory manager, the continuous system sends a semaphore for inter-process communication to the coordinating controller. The discrete system on the OMNet++ side monitors the semaphore and advances the discrete system simulation time to the time synchronization point when the semaphore occurs. After the discrete system advances and executes the simulation according to the time synchronization point and the target digital signal read from the first shared memory, it sends an acknowledgment signal to the coordinating controller. Upon receiving the acknowledgment signal from the coordinating controller, it reads the target analog signal from the second shared memory maintained by the digital-to-analog converter module of the intelligent electronic device.

[0036] In this embodiment, by sending communication semaphores to the coordination controller, the running status and interaction requirements of the distributed processes can be centrally transmitted. When the discrete system detects the semaphore and triggers its simulation to proceed according to the time synchronization point, the timing accuracy of the simulation process is ensured. Meanwhile, the discrete system synchronously sends an acknowledgment signal to the coordination controller, allowing the coordination center to monitor the simulation progress in real time. After the process receives the acknowledgment signal from the coordination controller, it reads the target simulation signal from the second shared memory, ensuring the reliability of subsequent data reading.

[0037] In one embodiment, after sending semaphores for inter-process communication to the coordination controller, the coordination controller's execution process includes: performing non-blocking detection via semaphores; issuing a time advance instruction to the discrete system when the first shared memory is idle; and determining the acknowledgment signal fed back by the discrete system based on a preset waiting mechanism.

[0038] Among them, the coordination controller, as the central decision-making system between the continuous system on the Simulink side and the discrete system on the OMNeT++ side, undertakes the following tasks: time synchronization arbitration: ensuring that the simulation clocks of the power system (continuous time) and the communication system (discrete events) are strictly aligned; data exchange management: controlling the read and write permissions and transmission timing of shared memory; and abnormal state handling: detecting and recovering from synchronization failure scenarios.

[0039] Specifically, such as Figure 4 As shown, Figure 4 This is a flowchart illustrating the coordinated controller execution process. When the power system initiates a new simulation step, it performs non-blocking checks on the shared memory using semaphores. For example, if the first shared memory (Buffer A) is free, it indicates that data needs to be written; if the second shared memory (Buffer B) has data, it needs to be read. When the shared memory buffer is free, it needs to write the state signal associated with the power model. At this time, the continuous system publishes a time advance command to the discrete system through ZMQ (a high-performance asynchronous message communication library), that is, publishes the timestamp of the time synchronization point to the discrete system, so that the discrete system can determine the acknowledgment signal fed back by the discrete system based on a preset waiting mechanism.

[0040] In this embodiment, non-blocking detection using semaphores enables real-time perception of the shared memory status without interrupting other system operations, avoiding the efficiency loss caused by continuous resource consumption for blocking detection. Issuing time-advancement instructions to the discrete system ensures the timeliness and accuracy of instruction delivery; and determining the acknowledgment signal from the discrete system based on a preset waiting mechanism standardizes the signal feedback waiting process, preventing system response chaos caused by irregular waiting.

[0041] In one embodiment, data interaction between digital and analog signals is achieved using TCP / IP sockets, and a Socket client module is developed in the continuous system on the Simulink side, while the discrete system on the OMNeT++ side is constructed as a Socket server.

[0042] In one embodiment, determining the acknowledgment signal of discrete system feedback based on a preset waiting mechanism includes: starting a high-precision timer and determining an absolute time point; performing non-blocking polling monitoring based on the absolute time point to determine the average delay when discrete system feedback is obtained; and dynamically adjusting the waiting time based on the average delay to determine the acknowledgment signal of discrete system feedback based on the waiting time.

[0043] Specifically, the continuous system starts a high-precision timer to wake up at the next absolute time point in each loop, ensuring a strictly fixed control / transmission cycle. By monitoring the ZMQACK channel (non-blocking polling monitoring method), it determines whether an acknowledgment signal (ACK) has been received from the discrete system. If so, the time of receipt is recorded, and the average latency is updated. The waiting timeout threshold is dynamically adjusted as follows: timeout = max(1.5 × average latency, 200μs). If a timeout occurs, exception handling is triggered. If an acknowledgment signal is received from the discrete system, the target analog signal continues to be read from the second shared memory associated with the network communication system.

[0044] In this embodiment, a high-precision timer is started to determine the absolute time point, providing an accurate benchmark for delay monitoring; non-blocking polling is then performed to accurately calculate the average delay of the discrete system feedback; the waiting time is dynamically adjusted accordingly to match the actual feedback speed, preventing misjudgment and avoiding waste, and ultimately accurately determining the confirmation signal to ensure the accuracy and efficiency of the interaction.

[0045] In one embodiment, triggering the discrete system to advance the simulation according to the time synchronization point and updating the second shared memory according to the target digital signal read from the first shared memory includes: pausing the current event processing of the discrete system and determining the target event corresponding to the time synchronization point; reading the target digital signal associated with the target event from the first shared memory and triggering the discrete system to execute the target event and obtain the execution result; and updating the second shared memory associated with the discrete system according to the execution result.

[0046] Specifically, such as Figure 5 As shown, Figure 5 This is a flowchart of the time and data synchronization process for a discrete system. When the OMNet++ simulation kernel in the discrete system determines the target time for event processing, i.e., the time synchronization point, it reads the target digital signal from the first shared memory maintained by the analog-to-digital converter module. The discrete system then initiates the current event processing, rapidly advancing the simulation clock to the time synchronization point and processing all target events corresponding to that point to obtain the execution result. When waiting for external time advancement is required, high-precision waiting can be performed at 100μs polling intervals to avoid busy waiting. Finally, based on the execution result, the discrete system updates the second shared memory maintained by the analog-to-digital converter module and sends a confirmation signal back to the coordinator controller.

[0047] In this embodiment, the current event processing of the discrete system is first paused and the target event at the time synchronization point is locked to avoid event conflict interference; then the digital signal of the target event in the first shared memory is read to ensure the accuracy of the execution basis; after the result of the target event is obtained, the second shared memory is updated to realize the focus of event processing and data synchronization, and to ensure the accuracy of discrete system event execution and the timeliness of data.

[0048] In one embodiment, the discrete system may use a fixed time step (e.g., 10 ms) to poll for signals.

[0049] In one embodiment, the system further includes a protocol application module, a protocol stack, a virtual network, a smart device, and a protocol processing module, wherein: the protocol application module and the protocol stack are used to convert the target analog signal into a dataset and a protocol message, respectively, and send them to the virtual network; the smart device is used to interact with the virtual network and complete data sampling and structure conversion; and the protocol processing module is used to parse the dataset and trigger the simulation process update of the power model.

[0050] The structure of the analog-to-digital conversion shared memory can include timestamps, three-phase voltages, three-phase currents, circuit breaker status, data quality flags, checksums, etc.; the structure of the digital-to-analog conversion shared memory can include command type (0: none, 1: open, 2: close), device identifier, validity period, maximum of 10 concurrent commands, etc. Through the participation of analog-to-digital conversion shared memory, digital-to-analog conversion shared memory, and the coordination controller, combined with protocols such as the GOOSE protocol under the IEC 61850 standard, data interaction during offline, non-real-time hybrid simulation of power systems and network communication systems can be achieved.

[0051] Specifically, such as Figure 6 As shown, Figure 6 This is a schematic diagram of a multi-platform hybrid power model simulation system. The network communication system first initializes, including connecting to shared memory, loading device mapping configurations based on XML-configured mapping rules, creating GOOSE publishers, and registering subscription callbacks. When reading state signals from the analog-to-digital conversion shared memory, such as power model status signals, the protocol application module and protocol stack convert the target analog signal into GOOSE datasets and GOOSE protocol messages, respectively, and send them to the virtual network and set the next synchronization. The protocol message structure generation process includes creating GOOSE messages conforming to IEC 61850-8-1, setting the protocol header, adding datasets, and setting time parameters. This enables customization of the GOOSE message structure and supports parallel processing of multiple protocols.

[0052] Next, the network communication system and the power system complete data mapping and time synchronization. Specifically, this process involves monitoring the signals sent by the coordinating controller, obtaining the time synchronization point, and executing event jumps to handle the execution of all target events corresponding to that time synchronization point. During the execution of target events, the protocol processing module parses the dataset and, triggered by control commands, writes it to the digital-to-analog converter shared memory, thus triggering an update to the power model's simulation process.

[0053] In this embodiment, the protocol application module and protocol stack convert the target analog signal into a dataset and protocol messages and send them to the virtual network, ensuring subsequent data transmission; the smart device interacts with the virtual network to complete data sampling and structure conversion, ensuring data adaptability; the protocol processing module parses the dataset to trigger the power model simulation update, ensuring the accuracy of the power model simulation data and the real-time process.

[0054] In summary, this application provides a method for implementing a time-synchronized non-real-time hybrid simulation system for power cyber-physical systems. By unifying time synchronization and simulation progress, a non-real-time hybrid simulation system for power CPS is built, eliminating the inherent latency introduced by network communication devices, overcoming the scale limitations of real-time simulation (supporting >500 nodes), and achieving microsecond-level synchronization between continuous systems (power systems) and discrete systems (network communication systems). The microsecond-level synchronization mechanism ensures timestamp-driven asynchronous progress (jumping of OMNet++ event execution) and eliminates read / write conflicts using double-buffered shared memory. Furthermore, this application achieves transparent device mapping based on XML-configured dynamic binding between power and communication devices, supporting complex 1:N mapping relationships.

[0055] Therefore, the technical solution of this application is applicable to power companies, energy management agencies, smart grid operators, and research institutions engaged in power system design, testing, and optimization. It can be used for smart grid security attack and defense drills, new energy power plant grid connection communication verification, distribution network self-healing control strategy testing, power IoT protocol compatibility testing, and substation automation system reliability assessment. It can support simulation of a one-year power grid operation scenario within 24 hours; hardware costs are reduced by 85% (from 2 million to 300,000 for general-purpose servers); and the development cycle is shortened by 70% (from 12 months to 3.5 months). Its application value can reduce the testing cycle of new energy power plants by 83% (from 3 months to 2 weeks) and reduce the cost of power grid attack and defense drills to 10% of traditional solutions.

[0056] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0057] Based on the same inventive concept, this application also provides a multi-platform hybrid power model simulation device for implementing the multi-platform hybrid power model simulation method described above. The solution provided by this device is similar to the implementation described in the above method. Therefore, the specific limitations in one or more embodiments of the multi-platform hybrid power model simulation device provided below can be found in the limitations of the multi-platform hybrid power model simulation method described above, and will not be repeated here.

[0058] In one embodiment, a multi-platform hybrid power model simulation device is provided, comprising: a first shared memory write module, a second shared memory update module, and a power model simulation module, wherein: The first shared memory writing module is used to determine the next time synchronization point during the current simulation of the power model, and write the associated state signals and time synchronization points of the power model into the first shared memory.

[0059] The second shared memory update module is used to trigger the discrete system to advance the simulation according to the time synchronization point, and update the second shared memory according to the target digital signal read from the first shared memory.

[0060] The power model simulation module is used to read the target simulation signal from the second shared memory associated with the discrete system and continue the power model simulation based on the target simulation signal.

[0061] The various modules in the aforementioned multi-platform hybrid power model simulation can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the corresponding operations of each module.

[0062] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 7 As shown, this computer device includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores digital and analog signals. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a multi-platform hybrid power model simulation method.

[0063] Those skilled in the art will understand that Figure 7The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0064] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0065] In one embodiment, a computer-readable storage medium is provided storing a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0066] In one embodiment, a computer program product or computer program is provided, the computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and executes the computer instructions, causing the computer device to perform the steps in the above method embodiments.

[0067] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0068] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0069] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A multi-platform hybrid power model simulation method, characterized in that, The multi-platform approach includes continuous and discrete systems, and the method is applied to continuous systems, including: Determine the next time synchronization point during the current simulation of the power model, and write the state signal associated with the power model and the time synchronization point into the first shared memory; The discrete system is triggered to perform simulation progress according to the time synchronization point, and the second shared memory is updated according to the target digital signal read from the first shared memory; The target analog signal is read from the second shared memory associated with the discrete system, and the simulation of the power model continues based on the target analog signal.

2. The method according to claim 1, characterized in that, The multi-platform also includes a coordination controller; the method further includes: Send semaphores for inter-process communication to the coordination controller; When the discrete system detects the occurrence of the signal, it triggers the discrete system to perform simulation progress according to the time synchronization point and sends an acknowledgment signal to the coordinating controller. When an acknowledgment signal is received from the coordinating controller, the target analog signal is read from the second shared memory.

3. The method according to claim 2, characterized in that, After sending semaphores for inter-process communication to the coordination controller, the execution process of the coordination controller includes: Non-blocking detection is performed using the semaphore. When the first shared memory is in an idle state, a time advance instruction is issued to the discrete system. Based on a preset waiting mechanism, the confirmation signal of the discrete system feedback is determined.

4. The method according to claim 3, characterized in that, The determination of the acknowledgment signal fed back by the discrete system based on the preset waiting mechanism includes: Start the high-precision timer and determine the absolute time point; Non-blocking polling monitoring is performed based on the absolute time point to determine the average delay when the feedback from the discrete system is obtained. The waiting time is dynamically adjusted based on the average delay to determine the confirmation signal fed back by the discrete system based on the waiting time.

5. The method according to claim 1, characterized in that, Triggering the discrete system to perform simulation progression according to the stated time synchronization point, and updating the second shared memory based on the target digital signal read from the first shared memory, including: Pause the current event processing of the discrete system and determine the target event corresponding to the time synchronization point; Read the target digital signal associated with the target event from the first shared memory, and trigger the discrete system to execute the target event to obtain the execution result; Update the second shared memory associated with the discrete system based on the execution result.

6. The method according to any one of claims 1 to 5, characterized in that, The scheduling of the first shared memory and the second shared memory is implemented through a memory manager; The first shared memory represents the shared memory that the analog signal is written to according to the mapping file configuration after analog-to-digital conversion, realizing the writing of analog signals in continuous systems and the reading of digital signals in discrete systems; The second shared memory represents the shared memory that is written to after digital signals are converted from digital to analog according to the mapping file configuration, enabling the writing of digital signals to discrete systems and the reading of analog signals to continuous systems.

7. A multi-platform hybrid power model simulation system, characterized in that, The system includes a continuous system, a discrete system, a first shared memory, and a second shared memory, wherein: A continuous system is used to determine the next time synchronization point during the current simulation of the power model, and writes the state signal associated with the power model and the time synchronization point into the first shared memory; A discrete system for performing simulation progression according to the time synchronization point and updating the second shared memory based on the target digital signal read from the first shared memory; The continuous system is also used to read the target analog signal from the second shared memory associated with the discrete system and to continue the simulation of the power model based on the target analog signal.

8. The system according to claim 7, characterized in that, The system also includes a protocol application module, a protocol stack, a virtual network, smart devices, and a protocol processing module, wherein: The protocol application module and protocol stack are used to convert the target analog signal into a dataset and protocol messages, respectively, and send them to the virtual network; The intelligent device is used to interact with the virtual network and perform data sampling and structure transformation; The protocol processing module is used to parse the dataset and trigger the simulation process update of the power model.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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