Semiconductor device preparation method

Abstract

The invention relates to the technical field of semiconductors, and provides a semiconductor device preparation method which is used for forming a through hole in a glass substrate. The hard mask layer is stacked on one side of the glass substrate, and the hard mask is made of a high-stability material, so that the structure of the hard mask layer is stable, the etching rate of the hard mask layer in the dry etching process is low, and the selection ratio of the hard mask layer relative to the glass substrate is higher. Therefore, the depth of the through hole processed on the glass substrate can be relatively deeper. In the through hole forming process, the flow of physical etching gas in the dry etching process is gradually reduced. By reducing the flow of the physical etching gas, the ion bombardment energy of the physical etching gas can be reduced, so that the generation of micro-grooves in the side wall and the bottom of the through hole by the physical etching gas can be relieved to a certain extent, and the flatness of the side wall and the bottom of the through hole of the glass substrate is better.

Description

Technical Field

[0001] This application relates to a method for fabricating a semiconductor device, belonging to the field of semiconductor technology. Background Technology

[0002] Through-Glass Via (TGV) technology is based on insulating glass substrates (commonly silicate glass or borosilicate glass). Micron-sized vias (typically 5-50 μm in diameter) are formed on the glass substrate, and then a conductive layer is deposited on the via walls through metallization treatment (such as electroplating copper / aluminum) to ultimately form a vertical electrical path.

[0003] Currently, glass through-hole technology uses laser drilling, plasma etching, or chemical etching. However, the through-holes formed by these methods have a large taper, resulting in irregular shapes and structures, affecting the uniformity of metal deposition within the through-holes, and ultimately leading to poor electrical performance of the glass substrate. Summary of the Invention

[0004] This application provides a method for fabricating a semiconductor device to solve the problem of poor electrical performance of glass substrates in related technologies.

[0005] To achieve the above objectives, this application adopts the following technical solution:

[0006] This application provides a method for fabricating a semiconductor device, including:

[0007] Provide glass substrates;

[0008] A hard mask layer is formed, the hard mask layer is located on one side surface of the glass substrate in the thickness direction, the hard mask layer has a hard mask hole extending along the thickness direction of the glass substrate, the hard mask hole penetrates the hard mask layer;

[0009] Through a dry etching process, through holes are formed on the glass substrate along the extension direction of the hard mask holes, and the through holes are connected to the hard mask holes.

[0010] The process gas used in the dry etching process includes physical etching gas;

[0011] The dry etching process includes: using the physical etching gas to etch the via, and gradually decreasing the flow rate of the physical etching gas as the depth of the via gradually increases.

[0012] In some embodiments, as the depth of the via gradually increases, the physical etching gas has a first flow rate, a second flow rate, a third flow rate, and a fourth flow rate, wherein the first flow rate, the second flow rate, the third flow rate, and the fourth flow rate decrease sequentially.

[0013] In some embodiments, the physical etching gas flow rate is maintained at the first flow rate for a first duration, the physical etching gas flow rate is maintained at the second flow rate for a second duration, the physical etching gas flow rate is maintained at the third flow rate for a third duration, and the physical etching gas flow rate is maintained at the fourth flow rate for a fourth duration.

[0014] The first duration, the second duration, the third duration, and the fourth duration are all equal.

[0015] In some implementations, the first duration is 400-600 seconds.

[0016] In some embodiments, the physical etching gas includes argon gas, and the flow rate of the physical etching gas is 600 sccm-900 sccm.

[0017] In some embodiments, the process gas also includes a chemical etching gas.

[0018] In some embodiments, the chemical etching gas includes octafluorocyclobutane.

[0019] In some embodiments, the flow rate of the chemical etching gas is 6 sccm-15 sccm.

[0020] In some embodiments, the process gas also includes a cleaning gas.

[0021] In some embodiments, as the depth of the through-hole gradually increases, the cleaning gas has a fifth flow rate, a sixth flow rate, and a seventh flow rate, which increase sequentially.

[0022] In some embodiments, when the flow rate of the physical etching gas is the first flow rate and the second flow rate, the flow rate of the cleaning gas is the fifth flow rate;

[0023] When the flow rate of the physical etching gas is the third flow rate, the flow rate of the cleaning gas is the sixth flow rate;

[0024] When the flow rate of the physical etching gas is the fourth flow rate, the flow rate of the cleaning gas is the seventh flow rate.

[0025] In some embodiments, the cleaning gas includes oxygen, and the flow rate of the cleaning gas is 8 sccm-20 sccm.

[0026] In some embodiments, forming the hard mask layer includes:

[0027] A hard mask preform layer is provided on one side surface of the glass substrate in the thickness direction;

[0028] A photomask layer is disposed on the side of the hard mask preform layer facing away from the glass substrate. The photomask layer has a photomask hole that penetrates the photomask layer along the thickness direction of the glass substrate.

[0029] The hard mask aperture is formed on the hard mask blank layer along the photolithographic mask aperture using a dry etching process.

[0030] In some embodiments, after forming through-holes on the glass substrate using a dry etching process, the semiconductor device fabrication method further includes:

[0031] Clean the glass substrate.

[0032] In some embodiments, the glass substrate is repeatedly formed by dry etching and the glass substrate is cleaned.

[0033] In some embodiments, the ratio of the depth of the via to the thickness of the hard mask layer is greater than or equal to 8 and less than or equal to 14.

[0034] In the semiconductor device fabrication method provided in this application, a hard mask layer is disposed on the first side of a glass substrate, such that the hard mask layer and the glass substrate are stacked along the thickness direction of the glass substrate. The hard mask apertures of the hard mask layer extend along the thickness direction of the glass substrate, and one opening of the hard mask aperture is located on the side of the hard mask layer opposite to the glass substrate. The hard mask apertures play a positioning role in the dry etching process, allowing processing of the glass substrate from one side surface along the thickness direction through the hard mask apertures to form through-holes, thus obtaining a glass substrate with through-holes. The hard mask is made of a highly stable material, making the hard mask layer structurally stable. This results in a lower etching rate for the hard mask layer during the dry etching process, and a higher selectivity of the hard mask layer relative to the glass substrate. Consequently, the depth of the through-holes processed on the glass substrate can be relatively deeper, thereby improving the vertical interconnect capability of the semiconductor device fabricated by the semiconductor device fabrication method of this application. During the through-hole formation process, the flow rate of the physical etching gas in the dry etching process gradually decreases. By reducing the flow rate of the physical etching gas, the ion bombardment energy of the physical etching gas can be reduced, which can alleviate the formation of microgrooves on the sidewalls and bottom of the via to a certain extent, resulting in better flatness of the sidewalls and bottom of the via in the glass substrate. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 A flowchart of a semiconductor device fabrication method provided in the embodiments of this application;

[0037] Figure 2 This is one of the structural diagrams of the semiconductor device fabrication method provided in the embodiments of this application;

[0038] Figure 3 This is a second structural diagram of the semiconductor device fabrication method provided in the embodiments of this application;

[0039] Figure 4 This is the third structural diagram of the semiconductor device fabrication method provided in the embodiments of this application;

[0040] Figure 5 The fourth structural diagram of the semiconductor device fabrication method provided in the embodiments of this application;

[0041] Figure 6 The fifth structural diagram of the semiconductor device fabrication method provided in the embodiments of this application;

[0042] Figure 7 This is the sixth structural diagram of the semiconductor device fabrication method provided in the embodiments of this application.

[0043] Explanation of reference numerals in the attached figures:

[0044] 100 - Glass substrate; 110 - Through hole;

[0045] 200 - Hard mask layer; 210 - Hard mask aperture; 200a - Hard mask blank layer;

[0046] 300 - Photolithography mask layer; 310 - Photolithography mask hole. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0048] Through-Glass Via (TGV) technology is based on insulating glass substrates (commonly silicate glass or borosilicate glass). Micron-sized vias (typically 5-50 μm in diameter) are formed on the glass substrate, and then a conductive layer is deposited on the via walls through metallization treatment (such as electroplating copper / aluminum) to ultimately form a vertical electrical path.

[0049] Currently, glass through-hole technology uses laser drilling, plasma etching, or chemical etching. However, the through-holes formed by these methods have a large taper, resulting in irregular shapes and structures, affecting the uniformity of metal deposition within the through-holes, and ultimately leading to poor electrical performance of the glass substrate.

[0050] In the semiconductor device fabrication method proposed in this application, a hard mask layer is disposed on the first side of a glass substrate, such that the hard mask layer and the glass substrate are stacked along the thickness direction of the glass substrate. The hard mask apertures of the hard mask layer extend along the thickness direction of the glass substrate, and one side of the hard mask aperture is located on the side of the hard mask layer opposite to the glass substrate. The hard mask apertures play a positioning role in the dry etching process, allowing processing of the glass substrate from one side surface along the thickness direction through the hard mask apertures to form through-holes, thus obtaining a glass substrate with through-holes. The hard mask is made of a highly stable material, resulting in a stable structure and a lower etching rate during the dry etching process, and a higher selectivity of the hard mask layer relative to the glass substrate. Therefore, the depth of the through-holes processed on the glass substrate can be relatively deeper, thereby improving the vertical interconnect capability of the semiconductor device fabricated by the method of this application. During the through-hole formation process, the flow rate of the physical etching gas in the dry etching process gradually decreases. By reducing the flow rate of the physical etching gas, the ion bombardment energy of the physical etching gas can be reduced, which can alleviate the formation of microgrooves on the sidewalls and bottom of the via to a certain extent, resulting in better flatness of the sidewalls and bottom of the via in the glass substrate.

[0051] The contents of this application will now be described in detail with reference to the accompanying drawings, so that those skilled in the art can have a clearer and more detailed understanding of the contents of this application.

[0052] This application discloses a method for fabricating a semiconductor device, which can produce a glass substrate with deep through-holes. The method includes the following steps:

[0053] refer to Figure 1 and Figure 2 As shown, S100 provides a glass substrate.

[0054] The glass substrate 100 has a first side and a second side that are opposite to each other in its thickness direction.

[0055] The glass substrate 100 exhibits high stability, high surface flatness, and a low coefficient of thermal expansion, enabling it to maintain structural stability during subsequent processing. Specifically, the glass substrate 100 can be made of borosilicate glass, quartz glass, or soda-lime glass.

[0056] When borosilicate glass is used for the glass substrate 100, the coefficient of thermal expansion of the glass substrate 100 is lower, thereby reducing the thermal stress generated in the glass substrate 100 during the manufacturing process. In addition, borosilicate glass also has better chemical stability.

[0057] When quartz glass is used for the glass substrate 100, the coefficient of thermal expansion of the glass substrate 100 is lower, thereby reducing the thermal stress generated in the glass substrate 100 during the manufacturing process. In addition, the quartz glass substrate 100 also has high light transmittance and good high-temperature resistance.

[0058] When the glass substrate 100 is made of soda-lime glass, the cost of the glass substrate 100 can be relatively low, thereby reducing the manufacturing cost of the semiconductor device of this application.

[0059] refer to Figure 6 As shown, in step S200, a hard mask layer is formed, which is located on one side surface of the glass substrate in the thickness direction.

[0060] Specifically, the hard mask layer 200 can be disposed on the first side of the substrate, so that the hard mask layer 200 can be stacked on the glass substrate 100.

[0061] The hard mask layer 200 has a hard mask hole 210 that extends through the hard mask layer 200 along the thickness direction of the glass substrate 100. Specifically, one end of the hard mask hole 210 is located on the side of the hard mask layer 200 away from the glass substrate 100, and the other end of the hard mask hole 210 extends into the glass substrate 100. The hard mask hole 210 exposes the portion of the glass substrate 100 opposite to the hard mask hole 210, and the other components of the hard mask layer 200, except for the hard mask hole 210, can protect the glass substrate 100 and prevent the misalignment between the glass substrate 100 and the hard mask hole 210 from being affected in subsequent processes.

[0062] refer to Figure 7 As shown, S300 forms a through hole on the glass substrate along the extension direction of the hard mask hole using a dry etching process. The through hole is connected to the hard mask hole.

[0063] Since the hard mask layer 200 has hard mask holes 210, through-holes 110 are formed on the glass substrate 100 along the hard mask holes 210 using a dry etching process, making the through-holes 110 connected to the hard mask holes 210. This ensures that other parts of the glass substrate 100 that are misaligned with the hard mask holes 210 are not affected by the dry etching process. Therefore, the inner diameter of the through-holes 110 on the glass substrate 100 can be determined by the inner diameter of the hard mask holes 210. When the outer diameter of the hard mask holes 210 is larger, the inner diameter of the through-holes 110 formed by the dry etching process can be set to be larger; when the outer diameter of the hard mask holes 210 is smaller, the inner diameter of the through-holes 110 formed by the dry etching process can be set to be smaller.

[0064] It should be understood that the hard mask layer 200 has a high melting point and stability. By setting the hard mask layer 200, the hard mask layer 200 is less affected by the dry etching process, which can increase the etching selectivity.

[0065] In this application, the process gas used in the dry etching process includes a physical etching gas. After the physical etching gas is delivered to the hard mask hole 210 of the hard mask layer 200, it can etch the portion of the glass substrate 100 opposite to the hard mask hole 210 to form a via 110. During the physical etching process of the glass substrate 100, the depth of the via 110 gradually increases during the dry etching process.

[0066] It should be understood that although the intense physical etching of the dry etching process can make the inner wall of the via 110 steep and increase the etching rate, the excessively high ion bombardment energy can easily generate microgrooves on the sidewalls and bottom of the via 110, resulting in abnormal etching morphology of the via 110, which has a significant impact on the performance and reliability of subsequent devices.

[0067] In this application, as the depth of the via 110 is gradually increased through a dry etching process, the flow rate of the physical etching gas is gradually reduced. By reducing the flow rate of the physical etching gas, the ion bombardment energy of the physical etching gas can be reduced, thereby mitigating the formation of microgrooves on the sidewalls and bottom of the via 110 to a certain extent, resulting in better flatness of the sidewalls and bottom of the via 110 in the glass substrate 100.

[0068] Specifically, by reducing the flow rate of the physical etching gas, the mean free path of the physical etching gas separation is increased, reducing the probability of collision between the physical etching gas and the inner wall of the via 110. Furthermore, reducing the flow rate of the physical etching gas also reduces turbulence generated by the gas, stabilizes the sheath electric field, thereby increasing the proportion of vertically incident ions in the physical etching gas, concentrating energy, and reducing random bombardment of the sidewalls by ions in the physical etching gas.

[0069] Therefore, by reducing the flow rate of the physical etching gas, the bottom and sidewalls of the via 110 of the glass substrate 100 can be made flatter, and the verticality of the sidewalls of the via 110 can be better.

[0070] In some embodiments, the physical etching gas used in the dry etching process of this application is argon, which is an inert gas. Argon is ionized into high-energy argon ions in plasma and bombards the surface of the glass substrate 100 in a vertical direction. The chemical bonds of the glass substrate 100 are broken through kinetic energy transfer, thereby achieving physical sputtering etching.

[0071] Argon ions have a large mass and a high collision cross-section, which can maintain the stability of plasma discharge and avoid uneven etching rates caused by process fluctuations. Therefore, by using argon as the physical etching gas, the lateral drilling of the physical etching gas toward the sidewall of the aperture can be significantly suppressed, and the etching verticality of the via 110 can be improved (up to 89° or more), so that the via 110 can have a high aspect ratio structure.

[0072] In some embodiments, during the process of processing through holes 110 on glass substrate 100 using a dry etching process with physical etching gas, and as the depth of through holes 110 gradually increases, the physical etching gas has a first flow rate, a second flow rate, a third flow rate, and a fourth flow rate, which decrease sequentially.

[0073] Specifically, when the via 110 has not yet been formed on the glass substrate 100, the flow rate of the physical etching gas can be set to a first flow rate, so that the physical etching gas begins to etch the glass substrate 100 at the first flow rate. As the depth of the via 110 increases, the flow rate of the physical etching gas decreases to a second flow rate. As the depth of the via 110 continues to increase, the flow rate of the physical etching gas can continue to decrease to a third flow rate, and when the via 110 further increases in size, the flow rate of the physical etching gas decreases to a fourth flow rate, until the depth of the via 110 reaches the required level, and the etching of the via 110 is completed.

[0074] In this way, the flow rate of the physical etching gas can gradually decrease as the depth of the through hole 110 increases, resulting in better flatness of the bottom and side walls of the through hole 110 and better verticality of the side walls of the through hole 110.

[0075] In some embodiments, the physical etching gas flow rate is maintained at the first flow rate for a first duration, at the second flow rate for a second duration, at the third flow rate for a third duration, and at the fourth flow rate for a fourth duration. Since the first, second, third, and fourth durations are equal, the physical etching gas can etch the glass substrate 100 for the same duration at each of the first, second, third, and fourth flow rates. This allows the physical etching gas flow rate to change stably in a gradient, resulting in better flatness of the inner wall of the through-hole 110 and better verticality of the sidewalls of the through-hole 110 during etching of the glass substrate 100.

[0076] In some embodiments, the first time duration in this application is 400-600 seconds, and the corresponding second, third, and fourth time durations are also 400-600 seconds. This allows the physical etching gas to sufficiently etch the glass substrate 100 to form the via 110 at the first, second, third, and fourth flow rates, respectively. Furthermore, by setting the first, second, third, and fourth time durations to 400-600 seconds, over-etching of the glass substrate 100 by the physical etching gas can be avoided, which could result in poor flatness of the inner wall and perpendicularity of the sidewalls of the via 110.

[0077] Specifically, the first, second, third, and fourth durations are all 500 seconds.

[0078] In some implementations, the flow rate of the physical etching gas is 600 sccm-900 sccm.

[0079] In some embodiments, the process gas used in the dry etching process of this application also includes a chemical etching gas. After the chemical etching gas is delivered to the hard mask hole 210 of the hard mask layer 200, it can etch the portion of the glass substrate 100 body opposite to the hard mask hole 210 to form a via 110. During the chemical etching process of the glass substrate 100, the depth of the via 110 gradually increases during the dry etching process.

[0080] In this process, after the chemical etching gas is delivered into the hard mask hole 210 of the hard mask layer 200, the chemical etching gas of the plasma reacts chemically with the surfaces of the glass substrate 100 and the hard mask hole 210, thereby selectively removing the glass substrate 100 by generating volatile byproducts. This allows the portion of the glass substrate 100 and the hard mask hole 210 that are opposite each other to form the through hole 110.

[0081] Specifically, the active free radicals generated by the plasma-activated chemical etching gas react chemically with the glass substrate 100 to produce volatile products, which are then extracted, thereby forming the through-hole 110. The chemical etching gas is a fluorine-based gas, which dissociates in the plasma to generate highly active fluorine free radicals. These free radicals react with silicon dioxide, the main component of the glass substrate 100, to generate volatile silicon tetrafluoride. The reaction product, silicon tetrafluoride, has a low boiling point, specifically -86°C, and can be rapidly extracted by a vacuum system, achieving partial selective removal of the glass substrate 100 relative to the hard mask hole 210.

[0082] In some embodiments, the chemical etching gas of this application includes octafluorocyclobutane. Octafluorocyclobutane has a high carbon content, which promotes the deposition of carbon-containing polymers, such as difluoride groups, generated by the reaction of octafluorocyclobutane with the glass substrate 100 on the sidewalls of the via 110, forming a passivation protective layer. This inhibits the chemical etching gas from laterally etching the sidewalls of the via 110, thereby improving the perpendicularity and flatness of the sidewalls of the via 110. Furthermore, the carbon-containing polymer generated by the reaction of octafluorocyclobutane with the glass substrate 100 is thicker, providing more adequate protection for the sidewalls of the via 110.

[0083] Specifically, argon gas can bombard and break the surface bond energy of silicon dioxide in the glass substrate 100. Subsequently, the free radicals of octafluorocyclobutane can react rapidly with the glass substrate 100, and the resulting carbon-containing sidewall polymer can suppress lateral etching to protect the sidewalls of the via 110, thereby improving the perpendicularity of the sidewalls of the via 110.

[0084] When etching high aspect ratio structures, such as narrow trenches in optical waveguides, the carbon-containing polymer generated by the reaction of octafluorocyclobutane with the glass substrate 100 can balance the etching rate difference between the wide and narrow trenches and reduce the loading effect.

[0085] In some embodiments, the flow rate of the chemical etching gas in this application can be set from 6 sccm to 15 sccm, which makes the flatness of the inner wall and the perpendicularity of the sidewall of the through hole 110 formed by the chemical etching gas etching the glass substrate 100 better.

[0086] Specifically, when the flow rate of the chemical etching gas exceeds 15 sccm, the excessive flow rate and velocity of the chemical etching gas can lead to localized turbulence within the via 110. This results in uneven distribution of the chemical etching gas within the via 110, causing the sidewalls of the via 110 to tilt and reducing its verticality, or the bottom of the via 110 to become uneven and reduce its flatness. Furthermore, an excessively high flow rate of the chemical etching gas also leads to greater consumption of the chemical etching gas, thereby increasing the cost of the semiconductor device fabrication method described in this application.

[0087] When the flow rate of the chemical etching gas is less than 6 sccm, the flow rate is too low, resulting in insufficient supply of active free radicals, a decrease in the reaction rate, and an inability to reach the target etching depth. Insufficient flow rate of the chemical etching gas can also lead to the retention of volatile byproducts, such as silicon tetrafluoride, on the surface of the via 110, forming a micromasking or "black silicon" effect, causing byproducts from the etching process to remain inside the via 110.

[0088] In some embodiments, the process gas for the dry etching process in this application also includes a cleaning gas. It should be understood that when the glass substrate 100 is etched by an optical etching gas, fluoropolymers may adhere to the inner walls of the vias 110 of the glass substrate 100. These polymers, after adhering to the inner walls of the vias 110, will form a redeposition layer, thereby affecting the escape of byproducts generated during the dry etching process of the glass substrate 100.

[0089] The cleaning gas can react with the fluoropolymer to remove it, preventing the fluoropolymer from adhering to the inner wall of the through-hole 110 and allowing byproducts generated during the dry etching process of the glass substrate 100 to escape sufficiently. Specifically, the cleaning gas may include oxygen.

[0090] In some embodiments, during the process of machining through holes 110 on glass substrate 100 using a dry etching process with physical etching gas, and as the depth of the through holes 110 gradually increases, the cleaning gas has a fifth flow rate, a sixth flow rate, and a seventh flow rate, which increase sequentially.

[0091] Specifically, when the via 110 is first formed on the glass substrate 100, the flow rate of the cleaning gas can be set to the fifth flow rate, so that the cleaning gas begins to react with the polymer inside the via 110 at the fifth flow rate. As the depth of the via 110 increases, the cleaning flow rate increases to the sixth flow rate. As the depth of the via 110 continues to increase, the flow rate of the cleaning gas can continue to increase to the seventh flow rate, until the depth of the via 110 reaches the required level, and the etching of the via 110 is completed.

[0092] In this way, the flow rate of the cleaning gas can gradually increase as the depth of the through hole 110 increases, so that the polymer generated in the through hole 110 can be more fully reacted and decomposed, resulting in better flatness of the bottom wall and side wall of the through hole 110, and better verticality of the side wall of the through hole 110.

[0093] In some embodiments, when the flow rate of the physical etching gas in this application is a first flow rate and a second flow rate, the flow rate of the cleaning gas is a fifth flow rate. When the flow rate of the physical etching gas in this application is a third flow rate, the flow rate of the cleaning gas is a sixth flow rate. When the flow rate of the physical etching gas in this application is a fourth flow rate, the flow rate of the cleaning gas is a seventh flow rate.

[0094] Specifically, the cleaning gas maintains its fifth flow rate for a longer period than it maintains its sixth and seventh flow rates. This prevents the cleaning gas flow rate from being too high in the initial stage of forming the vias 110 in the glass substrate 100, which could affect the etching effect of the physical and chemical etching gases on the glass substrate 100. As the depth of the vias 110 in the glass substrate 100 gradually increases, the amount of polymer generated within the vias 110 increases, and the oxygen flow rate can be gradually increased, allowing the polymer within the vias 110 to react and decompose sufficiently.

[0095] In some embodiments, the flow rate of the cleaning gas in this application can be set to 8 sccm-20 sccm. By setting the flow rate of the cleaning gas to 8 sccm-20 sccm, it is possible to avoid the cleaning gas flow rate being too large, which would prevent the physical etching gas and chemical etching gas from being insufficient, and it is also possible to avoid the cleaning gas flow rate being too small, which would prevent the polymer in the through hole 110 from being fully reacted and decomposed.

[0096] In some embodiments, in order to form a hard mask layer 200 on the first side of the glass substrate 100, the semiconductor device fabrication method of this application may further include:

[0097] refer to Figure 3 As shown in S210, a hard mask preform layer is provided on the first side of the glass substrate.

[0098] Specifically, the hard mask blank layer 200a is an integral structure, and no hard mask hole 210 structure is opened on the hard mask blank layer 200a.

[0099] refer to Figure 4 As shown in S220, a photomask layer is provided on the side of the hard mask preform layer facing away from the glass substrate. The photomask layer has a photomask hole, which penetrates the photomask layer along the thickness direction of the glass substrate.

[0100] Specifically, the photomask layer 300 can be photoresist, and photomask holes 310 are formed on the photomask layer 300 by photolithography.

[0101] refer to Figure 5 As shown in S230, a hard mask hole is formed on the hard mask material layer along the photolithographic mask hole by a dry etching process to form a hard mask layer.

[0102] The thickness of the photomask layer 300 can be determined based on the selectivity ratio of the photomask layer 300 to the hard mask preform layer 200a. Specifically, the greater the selectivity ratio of the hard mask preform layer 200a to the photomask layer 300, the greater the thickness of the photomask layer 300, and vice versa.

[0103] refer to Figure 6 As shown, S240 is used to clean the photolithography mask layer.

[0104] In some embodiments, after the via 110 is formed on the glass substrate 100 by the semiconductor device fabrication method of this application, the semiconductor device fabrication method of this application may further include:

[0105] S400 cleans the glass substrate.

[0106] It should be understood that during the formation of vias 110 on the glass substrate 100 using a dry etching process, the physical etching gas and chemical etching gas may react with the glass substrate 100 to generate non-volatile byproducts, such as polymers or unreacted residual photoresist. If these byproducts are not removed, they may hinder subsequent processes, such as metal deposition, bonding, or photolithography, leading to short circuits, poor contact, or delamination problems in the semiconductor devices of this application.

[0107] Specifically, the through-hole 110 can be cleaned using a dry cleaning process. This process removes residual photoresist within the through-hole 110 through plasma bombardment. The plasma oxygen reacts chemically with the organic matter within the through-hole 110, and the synergistic effect of both processes efficiently removes byproducts. Compared to chemical wet cleaning processes, this avoids the introduction of secondary contaminants and improves the cleanliness of the through-hole 110.

[0108] In some embodiments, the semiconductor device fabrication method of this application further includes:

[0109] The S500 cycles through a dry etching process to form vias on a glass substrate and a dry cleaning process to clean the glass substrate.

[0110] By performing multiple dry etching processes on the glass substrate 100, the depth of the via 110 can be gradually increased until the target depth is reached. After each dry etching process, the glass substrate 100 is cleaned using a dry cleaning process to prevent excessive byproducts within the via 110. This further improves the flatness of the inner wall of the via 110 and the perpendicularity of its sidewalls.

[0111] In some embodiments, the thickness of the hard mask layer 200 can be determined based on the target depth of the via 110 in the glass substrate 100. The ratio of the depth of the via 110 in the glass substrate 100 to the thickness of the hard mask layer 200 is greater than or equal to 8 and less than or equal to 14.

[0112] Specifically, the deeper the via 110 needs to be fabricated on the glass substrate 100, the greater the thickness of the hard mask layer 200 needs to be. When the ratio of the depth of the via 110 to the thickness of the hard mask layer 200 is less than 8, the depth of the via 110 cannot reach the target depth. When the ratio is greater than 14, the thickness of the hard mask layer 200 is too large, resulting in excessively high costs for the semiconductor fabrication method of this application.

[0113] It should be noted that the terms "one embodiment," "embodiment," "exemplary embodiment," "some embodiments," etc., mentioned in the specification indicate that the described embodiment may include a specific feature, structure, or characteristic, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the knowledge scope of those skilled in the art.

[0114] Generally speaking, terms should be understood at least in part by their use in context. For example, at least in part by context, the term "one or more" as used in the text can be used to describe any feature, structure, or characteristic of the singular meaning, or a combination of features, structures, or characteristics of the plural meaning. Similarly, at least in part by context, terms such as "a" or "the" can also be understood to convey either singular or plural usage.

[0115] It should be readily understood that the terms “on,” “above,” and “on top of” in this application should be interpreted in the broadest possible sense, such that “on” means not only “directly on something” but also “on something” with an intermediate feature or layer therebetween, and that “above” or “on top of” means not only “on something” but also “on something” without an intermediate feature or layer therebetween (i.e., directly on something).

[0116] Furthermore, for ease of explanation, spatially relative terms such as "below," "below," "under," "above," and "above" may be used to describe the relationship of one element or feature relative to other elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation other than those shown in the figures. The device may have other orientations (rotated 90° or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0117] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: Provide a glass substrate (100); A hard mask layer (200) is formed, the hard mask layer (200) is located on one side surface of the glass substrate (100) in the thickness direction, the hard mask layer (200) has a hard mask hole (210) extending in the thickness direction of the glass substrate (100), the hard mask hole (210) penetrates the hard mask layer (200). Through a dry etching process, a through hole (110) is formed on the glass substrate (100) along the extension direction of the hard mask hole (210), and the through hole (110) is connected to the hard mask hole (210). The process gas used in the dry etching process includes physical etching gas; The dry etching process includes: using the physical etching gas to etch the through hole (110), and gradually increasing the depth of the through hole (110) while gradually decreasing the flow rate of the physical etching gas.

2. The semiconductor device fabrication method according to claim 1, characterized in that, As the depth of the through hole (110) gradually increases, the physical etching gas has a first flow rate, a second flow rate, a third flow rate, and a fourth flow rate, which decrease sequentially.

3. The semiconductor device fabrication method according to claim 2, characterized in that, The physical etching gas flow rate is maintained at the first flow rate for a first duration, the physical etching gas flow rate is maintained at the second flow rate for a second duration, the physical etching gas flow rate is maintained at the third flow rate for a third duration, and the physical etching gas flow rate is maintained at the fourth flow rate for a fourth duration. The first duration, the second duration, the third duration, and the fourth duration are all equal.

4. The semiconductor device fabrication method according to claim 3, characterized in that, The first duration is 400-600 seconds.

5. The semiconductor device fabrication method according to claim 4, characterized in that, The physical etching gas includes argon gas, and the flow rate of the physical etching gas is 600 sccm-900 sccm.

6. The method for fabricating a semiconductor device according to any one of claims 1-5, characterized in that, The process gases also include chemical etching gases.

7. The semiconductor device fabrication method according to claim 6, characterized in that, The chemical etching gas includes octafluorocyclobutane; and / or... The flow rate of the chemical etching gas is 6 sccm-15 sccm.

8. The method for fabricating a semiconductor device according to any one of claims 2-5, characterized in that, The process gas also includes a cleaning gas; as the depth of the through hole (110) gradually increases, the cleaning gas has a fifth flow rate, a sixth flow rate and a seventh flow rate, which increase sequentially.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, When the flow rate of the physical etching gas is the first flow rate and the second flow rate, the flow rate of the cleaning gas is the fifth flow rate; When the flow rate of the physical etching gas is the third flow rate, the flow rate of the cleaning gas is the sixth flow rate; When the flow rate of the physical etching gas is the fourth flow rate, the flow rate of the cleaning gas is the seventh flow rate.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, The cleaning gas includes oxygen, and the flow rate of the cleaning gas is 8 sccm-20 sccm.

11. The method for fabricating a semiconductor device according to any one of claims 1-5, characterized in that, The formation of the hard mask layer (200) includes: A hard mask preform layer (200a) is provided on one side surface of the glass substrate (100) in the thickness direction. A photomask layer (300) is provided on the side of the hard mask preform layer (200a) facing away from the glass substrate (100). The photomask layer (300) has a photomask hole (310) that penetrates the photomask layer (300) along the thickness direction of the glass substrate (100). The hard mask hole (210) is formed on the hard mask blank layer (200a) along the photolithographic mask hole (310) using a dry etching process.

12. The method for fabricating a semiconductor device according to any one of claims 1-5, characterized in that, The ratio of the depth of the via (110) to the thickness of the hard mask layer (200) is greater than or equal to 8 and less than or equal to 14.

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