Manufacturing method of semiconductor device

Abstract

The invention relates to the technical field of semiconductors, and provides a manufacturing method of a semiconductor device. The manufacturing method comprises the steps that an edge area of a wafer is trimmed from a first face of the wafer to form a step, the step comprises a step face and a step side face, and the width of the step face is smaller than or equal to that of the edge area; forming a bonding layer on the first surface of the wafer and the side surface of the step so as to fix the wafer on the slide glass; wherein the step surface comprises a plurality of areas arranged along the circumferential direction of the wafer, and the contact area between a first area in the plurality of areas and the bonding layer is smaller than the contact area between a second area and the bonding layer; cutting an edge area where the first area is located from the second surface, wherein a notch extends from the second surface to the step surface; and performing a thinning process on the wafer from the second surface. According to the invention, the edge region where the first region is located is cut before the thinning process, so that the width of the step surface is reduced, the moment applied to the first region in the wafer thinning process is reduced, the risk of edge collapse is reduced, and the yield and reliability of chips are improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to methods for manufacturing semiconductor devices. Background Technology

[0002] The rise of 3D chip stacking is a significant trend in the semiconductor industry in recent years. 3D chip stacking, through 3D stacking technology and Through Silicon Via (TSV) technology, achieves bandwidth and low power consumption far exceeding traditional memory, driving the construction of next-generation computing platforms and meeting the development needs of artificial intelligence, high-performance computing, and advanced graphics processors. The back-side via exposure process is one of the key steps in stacked chip fabrication. In this process, insufficient step support at the wafer edge by the adhesive layer bonding the wafer and the carrier can lead to wafer edge collapse, affecting chip yield and reliability. Summary of the Invention

[0003] To address this issue, this disclosure provides a method for manufacturing a semiconductor device.

[0004] Some embodiments of this disclosure provide a method for manufacturing a semiconductor device, including: A wafer is provided, the wafer having opposing first and second sides; A step is formed by trimming the edge region of the wafer from the first surface; the step includes a step surface and a step side surface, the step surface connects to the side surface of the wafer, the width of the step surface is less than or equal to the width of the edge region, and the step side surface connects the step surface and the first surface; An adhesive layer is formed on the first surface of the wafer and the step side surface to fix the wafer onto a carrier; wherein the step surface includes a plurality of regions arranged along the circumference of the wafer, the plurality of regions including a first region and a second region, the contact area between the first region and the adhesive layer is smaller than the contact area between the second region and the adhesive layer; The edge area containing the first region is cut from the second surface, and the cut extends from the second surface to the stepped surface; the width of the first region after cutting is greater than or equal to zero and less than or equal to a preset value. The wafer is thinned from the second face.

[0005] In some embodiments, the cut first region is in contact with the adhesive layer at each location.

[0006] In some embodiments, cutting the edge region containing the first region from the second surface, with the cut extending from the second surface to the stepped surface, includes: Cut the edge area containing the first region from the second surface along the plane containing the side of the step to remove the first region.

[0007] In some embodiments, the manufacturing method further includes: Cut the edge area where the second region is located and the adhesive layer from the second surface along the plane where the side of the step is located, to remove the second region and the adhesive layer located on the side of the step.

[0008] In some embodiments, the cut is formed using a mechanical cutting process; Alternatively, if the plurality of regions includes the first region, the edge region is cut from the second face along the circumference of the wafer, and the step widths of the different regions after cutting are equal to each other.

[0009] In some embodiments, providing the wafer includes: A substrate is provided, and a plurality of through-conductive structures extending into the substrate are formed from a surface of the substrate. An integrated circuit layer and a first pad layer are sequentially formed on a surface of the substrate. The plurality of through-conductive structures are connected to the integrated circuit layer, and the integrated circuit layer is connected to the first pad layer. The thinning process performed on the wafer from the second surface includes: thinning the substrate from the opposite surface of the substrate to the other surface of the integrated circuit layer until the plurality of the through conductive structures are exposed.

[0010] Some embodiments of this disclosure also provide a method for manufacturing a semiconductor device, including: A wafer is provided, the wafer having opposing first and second sides; A step is formed by trimming the edge region of the wafer from the first surface; the step includes a step surface and a step side surface, the step surface connects to the side surface of the wafer, the width of the step surface is less than or equal to the width of the edge region, and the step side surface connects the step surface and the first surface; An adhesive layer is formed on the first surface of the wafer and the step side surface to fix the wafer onto a carrier; wherein the step surface includes a plurality of regions arranged along the circumference of the wafer, the plurality of regions including a first region and a second region, the contact area between the first region and the adhesive layer is smaller than the contact area between the second region and the adhesive layer; A modified layer is formed inside the edge region where the first area is located using a stealth cutting process; wherein, the modified layer has a first end and a second end opposite to each other in a direction perpendicular to the first surface, and the first end and the second end are respectively located on both sides of the plane where the step surface is located; The wafer is thinned from the second face.

[0011] In some embodiments, where the plurality of regions includes a first region, the modified layer is disposed around the wafer along the edge region of the wafer.

[0012] In some embodiments, providing the wafer includes: A substrate is provided, and a plurality of through-conductive structures extending into the substrate are formed from a surface of the substrate. An integrated circuit layer and a first pad layer are sequentially formed on a surface of the substrate. The plurality of through-conductive structures are connected to the integrated circuit layer, and the integrated circuit layer is connected to the first pad layer. The thinning process performed on the wafer from the second surface includes: thinning the substrate from the opposite surface of the substrate to the other surface of the integrated circuit layer until the plurality of the through conductive structures are exposed.

[0013] In some embodiments, the first end of the modified layer is close to the second surface; Before the thinning process is performed, the first distance between the first end of the modified layer and the second surface is smaller than the second distance between the end of the through conductive structure near the second surface and the second surface. During the thinning process, the modified layer is exposed.

[0014] In some embodiments, the manufacturing method further includes: A second pad layer is formed on the second side of the thinned wafer, and the second pad layer connects multiple through conductive structures; Remove the adhesive layer and the carrier sheet from the first side; The thinned wafer is then cut into multiple chips.

[0015] In the semiconductor device manufacturing method provided in this disclosure, during wafer bonding and wafer carrier bonding, the contact area between the first region of the step surface and the adhesive layer is smaller than the contact area between the second region and the adhesive layer. This may weaken the support of the adhesive layer for the first region, leading to edge collapse in the first region during wafer thinning in the back-side via exposure process, affecting chip yield and reliability. Therefore, in this embodiment, before thinning, a cutting process is performed on the edge region where the first region is located, extending the cut to the step surface. This reduces the width of the first region after cutting, decreases the torque on the first region during wafer thinning, lowers the risk of edge collapse, and improves chip yield and reliability. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a wafer after the back-side via exposure process is performed, as provided in an embodiment of this disclosure. Figure 2aA schematic diagram of an edge-trimmed wafer provided in an embodiment of this disclosure; Figure 2b for Figure 2a The diagram shown illustrates the process of exposing back-side vias on a wafer. Figure 3 A schematic diagram of wafer defects during the thinning process provided in this embodiment of the disclosure; Figure 4a This is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure; Figure 4b A schematic flowchart illustrating a specific implementation of the manufacturing method provided in this disclosure; Figure 4c A schematic flowchart illustrating another specific embodiment of the manufacturing method provided in this disclosure; Figure 5a A schematic diagram illustrating how an adhesive layer, provided in an embodiment of this disclosure, fixes a wafer to a carrier. Figure 5b This is a schematic diagram of the wafer edge region provided in an embodiment of the present disclosure; Figure 5c A schematic diagram of a thinned wafer provided in an embodiment of this disclosure; Figure 5d A schematic diagram showing the through-conductive structure exposed on the second surface according to an embodiment of this disclosure; Figure 5e This is a schematic diagram of the formation of the second pad layer provided in an embodiment of the present disclosure; Figure 5f This is a schematic diagram showing the slide facing upwards, provided in an embodiment of this disclosure. Figure 5g This is a schematic diagram showing the removal of the substrate and adhesive layer according to an embodiment of the present disclosure; Figure 5h This is a schematic diagram of the wafer with the second side facing upwards, provided in an embodiment of the present disclosure; Figure 5i A schematic diagram of a semiconductor device provided in an embodiment of this disclosure; Figure 6 A schematic diagram of the adhesive layer and stepped surface provided in an embodiment of this disclosure; Figure 7 This is a schematic diagram of a wafer after the step-face cutting process is performed, provided in an embodiment of this disclosure. Figure 8a This is a schematic diagram of forming a modified layer in the edge region of a wafer, provided by an embodiment of this disclosure; Figure 8b A schematic diagram of a thinned wafer provided in an embodiment of this disclosure; Figure 8c A schematic diagram showing the through-conductive structure exposed on the second surface according to an embodiment of this disclosure; Figure 9 A schematic diagram of the modified layer provided in an embodiment of this disclosure. Detailed Implementation

[0017] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0018] Where possible, the same reference numerals will be used throughout the accompanying drawings to refer to the same or similar parts. It is obvious that the aspects described are only some, and not all, of the aspects of this disclosure. Features in the various aspects may be interchanged and / or combined.

[0019] In the description of this disclosure, it should be understood that the terms “length,” “width,” “depth,” “upper,” “lower,” “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0020] 3D chip stacking is a crucial direction for the semiconductor industry to overcome performance and integration bottlenecks. In some embodiments, 3D stacked memory includes logic chips and multiple core chips stacked on top of the logic chips. The core chips contain TSVs (Through-Side Vias) that form vertical interconnect pathways. Backside ViaReveal (BVR) is a key step in the core chip fabrication process, used to expose the TSVs within the substrate and connect them to the backside pad layer, thereby achieving vertical electrical connections.

[0021] For example, the fabrication process of the core chip includes: forming a TSV extending into the wafer from the front side, and sequentially forming a memory array, an interconnect layer, and a front pad layer on the front side of the wafer. Then, the wafer is thinned from the back side to expose the TSV, and a back pad layer connected to the TSV is formed on the thinned back side of the wafer. Figure 1 This is a schematic diagram of a wafer after the back-side via exposure process has been performed. (See diagram below.) Figure 1As shown, because the thickness of the edge region of the original wafer 100 is less than that of the center region, the wafer edge becomes sharp during the thinning process of the original wafer 100. In this state, the back side of the original wafer will subsequently undergo processes such as the fabrication of the back pad layer. When the mechanical stress and / or thermal stress generated by the fabrication process are applied to the original wafer, the wafer edge may experience cracks, delamination, or fragment peeling, leading to chip failure at the edge and resulting in yield loss. To avoid this problem, such as... Figure 2a As shown, after the front pad layer of wafer 200 is fabricated, the edges of the front side of wafer 200 can be trimmed to remove localized edge areas. This prevents sharp edges from appearing during the thinning process on the back side of wafer 200, reducing the risk of edge cracks, delamination, and fragment peeling in subsequent processes.

[0022] However, as Figure 2a As shown, to improve wafer support, an adhesive layer 300 needs to be coated on the front side of wafer 200 before the thinning process, and the front side of wafer 200 is then adhered to the carrier 400. During the coating of the adhesive layer 300 on the front side of wafer 200, the adhesive layer 300 in the trimmed area may be unevenly coated, resulting in localized missing adhesive in the trimmed area. For example... Figure 2b As shown, when using a grinding process to thin wafers, the support at the missing adhesive sites is poor, easily leading to stress concentration and problems such as edge collapse and cracks. Figure 3 As shown, cracks caused by edge collapse may extend horizontally into the wafer or penetrate the wafer vertically, causing chip failure near the edge, i.e., chip breakage. Furthermore, it may increase the difficulty of subsequent debonding and dicing operations, or even make the operations impossible and cause scrap, ultimately resulting in a significant loss of yield.

[0023] In view of this, the present disclosure provides a method for manufacturing a semiconductor device to improve the problem of wafer edge collapse in the back-side thinning process. Figure 4a This is a schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, such as... Figure 4a As shown, the manufacturing method includes: S100: Provides a wafer having opposing first and second sides; S200: A step is formed from the edge region of the wafer by trimming the first side; the step includes a step surface and a step side surface, the step surface connects to the side surface of the wafer, the width of the step surface is less than or equal to the width of the edge region, and the step side surface connects the step surface and the first side surface; S300: An adhesive layer is formed on the first side and the step side of the wafer to fix the wafer on the substrate; wherein the step side includes multiple regions arranged along the circumference of the wafer, the multiple regions include a first region and a second region, and the contact area between the first region and the adhesive layer is smaller than the contact area between the second region and the adhesive layer. S400: The dicing process is performed from the edge region where the first region of the second face of the wafer is located, and the cut extends at least to the plane where the step surface is located; S500: Performs thinning process on the wafer from the second face.

[0024] It should be understood that Figure 4a The steps shown are not exclusive, and other steps may be performed before, after, or between any of the steps shown. Figures 5a to 5i This is a schematic diagram illustrating the manufacturing process of a semiconductor device according to an embodiment of this disclosure. Reference is made below. Figure 4a , Figures 5a to 5i The manufacturing process of the semiconductor device shown in the figure is described in detail.

[0025] See Figure 5a In step S100, a wafer 200 is provided, the wafer 200 having a first surface 201 and a second surface 202 facing each other in a vertical direction. In some embodiments, providing the wafer 200 includes: providing a substrate 210, forming a plurality of through conductive structures 211 extending into the substrate 210 from a surface of the substrate 210, and sequentially forming an integrated circuit layer 220 and a first pad layer 230 on a surface of the substrate 210, the plurality of through conductive structures 211 being connected to the integrated circuit layer 220, and the integrated circuit layer 220 being connected to the first pad layer 230.

[0026] Wafer 200 includes a substrate 210, and an integrated circuit layer 220 and a first pad layer 230 sequentially stacked on one surface of the substrate 210. The integrated circuit layer 220 may include a device layer and an interconnect layer, with the device layer located between the substrate 210 and the interconnect layer. The surface of the substrate 210 in contact with the integrated circuit layer 220 and the first surface 201 of the wafer are located on the same side of the substrate 210. The first pad layer 230 is exposed on the first surface 201 of the wafer, and the other surface of the substrate 210 facing away from the integrated circuit layer 220 is exposed on the second surface 202 of the wafer.

[0027] In some embodiments, a memory cell array (not shown) is formed in the wafer 200, comprising a plurality of memory cells arranged in an array. The memory cell may be a DRAM (Dynamic Random Access Memory) memory cell, consisting of a transistor and a capacitor forming a 1T (Transistor) 1C (Capacitor) memory structure. In some embodiments, the transistor may be formed in the substrate 210. Specifically, a semiconductor pillar array can be formed by etching the substrate 210, doping the semiconductor pillars to form source, channel, and drain regions, and word lines forming between adjacent semiconductor pillars, thereby forming a transistor array. In this case, the device layer includes a capacitor array, with capacitors in the capacitor array coupled one-to-one with transistors in the transistor array to form the memory cell array.

[0028] In other embodiments, the memory cell array may be a three-dimensional DRAM memory cell array located in the device layer on the substrate 210, and the three-dimensional memory cell array may adopt any suitable architecture, such as a horizontal word line architecture or a horizontal bit line architecture, without any limitation in this disclosure.

[0029] In some embodiments, peripheral circuitry is formed in wafer 200. This peripheral circuitry primarily includes circuitry that directly operates the memory cell array, such as word line drivers, sensitive amplifiers, and I / O (input / output) gate circuits. In one specific embodiment, various types of circuitry in the peripheral circuitry can be formed using metal-oxide-semiconductor (MODS) technology. The peripheral circuitry includes transistors, capacitors, diodes, etc., used to form various types of circuitry. All or part of the transistors can be formed in substrate 210. Source and drain regions of the transistors are formed by doping the substrate 210, and the gate dielectric layer and gate of the transistor are formed in the device layer on substrate 210. Isolation regions (e.g., shallow trench isolation (STI)) can also be formed in substrate 210.

[0030] A plurality of through-conductive structures 211 extending from one surface of a substrate 210 into the substrate 210 are formed in wafer 200. The through-conductive structures 211 may be through-silicon vias (TSVs). For example, the step of forming the through-conductive structures 211 may be performed before the step of forming the device layer. In this case, the plurality of through-conductive structures 211 are located in the substrate 210, and contact plugs connecting the through-conductive structures 211 and interconnect layers may be provided in the device layer. For example, the step of forming the through-conductive structures 211 may be performed after the step of forming the device layer. In this case, the plurality of through-conductive structures 211 pass through the device layer and extend into the substrate 210. Also for example, the through-conductive structures 211 may be formed during the formation of the device layer. For example, after a portion of the device layer is formed, the plurality of through-conductive structures 211 extending through the device layer into the substrate 210 may be formed, and then the remaining portion of the device layer may continue to be formed. This disclosure does not impose excessive restrictions on the fabrication sequence of the through-conductive structures 211 and the device layer, or on the positional relationship between the through-conductive structures 211 and the device layer.

[0031] For example, the fabrication process of the through-conductive structure 211 is illustrated by forming a through-conductive structure 211 in the substrate 210. First, the substrate 210 is etched to form a plurality of vias extending from one surface of the substrate 210 into the substrate 210, with the bottom of the vias remaining in the substrate 210 and not penetrating it. Next, an insulating layer is formed on the sidewalls and bottom of each via, and the through-conductive structure 211 is formed in the remaining area of ​​the via.

[0032] Interconnect layers reside on multiple through-conductive structures 211 and device layers, and can broadly include any suitable type of interconnect. For example, interconnect layers may include local interconnects such as word line contacts, bit line contacts, and contact plugs. Interconnect layers may also include multiple interlayer dielectric layers, multiple wiring layers therein, and conductive vias located between adjacent wiring layers. Wiring layers include laterally extending wiring, and conductive vias connect the wiring of adjacent wiring layers. Contacts, wiring, and conductive vias may include conductive materials, including but not limited to tungsten, cobalt, copper, aluminum, silicides, or any combination thereof. Interlayer dielectric layers in interconnect layers may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0033] The device layer and multiple through-conducting structures 211 can be connected to the interconnect layer via any suitable connection method. Circuits with different functions in the device layer are connected through the interconnect layer for signal interaction. For example, I / O gate circuits can be connected to word line drivers, sensitive amplifiers, etc., through the interconnect layer. Peripheral circuits can be coupled to word lines, bit lines, upper electrodes of capacitors, etc., of the memory cell array through the interconnect layer. Peripheral circuits can also be connected to the through-conducting structures 211 through the interconnect layer to receive signals transmitted in the through-conducting structures 211, or to transmit signals to the through-conducting structures 211 so that signals are transmitted through the through-conducting structures 211 to the logic chip. Signals include at least one of command, address, and data.

[0034] The interconnect layer can be connected to the first pad layer 230 via any suitable connection method to couple peripheral circuitry in the wafer to the first pad layer 230. The first pad layer 230 includes a pad dielectric layer and a plurality of first pads 231 located within the pad dielectric layer. For example, the first pads 231 may be bonding pads for hybrid bonding. The bonding pads have a flat surface and can be directly fused-bonded to bonding pads on another wafer or chip. For example, as... Figure 5a As shown, the first pad 231 can be a bump pad for bump interconnection, the bump pad is soldered to the bump, and interconnection is achieved by soldering the bump to the pad of another wafer or chip.

[0035] At this point, the fabrication process of the first surface 201 of wafer 200 is completed. Next, step S200 is performed to trim the edge region of wafer 200 from the first surface 201 to form a step 500; the step 500 includes a step surface 510 and a step side surface 520, the step surface 510 connects to the wafer side surface, the width of the step surface 510 is less than or equal to the width of the edge region, and the step side surface 520 connects the step surface 510 and the first surface 201.

[0036] The edge region of wafer 200 surrounds the central region, which is used to form an array of chips. The edge region of the wafer can be trimmed using processes such as mechanical cutting, laser cutting, or plasma etching to form a step 500. Vertically, the thickness of the trimmed area is less than the thickness of wafer 200. Horizontally, the width of the trimmed area is less than or equal to the width of the edge region, so that the trimmed portion of the edge region forms the step 500. For example, the step 500 extends circumferentially around wafer 200.

[0037] Step 500 includes a step surface 510 and a step side surface 520. The step surface 510 connects to the wafer side surface and extends laterally, and is approximately parallel to the plane of the wafer. Laterally refers to directions perpendicular to the vertical direction, i.e., the horizontal direction. The width W2 of the step surface 510 can be equal to or less than the width W1 of the edge region. For example, the width W2 of the step surface 510 is equal at all points along the wafer circumference.

[0038] The step side 520 connects the step surface 510 and the first surface 201 of the wafer 200. The step side 520 can be designed differently in different embodiments. In one embodiment, the step side 520 extends vertically, making the entire step side 520 of the wafer cylindrical. In another embodiment, the step side 520 extends in a direction intersecting the vertical, making the step side 520 inclined, and the entire step side 520 of the wafer frustum. In yet another embodiment, the step side 520 is an arc surface formed by rotating a curve around a fixed axis, and the entire step side 520 of the wafer is a curved surface of revolution, such as a circular arc surface of revolution. In this embodiment, as... Figure 5a As shown, the side of the step 520 extends basically in the vertical direction and is perpendicular to the step surface 510.

[0039] Next, step S300 is performed to form an adhesive layer 300 on the first surface 201 and the step side surface 520 of the wafer, and to fix the wafer 200 onto the carrier 400 using the adhesive layer 300. In this embodiment, the carrier 400 is a wafer carrier, such as a silicon wafer. In other embodiments, the carrier 400 may also be other types of carriers such as glass carriers, metal carriers, polymer carriers, or ceramic carriers.

[0040] The adhesive layer 300 is used to temporarily bond the wafer 200 and the carrier 400. After the second pad layer is formed on the second side 202 of the wafer 200, the carrier 400 can be separated from the wafer 200 by a debonding process, and the residual adhesive layer 300 can be removed to ensure the wafer surface is clean. The carrier 400 can be reused in different product batches.

[0041] For example, any suitable process, such as coating or lamination, or a combination thereof, can be used to form the adhesive layer 300. Coating processes include spraying, spin coating, and slot coating. In the coating process for forming the adhesive layer 300, a liquid adhesive is applied to the surface of the wafer or carrier 400, followed by curing operations such as heating and UV (Ultraviolet) irradiation, causing the liquid adhesive to form the adhesive layer 300, bonding the wafer 200 and the carrier 400 together. The lamination process involves attaching a pre-made solid adhesive film (such as tape, pre-cured film, or thermo-pressure adhesive film) to the surface of the carrier 400, aligning the wafer 200 and the carrier 400, and mechanically pressing the solid adhesive film onto the wafer surface, thus achieving bonding between the wafer 200 and the carrier 400.

[0042] The adhesive layer 300 may include various adhesives, adhesive films, or combinations thereof commonly used in temporary wafer bonding. For example, liquid adhesives may include thermosetting adhesives, UV adhesives, or thermoplastic resins. Solid adhesive films may include pyrolytic films, UV adhesive films, laser-disintegrating films, etc.

[0043] For example, the adhesive layer 300 can be a composite layer structure, including a protective layer 310, a release layer 320, and a support layer 330 sequentially stacked on the wafer surface. The protective layer 310 is in direct contact with the first side of the wafer, protecting the delicate structures on the wafer surface (such as the first pad layer) from contamination, scratches, or chemical corrosion during the bonding process. The protective layer 310 has low adhesion to avoid damage to the wafer during separation and also has a certain degree of flexibility. The release layer 320 is a controllable separation layer that undergoes physical or chemical property changes (such as decomposition, softening, or loss of adhesion) through external stimuli (such as laser irradiation, heating, or chemical etching), reducing adhesion and making it easier to separate the wafer from the carrier. The support layer 330 is combined with the carrier 400, providing mechanical support and enhancing the strength and stability of the bond to prevent wafer warping or deformation.

[0044] For example, one or more of the protective layer 310, release layer 320, and support layer 330 can be formed using coating processes such as spin coating or slot coating to better cover the step sides of the wafer. In one specific embodiment, the protective layer 310, release layer 320, and support layer 330 are all formed using a coating process. For example, the material of the protective layer 310 may include one or a combination of p-menthane and mesitylene. The release layer 320 may be made of a siloxane polymer, such as octamethyl-trisiloxane. The material of the support layer 330 may include cyclopentanone, etc.

[0045] Figure 6 This is a schematic diagram of the adhesive layer 300 and the stepped surface 510 provided in an embodiment of this disclosure. Figure 6This shows the 300 and step surface 510 as viewed from the plane containing the first surface 201 of wafer 200. Figure 6 The detailed structure of the first surface of the wafer is not shown. Figure 6 As shown, the step surface 510 includes multiple regions arranged along the circumference of the wafer, each region having a substantially equal area. For example, the number of regions can be two, three, four, or even more; this disclosure does not impose any restrictions on this. The multiple regions include a first region and a second region, wherein the contact area between the first region and the adhesive layer 300 is smaller than the contact area between the second region and the adhesive layer 300.

[0046] like Figure 5a As shown, the adhesive layer 300 covers the first surface 201 of the wafer 200 and extends to the step side surface 520, wherein the top of the adhesive layer 300 located on the step side surface 520 contacts the step surface 510. It is understood that when the adhesive layer 300 is uniformly coated on the first surface 201 and the step side surface 520, the contact area between each region of the step surface 510 and the adhesive layer 300 is approximately equal. However, the coating process is complex, and problems in any step can lead to uneven coating, such as positioning deviations, uneven coating speeds, or uneven pressure between the coating roller and the wafer. Uneven coating or alignment deviations during wafer-carrier bonding can result in uneven distribution of the final adhesive layer 300 on the step side surface 520, thus leading to… Figure 6 The contact area between the first region of the stepped surface 510 and the adhesive layer 300 is smaller than the contact area between the second region and the adhesive layer 300.

[0047] For example, the first region of the step surface 510 can be a low-adhesion region, meaning the contact area between the first region and the adhesive layer 300 is greater than zero, but smaller than the contact area between the second region or other regions besides the first and second regions and the adhesive layer 300. Also for example, such as... Figure 5a and Figure 6 As shown, the first region can also be a region lacking adhesive, where the first region is basically not in contact with the adhesive layer 300, meaning the contact area between the first region and the adhesive layer 300 is essentially zero. Insufficient or absent adhesive can weaken the support of the adhesive layer 300 for the first region of the step surface 510, potentially causing edge collapse at the first region during subsequent thinning of the second surface 202 of the wafer.

[0048] To solve this problem, step S400 is performed, in which a cutting process is performed on the edge region where the first region is located from the second side 202 of the wafer, and the cut extends at least to the plane where the step surface 510 is located.

[0049] In this article, "cut" can broadly refer to the cutting mark left on the wafer by the cutting process. The cut can be a region of material removal, material separation, or material modification resulting from the cutting process. Cutting processes include, but are not limited to, mechanical cutting (or blade cutting), laser ablation cutting, laser stealth cutting, and plasma etching cutting. In mechanical cutting, laser ablation cutting, and plasma etching cutting, the cut can be an area formed by removing part of the material. In laser stealth cutting, the cut can be a modified layer formed by laser cutting.

[0050] In some embodiments, such as Figure 4b and Figure 5b As shown, step S400 may specifically include: S410: cutting the edge area where the first region is located from the second surface, with the cut extending from the second surface to the step surface; the width of the first region after cutting is greater than or equal to zero and less than or equal to a preset value.

[0051] See Figure 5b With the second side 202 of wafer 200 facing downwards, wafer 200 can be cut using mechanical cutting, laser ablation cutting, or plasma cutting processes. Taking mechanical cutting as an example, the blade contacts the second side 202 of the wafer and continues to cut downwards until all or part of the step surface 510 of the first region is removed. The reduced width of the first region after cutting decreases the torque experienced by the first region during subsequent wafer thinning, reducing the stress at the interface between the step side 520 and the step surface 510. This reduces the risk of edge collapse or cracking, thereby lowering the probability of chip damage in the central area and improving chip yield and reliability. For example, the width of the first region after cutting is less than or equal to a preset value. The preset value is related to the contact area between the adhesive layer 300 and the first region, process parameters in subsequent wafer thinning, etc., and can be determined through simulation, multiple experiments, or experience.

[0052] In some embodiments, the preset value is, for example, 5-15 micrometers.

[0053] In other embodiments, the preset value is determined based on the contact area between the adhesive layer 300 and the first region. For example, such as Figure 7 As shown, the step surface 510 of the first region is cut to align with the adhesive layer 300. At this point, the width W3 of the cut first region is equal to the thickness of the adhesive layer 300 on the step side surface 520 corresponding to the first region. In other words, the cut first region is in contact with the adhesive layer 300 at all points. Thus, during subsequent wafer thinning, the thinned first region is supported by the adhesive layer 300, significantly reducing the stress at the interface between the step side surface 520 and the step surface 510, and lowering the risk of edge collapse.

[0054] In some other implementations, such as Figure 5bAs shown, the entire step surface 510 of the first region is cut off. At this point, the width of the cut first region is zero. This way, the edge area where the first region is located is essentially not subjected to torque, preventing edge collapse. For example, in this embodiment, when the step side 520 extends vertically, the edge area where the first region is located can be cut from the second surface 202 along the plane containing the step side 520 to remove the first region. In other embodiments, the first region can be cut along the plane extending vertically along the boundary line between the step side 520 and the step surface 510 to remove the first region.

[0055] See back Figure 6 The step surface 510 also includes a second region. For example, the second region is an overflow region, that is, the contact area between the second region and the adhesive layer 300 is larger than the normal area. The normal area refers to the contact area between each region of the step surface 510 and the adhesive layer 300 when the adhesive layer 300 evenly covers the side surface 520 of the step.

[0056] In some embodiments, the manufacturing method further includes cutting the edge area and adhesive layer of the second region along the plane of the step side from the second surface to remove the second region and the adhesive layer located on the step side.

[0057] like Figure 5b As shown, the step surface 510 of the adhesive overflow area and the adhesive layer 300 located on the step side 520 and in contact with the adhesive overflow area can be completely cut off. At this time, the width of the cut second area is zero, and the edge area where the second area is located is basically not subjected to torque, thus avoiding the problem of edge collapse. In this embodiment, when the step side 520 extends vertically, the edge area where the second area is located can be cut from the second surface 202 along the plane where the step side 520 is located to remove the second area and the corresponding adhesive layer 300. In other embodiments, the second area and the adhesive layer can be cut along the plane extending vertically where the boundary line between the step side 520 and the step surface 510 is located, or along another plane where the boundary line is located, to remove the second area and the adhesive layer.

[0058] In other embodiments, such as Figure 7 As shown, the step surface 510 of the second region can also be cut to align with the adhesive layer 300 to reduce the risk of edge collapse.

[0059] In some embodiments, where multiple regions include a first region, edge regions are cut circumferentially from the second face 202 along the wafer, and the widths of the step surfaces 510 after cutting the different regions are equal to each other.

[0060] In this embodiment, if there are areas with insufficient or no adhesive on the step surface 510, then regardless of whether the second region is a normal region or an area with excess adhesive, the edge region is circumferentially cut off along the wafer, and the width of the step surface 510 cut off in each region is basically equal, so that the width of the step surface 510 after cutting in each region is equal to that of each region. For example, the width of the step surface 510 after cutting in each region is less than or equal to a preset value. The preset value here can be the preset value described in any of the embodiments above. For example, the preset value can be determined based on the ratio of the width of the step surface before and after cutting, or it can be determined based on the contact area between the first region and the adhesive layer.

[0061] The circumferential trimming of the edge region ensures the symmetry of the wafer after dicing, thereby maintaining its mechanical stability and consistency. This ensures the dynamic balance of the wafer during subsequent thinning processes, which require rotation, and avoids process deviations caused by eccentricity. Furthermore, it prevents stress concentration at the boundary between the diced and undicated areas. The circumferential trimming creates a uniform, smooth circular edge, distributing stress evenly across the edge region and reducing the risk of collapse or cracking.

[0062] In one specific implementation, such as Figure 5b As shown, the step surfaces 510 of each region can be completely cut off along the circumference of the wafer 200, so that the width of the step surfaces after cutting each region is zero. For example, the cut wafer side extends vertically and presents an overall cylindrical surface. The cut wafer side is smooth with virtually no stress concentration areas, which can avoid wafer collapse or cracking problems.

[0063] See Figure 5c and Figure 5d Step S500 is performed, in which a thinning process is applied to the wafer from the second side 202. For example, step S500 specifically includes thinning the substrate 210 of the wafer from the second side 202 until a plurality of through conductive structures 211 are exposed.

[0064] For example, the substrate 210 can be thinned using one or a combination of grinding and etching processes. Grinding processes include back grinding (BG), chemical mechanical polishing (CMP), etc., and etching processes include wet etching, dry etching, etc. In one embodiment, the substrate 210 can be thinned twice.

[0065] like Figure 5cAs shown, in the first thinning operation, mechanical grinding and / or chemical mechanical polishing are performed on the substrate 210 from the second surface 202, significantly reducing the thickness of the substrate 210. In this disclosure, by reducing the width of the step surface 510 in step S400, or even completely cutting off the step surface 510, the risk of wafer edge collapse and cracking during mechanical grinding and chemical mechanical polishing can be improved or avoided.

[0066] For example, after the first thinning, multiple through-conductive structures 211 were not exposed. Figure 5d As shown, a second thinning operation is performed on the substrate 210, which can be achieved through wet etching and / or dry etching, exposing a section of the through-conductive structure 211, thus completing the thinning operation on the wafer (i.e., the substrate 210). Next, an isolation layer 240 is applied to the surface of the thinned substrate 210 and the exposed surface of the through-conductive structure 211. Then, chemical mechanical polishing is performed on the through-conductive structure 211 until it is flush with the isolation layer 240 on the surface of the substrate 210. At this point, the final through-conductive structure 211 is formed through the thinned substrate 210.

[0067] In some embodiments, the manufacturing method further includes: forming a second pad layer on a second side of the thinned wafer, the second pad layer connecting a plurality of through conductive structures; removing the adhesive layer and carrier on the first side; and dicing the thinned wafer into a plurality of chips.

[0068] See Figure 5e A second pad layer 250 is formed on the second side 202 of the thinned wafer. The second pad layer 250 includes a pad dielectric layer and a plurality of second pads 251 located within the pad dielectric layer. A plurality of through-conductive structures 211 can be connected to the second pads 251 of the second pad layer via any suitable connection method. For example, the second pads 251 may be bonding pads for hybrid bonding. The bonding pads have a flat surface and can be directly fused-bonded to bonding pads on another wafer or chip. For example, as... Figure 5e As shown, the second pad 251 can be a bump pad for bump interconnection. The bump pad is soldered to bump 260 and interconnected with pads on another wafer or chip via bump 260. For example, the material of bump 260 can be metal. Thus, in each chip of the wafer, a vertical interconnect path is formed sequentially through the first pad 231, the interconnect layer (included in the integrated circuit layer 220), the conductive structure 211, and the second pad 251.

[0069] In some embodiments, the manufacturing method may further include: forming a redistribution layer (not shown) on the second side 202 of the thinned wafer, the redistribution layer being located between the thinned substrate 210 and the second pad layer 250, a plurality of through conductive structures 211 connecting the redistribution layer, and the redistribution layer connecting the second pad layer 250.

[0070] The redistribution layer includes at least one routing layer and conductive vias located between adjacent routing layers. Through-conductive structures 211 can be connected to the lowest routing layer of the redistribution layer, and the highest routing layer is connected to the second pad. The redistribution layer can resolve the mismatch between the position and spacing of multiple through-conductive structures 211 and the second pads of the second pad layer, connecting the through-conductive structures 211 to the corresponding second pads via metal wiring.

[0071] See Figure 5f and 5g After forming the second pad layer 250, the wafer is flipped so that the carrier 400 faces upwards. Then, the adhesive layer 300 is debonded through methods such as thermal slip debonding, thermal decomposition debonding, laser debonding, chemical release debonding, and mechanical debonding, thereby achieving separation of the wafer and the carrier 400. Simultaneously, any remaining adhesive layer 300 is removed to ensure a clean wafer surface. During the removal of the carrier 400, any suitable device can be used to hold and support the wafer.

[0072] In this embodiment, as Figure 5f As shown, during mechanical debonding, wafer 200 is fixed on a first mounting ring 610 containing a first dicing film 620, wherein the second side 202 of the wafer is attached to the first dicing film 620. The wafer carrier 400 can be fixed on a vacuum chuck, and the debonding blade is inserted from one edge of the wafer carrier 400 (e.g., from a point on the edge of the wafer carrier 400). Figure 5f The debonding blade (indicated by the triangle in the middle) is inserted into the adhesive layer 300 between the carrier 400 and the wafer 200. The debonding blade slowly advances along the interface, eventually separating the wafer from the carrier 400. Figure 5g As shown, after the substrate 400 and adhesive layer 300 are removed, the first pad layer 230 of the first surface 201 of the wafer is exposed.

[0073] See Figure 5h After the first pad layer 230 of the first surface 201 is exposed, the first surface 201 of the wafer is fixed on the second mounting ring 630 containing the second dicing film 640, and the first dicing film 620 of the second surface 202 of the wafer is removed, exposing the second surface 202 of the wafer. The wafer is then placed with the second surface 202 facing upwards and diced. For example, mechanical dicing, laser stealth dicing, laser ablation, or other dicing methods can be used to dice the wafer 200 along the dicing tracks, thereby dividing the wafer 200 into multiple chips.

[0074] For example, the chips diced from a wafer can be DRAM chips (or core chips). For instance... Figure 5iAs shown, the manufacturing method may further include: stacking multiple core chips 710 on a logic chip 800 in a vertical direction to obtain a semiconductor device. For example, the semiconductor device is a three-dimensional stacked memory.

[0075] In one implementation, such as Figure 5i As shown, the first pad layer 230 of each core chip 710 is connected to the second pad layer 250 of the adjacent core chip 710 via bumps 260. The bumps 260 include microbumps. The through-conductive structure 211 within each core chip 710 is a key channel for vertical interconnection within the core chip. Multiple core chips 710 are coupled to the logic chip 800 through the through-conductive structure 211 for signal interaction with the logic chip 800. For example, the semiconductor device also includes a top-layer chip 720, whose structure may be the same as or different from that of the core chips 710. In one specific embodiment, the through-conductive structure 211 may not be formed in the top-layer chip 720.

[0076] Furthermore, in some other embodiments, the first pad layer 230 of each core chip 710 can also be bonded to the second pad layer 250 of the adjacent core chip 710. In other still embodiments, the structure of the semiconductor device can also start from the core chip closest to the logic chip, with each pair of adjacent core chips forming a chipset. The two core chips within a chipset are bonded face-to-face, and adjacent chipsets can be bonded together or connected by bumps.

[0077] This disclosure also provides an edge region cutting process. In some embodiments, such as Figure 4a and Figure 4c As shown, step S400 may specifically include: S420: forming a modified layer inside the edge area where the first region is located using an invisible cutting process; wherein, the modified layer has a first end and a second end opposite to each other in a direction perpendicular to the first surface, and the first end and the second end are respectively located on both sides of the plane where the step surface is located.

[0078] Figures 8a to 8c This is a schematic diagram illustrating another manufacturing process of a semiconductor device provided in an embodiment of this disclosure. The following is in conjunction with... Figure 4c , Figures 8a to 8c The process of creating an incision using a stealth cutting technique is described in detail.

[0079] Stealth dicing, also known as laser stealth dicing, involves using a high-precision optical system to focus a laser beam inside a wafer. The laser energy is absorbed by the material at the focal point, causing localized lattice disruption, melting, or vaporization due to high temperatures, forming a narrow modified layer. This modified layer can be understood as a region of relaxed material structure or a controllable crack. Figure 8aAs shown, during the laser stealth dicing process on the edge region of the wafer, the laser beam enters the interior of the substrate 210 from the second surface 202 of the substrate 210, focuses inside the wafer, and forms a modified layer 910. The modified layer 910 is located inside the edge region and is not exposed on any surface of the wafer 200.

[0080] Within the edge region, the modified layer 910 is located between the central region and the step surface 510, such that the orthographic projection of the modified layer 910 in the vertical direction lies on the first surface 201 of the wafer. The modified layer 910 has a first end 911 and a second end 912 opposite each other in the vertical direction. The first end 911 is close to the second surface 202, and the first end 911 and the second end 912 are located on opposite sides of the plane A containing the step surface 510. In other words, the modified layer 910 passes through the plane A containing the step surface 510 in the vertical direction. In this embodiment, the modified layer 910 disrupts the lateral continuity of the edge region. The modified layer 910 can disperse stress, reduce stress concentration at the junction of the step surface 510 and the step side surface 520, thereby reducing the risk of edge collapse. Furthermore, in the case of edge collapse, since the modified layer passes through the plane A where the step surface is located in the vertical direction, when the crack extends approximately along plane A to the modified layer, the modified layer can relax the stress at the crack tip, prevent the crack from continuing to extend into the wafer, and avoid the formation of linear through cracks.

[0081] In some embodiments, such as Figure 8a As shown, before the thinning process, the first distance L1 between the first end 911 of the modified layer 910 and the second surface 202 is smaller than the second distance L2 between the end of the conductive structure 211 near the second surface and the second surface 202. Figure 8b and Figure 8c As shown, the modified layer 910 is exposed during the thinning process.

[0082] For example, such as Figure 8b As shown, in the thinning process, the modified layer 910 is exposed before the through-conductive structure 211. For example, the modified layer 910 can be exposed after mechanical grinding or chemical mechanical polishing, at which point the through-conductive structure 211 is not yet exposed. In this embodiment, the first distance L1 between the modified layer 910 and the second surface 202 is smaller than the second distance L2 between the through-conductive structure 211 and the second surface 202, so that the modified layer 910 can disperse the stress on the top of the through-conductive structure 211 during the grinding process, reducing the probability of defects in the through-conductive structure 211 and improving reliability. For example, refer to... Figure 5c and Figure 5d Two thinning operations are performed to reduce the wafer thickness by 200.

[0083] In some embodiments, the third spacing L3 between the modified layer 910 and the step side surface 520 ranges from 100 μm to 200 μm. When the third spacing between the modified layer 910 and the step side surface 520 is within this range, it can effectively disperse the stress at the interface between the step side surface and the step surface. If the third spacing is too large, the effect on improving the stress distribution at the interface between the step side surface and the step surface is limited; if the third spacing is too small, it may lead to a weakening of the strength at the interface between the step side surface and the step surface, which is not conducive to improving the edge collapse problem.

[0084] In some embodiments, there is a fourth spacing L4 between the first end 911 of the modified layer 910 and the plane A containing the step surface. There is a fifth spacing between the second end 912 and the plane A containing the step surface. The fourth spacing can be smaller than the fifth spacing, thereby better preventing cracks during subsequent grinding. Figure 9 A schematic diagram of the modified layer provided in an embodiment of this disclosure. Figure 9 Showing Figure 8a The wafer in the image is cut from the side of the step by a horizontal plane (a plane perpendicular to the vertical direction), and the modified layer 910, the adhesive layer 300 and the step surface 510 are observed. Figure 9 Other structures within the wafer besides the modified layer are not shown. In some embodiments, such as Figure 8a and Figure 9 As shown, in the case of multiple regions including the first region, the modified layer 910 is disposed around the wafer 200 along the edge region of the wafer.

[0085] In this embodiment, if there are areas with insufficient or no adhesive on the step surface 510, then regardless of whether the second region is a normal region or an area with excess adhesive, the modified layer 910 surrounds the wafer circumferentially to form a crack-blocking ring. During the mechanical grinding or chemical mechanical polishing process of the back-side via exposure (BVR) process, the crack-blocking ring can prevent cracks from extending inward from all directions, avoiding the formation of linear through cracks.

[0086] Then, multiple chips can be formed by referring to steps 5e to 5h. And refer to... Figure 5i The fabrication of semiconductor devices will not be discussed further here.

[0087] This disclosure also provides a semiconductor structure, such as... Figure 8a or Figure 8bAs shown, the semiconductor structure includes a wafer 200 and a modification layer 910. A step is formed in the edge region of the wafer. The step includes a step surface 510 and a step side surface 520. The step surface 510 connects to the wafer side surface, and the width of the step surface 510 is smaller than the width of the edge region. The step side surface 520 connects the step surface 510 and a first surface 201 of the wafer perpendicular to the wafer thickness direction. The modification layer 910 is located inside the wafer in the edge region. The orthographic projection of the modification layer 910 is located on the first surface. The modification layer 910 has a first end 911 and a second end 912 opposite to each other along the wafer thickness direction. The first end 911 and the second end 912 are located on opposite sides of the plane A containing the step surface.

[0088] In some embodiments, such as Figure 9 As shown, the steps are arranged around the wafer along the edge region of the wafer, and the modified layer 910 is arranged around the wafer along the edge region of the wafer.

[0089] In this embodiment, mechanical circumferential cutting is performed at the edge after bonding the wafer and the substrate to remove poorly filled portions of the edge. This improves edge cracking issues during mechanical grinding or chemical mechanical polishing in the back-side via exposure process. Alternatively, mechanical circumferential cutting can be performed at the edge after bonding the wafer and the substrate, forming a crack-blocking ring through laser stealth circumferential cutting. This prevents cracks from extending into the wafer during mechanical grinding or chemical mechanical polishing in the back-side via exposure process, thus avoiding the formation of linear through-cracks.

[0090] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0091] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A wafer is provided, the wafer having opposing first and second sides; A step is formed by trimming the edge region of the wafer from the first surface; The step includes a step surface and a step side surface. The step surface connects to the side surface of the wafer. The width of the step surface is less than or equal to the width of the edge region. The step side surface connects the step surface and the first surface. An adhesive layer is formed on the first surface of the wafer and the step side surface to fix the wafer onto a carrier; wherein the step surface includes a plurality of regions arranged along the circumference of the wafer, the plurality of regions including a first region and a second region, the contact area between the first region and the adhesive layer is smaller than the contact area between the second region and the adhesive layer; The edge area containing the first region is cut from the second surface, and the cut extends from the second surface to the stepped surface; the width of the first region after cutting is greater than or equal to zero and less than or equal to a preset value. The wafer is thinned from the second face.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The first region after cutting is in contact with the adhesive layer at all points.

3. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The step of cutting the edge area containing the first region from the second surface, with the cut extending from the second surface to the stepped surface, includes: Cut the edge area containing the first region from the second surface along the plane containing the side of the step to remove the first region.

4. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The manufacturing method further includes: Cut the edge area where the second region is located and the adhesive layer from the second surface along the plane where the side of the step is located, to remove the second region and the adhesive layer located on the side of the step.

5. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, characterized in that, The cut is formed using a mechanical cutting process; Alternatively, if the plurality of regions includes the first region, the edge region is cut from the second face along the circumference of the wafer, and the step widths of the different regions after cutting are equal to each other.

6. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The provision of the wafer includes: A substrate is provided, and a plurality of through-conductive structures extending into the substrate are formed from a surface of the substrate. An integrated circuit layer and a first pad layer are sequentially formed on a surface of the substrate. The plurality of through-conductive structures are connected to the integrated circuit layer, and the integrated circuit layer is connected to the first pad layer. The thinning process performed on the wafer from the second surface includes: thinning the substrate from the opposite surface of the substrate to the other surface of the integrated circuit layer until the plurality of the through conductive structures are exposed.

7. A method for manufacturing a semiconductor device, characterized in that, include: A wafer is provided, the wafer having opposing first and second sides; A step is formed by trimming the edge region of the wafer from the first surface; The step includes a step surface and a step side surface. The step surface connects to the side surface of the wafer. The width of the step surface is less than or equal to the width of the edge region. The step side surface connects the step surface and the first surface. An adhesive layer is formed on the first surface of the wafer and the step side surface to fix the wafer onto a carrier; wherein the step surface includes a plurality of regions arranged along the circumference of the wafer, the plurality of regions including a first region and a second region, the contact area between the first region and the adhesive layer is smaller than the contact area between the second region and the adhesive layer; A modified layer is formed inside the edge region where the first area is located using a stealth cutting process; wherein, the modified layer has a first end and a second end opposite to each other in a direction perpendicular to the first surface, and the first end and the second end are respectively located on both sides of the plane where the step surface is located; The wafer is thinned from the second face.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, In the case where the plurality of regions include the first region, the modified layer is disposed around the wafer along the edge region of the wafer.

9. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The provision of the wafer includes: A substrate is provided, and a plurality of through-conductive structures extending into the substrate are formed from a surface of the substrate. An integrated circuit layer and a first pad layer are sequentially formed on a surface of the substrate. The plurality of through-conductive structures are connected to the integrated circuit layer, and the integrated circuit layer is connected to the first pad layer. The thinning process performed on the wafer from the second surface includes: thinning the substrate from the opposite surface of the substrate to the other surface of the integrated circuit layer until the plurality of the through conductive structures are exposed.

10. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The first end of the modified layer is close to the second surface; Before the thinning process is performed, the first distance between the first end of the modified layer and the second surface is smaller than the second distance between the end of the through conductive structure near the second surface and the second surface. During the thinning process, the modified layer is exposed.

11. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The manufacturing method further includes: A second pad layer is formed on the second side of the thinned wafer, and the second pad layer connects multiple through conductive structures; Remove the adhesive layer and the carrier sheet from the first side; The thinned wafer is then cut into multiple chips.

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