FVF architecture fast transient response-based off-chip capacitor-free LDO (Low Dropout Regulator)
By introducing an error amplifier and an FVF stage circuit into the LDO to form a high-gain loop, and adding overshoot and undershoot suppression circuits, the problems of traditional LDOs being sensitive to process, voltage and temperature and having poor load regulation are solved, realizing a fast-response and high-precision LDO without external capacitors.
Patent Information
- Application Number
- CN202511025161.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-24
- Publication Date
- 2025-11-14
AI Technical Summary
Traditional LDOs are sensitive to changes in process, voltage, and temperature, and have poor load regulation and output accuracy, while also increasing the space and cost of additional off-chip components.
It adopts a fast transient response LDO with no external capacitor based on FVF architecture, combined with an error amplifier and FVF stage circuit to form a high-gain loop, and introduces overshoot suppression and undershoot suppression circuits to improve output accuracy and load regulation.
It improves the output accuracy and load regulation of LDO, reduces output voltage fluctuations, enhances response speed and stability, and avoids the space and cost of additional off-chip capacitors.
Smart Images
Figure CN120949876A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a low-dropout linear regulator (LDO) circuit with fast transient response based on a flipped voltage follower (FVF) architecture and no external capacitor. Background Technology
[0002] LDOs play a crucial role in power management ICs, offering advantages such as simple structure, stable output, and small size. Traditional LDOs typically use large off-chip capacitors for compensation, which also provide voltage regulation, reducing overshoot and undershoot voltages caused by load transitions. However, given the high integration requirements of today's mobile devices, LDOs with off-chip capacitors require additional off-chip components, occupying more space and introducing additional capacitor costs. Therefore, LDOs without off-chip capacitors have emerged as a solution.
[0003] In recent years, some researchers have introduced the FVF structure into LDOs, proposing a new LDO structure. This structure has good transient response, but it is very sensitive to changes in process, voltage and temperature. Furthermore, due to the low gain of the control loop, its load regulation and output accuracy are poor. Summary of the Invention
[0004] The present invention aims to address the aforementioned problems by proposing a fast transient response LDO with no external capacitor based on an FVF architecture.
[0005] To achieve the above objectives, the present invention adopts the following technical solution:
[0006] A fast transient response LDO without external capacitors based on FVF structure includes an error amplifier, an FVF stage circuit, and a transient enhancement circuit.
[0007] The negative terminal of the error amplifier is connected to a reference voltage V. REF The positive terminal is connected to the output resistor, and the feedback voltage V is formed by voltage division through the feedback resistor. FB The output terminal is connected to the input terminal of the FVF stage, and the output terminal of the FVF stage is connected to V. OUT This forms a high-gain loop, improving the LDO output accuracy and load regulation; the FVF stage circuit internally forms a fast loop with low gain and high bandwidth characteristics, enabling rapid feedback to suppress output voltage fluctuations; the transient enhancement circuit simultaneously compares V... FB Voltage and V OUT The voltage is fed back to the gate of the power transistor to further suppress the overshoot and undershoot of the output voltage.
[0008] The FVF stage circuit includes a first current source I1, a second current source I2, a third current source I3, a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, a first capacitor C1, a second capacitor C2, and a first resistor R1. The gate of the first MOSFET M1 is connected to the output terminal of the error amplifier, and the source of the first MOSFET M1 is connected to the drain of the fourth MOSFET M4, the gate of the fifth MOSFET M5, and the upper plate of the second capacitor C2. The connection point is the output terminal V. OUT The drain of the first MOSFET M1 is connected to the inlet of the third current source I3, the upper plate of the first capacitor C1, the lower plate of the second capacitor C2, the gate of the second MOSFET M2, and the drain of the sixth MOSFET M6; the lower plate of the first capacitor C1 is connected to one end of the first resistor R1; the source of the second MOSFET M2 is connected to the outlet of the first current source I1, the drain of the third MOSFET M3, and the gate of the fourth MOSFET M4; the drain of the second MOSFET M2 is connected to the gate of the third MOSFET M3 and the inlet of the second current source I2; the drain of the fifth MOSFET M5 is connected to the gate of the sixth MOSFET and the gate and drain of the seventh MOSFET; the sources of the fourth MOSFET M4 and the fifth MOSFET, and the inlet of the first current source I1 are all connected to the power rail VDD; the sources of the third MOSFET M3, the sixth MOSFET M6, the seventh MOSFET M7, the other end of the first resistor R1, the outlet of the second current source I2, and the outlet of the third current source I3 are all connected to the ground power rail GND.
[0009] The transient enhancement circuit includes an overshoot suppression circuit and an undershoot suppression circuit;
[0010] The overshoot suppression circuit includes an eighth MOSFET M8, a ninth MOSFET M9, a tenth MOSFET M10, an eleventh MOSFET M11, a twelfth MOSFET M12, and a fourth current source I4; wherein the gate of the eighth MOSFET M8 is connected to a reference voltage V. REF Its source is connected to the source of the ninth MOSFET M9 and the inflow terminal of the fourth current source I4; the drain of the eighth MOSFET M8 is connected to the drain and gate of the tenth MOSFET M10 and the gate of the eleventh MOSFET M11; the gate of the ninth MOSFET M9 is connected to the feedback voltage V. FBThe drain of the eleventh MOSFET M11 is connected to the drain of the ninth MOSFET M9 and the gate of the twelfth MOSFET M12; the ratio of the number of parallel connections of the tenth MOSFET M10 and the eleventh MOSFET M11 is 1:K, where K is greater than 3; the drain of the twelfth MOSFET M12 is connected to the gate of the fourth MOSFET M4 in the FVF stage circuit; the output terminal of the fourth current source I4 is connected to the ground power rail GND; the sources of the tenth MOSFET M10, the eleventh MOSFET M11, and the twelfth MOSFET M12 are all connected to the power rail VDD.
[0011] The undershoot suppression circuit includes a thirteenth MOSFET M13, a fourteenth MOSFET M14, a fifteenth MOSFET M15, a sixteenth MOSFET M16, a seventeenth MOSFET M17, and a fifth current source I5; wherein the gate of the thirteenth MOSFET M13 is connected to the feedback power supply V. FB Its source is connected to the source of the fourteenth MOSFET M14 and the inflow terminal of the fifth current source I5; the drain of the thirteenth MOSFET M13 is connected to the drain of the fifteenth MOSFET M15 and the gate of the seventeenth MOSFET M17; the gate of the fourteenth MOSFET M14 is connected to the reference voltage V. REF Its drain is connected to the gate and drain of the sixteenth MOSFET M16 and the gate of the fifteenth MOSFET M15; the ratio of the number of parallel connections of the sixteenth MOSFET M16 and the fifteenth MOSFET M15 is 1:K, where K is greater than 3; the drain of the seventeenth MOSFET M17 is connected to the gate of the fourth MOSFET M4 in the FVF stage circuit; the source of the fifteenth MOSFET M15, the source of the sixteenth MOSFET M16, and the source of the seventeenth MOSFET M17 are connected to the ground power rail GND; the inflow terminal of the fifth current source I5 is connected to the power rail VDD.
[0012] Compared with existing technologies, the advantages of this invention are as follows: This invention proposes a fast transient response LDO without external capacitors based on an FVF architecture. Compared with the traditional FVF structure that uses mirrored MOSFETs to generate the control voltage, the structure proposed in this invention combines an error amplifier and an FVF stage, introducing a high-gain loop, which improves the output accuracy and load regulation of the LDO. The FVF stage introduces dynamic bias, which can provide a larger instantaneous current when the load changes and causes the output voltage to undershoot, effectively improving the slew rate and response speed. Overshoot suppression circuits and undershoot suppression circuits are also introduced to provide fast responses to light load to heavy load and heavy load to light load, respectively, reducing the output voltage change during load transitions. Attached Figure Description
[0013] Figure 1 This is the overall block diagram of the LDO without external capacitors proposed in this invention;
[0014] Figure 2 The circuit diagram of the FVF level proposed in this invention;
[0015] Figure 3 This is the circuit diagram for the overshoot suppression circuit;
[0016] Figure 4 This is the circuit diagram for the undershoot suppression circuit;
[0017] Figure 5 This is a waveform diagram of the LDO proposed in this invention during load transition. Detailed Implementation
[0018] This invention relates to a capacitorless LDO with fast transient response based on an FVF architecture, comprising an error amplifier, an FVF stage, and a transient enhancement circuit. Its key features are: modifications to the traditional FVF architecture; the use of an error amplifier to generate the loop gain, thereby improving the LDO's accuracy and load regulation; and the addition of overshoot and undershoot suppression circuits to suppress output voltage fluctuations that are prone to occur during load transitions in the capacitorless LDO.
[0019] like Figure 1 As shown, the capacitorless LDO based on FVF architecture with fast transient response has two loops, namely a high-gain loop and a fast-response loop.
[0020] The error amplifier is used to amplify the LDO output voltage V. OUT The feedback voltage V generated after being divided by resistors FB With reference voltage V REF The error is such that its output signal is connected to the gate of the first MOS transistor M1 in the FVF stage, and the source of the first MOS transistor is the LDO output voltage V. OUT Due to the involvement of the error amplifier, this loop forms a high-gain loop. Compared to the traditional FVF structure which only uses a current mirror, this structure introduces loop regulation to ensure the LDO output accuracy and performance.
[0021] like Figure 2As shown, the FVF stage circuit includes a first current source I1, a second current source I2, a third current source I3, a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, a first capacitor C1, a second capacitor C2, and a first resistor R1. The gate of the first MOSFET M1 is connected to the output terminal of the error amplifier. The source of the first MOSFET M1 is connected to the drain of the fourth MOSFET M4, the gate of the fifth MOSFET M5, and the upper plate of the second capacitor C2, and is the output terminal VOUT. The drain of the first MOSFET M1 is connected to the first current source I3, the positive terminal of the first resistor R1, the lower plate of the second capacitor C2, and the second... The gate of MOSFET M2 and the drain of the sixth MOSFET M6 are connected; the source of the second MOSFET M2 is connected to the third current source I1, the drain of the third MOSFET M3, and the gate of the fourth MOSFET M4, and its drain is connected to the gate of the third MOSFET M3 and the second current source I3; the drain of the fifth MOSFET M5 is connected to the gate of the sixth MOSFET, the gate and drain of the seventh MOSFET; the sources of the fourth MOSFET M4 and the fifth MOSFET, and the upper end of the first current source I1 are all connected to the power rail VDD; the sources of the third MOSFET M3, the sixth MOSFET M6, the seventh MOSFET M7, the lower plate of the first capacitor C1, the lower end of the second current source I2, and the lower end of the third current source I3 are all connected to the ground power rail GND;
[0022] The FVF stage forms a fast-response loop. Since this loop's bandwidth is significantly higher than the high-gain loop, when the output voltage fluctuates, the fast-response loop responds and adjusts before the high-gain loop. Therefore, the voltage at the error amplifier output, i.e., at the gate of the first MOS transistor M1 in the FVF stage, can be considered stable, and the voltage at the source of the first MOS transistor M1 is V... OUT Voltage fluctuations are mitigated through negative feedback regulation of the FVF stage, achieving a fast response effect. When switching from heavy load to light load, the slew rate of the FVF stage is large enough due to the large current, so it does not limit the response speed. When switching from light load to heavy load, the slew rate limits the response speed due to the small current and the presence of the first capacitor C1 and the second capacitor C2. The slew rate problem under light load can be solved by introducing dynamic bias through the fifth MOSFET M5, the sixth MOSFET M6 and the seventh MOSFET M7.
[0023] The transient enhancement circuit is divided into an overshoot suppression circuit and an undershoot suppression circuit;
[0024] like Figure 3 As shown, the overshoot suppression circuit includes an eighth MOSFET M8, a ninth MOSFET M9, a tenth MOSFET M10, an eleventh MOSFET M11, a twelfth MOSFET M12, and a fourth current source I4; wherein the gate of the eighth MOSFET M8 is connected to the reference voltage V. REFIts source is connected to the source of the ninth MOSFET M9 and the fourth current source I4; the drain of the eighth MOSFET M8 is connected to the drain and gate of the tenth MOSFET M10 and the gate of the eleventh MOSFET M11; the gate of the ninth MOSFET M9 is connected to the feedback voltage V. FB The drain of the eleventh MOSFET M11 is connected to the drain of the ninth MOSFET M9 and the gate of the twelfth MOSFET M12; the drain of the twelfth MOSFET M12 is connected to the gate of the fourth MOSFET M4 in the FVF stage circuit; the lower end of the fourth current source I4 is connected to the ground power rail GND; the drains of the tenth MOSFET M10, the eleventh MOSFET M11, and the twelfth MOSFET M12 are all connected to the power rail VDD.
[0025] like Figure 4 As shown, the undershoot suppression circuit includes a thirteenth MOSFET M13, a fourteenth MOSFET M14, a fifteenth MOSFET M15, a sixteenth MOSFET M16, a seventeenth MOSFET M17, and a fifth current source I5; wherein the gate of the thirteenth MOSFET M13 is connected to the feedback power supply V. FB Its source is connected to the source of the fourteenth MOSFET M14 and the fifth current source I5; the drain of the thirteenth MOSFET M13 is connected to the drain of the fifteenth MOSFET M15 and the gate of the seventeenth MOSFET M17; the gate of the fourteenth MOSFET M14 is connected to the reference voltage V. REF Its drain is connected to the gate and drain of the sixteenth MOSFET M16 and the gate of the fifteenth MOSFET M15; the drain of the seventeenth MOSFET M17 is connected to the gate of the fourth MOSFET M4 in the FVF stage circuit; the source of the fifteenth MOSFET M15, the source of the sixteenth MOSFET M16 and the source of the seventeenth MOSFET M17 are connected to the ground power rail GND; the upper end of the fifth current source I5 is connected to the power rail VDD;
[0026] The overshoot suppression circuit also compares the reference voltage V. REF The feedback voltage V obtained by dividing the output voltage and the feedback voltage V FB When the LDO is working normally, because the number of parallel connections of the eleventh MOSFET M11 is K times that of the tenth MOSFET M10, the gate of the twelfth MOSFET M23 is pulled high, keeping it in the off state and not participating in loop regulation; when the LDO transitions from light load to heavy load, V FB The downsampling, after being amplified in reverse by the ninth MOSFET M9, increases the gate voltage of the twelfth MOSFET M12. The twelfth MOSFET M12 remains off and does not participate in regulation. When the LDO transitions from heavy load to light load, the output voltage V... OUT Generates an upward surge, V FB It also surges proportionally, V FBThe reverse amplification via the ninth MOSFET M9 pulls down the gate voltage of the twelfth MOSFET M12, turning it on. Since the drain of this MOSFET is connected to the gate of the power transistor, it pulls up the gate voltage of the power transistor, thereby reducing the overshoot of the output voltage. Similarly, the undershoot suppression circuit compares the reference voltage V... REF and feedback voltage V FB When the LDO is working normally, since the number of parallel connections of the fifteenth MOSFET M15 is K times that of the seventeenth MOSFET M17, the gate of the seventeenth MOSFET M17 is pulled low, and this MOSFET is in the off state and does not participate in regulation. When the LDO transitions from heavy load to light load, the output voltage surges. After being amplified in reverse by the thirteenth MOSFET M13, the gate voltage of the seventeenth MOSFET M17 drops, and this MOSFET remains off and does not participate in regulation. When the LDO transitions from light load to heavy load, the output voltage drops. After being amplified in reverse by the thirteenth MOSFET M13, the gate voltage of the seventeenth MOSFET M17 is pulled up, turning it on. Because the drain of this MOSFET is connected to the gate of the power transistor, it will pull down the gate voltage of the power transistor, thereby reducing the dropout of the output voltage.
[0027] like Figure 5 As shown, at time t1, the LDO transitions from light load to heavy load. Due to the smaller bandwidth of the high-gain loop, there is no response at this time, and the undershoot suppression circuit is also not activated due to the decrease in output voltage. At this time, the LDO reduces the undershoot voltage through the combined action of the fast response loop and the undershoot suppression circuit, thereby achieving a faster response speed and a lower undershoot voltage. At time t2, the error amplifier begins to respond. At time t3, the LDO transitions from heavy load to light load. Similarly, the high-gain loop does not respond at this time, and the overshoot suppression circuit is also not activated. At this time, the LDO relies on the combined adjustment of the fast loop and the overshoot suppression circuit to reduce the overshoot voltage and accelerate the transient response of the circuit. At time t4, the error amplifier begins to respond and participates in the loop adjustment.
[0028] In summary, this invention proposes a capacitorless LDO with fast transient response based on an FVF architecture. Its key features include: modifications to the traditional FVF architecture; the use of an error amplifier to increase the loop gain, thereby improving the LDO's accuracy and load regulation; and the addition of overshoot and undershoot suppression circuits to suppress output voltage fluctuations that are prone to occur during load transitions in capacitorless LDOs.
Claims
1. A fast transient response LDO with no external capacitor based on FVF architecture, characterized in that, This includes an error amplifier, an FVF stage circuit, and a transient enhancement circuit; The negative terminal of the error amplifier is connected to a reference voltage V. REF The positive terminal is connected to the feedback voltage V. FB The output terminal is connected to the input terminal of the FVF stage, and the output terminal of the FVF stage is the output terminal of the LDO, V. OUT The FVF stage circuit has an internal fast loop with low gain and high bandwidth, enabling rapid feedback to suppress output voltage fluctuations; the transient enhancement circuit compares V... FB Voltage and V OUT The voltage is fed back to the FVF stage circuit to suppress overshoot and undershoot of the output voltage.
2. The fast transient response LDO with no external capacitor based on FVF architecture according to claim 1, characterized in that, The FVF stage circuit includes a first current source I1, a second current source I2, a third current source I3, a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, a first capacitor C1, a second capacitor C2, and a first resistor R1. The gate of the first MOSFET M1 is connected to the output terminal of the error amplifier, and the source of the first MOSFET M1 is connected to the drain of the fourth MOSFET M4, the gate of the fifth MOSFET M5, and the upper plate of the second capacitor C2. The connection point is the output terminal V. OUT The drain of the first MOSFET M1 is connected to the inlet of the third current source I3, the upper plate of the first capacitor C1, the lower plate of the second capacitor C2, the gate of the second MOSFET M2, and the drain of the sixth MOSFET M6; the lower plate of the first capacitor C1 is connected to one end of the first resistor R1; the source of the second MOSFET M2 is connected to the outlet of the first current source I1, the drain of the third MOSFET M3, and the gate of the fourth MOSFET M4; the drain of the second MOSFET M2 is connected to the gate of the third MOSFET M3 and the inlet of the second current source I2; the drain of the fifth MOSFET M5 is connected to the gate of the sixth MOSFET and the gate and drain of the seventh MOSFET; the sources of the fourth MOSFET M4 and the fifth MOSFET, and the inlet of the first current source I1 are all connected to the power rail VDD; the sources of the third MOSFET M3, the sixth MOSFET M6, the seventh MOSFET M7, the other end of the first resistor R1, the outlet of the second current source I2, and the outlet of the third current source I3 are all connected to the ground power rail GND.
3. The fast transient response LDO with no external capacitor based on FVF architecture according to claim 2, characterized in that, The transient enhancement circuit includes an overshoot suppression circuit and an undershoot suppression circuit; The overshoot suppression circuit includes an eighth MOSFET M8, a ninth MOSFET M9, a tenth MOSFET M10, an eleventh MOSFET M11, a twelfth MOSFET M12, and a fourth current source I4; wherein the gate of the eighth MOSFET M8 is connected to a reference voltage V. REF Its source is connected to the source of the ninth MOSFET M9 and the inflow terminal of the fourth current source I4; the drain of the eighth MOSFET M8 is connected to the drain and gate of the tenth MOSFET M10 and the gate of the eleventh MOSFET M11; the gate of the ninth MOSFET M9 is connected to the feedback voltage V. FB The drain of the eleventh MOSFET M11 is connected to the drain of the ninth MOSFET M9 and the gate of the twelfth MOSFET M12; the ratio of the number of parallel connections of the tenth MOSFET M10 and the eleventh MOSFET M11 is 1:K, where K is greater than 3; the drain of the twelfth MOSFET M12 is connected to the gate of the fourth MOSFET M4 in the FVF stage circuit; the output terminal of the fourth current source I4 is connected to the ground power rail GND; the sources of the tenth MOSFET M10, the eleventh MOSFET M11, and the twelfth MOSFET M12 are all connected to the power rail VDD. The undershoot suppression circuit includes a thirteenth MOSFET M13, a fourteenth MOSFET M14, a fifteenth MOSFET M15, a sixteenth MOSFET M16, a seventeenth MOSFET M17, and a fifth current source I5; wherein the gate of the thirteenth MOSFET M13 is connected to the feedback power supply V. FB Its source is connected to the source of the fourteenth MOSFET M14 and the inflow terminal of the fifth current source I5; the drain of the thirteenth MOSFET M13 is connected to the drain of the fifteenth MOSFET M15 and the gate of the seventeenth MOSFET M17; the gate of the fourteenth MOSFET M14 is connected to the reference voltage V. REF Its drain is connected to the gate and drain of the sixteenth MOSFET M16 and the gate of the fifteenth MOSFET M15; the ratio of the number of parallel connections of the sixteenth MOSFET M16 and the fifteenth MOSFET M15 is 1:K, where K is greater than 3; the drain of the seventeenth MOSFET M17 is connected to the gate of the fourth MOSFET M4 in the FVF stage circuit; the source of the fifteenth MOSFET M15, the source of the sixteenth MOSFET M16, and the source of the seventeenth MOSFET M17 are connected to the ground power rail GND; the inflow terminal of the fifth current source I5 is connected to the power rail VDD.