PCIe topology switching method, device and equipment and readable storage medium

Abstract

The invention provides a PCIe topology switching method, device and equipment and a readable storage medium, and the method comprises the steps: obtaining the state information of current in-place PCIe equipment in response to a topology switching request; adjusting PCIe equipment associated with a non-gating target according to the gating target shown by the topology switching request and the obtained state information of the current in-place PCIe equipment; and issuing a gating instruction to enable the MUX chip to switch and gate to the gating target, and reconfiguring the PCIe resources after the MUX chip completes the switching and the gating. According to the technical scheme, the gating target of the MUX chip is dynamically adjusted, the PCIe device associated with the non-gating target is adjusted according to the current in-place PCIe device state information before switching, reconfiguration of PCIe resources in the server is achieved, shutdown or restarting is not needed, the hardware topology adjustment process is simplified, and the configuration flexibility and the operation and maintenance efficiency of the server are improved.

Description

Technical Field

[0001] This specification relates to the field of communication technology, and in particular to a PCIe topology switching method, apparatus, device, and readable storage medium. Background Technology

[0002] With the rapid development of artificial intelligence, scientific computing, and high-performance data analytics, graphics processing unit (GPU) servers have become the core infrastructure of modern data centers. With the widespread adoption of mainstream GPU architectures, the need for flexible configuration of server topologies is increasingly prominent. Typical current applications, such as large-scale machine learning training and real-time data analysis, not only require servers to provide ultra-high computing density but also need to dynamically adjust resource allocation strategies according to different workloads. For example, maximizing interconnect bandwidth between GPUs may be necessary during deep learning training, while prioritizing storage device bandwidth is crucial during data preprocessing. This dynamic resource optimization requirement makes flexible switching of server topologies a key technology for improving computing efficiency.

[0003] In one technical solution, taking an 8-port topology server architecture as an example, this architecture is based on a dual-CPU design, with each CPU equipped with six high-speed channels: one channel is dedicated to the interconnect link between the two CPUs, four channels are grouped into two pairs to connect to two switch chips (each switch chip is allocated two uplink channels), and the last channel is fixedly connected to a PCIe Riser adapter card. The switch chip acts as the core switching hub, with its downlink connecting various PCIe devices, including GPU accelerator cards, high-speed network interface cards (NICs), and NVMe solid-state storage devices. While this architecture can provide stable high-performance computing capabilities under static configuration, its topology is inherently rigid. When users need to adjust the topology configuration, such as switching from GPU-intensive computing mode to storage-optimized mode, the server must be completely powered off, requiring maintenance personnel to physically unpack and manually adjust cable connections, replace adapter card layouts, or reconfigure jumpers.

[0004] This hardware-level operation not only requires on-site implementation by professionals, but also significantly extends server downtime, with the average downtime for a single topology adjustment exceeding 30 minutes, and may trigger a chain of service interruptions in complex data center environments. Summary of the Invention

[0005] In view of this, this specification provides a PCIe topology switching method, apparatus, device, and readable storage medium to improve the problem of slow topology switching speed.

[0006] The specific technical solution is as follows:

[0007] This specification provides a PCIe topology switching method applied to a server's BMC device. The server includes a CPU with at least two PCIe lanes. The CPU is connected to a PCIe Switch through one PCIe lane and to a MUX chip through the other PCIe lane. The MUX chip is connected to a PCIe adapter card and the PCIe Switch. The MUX chip selects the PCIe adapter card or PCIe Switch it is connected to. The method includes: responding to a topology switching request, obtaining the status information of currently present PCIe devices; adjusting the PCIe devices associated with non-selection targets according to the selection target indicated in the topology switching request and the obtained status information of currently present PCIe devices, wherein the selection target is a PCIe adapter card or a PCIe Switch; issuing a selection command to cause the MUX chip to switch to the selection target; and reconfiguring PCIe resources after the MUX chip completes the switching selection.

[0008] As a technical solution, the topology switching request indicates that the selection target is a PCIe Switch; adjusting the PCIe devices associated with non-selection targets according to the selection target indicated by the topology switching request and the obtained status information of the currently in-situ PCIe devices includes: disabling the currently in-situ PCIe devices on the adapter card according to the obtained status information of the currently in-situ PCIe devices on the adapter card; reconfiguring PCIe resources after the MUX chip completes the switching selection includes: reconfiguring more PCIe resources for the PCIe devices located at the PCIe Switch than before the reconfiguration.

[0009] As a technical solution, the gating target indicated by the topology switching request is the adapter card; adjusting the PCIe devices associated with non-gating targets according to the gating target indicated by the topology switching request and the obtained current in-situ PCIe device status information includes: reconfiguring fewer PCIe resources for the PCIe devices located at the PCIe Switch than before reconfiguration; reconfiguring PCIe resources after the MUX chip completes the switching gating includes: configuring PCIe resources for the PCIe devices located at the adapter card.

[0010] As a technical solution, the server includes a CPU with at least 2N PCIe lanes. The CPU is connected to N PCIe switches through N of the PCIe lanes and to N MUX chips through another N of the PCIe lanes. Each MUX chip is connected to a PCIe adapter card and to one of the N PCIe switches. Each MUX chip selects the PCIe adapter card or PCIe switch it is connected to.

[0011] This specification also provides a PCIe topology switching device applied to a server's BMC device. The server includes a CPU with at least two PCIe lanes. The CPU is connected to a PCIe Switch through one PCIe lane and to a MUX chip through the other PCIe lane. The MUX chip is connected to a PCIe adapter card and the PCIe Switch. The MUX chip selects the PCIe adapter card or PCIe Switch it is connected to. The device includes: a first module for obtaining the status information of currently present PCIe devices in response to a topology switching request; a second module for adjusting the PCIe devices associated with non-selection targets based on the selection target indicated in the topology switching request and the obtained status information of currently present PCIe devices, where the selection target is a PCIe adapter card or a PCIe Switch; and a third module for issuing a selection command to cause the MUX chip to switch to the selection target, and reconfiguring PCIe resources after the MUX chip completes the switching selection.

[0012] As a technical solution, the topology switching request indicates that the selection target is a PCIe Switch; adjusting the PCIe devices associated with non-selection targets according to the selection target indicated by the topology switching request and the obtained status information of the currently in-situ PCIe devices includes: disabling the currently in-situ PCIe devices on the adapter card according to the obtained status information of the currently in-situ PCIe devices on the adapter card; reconfiguring PCIe resources after the MUX chip completes the switching selection includes: reconfiguring more PCIe resources for the PCIe devices located at the PCIe Switch than before the reconfiguration.

[0013] As a technical solution, the gating target indicated by the topology switching request is the adapter card; adjusting the PCIe devices associated with non-gating targets according to the gating target indicated by the topology switching request and the obtained current in-situ PCIe device status information includes: reconfiguring fewer PCIe resources for the PCIe devices located at the PCIe Switch than before reconfiguration; reconfiguring PCIe resources after the MUX chip completes the switching gating includes: configuring PCIe resources for the PCIe devices located at the adapter card.

[0014] As a technical solution, the server includes a CPU with at least 2N PCIe lanes. The CPU is connected to N PCIe switches through N of the PCIe lanes and to N MUX chips through another N of the PCIe lanes. Each MUX chip is connected to a PCIe adapter card and to one of the N PCIe switches. Each MUX chip selects the PCIe adapter card or PCIe switch it is connected to.

[0015] This specification also provides a server, including: a BMC device, which is used to respond to a topology switching request, obtain the status information of currently present PCIe devices, and adjust the PCIe devices associated with non-selection targets according to the selection target indicated in the topology switching request and the obtained status information of currently present PCIe devices, wherein the selection target is a PCIe adapter card or a PCIe switch, and then issue a selection command to cause the MUX chip to switch to the selection target, and reconfigure the PCIe resources after the MUX chip completes the switching selection; a CPU, which has at least two PCIe lanes, the CPU is connected to the PCIe switch through one PCIe lane and connected to the MUX chip through the other PCIe lane; a PCIe switch, which is connected to the CPU through a PCIe lane, and the PCIe switch can have one or more PCIe devices connected to it, the one or more PCIe devices sharing the PCIe bandwidth between the PCIe switch and the CPU; and a MUX chip, which is connected to the PCIe adapter card and the PCIe... Switch, MUX chip selects the PCIe adapter card or PCIe Switch connected to itself; PCIe adapter card, the PCIe adapter card can be connected to PCIe devices.

[0016] As a technical solution, a CPLD is used to connect a BMC device, a MUX chip, and a PCIe adapter card. The CPLD obtains the status information of the in-situ PCIe device on the PCIe adapter card from the signaling of the BMC device and feeds it back to the BMC device. The CPLD controls the MUX chip to switch and select according to the signaling of the BMC device.

[0017] This specification also provides an electronic device, including a processor and a readable storage medium storing machine-executable instructions that can be executed by the processor, the processor executing the machine-executable instructions to implement the aforementioned PCIe topology switching method.

[0018] This specification also provides a readable storage medium storing machine-executable instructions that, when invoked and executed by a processor, cause the processor to implement the aforementioned PCIe topology switching method.

[0019] The technical solutions provided in this specification offer at least the following beneficial effects:

[0020] The system dynamically adjusts the selection target of the MUX chip and adjusts the PCIe devices associated with non-selection targets based on the current status information of in-place PCIe devices before switching. This enables the reconfiguration of PCIe resources within the server without the need for shutdown or restart, simplifying the hardware topology adjustment process and improving server configuration flexibility and operational efficiency. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the drawings used in the description of the embodiments of this specification or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained based on these drawings of the embodiments of this specification.

[0022] Figure 1 This is a flowchart of a PCIe topology switching method in one embodiment of this specification;

[0023] Figure 2 This is a structural diagram of a PCIe topology switching device according to one embodiment of this specification;

[0024] Figure 3 This is a schematic diagram of the server hardware structure in one embodiment of this specification;

[0025] Figure 4 This is a hardware structure diagram of an electronic device according to one embodiment of this specification.

[0026] Reference numerals: Module 1 21, Module 22, Module 3 23. Detailed Implementation

[0027] The terminology used in the embodiments described herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this specification. The singular forms “a,” “described,” and “the” as used in this specification and claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to any and all possible combinations comprising one or more of the associated listed items.

[0028] It should be understood that although the terms first, second, third, etc., may be used to describe various information in embodiments of this specification, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this specification, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" may also be interpreted as "when," "when," or "in response to a determination."

[0029] This specification provides a PCIe topology switching method, apparatus, device, and readable storage medium to at least improve one of the above-mentioned technical problems.

[0030] The specific technical solution is described below.

[0031] In one embodiment, this specification provides a PCIe topology switching method applied to a server's BMC device. The server includes a CPU with at least two PCIe lanes. The CPU is connected to a PCIe Switch through one PCIe lane and to a MUX chip through the other PCIe lane. The MUX chip is connected to a PCIe adapter card and the PCIe Switch. The MUX chip selects the PCIe adapter card or PCIe Switch it is connected to. The method includes: responding to a topology switching request, obtaining the status information of currently present PCIe devices; adjusting the PCIe devices associated with non-selection targets according to the selection target indicated in the topology switching request and the obtained status information of currently present PCIe devices, wherein the selection target is a PCIe adapter card or a PCIe Switch; issuing a selection command to cause the MUX chip to switch to the selection target; and reconfiguring PCIe resources after the MUX chip completes the switching selection.

[0032] Specifically, such as Figure 1 This includes the following steps:

[0033] The server configuration includes at least one CPU with multiple PCIe lanes. One PCIe lane is directly connected to a PCIe switch, and another is connected to a MUX chip. The MUX chip is connected to a PCIe adapter card (typically used to install a GPU or other high-performance computing card) and also to the aforementioned PCIe switch. The core function of the MUX chip is its ability to selectively connect the CPU's PCIe lanes to the PCIe adapter card or PCIe switch based on control signals, thereby enabling dynamic switching of the topology.

[0034] Step S11: In response to the topology switching request, obtain the status information of the currently in-situ PCIe device.

[0035] A topology switch request is responded to by the BMC device. This request can originate from an administrator's command via a management interface (such as a Web UI, command-line tool, or API call), or it can be triggered based on preset policies or automated scripts. For example, when the system detects that the currently running deep learning training task has extremely high GPU computing power requirements, but the existing GPU connection method causes bandwidth to become a bottleneck, the system can automatically initiate a switch request to optimize the GPU connection path to achieve a higher data transfer rate. As an independent management controller for the server, the BMC has the ability to monitor and control the hardware status, and therefore can receive and process such requests. Upon receiving a topology switch request, the BMC obtains the status information of the currently present PCIe devices, including but not limited to identifying the type, quantity, current operating status (such as whether it is active, standby, or faulty), firmware version, and their position in the PCIe topology of all devices currently connected through PCIe adapter cards and PCIe switches.

[0036] The BMC can collect this information by reading the PCIe configuration space, querying the device's health status register, or interacting with the device driver. For example, the BMC can send probe commands to all ports connected to the PCIe switch to identify which ports have devices connected and read the Vendor ID and Device ID of these devices to determine their identity.

[0037] Step S12: Based on the gating target shown in the topology switching request and the obtained current in-situ PCIe device status information, adjust the PCIe devices associated with the non-gating target.

[0038] After obtaining detailed current device status information, BMC will adjust the PCIe devices associated with non-gated targets based on the "gating target" explicitly specified in the topology switching request, i.e. the device that the MUX chip is ultimately connected to (whether it is a PCIe adapter card or a PCIe switch), and the current device status.

[0039] The "adjustment" here does not refer to a simple physical disconnection, but rather to preparing for a connection change through software means, such as notifying the operating system, drivers, or the device itself. The purpose is to ensure that all devices associated with the path to be disconnected are in a safe state before the MUX chip performs a physical switch, thus preventing data loss or system crashes.

[0040] For example, if the selected target is a PCIe adapter card, it means the MUX chip will switch from connecting to a PCIe switch to connecting to the PCIe adapter card. In this case, non-critical devices connected to the PCIe switch (such as some auxiliary NVMe hard drives or low-priority network cards) need to be safely offloaded or placed in low-power mode. The BMC can notify the server's operating system to prepare for device removal via IPMI (Intelligent Platform Management Interface) commands or other management protocols. The operating system will then execute the corresponding driver uninstallation and resource release procedures. For some hot-swappable devices that depend on a specific path, it may also be necessary to migrate their workloads to other available paths. This adjustment process is crucial to ensuring a smooth and lossless topology switch, demonstrating the intelligent coordination capabilities of this approach at the software level.

[0041] Step S13: Issue a selection command to enable the MUX chip to switch to the selection target, and reconfigure the PCIe resources after the MUX chip completes the switching selection.

[0042] After adjusting the non-selected target associated devices, the BMC issues a selection command. This command is sent through a dedicated control channel between the BMC and the MUX chip (via CPLD, but depending on the hardware circuitry, it can also be sent via a dedicated bus such as I2C, SMBus, or GPIO), instructing the MUX chip to change its internal switching state, thereby switching the CPU's PCIe channel from the currently connected path to the requested selection target path.

[0043] For example, if the current MUX chip is connected to a PCIe switch, and the request is to switch to a PCIe adapter card, then the communication selection command will trigger the electronic switch inside the MUX chip, disconnecting the connection with the PCIe switch and simultaneously establishing a connection with the PCIe adapter card.

[0044] After confirming that the MUX chip has completed the switching selection, the BMC reconfigures the PCIe resources. Reconfiguration mainly includes two aspects: first, notifying the operating system and related drivers that the current PCIe topology has changed, requiring re-enumeration and identification of devices on the new connection path; second, based on the new topology, it may be necessary to adjust parameters such as the width and speed of the PCIe links to achieve optimal performance.

[0045] For example, when the MUX chip switches to a PCIe adapter card, the BMC instructs the operating system to perform a PCIe bus scan. The operating system will then discover GPU devices that may have been previously unrecognized or not fully enabled, and load the corresponding drivers. Simultaneously, the BMC or BIOS / UEFI firmware may need to reallocate system resources such as interrupts and memory address spaces based on the new connection method. For some high-performance devices, such as GPUs, more granular configuration via ACPI (Advanced Configuration and Power Interface) or specific firmware interfaces may be required to ensure maximum performance under the new topology. Furthermore, the BMC itself will update its internal device status database to record this topology change for subsequent management and monitoring.

[0046] In one implementation, the gating target indicated by the topology switching request is a PCIe Switch; adjusting the PCIe devices associated with non-gating targets based on the gating target indicated by the topology switching request and the obtained status information of currently in-place PCIe devices includes: disabling the currently in-place PCIe devices on the adapter card based on the obtained status information of currently in-place PCIe devices on the adapter card; reconfiguring PCIe resources after the MUX chip completes the switching gating includes: reconfiguring more PCIe resources for the PCIe devices located at the PCIe Switch than before the reconfiguration.

[0047] In one implementation, the gating target indicated by the topology switching request is a switch card; adjusting the PCIe devices associated with non-gating targets based on the gating target indicated by the topology switching request and the obtained current in-situ PCIe device status information includes: reconfiguring fewer PCIe resources for PCIe devices located at the PCIe Switch than before reconfiguration; reconfiguring PCIe resources after the MUX chip completes the switching gating includes: configuring PCIe resources for PCIe devices located at the switch card.

[0048] In one embodiment, the server includes a CPU with at least 2N PCIe lanes. The CPU is connected to N PCIe switches through N of the PCIe lanes and to N MUX chips through another N of the PCIe lanes. Each MUX chip is connected to a PCIe adapter card and to one of the N PCIe switches. Each MUX chip selects the PCIe adapter card or PCIe switch to which it is connected.

[0049] In one implementation, taking a symmetrical installation of two CPUs in a 2U server configuration as an example, each CPU provides six x16 PCIe Gen5 high-speed lanes. One x16 lane is permanently fixed as the UPI interconnect between the two CPUs, and the remaining five x16 lanes are split: two directly connect to the uplink ports of Switch-A and Switch-B, two connect to the uplink ports of Switch-C and Switch-D after passing through a low-latency 8-lane PCIe MUX chip, and the last x16 lane is connected to a hot-swappable OCP 3.0 Riser adapter card through another set of differential lines on the same MUX chip. The Riser card has two reserved x8 slots for inserting dual-port NICs or dual-port NVMe SSD expansion modules. The MUX chip integrates I2C and SMBus management interfaces, and its SEL0 / SEL1 select pins are directly driven by the motherboard CPLD; the CPLD is connected to the BMC AST2600 through the LPC bus, thus forming a control path of "BMC→CPLD→MUX". The BMC firmware maintains a real-time PCIe device presence table in memory, which is continuously updated by the CPLD polling the Riser card and all downstream terminals of the Switch with the PRSNT#, PWRGD, and PERST# signals.

[0050] Whenever maintenance personnel perform topology switching on the WebUI or Redfish API, the BMC first verifies that the current GPU temperature is below 65°C and there is no active DMA on the link. Then, it calls an internal script to read the presence table: if the current mode is 8-port, the Riser slot must be empty or the NIC in it must be in D3cold; if the current mode is 4-port, all downstream GPUs of Switch-C and Switch-D must be in D3cold. After the verification is successful, the BMC sends the list of devices to be isolated to the host OS using the ACPI_DSM method. The operating system then safely removes the devices via PCIe hot-reset. Next, the BMC sends a 0xA5 switching command word to the CPLD, the CPLD toggles the SEL0 / SEL1 level, and the MUX internal crossbar switch switches to another set of differential lines.

[0051] After the switchover, the CPLD raises the "DONE" interrupt on the MUX. Upon receiving this, the BMC triggers the BIOS SMI handler, and the BIOS re-enumerates the PCIe topology and updates the IOMEM and IRQ routes. Simultaneously, the BMC sends instructions to the Switch via NC-SI to ensure that all links renegotiate their rates at Gen5 x16. The entire system remains powered on during the switchover process, the GPU driver does not need to be reloaded, and the VFIO pass-through devices in the virtual machine only experience one PCIe hot-plug event, resulting in virtually zero impact on user services.

[0052] Taking a typical "8-port to 4-port" operation as an example, assume that the data center runs AI training tasks during the day, with eight GPUs occupying all eight x16 downlink bandwidths via Switch-A / B / C / D in a fully interconnected Fat-Tree configuration. At night, after the task ends, the operations team plans to power off four of the GPUs to save energy and insert two NVMe SSDs for data lake ETL. At the start of the operation, the BMC WebUI displays a confirmation dialog. After user confirmation, the BMC writes instructions to the four GPUs connected downstream of Switch-C / D to put them into a specific state. Then, the BMC reads the CPLD register via I2C to confirm that the Riser slot is empty, meeting the switching conditions. Next, the BMC executes instructions to trigger the Linux PCIe core to remove Switch-C / D and its connected GPUs. Subsequently, the BMC sets SEL0 to 0 and SEL1 to 1, and the MUX switches the two x16 slots originally leading to Switch-C / D to the Riser. The BIOS calls PcieRpReEnumerate() in SMI to allocate a new 32GB IOMEM window for the Riser slot and updates _CRS in the ACPI table.

[0053] After each successful switchover, BMC writes the event to the SEL log, including the switchover type, power consumption before and after the switchover, peak GPU temperature, and link negotiation rate, for subsequent capacity planning and fault backtracking.

[0054] In one implementation, such as Figure 2 This specification also provides a PCIe topology switching device applied to the BMC device of a server. The server includes a CPU with at least two PCIe lanes. The CPU is connected to a PCIe Switch through one PCIe lane and to a MUX chip through the other PCIe lane. The MUX chip is connected to a PCIe adapter card and the PCIe Switch. The MUX chip selects the PCIe adapter card or PCIe Switch it is connected to. The device includes: a first module for obtaining the status information of currently present PCIe devices in response to a topology switching request; a second module for adjusting the PCIe devices associated with non-selection targets according to the selection target indicated in the topology switching request and the obtained status information of currently present PCIe devices, wherein the selection target is a PCIe adapter card or a PCIe Switch; and a third module for issuing a selection command to cause the MUX chip to switch to the selection target, and reconfiguring PCIe resources after the MUX chip completes the switching selection.

[0055] In one implementation, the gating target indicated by the topology switching request is a PCIe Switch; adjusting the PCIe devices associated with non-gating targets based on the gating target indicated by the topology switching request and the obtained status information of currently in-place PCIe devices includes: disabling the currently in-place PCIe devices on the adapter card based on the obtained status information of currently in-place PCIe devices on the adapter card; reconfiguring PCIe resources after the MUX chip completes the switching gating includes: reconfiguring more PCIe resources for the PCIe devices located at the PCIe Switch than before the reconfiguration.

[0056] In one implementation, the gating target indicated by the topology switching request is a switch card; adjusting the PCIe devices associated with non-gating targets based on the gating target indicated by the topology switching request and the obtained current in-situ PCIe device status information includes: reconfiguring fewer PCIe resources for PCIe devices located at the PCIe Switch than before reconfiguration; reconfiguring PCIe resources after the MUX chip completes the switching gating includes: configuring PCIe resources for PCIe devices located at the switch card.

[0057] In one embodiment, the server includes a CPU with at least 2N PCIe lanes. The CPU is connected to N PCIe switches through N of the PCIe lanes and to N MUX chips through another N of the PCIe lanes. Each MUX chip is connected to a PCIe adapter card and to one of the N PCIe switches. Each MUX chip selects the PCIe adapter card or PCIe switch to which it is connected.

[0058] In one implementation, such as Figure 3The implementation of PCIe topology switching devices relies on specific hardware architecture support. Taking a dual-CPU server platform as an example, each CPU is equipped with six high-speed PCIe 5.0 x16 lanes. Lanes 1 and 2 are directly connected to two PCIe switch chips, lanes 3 and 4 are connected to MUX chips respectively, lane 5 is used for inter-CPU UPI interconnection, and lane 6 is fixedly connected to a PCIe riser. The MUX chip, as the core routing device, connects its input ports to either the 3rd or 4th lane of the CPU, and its two output ports connect to the uplink ports of the riser and the PCIe switch respectively. This design allows a single CPU lane to be dynamically routed through the MUX. When the MUX selects a switch, that lane becomes an additional uplink for the switch; when it selects a riser, it activates the PCIe device expansion capabilities on the riser. In a typical 8-port topology configuration, of the six channels of the two CPUs, four channels (channels 1-4) are connected to four switch chips via direct connection or MUX gating (each switch gets two uplink channels), allowing the system to support 32 GPUs. In a 4-port topology, the MUX switches the channels to the Riser, retaining only the two direct connection channels to the Switch (each switch has only one uplink channel). In this case, the NVMe storage array on the Riser is activated, halving the number of GPUs but increasing storage bandwidth by 300%.

[0059] During system power-on initialization, the Baseboard Management Controller (BMC) loads the default configuration register of the MUX chip via the I2C bus, setting the initial topology to 8-port mode. At this time, the CPLD continuously monitors the PRSNT# signal pin of the Riser slot. When a Riser card is detected inserted, it updates the in-situ status code and stores it in the BMC's shared memory area. When maintenance personnel initiate a topology switch request (e.g., switching from 8-port to 4-port) through the BMC's Redfish API interface, the BMC first calls the device status acquisition module. This module sends an SDR command to the CPLD via the IPMB bus to read the PCIe device in-situ status register. If the register returns the first signal (indicating the Riser card is in place), it continues to query the Switch connection status register; if it returns the second signal (Riser card not inserted), the BMC terminates the switch process and returns the error code ERR_DEVICE_MISSING. After obtaining the device status, the BMC performs a masking operation on the non-gated target device. Taking the switch to 4-port mode as an example, the gated target is the Riser (the non-gated target is the Switch). The BMC clears the VF Enable bit of the SR-IOV function register of the downstream Switch to zero through the PCIe configuration space access mechanism, and at the same time sends the ACPI_OFF command to the BIOS to make the relevant PCIe function domain enter the D3cold state.

[0060] After device shielding is completed, the BMC triggers the MUX switching sequence via GPIO pins. Specifically, the BMC's GPIO12 pin is connected to the SEL control terminal of the MUX chip. It outputs a high level (3.3V) when the Riser needs to be selected and a low level (0V) when the Switch needs to be selected. After the level change, the MUX chip completes the channel switching within 50ns and sends an interrupt signal to the BMC via the INT# pin. Upon receiving the interrupt, the BMC starts a 50ms delay timer. After the signal stabilizes, it reads bit 0x0F of the MUX status register. When this bit value equals the selection target code (Riser = 0xAA, Switch = 0x55), the switching is confirmed to be successful. At this point, the BMC notifies the BIOS to perform PCIe resource reconfiguration via IPMI command 0x30. The BIOS first scans the PCIe tree structure. For newly added devices (such as the Riser card appearing when switching to 4 ports), it adds a _PRT route entry to the ACPI table and assigns a new Bus / Device / Function number. For blocked devices, it releases the MMIO space they occupy (for example, in 8-port mode, after a GPU device that originally occupied 4GB MMIO is removed, that address space is marked as available). It's worth noting that during the resource reconfiguration phase, the BIOS calls the PCIe Hot-Plug service routine to perform a Secondary Bus Reset operation on the Switch chip. Downstream devices will undergo a link retraining process, but the operating system can recognize the new topology without a reboot.

[0061] In one embodiment, this specification also provides a server, comprising: a BMC device, the BMC device being configured to, in response to a topology switching request, obtain the status information of currently present PCIe devices, and, based on the gating target indicated in the topology switching request and the obtained status information of the currently present PCIe devices, adjust the PCIe devices associated with non-gating targets, the gating target being a PCIe adapter card or a PCIe switch, and then issue a gating command to cause a MUX chip to switch gating to the gating target, and reconfigure PCIe resources after the MUX chip completes the gating switch; a CPU, the CPU having at least two PCIe lanes, the CPU being connected to a PCIe switch through one PCIe lane and to a MUX chip through the other PCIe lane; a PCIe switch, the PCIe switch being connected to the CPU through a PCIe lane, the PCIe switch being able to connect to one or more PCIe devices, the one or more PCIe devices sharing the PCIe bandwidth between the PCIe switch and the CPU; and a MUX chip, the MUX chip being connected to a PCIe adapter card and connected to the PCIe... Switch, MUX chip selects the PCIe adapter card or PCIe switch connected to itself; PCIe adapter card, the PCIe adapter card can be connected to PCIe devices.

[0062] In one embodiment, a CPLD is used to connect a BMC device, a MUX chip, and a PCIe adapter card. The CPLD obtains the status information of the in-situ PCIe device on the PCIe adapter card from the signaling of the BMC device and feeds it back to the BMC device. The CPLD controls the switching and selection of the MUX chip according to the signaling of the BMC device.

[0063] In one embodiment, this specification provides an electronic device including a processor and a readable storage medium storing machine-executable instructions executable by the processor. The processor executes the machine-executable instructions to implement the aforementioned PCIe topology switching method. From a hardware perspective, a hardware architecture diagram can be found... Figure 4 As shown.

[0064] In one embodiment, this specification provides a readable storage medium storing machine-executable instructions that, when invoked and executed by a processor, cause the processor to implement the aforementioned PCIe topology switching method.

[0065] Here, a readable storage medium can be any electronic, magnetic, optical, or other physical storage device that can contain or store information, such as executable instructions, data, etc. For example, a readable storage medium can be: RAM (Random Access Memory), volatile memory, non-volatile memory, flash memory, storage drives (such as hard disk drives), solid-state drives, any type of storage disk (such as optical discs, DVDs, etc.), or similar storage media, or combinations thereof.

[0066] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer, which can take the form of a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email sending and receiving device, game console, tablet computer, wearable device, or any combination of these devices.

[0067] For ease of description, the above devices are described in terms of function, divided into various units. Of course, in implementing this specification, the functions of each unit can be implemented in one or more software and / or hardware components.

[0068] Those skilled in the art will understand that embodiments of this specification can be provided as methods, systems, or computer program products. Therefore, this specification may take the form of a completely hardware implementation, a completely software implementation, or an implementation combining software and hardware aspects. Furthermore, embodiments of this specification may take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0069] This specification is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments thereof. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0070] Furthermore, these computer program instructions can also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in the process. Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0071] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0072] Those skilled in the art will understand that embodiments of this specification can be provided as methods, systems, or computer program products. Therefore, this specification can take the form of a completely hardware implementation, a completely software implementation, or an implementation combining software and hardware aspects. Furthermore, this specification can take the form of a computer program product implemented on one or more computer-usable storage media (which may include, but are not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0073] The above description is merely an embodiment of this specification and is not intended to limit this specification. Various modifications and variations can be made to this specification by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of the claims of this specification.

Claims

1. A PCIe topology switching method, characterized in that, A BMC device for use in servers, the server including a CPU with at least two PCIe lanes, the CPU being connected to a PCIe switch through one PCIe lane and to a MUX chip through the other PCIe lane, the MUX chip being connected to a PCIe adapter card and the PCIe switch, the MUX chip selectively selecting either the PCIe adapter card or the PCIe switch connected to it, the method comprising: In response to a topology switch request, obtain the status information of the currently in-situ PCIe devices; Based on the gating target shown in the topology switching request and the obtained current in-situ PCIe device status information, adjust the PCIe devices associated with non-gating targets, where the gating target is a PCIe adapter card or a PCIe switch. A selection command is issued to switch the MUX chip to the selection target. After the MUX chip completes the selection switch, the PCIe resources are reconfigured.

2. The method according to claim 1, characterized in that, The topology switching request indicates that the selected target is PCIeSwitch; The step of adjusting the PCIe devices associated with non-gated targets based on the gating target shown in the topology switching request and the obtained current in-place PCIe device status information includes: Based on the obtained status information of the currently present PCIe devices on the adapter card, the currently present PCIe devices on the adapter card are blocked. The reconfiguration of PCIe resources after the MUX chip completes the switching selection includes: To reconfigure more PCIe resources on a PCIe device located at a PCIe Switch than before the reconfiguration.

3. The method according to claim 1, characterized in that, The topology switching request indicates that the selected target is the adapter card; The step of adjusting the PCIe devices associated with non-gated targets based on the gating target shown in the topology switching request and the obtained current in-place PCIe device status information includes: To reconfigure fewer PCIe resources on a PCIe device located at a PCIe Switch than before the reconfiguration; The reconfiguration of PCIe resources after the MUX chip completes the switching selection includes: Configure PCIe resources for PCIe devices located on the adapter card.

4. The method according to claim 1, characterized in that, The server includes a CPU with at least 2N PCIe lanes. The CPU is connected to N PCIe switches through N of the PCIe lanes and to N MUX chips through another N of the PCIe lanes. Each MUX chip is connected to a PCIe adapter card and to one of the N PCIe switches. Each MUX chip selects the PCIe adapter card or PCIe switch it is connected to.

5. A PCIe topology switching device, characterized in that, A BMC device for use in servers, the server including a CPU with at least two PCIe lanes, the CPU being connected to a PCIe switch through one PCIe lane and to a MUX chip through the other PCIe lane, the MUX chip being connected to a PCIe adapter card and the PCIe switch, the MUX chip selectively selecting either the PCIe adapter card or the PCIe switch connected to it, the device comprising: The first module is used to respond to topology switching requests and obtain the status information of the currently in-situ PCIe devices; The second module is used to adjust the PCIe devices associated with non-gated targets based on the gating targets shown in the topology switching request and the obtained current in-situ PCIe device status information. The gating targets are PCIe adapter cards or PCIe switches. The third module is used to issue selection commands to enable the MUX chip to switch to the selection target, and to reconfigure PCIe resources after the MUX chip completes the switching selection.

6. The apparatus according to claim 5, characterized in that, The topology switching request indicates that the selected target is PCIeSwitch; The step of adjusting the PCIe devices associated with non-gated targets based on the gating target shown in the topology switching request and the obtained current in-place PCIe device status information includes: Based on the obtained status information of the currently present PCIe devices on the adapter card, the currently present PCIe devices on the adapter card are blocked. The reconfiguration of PCIe resources after the MUX chip completes the switching selection includes: To reconfigure more PCIe resources on a PCIe device located at a PCIe Switch than before the reconfiguration.

7. The apparatus according to claim 5, characterized in that, The topology switching request indicates that the selected target is the adapter card; The step of adjusting the PCIe devices associated with non-gated targets based on the gating target shown in the topology switching request and the obtained current in-place PCIe device status information includes: To reconfigure fewer PCIe resources on a PCIe device located at a PCIe Switch than before the reconfiguration; The reconfiguration of PCIe resources after the MUX chip completes the switching selection includes: Configure PCIe resources for PCIe devices located on the adapter card.

8. The apparatus according to claim 5, characterized in that, The server includes a CPU with at least 2N PCIe lanes. The CPU is connected to N PCIe switches through N of the PCIe lanes and to N MUX chips through another N of the PCIe lanes. Each MUX chip is connected to a PCIe adapter card and to one of the N PCIe switches. Each MUX chip selects the PCIe adapter card or PCIe switch it is connected to.

9. A server, characterized in that, include: The BMC device is used to respond to a topology switching request, obtain the status information of the currently in-situ PCIe devices, and adjust the PCIe devices associated with non-selection targets according to the selection target shown in the topology switching request and the obtained status information of the currently in-situ PCIe devices. The selection target is a PCIe adapter card or a PCIe switch. Then, a selection command is issued to make the MUX chip switch to the selection target. After the MUX chip completes the switching selection, the PCIe resources are reconfigured. The CPU has at least two PCIe lanes. The CPU is connected to a PCIe Switch through one PCIe lane and to a MUX chip through the other PCIe lane. A PCIe switch is connected to the CPU via a PCIe channel. The PCIe switch can have one or more PCIe devices connected to it, and the one or more PCIe devices share the PCIe bandwidth between the PCIe switch and the CPU. The MUX chip is connected to the PCIe adapter card and the PCIe switch. The MUX chip can select either the PCIe adapter card or the PCIe switch to which it is connected. PCIe adapter card, which can be connected to PCIe devices.

10. The server according to claim 9, characterized in that, include: The CPLD is used to connect the BMC device, the MUX chip, and the PCIe adapter card. The CPLD obtains the status information of the PCIe device in place on the PCIe adapter card from the signaling of the BMC device and feeds it back to the BMC device. The CPLD controls the MUX chip to switch and select according to the signaling of the BMC device.

11. An electronic device, characterized in that, include: A processor and a readable storage medium storing machine-executable instructions that can be executed by the processor to implement the method of any one of claims 1-4.

12. A readable storage medium, characterized in that, The readable storage medium stores machine-executable instructions that, when invoked and executed by a processor, cause the processor to implement the method described in any one of claims 1-4.

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