Semiconductor wafer, method of processing semiconductor wafer, and semiconductor chip

Abstract

The invention relates to a semiconductor wafer, a method of processing a semiconductor wafer, and a semiconductor chip. A semiconductor chip according to an embodiment includes: a substrate including a chip region and a residual scribe surrounding the chip region; and an infrared mark disposed in the chip area or in the residual scribe line. The infrared marker includes a plurality of optical patterns. The plurality of optical patterns includes integrated circuit structures having different stack structures over the substrate, and the plurality of optical patterns have different infrared reflection characteristics.

Description

Technical Field

[0001] This disclosure relates generally to semiconductor wafer manufacturing, including but not limited to semiconductor wafer dicing. Background Technology

[0002] Multiple semiconductor devices are formed on a semiconductor wafer using integrated circuit technology. The multiple semiconductor devices formed on the semiconductor wafer are then separated into individual semiconductor chips by wafer dicing.

[0003] Recently, with the increase in semiconductor integration, the thickness of semiconductor wafers has decreased, and wafer dicing methods have become more diversified. For example, wafer dicing can be classified into blade dicing, laser dicing, plasma dicing, etc. Summary of the Invention

[0004] A semiconductor chip according to an embodiment of the present disclosure includes: a substrate including a chip region and residual scribe lines surrounding the chip region; and an infrared marker disposed within the chip region or in the residual scribe lines. The infrared marker includes a plurality of optical patterns. The plurality of optical patterns include an integrated circuit structure with different stack-up structures above the substrate, and the plurality of optical patterns have different infrared reflectance characteristics.

[0005] A semiconductor wafer according to an embodiment of the present disclosure includes unit frames repeatedly arranged on a substrate. Each unit frame includes a plurality of chip regions, scribe lines disposed between the plurality of chip regions, and a frame identifier disposed in at least one of the plurality of chip regions or within a scribe line. The frame identifier provides a reference for identifying the positions of the plurality of scribe lines.

[0006] A method for processing a semiconductor wafer according to embodiments of the present disclosure may include the following steps: forming a semiconductor wafer comprising unit frames repeatedly arranged on a substrate. At least one unit frame includes a frame identifier located in a scribe line between one or more chip regions or between multiple chip regions. The frame identifier is used to determine the positions of multiple scribe lines in the scribe line. The multiple scribe lines are configured to separate the multiple chip regions. Process conditions for a dicing process are determined for at least one position of the multiple scribe lines. The semiconductor wafer is diced along the multiple scribe lines based on the process conditions. Attached Figure Description

[0007] Figures 1A to 1E A perspective view of a wafer during a wafer fabrication process according to an embodiment of the present disclosure is shown.

[0008] Figures 2A to 2E A cross-sectional view of a wafer during a wafer fabrication process is shown according to an embodiment of the present disclosure.

[0009] Figure 3This is a plan view showing a semiconductor wafer according to an embodiment of the present disclosure.

[0010] Figure 4 This is a diagram showing the unit frame and cleaved lines of a semiconductor wafer according to an example of this disclosure.

[0011] Figure 5 This is a diagram illustrating the unit frame and cleaved lines of a semiconductor wafer according to an embodiment of the present disclosure.

[0012] Figure 6 and Figure 7 This is a diagram illustrating the frame identifier according to an embodiment of the present disclosure.

[0013] Figure 8A and Figure 8B This is a diagram illustrating the frame identifier according to an embodiment of the present disclosure.

[0014] Figure 9 This is a diagram illustrating the unit frame and cleaved lines of a semiconductor wafer according to an embodiment of the present disclosure.

[0015] Figures 10A to 10C This is a cross-sectional view showing the frame identifier according to an embodiment of the present disclosure.

[0016] Figures 11A to 11C This is a cross-sectional view showing the frame identifier according to an embodiment of the present disclosure.

[0017] Figure 12 This is a flowchart illustrating a method for processing a semiconductor wafer according to an embodiment of the present disclosure.

[0018] Figure 13 This is a flowchart illustrating a method for determining the position of a tangent line according to an embodiment.

[0019] Figure 14 This is a flowchart illustrating a method for determining the scribing process conditions according to an embodiment.

[0020] Figure 15 This is a plan view showing the unit frame and cleaved lines on a semiconductor wafer according to an embodiment of the present disclosure.

[0021] Figures 16 to 19 This is a flowchart illustrating a method for processing a semiconductor wafer according to an embodiment of the present disclosure.

[0022] Figures 20A to 20D This is a diagram illustrating a semiconductor chip according to an embodiment of the present disclosure. Detailed Implementation

[0023] Embodiments of this disclosure are described in detail with reference to the accompanying drawings. Specific structural or functional descriptions of the embodiments are provided as examples to illustrate the concepts disclosed in this application. Examples or embodiments based on these concepts can be implemented in various forms, and the scope of this disclosure is not limited to the examples or embodiments described in this specification.

[0024] When one component is marked "connected" to another component, the components can be connected directly or through an intermediate component between them. When two components are marked "directly connected," one component is directly connected to the other, and there is no intermediate component between the two components.

[0025] Terms such as “bottom,” “upper,” “lower,” “below,” “above,” “on,” “left,” “side,” “outer,” “upper,” “lower,” “higher,” “column,” “row,” “height,” and other terms that suggest relative spatial relationships or orientations are used for ease of description or reference to the accompanying drawings only and are not intended to limit in any other way.

[0026] Cross-shading throughout the figures indicates corresponding or similar areas between figures, rather than indicating material associated with those areas.

[0027] Regarding the wafer dicing process sequence, compared to known methods that perform wafer sawing after back-side grinding, back-side grinding can be performed after half-sawing of the wafer. Half-sawing of the wafer may include laser stealth dicing that uses laser energy to remove internal regions of the semiconductor wafer.

[0028] Figures 1A to 1E A perspective view of a wafer during a wafer fabrication process according to an embodiment of the present disclosure is shown. Figures 2A to 2E A cross-sectional view of the wafer is shown during the wafer fabrication process. In the embodiment, regarding... Figures 1A to 1E and Figures 2A to 2E The wafer fabrication process described can be a wafer dicing process that includes a process involving stealth dicing (SDBG) before grinding.

[0029] Reference Figure 1A and Figure 2A A semiconductor wafer 10 is formed, which includes a substrate 12 having an upper surface 12S1 and a lower surface 12S2, and an integrated circuit structure 11 formed on the upper surface 12S1 of the substrate 12. A protective strip 13 covering the integrated circuit structure 11 is laminated on the upper surface 12S1 along the direction D1 using a roller 51.

[0030] Reference Figure 1B and Figure 2BA laser device 52 is used to perform stealth dicing on the semiconductor wafer 10. Stereoscopic dicing can be performed by irradiating a laser L52 from the lower surface 12S2 of the substrate 12 into the interior region of the substrate 12. Stereoscopic dicing can be performed by irradiating a laser L52 on the semiconductor wafer 10 along a given direction. Stereoscopic dicing divides the integrated circuit structure 11, thereby separating the semiconductor chip regions from each other.

[0031] Laser L52 forms a modified layer SD in an internal region of substrate 12 and generates cracks V in adjacent regions of the modified layer SD. The cracks V then advance into the integrated circuit structure 11 and divide the integrated circuit structure 11. The integrated circuit structure 11 is divided into individual semiconductor chip regions.

[0032] For example, thermal expansion may occur in the modified layer SD in two lateral directions due to irradiation by laser L52. This thermal expansion generates tensile stress in both lateral directions relative to the substrate 12 and the integrated circuit structure 11. Cracks V are generated due to the tensile stress that divides the integrated circuit structure 11.

[0033] Reference Figure 1C and Figure 2C The substrate 12 is polished from its lower surface 12S2 using a polishing apparatus 53. The polishing process is performed until the cracks V formed within the substrate 12 are exposed. Due to the polishing process, the thickness of the substrate 12 is reduced, resulting in a device substrate 12n. A device wafer 10n is fabricated, which includes a plurality of semiconductor chip regions 11n separated from each other on the surface of the device substrate 12n.

[0034] Reference Figure 1D and Figure 2D Device wafer 10n is mounted on scribe line 15. Scribe line 15 is secured by a retaining frame 54. In one embodiment, the process of mounting device wafer 10n on scribe line 15 is performed by attaching die attachment film 14 to the surface of device substrate 12n and bonding die attachment film 14 to scribe line 15. In another embodiment, the surface of device substrate 12n is bonded to scribe line 15 without using die attachment film 14. Protective strips 13 located on multiple semiconductor chip regions 11n are peeled off along direction D2.

[0035] Reference Figure 1E and Figure 2E A force is applied to the bottom of the scribe strip 15 in the upward direction D3. As a result of the applied force, the scribe strip 15 expands in the lateral direction D4, such that the device wafer 10n, including the semiconductor chip region 11n, is divided into unit semiconductor chips SC1 and SC2.

[0036] Figure 3 This is a plan view showing a semiconductor wafer 10 according to an embodiment of the present disclosure. (Refer to...) Figure 3 The semiconductor integration process (which may include photolithography) repeatedly forms the same pattern on the semiconductor wafer 10, in units of frame exposure (UF). After the semiconductor integration process is completed, the semiconductor wafer 10 includes a plurality of unit frames (UF) repeatedly arranged along a first direction and a second direction. The plurality of unit frames (UF) are arranged regularly, and the configuration of the semiconductor integrated circuits arranged within the plurality of unit frames (UF) may be substantially the same. Figure 3 As shown, when the pattern of the exposed frame US is not transferred as a whole to the unit frame UF' positioned along the edge of the semiconductor wafer 10, the unit frame UF' positioned along the edge has an incomplete integrated circuit configuration.

[0037] Figure 4 This is a diagram showing the unit frame UFO and cleaved lines of a semiconductor wafer according to an example of this disclosure. Figure 4 The unit frame UF0 shown corresponds to the reference. Figure 3 The unit frame UF of the semiconductor wafer 10 is described.

[0038] Reference Figure 4 The unit frame UF0 includes multiple chip regions CR regularly arranged along a first direction and a second direction, and scribe lines SL arranged outside the multiple chip regions CR. The chip regions CR include integrated circuits that constitute the electronic devices in the chip cell. The scribe line SL is the area surrounding the chip regions CR. Various types of test patterns used to evaluate the process characteristics or device characteristics of the integrated circuits can be set in the scribe line SL. Protective structures can be set at the boundary between the scribe line SL and the chip regions CR. Patterns applied to the photolithography process (e.g., photoalignment marks and overlay marks) are set in the scribe line SL.

[0039] Multiple chip regions CR include integrated circuits that are generally substantially similar or identical among the chip regions CR. At least one of the multiple chip regions CR includes an alignment mark CM. For example, the alignment mark CM is an identification pattern located at a specific location within the chip region CR. Figure 4 As shown, each of the multiple chip regions CR includes the same alignment mark CM located at the same position. The chip region CR to which the alignment mark CM belongs can be identified based on the alignment mark CM. The size and shape of the chip region CR can be determined based on the alignment mark CM.

[0040] After the process of forming the integrated circuit for multiple chip regions CR is completed, the reference... Figures 1A to 1E and Figures 2A to 2B The described multiple chip regions undergo a separation process (CR). In this example, a reference process is performed. Figure 1B and Figure 2B The description refers to the invisible cuts.

[0041] Based on the example, the unit frame (UF) is used as the unit. Figure 3 The semiconductor wafer 10 undergoes photolithography, but as Figure 4 As shown, invisible scribing is performed along the first invisible scribing line X0 and the second invisible scribing line Y0 between the chip regions CR, independent of the unit frame UF.

[0042] Reference Figure 4 A first invisible scribing line X0 is arranged at regular intervals along a first direction between multiple chip regions CR, and a second invisible scribing line Y0 is arranged at regular intervals along a second direction between multiple chip regions CR. When the size and shape of one of the chip regions CR are determined by identifying alignment marks CM, the positions of the first invisible scribing line X0 and the second invisible scribing line Y0 are located based on the determined size and shape of the chip region CR. Invisible scribing can be performed along the first invisible scribing line X0 under a first scribing condition, and can be performed along the second invisible scribing line Y0 under a second scribing condition.

[0043] As described, various types of test patterns, optical alignment marks, and overlay marks can be arranged in the scribe line SL of a unit frame UF0. Compared to integrated circuits arranged at the same location within each of multiple chip regions CR, the test patterns, optical alignment marks, and overlay marks can be arranged in specific areas of the scribe line SL within the unit frame UF0. That is, the arrangement or orientation of the test patterns, optical alignment marks, and overlay marks adjacent to or near one chip within the unit frame UF0 may differ from that of the test patterns, optical alignment marks, and overlay marks adjacent to or near another chip. Therefore, depending on the type of test pattern and dummy pattern, the material composition of the scribe line SL where the invisible scribe lines X0 and Y0 intersect may differ for various locations within the unit frame UF0.

[0044] Depending on the properties of the target material, stealth dicing can exhibit different dicing characteristics. When stealth dicing is performed under similar process conditions, undicated or over-dicated sections may occur in one or more of the dicing lines X0 and Y0. Undicated sections lead to dicing defects, while over-diced sections cause excessive thermal expansion in the semiconductor wafer undergoing stealth dicing, which can exacerbate wafer warpage. When excessive wafer warpage occurs, process defects often arise during subsequent backside polishing processes.

[0045] Figure 5 This is a diagram illustrating the unit frame UF1 and cleaved lines of a semiconductor wafer according to an embodiment of the present disclosure. Figure 5 The unit frame UF1 shown corresponds to the reference. Figure 3 The unit frame UF of the semiconductor wafer 10 is described. Figure 6 and Figure 7This is a diagram illustrating the frame identifiers FA1 and FB1 according to an embodiment of the present disclosure. Figure 6 Showing the arrangement in Figure 5 An enlarged view of the frame identifier FA1 in the first region SA of the unit frame UF1. Figure 7 Showing the arrangement in Figure 5 An enlarged view of the frame identifier FB1 in the second region SB of the unit frame UF1.

[0046] Reference Figure 5 The unit frame UF1 includes multiple chip regions CR and scribe lines SL positioned outside the multiple chip regions CR. The scribe lines SL surround the multiple chip regions CR. The unit frame UF1 includes frame identifiers FA1 and FB1 located within the scribe lines SL.

[0047] Frame identifiers FA1 and FB1 are arranged within unit frame UF1 in different positions and orientations. The shape of the first frame identifier FA1 differs from the shape of the second frame identifier FB1. For example, as... Figure 5 As shown, the first frame identifier FA1 has an L shape, and the second frame identifier FB1 has a straight shape.

[0048] In this implementation, the frame identifier can be set as a single identifier within a unit frame UF1. For example, the frame identifier could be... Figure 5 The first frame identifier is FA1, and the second frame identifier is FB1. In an implementation, three or more frame identifiers may be located at different positions within the unit frame UF1. In this example, the three or more identifiers may have two or more different shapes.

[0049] Reference Figure 5 Multiple scribe lines X1, X2, X3, X4, X5, Y1, Y2, and Y3 are established in the scribe line SL for scribe operations during the separation of multiple chip regions CR. The multiple scribe lines X1, X2, X3, X4, X5, Y1, Y2, and Y3 include a first scribe line X1, a second scribe line X2, a third scribe line X3, a fourth scribe line X4, and a fifth scribe line X5 arranged at regular intervals along a first direction, and a sixth scribe line Y1, a seventh scribe line Y2, and an eighth scribe line Y3 arranged at regular intervals along a second direction. In this embodiment, frame identifiers FA1 and FB1 are spaced apart from the multiple scribe lines X1, X2, X3, X4, X5, Y1, Y2, and Y3 in the scribe line SL.

[0050] In this implementation, frame identifiers FA1 and FB1 provide a reference for identifying the positions of multiple cleaved lines X1, X2, X3, X4, X5, Y1, Y2, and Y3. The relative positions of the multiple cleaved lines X1, X2, X3, X4, X5, Y1, Y2, and Y3 within the unit frame UF1 are determined based on frame identifiers FA1 and FB1. Therefore, the positions of the multiple cleaved lines X1, X2, X3, X4, X5, Y1, Y2, and Y3 are identified based on frame identifiers FA1 and FB1.

[0051] When multiple frame identifiers FA1 and FB1 are arranged within a unit frame UF1, they can function according to their priority. For example, when the first frame identifier FA1 has a higher priority, it is used as the identification benchmark before the second frame identifier FB1 is used. If the first frame identifier FA1 fails to provide a suitable identification benchmark, the second frame identifier FB1 replaces it as the identification benchmark.

[0052] In the implementation method, it is possible to utilize from Figure 3 Infrared light illuminating the lower surface of semiconductor wafer 10 will identify frame identifiers FA1 and FB1 as infrared patterns. (See reference...) Figures 10A to 10C The infrared pattern is described in detail. In another embodiment, it can be obtained from... Figure 3 Visible light illuminating the semiconductor wafer 10 from above will identify the frame identifiers FA1 and FB1 as visible light patterns. (Refer to...) Figures 11A to 11C Describe the visible light pattern in detail.

[0053] Reference Figure 5 The first frame identifier FA1, located in the first region SA of the unit frame UF1, is positioned in the scribing channel SL, adjacent to or close to the upper left corner where it intersects the long and short sides of the chip region CR. (Refer to...) Figure 6 The first frame identifier FA1 includes a plurality of optical patterns OP arranged along a first direction and a second direction, respectively, along the chip region CR. The plurality of optical patterns OP are arranged close to or adjacent to each other and have the same shape. The plurality of optical patterns OP are depicted as square patterns with the same dimensions (e.g., width and length). The plurality of optical patterns OP may include circular patterns or polygonal patterns with the same dimensions and shape. The plurality of optical patterns OP can be distinguished from each other by differences in brightness, for example, regarding... Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B and Figure 11C As described. For example, such as Figure 6As shown, each optical pattern OP is associated with a brightness level including one of the first level LV1, the second level LV2, and the third level LV3. Brightness levels are distinguishable or identifiable between consecutive optical patterns OP with frame identifiers. The number of brightness levels is not limited to three. Multiple optical patterns OP are associated with different numbers of brightness levels within a identifiable range of brightness differences between consecutive optical patterns OP.

[0054] Reference Figure 5 The second frame identifier FB1 can be set in the scribe line SL adjacent to the long or short side of the chip region CR. In an implementation, such as... Figure 7 As shown, the second frame identifier FB1 includes a plurality of optical patterns OP arranged along a second direction of the chip region CR. For example, each of the plurality of optical patterns OP is associated with a brightness level including one of a first level LV1, a second level LV2, and a third level LV3. The brightness levels are distinguishable or identifiable between consecutive optical patterns OP, for example, regarding... Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B and Figure 11C As described. In another example not shown, the second frame identifier FB1 may include multiple optical patterns OP arranged along a first direction of the chip region CR and identified by brightness differences.

[0055] Reference Figure 6 and Figure 7 Multiple optical patterns OP form a group of frame identifiers FA1 and FB1. Frame identifiers FA1 and FB1 are patterns distinct from the integrated structure set in the scribe line SL adjacent to the corresponding chip region CR. As described, frame identifiers FA1 and FB1 may include a square or grid pattern comprising multiple optical patterns OP distinguished from each other by brightness differences, for example, regarding... Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B and Figure 11C As described.

[0056] According to embodiments of this disclosure, when... Figure 3 When performing a dicing process on the semiconductor wafer 10, the following can be used Figure 5 The frame identifiers FA1 and FB1 are used to identify the relative positions of multiple cleaved lines X1, X2, X3, X4, X5, Y1, Y2, and Y3 within the unit frame UF1 of semiconductor wafer 10. This method differs from the reference method. Figure 4 The example described is because, during the dicing process, the relative positions of multiple dicing lines within the unit frame UF0 are not recognized by each other.

[0057] According to embodiments of this disclosure, process conditions for a dicing process are determined for at least one of a plurality of dicing lines X1, X2, X3, X4, X5, Y1, Y2, and Y3. The dicing process of the semiconductor wafer 10 is performed using the process conditions determined for one or more of the plurality of dicing lines X1, X2, X3, X4, X5, Y1, Y2, and Y3. For example, the dicing process may include reference to… Figure 13 and Figure 14 The description of invisible cutting, blade sawing, or reference Figures 17 to 19 The laser grooving described. The dicing process for semiconductor wafer 10 differs from the reference. Figure 4 The example described is a dicing process in which a dicing process for a first invisible dicing line X0 is performed under the same process conditions, and a dicing process for a second invisible dicing line Y0 is performed under the same process conditions.

[0058] Figure 8A and Figure 8B This is a diagram illustrating the frame identifiers FC and FD according to an embodiment of the present disclosure. Figure 8A and Figure 8B The frame identifiers FC and FD shown respectively have the same characteristics as the reference. Figures 5 to 7 The frame identifiers FA1 and FB1 are described as having different shapes.

[0059] Figure 8A The frame identifier FC has nine optical patterns OP arranged in three rows and three columns. Figure 8B The frame identifier FD has eight optical patterns OP arranged in two rows and four columns. Each optical pattern OP contained within the frame identifiers FC and FD is associated with a brightness level including one of the first level LV1, second level LV2, and third level LV3. Brightness levels can be distinguished or identified by differences in brightness. The frame identifiers FC and FD contain multiple optical patterns OP having a square or grid pattern. Therefore, each of the frame identifiers FC and FD includes a square or grid pattern comprising multiple optical patterns OP distinguished from each other by differences in brightness, for example, regarding... Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B and Figure 11C As described. The square or grid pattern can be symmetrical or asymmetrical. Figure 8A The position of the frame identifier FC within the unit frame can be as follows: Figure 5 and Figure 6 The position of the first frame identifier FA1 shown is, for example, adjacent to the upper left corner of the chip region CR where the long and short sides of the chip region CR intersect in the scribing SL. Alternatively, Figure 8AThe position of the frame identifier FC within the unit frame can be as follows: Figure 5 and Figure 7 The position of the second frame identifier FB1 shown is, for example, adjacent to one of the long or short sides of the chip region CR in the scribing channel SL. Figure 8B The position of the frame identifier FD can be related to Figure 5 and Figure 6 The position of the first frame identifier FA1 or Figure 5 and Figure 7 The position of the second frame identifier FB1 is basically the same.

[0060] Figure 9 This is a diagram showing the unit frame UF2 and cleaved lines of a semiconductor wafer according to an embodiment of the present disclosure. Figure 9 The unit frame UF2 shown corresponds to about Figure 3 The unit frame UF of the semiconductor wafer 10 is described.

[0061] Reference Figure 9 The unit frame UF2 includes multiple chip regions CR and channels SL located outside or around the multiple chip regions CR. The unit frame UF2 includes frame identifiers FA2 and FB2 located within the multiple chip regions CR.

[0062] Frame identifiers FA2 and FB2 are positioned and oriented differently within unit frame UF2. The third frame identifier FA2 is positioned near the upper left corner of chip region CR, where the long and short sides intersect. The fourth frame identifier FB2 is positioned along the edge of chip region CR, for example, along... Figure 9 The long side shown or the short side along the chip region CR. In an embodiment, the chip region CR includes a cell placement area and a peripheral circuit placement area. Frame identifiers FA2 and FB2 may be placed in the peripheral circuit placement area. Figure 9 As shown, frame identifiers FA2 and FB2 are separated from multiple tangent lines X1, X2, X3, X4, X5, Y1, Y2 and Y3.

[0063] The third frame identifier FA2 and the fourth frame identifier FB2 include multiple optical patterns associated with brightness differences, for example, regarding... Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B and Figure 11C The configuration of multiple optical patterns described herein can be compared with reference to... Figure 6 , Figure 7 , Figure 8A and Figure 8BThe configurations of the multiple optical pattern OPs described are basically the same.

[0064] exist Figure 9 In this embodiment, the shape of the third frame identifier FA2 differs from the shape of the fourth frame identifier FB2. In this embodiment, the frame identifier can be a single identifier within a unit frame UF2, or it can include three or more identifiers having two or more different shapes.

[0065] Figures 10A to 10C This is a cross-sectional view showing the frame identifier FI according to an embodiment of the present disclosure. Figures 10A to 10C This is a cross-sectional view showing the structure of a frame identifier FI disposed on a semiconductor wafer 10 when a NAND memory device is formed on the semiconductor wafer 10. The frame identifier FI includes a first optical pattern OP1, a second optical pattern OP2, and a third optical pattern OP3 associated with different brightness levels. The optical patterns OP1, OP2, and OP3 are disposed sequentially and may follow, for example, reference to... Figure 6 , Figure 7 , Figure 8A and Figure 8B The planar arrangement of the multiple optical patterns (OPs) described. (Refer to...) Figure 10A , Figure 10B and Figure 10C Describe the different cross-sectional structures of the first optical pattern OP1, the second optical pattern OP2, and the third optical pattern OP3.

[0066] Reference Figures 10A to 10C The frame identifier FI is identified as an infrared pattern by an inspection device such as an infrared inspection device 1010. For example, the infrared inspection device 1010 includes an infrared irradiation device, an infrared image capture device, and an image recognition device. The infrared irradiation device irradiates infrared light onto the lower surface 12S2 of the substrate 12, and the infrared image capture device acquires the infrared light reflected by the integrated circuit structure within the semiconductor wafer 10 in the form of an image. The image recognition device identifies the frame identifier FI by comparing the acquired infrared image with a pre-stored standard image. The frame identifier FI can be referenced... Figures 12 to 14 Used during the described invisible cut.

[0067] The frame identifier FI includes a substrate 12 and an integrated circuit structure 11 disposed on the substrate 12. The integrated circuit structure 11 includes a first structure 111a, 111b, and 111c, a second structure 112, a third structure 113, and a fourth structure 114 sequentially disposed on the substrate 12. The second structure 112 may be a memory cell structure disposed in a cell region CR. The first structures 111a, 111b, and 111c are disposed below the second structure 112 and may be peripheral circuit structures of the cell region CR, configured to electrically control or drive the memory cell structures. The third structure 113 may be an interconnect structure for the cell region CR, electrically interconnecting the memory cell structures or connecting the memory cell structures to peripheral circuit structures. For example, the third structure 113 includes a first interconnect line M1 and a second interconnect line M2. A contact MC1 electrically connects the first interconnect line M1 to the metal layer of the first structures 111a, 111b, and 111c. A via MC2 electrically connects the first interconnect line M1 to the second interconnect line M2. The fourth structure 114 can be a passivation structure for the unit region CR, which protects the first structures 111a, 111b, 111c, the second structure 112 and the third structure 113.

[0068] like Figures 10A to 10C As shown, the optical patterns OP1, OP2, and OP3 of the frame identifier FI include different stacked structures. In an embodiment, optical patterns OP1, OP2, and OP3 respectively include first structures 111a, 111b, and 111c, which contain different stacked structures. (Refer to...) Figure 10A The first structure 111a of the first optical pattern OP1 includes a gate electrode layer G disposed on the substrate 12. The first structure 111a includes a first lower metal layer P1, a second lower metal layer P2, and a third lower metal layer P3 disposed at different distances from the gate electrode layer G. The first structure 111a includes a first lower contact PC1 connecting the gate electrode layer G to the first lower metal layer P1, a second lower contact PC2 connecting the first lower metal layer P1 to the second lower metal layer P2, and a third lower contact PC3 connecting the second lower metal layer P2 to the third lower metal layer P3. The first structure 111a includes a contact plug PG disposed on the third lower metal layer P3.

[0069] Reference Figure 10B The first structure 111b of the second optical pattern OP2 does not include the gate electrode layer G, the lower metal layers P1, P2 and P3, and the lower contacts PC1, PC2 and PC3 from the first structure 111a of the first optical pattern OP1. (Refer to...) Figure 10C The first structure 111c of the third optical pattern OP3 includes a gate electrode layer G, but does not include the lower metal layers P1, P2 and P3 from the first structure 111a of the first optical pattern OP1, or the lower contacts PC1, PC2 and PC3.

[0070] Reference Figures 10A to 10C Due to the structural differences between the first structures 111a, 111b, and 111c, infrared light incident on the lower surface 12S2 of the substrate 12 exhibits different light reflection or light transmission characteristics. Different brightness levels exist in the image of the reflected light received by the infrared inspection device 1010. For example, the first optical pattern OP1, including lower metal layers P1, P2, and P3 made of a metallic material with relatively high infrared reflectivity, generates a brighter image than the second optical patterns OP2 and the third optical pattern OP3, which have relatively low infrared reflectivity. The third optical pattern OP3, including a gate electrode layer G made of a material with high infrared absorption, generates a darker image than the second optical pattern OP2, which does not include the gate electrode layer G.

[0071] Reference Figures 10A to 10C Different stacked structures for the first structures 111a, 111b, and 111c can be used to generate brightness differences between optical patterns OP1, OP2, and OP3, but this disclosure is not limited to this example. In embodiments, stacked structures such as the second structure 112, in addition to the first structures 111a, 111b, and 111c, can also be varied to generate brightness differences associated with optical patterns OP1, OP2, and OP3.

[0072] Figures 11A to 11C This is a cross-sectional view showing the frame identifier FV according to an embodiment of the present disclosure. Figures 11A to 11C This is a diagram showing a cross-sectional structure of a frame identifier FV disposed on a semiconductor wafer 10 when a NAND memory device is formed on the semiconductor wafer 10. The frame identifier FV includes a first optical pattern Opa, a second optical pattern OPb, and a third optical pattern OPc associated with different brightness levels. The optical patterns Opa, OPb, and OPc are arranged sequentially and follow, for example, reference to... Figure 6 , Figure 7 , Figure 8A and Figure 8B Describes the planar arrangement of multiple optical patterns (OPs). (Refer to...) Figure 11A , Figure 11B and Figure 11C Describe the different cross-sectional structures of the first optical pattern Opa, the second optical pattern OPb, and the third optical pattern OPc.

[0073] Reference Figures 11A to 11CThe frame identifier FV can be identified as a visible light pattern by the visible light inspection device 1020. In this embodiment, the visible light inspection device 1020 includes a visible light irradiation device, a visible light image capture device, and an image recognition device. The irradiation device irradiates the integrated circuit structure 11 with visible light from above the semiconductor wafer 10, and the visible light image capture device acquires the visible light reflected by the integrated circuit structure within the semiconductor wafer 10 in the form of an image. The image recognition device identifies the frame identifier FV by comparing the acquired visible light image with a pre-stored standard image. The frame identifier FV can be referenced... Figures 16 to 18 Used during the initial cutting process as described.

[0074] The frame identifier FV includes a substrate 12 and an integrated circuit structure 11 disposed on the substrate 12. The integrated circuit structure 11 includes a first structure 111, a second structure 112, a third structure 113a, 113b, and 113c, and a fourth structure 114a, 114b, and 114c, which are sequentially stacked on the substrate 12. The optical patterns OPa, OPb, and OPc of the frame identifier FV each have different stacked structures including the third structures 113a, 113b, and 113c and the fourth structures 114a, 114b, and 114c.

[0075] Reference Figure 11A In the example of the first optical pattern Opa, the cross-sections of the second interlayer insulating layer PW2 and the first interlayer insulating layer PN1 of the fourth structure 114a and the interlayer insulating layer PN2 of the third structure 113a are patterned such that the second interconnect M2, made of a metal or conductive material, is exposed. (Refer to...) Figure 11B Comparing the second optical pattern OPb with the first optical pattern OPa, the upper part of the second interconnect M2 is covered by the interlayer insulating layer PN2 of the third structure 113b and the first interlayer insulating layer PN1 and the second interlayer insulating layer PW2 of the fourth structure 114b. (Refer to...) Figure 11C Comparing the third optical pattern OPc with the first optical pattern OPa, the third structure 113c does not include the second interconnect M2 and the via MC2.

[0076] Reference Figures 11A to 11CVisible light emitted by the visible light inspection device 1020 and incident on the integrated circuit structure 11 from above the semiconductor wafer 10 exhibits different light reflection and transmission characteristics due to structural differences between the third structures 113a, 113b, and 113c and the fourth structures 114a, 114b, and 114c. Therefore, brightness differences appear in the images obtained from the reflected light acquired by the visible light inspection device 1020. For example, a first optical pattern Opa, including a second interconnect M2 made of a metallic material with relatively high reflectivity to visible light, generates a brighter image than a second optical pattern OPb and a third optical pattern OPc, which have relatively low reflectivity to visible light. A second optical pattern OPb, including the second interconnect M2 and via MC2 made of a metallic material, generates a brighter image than a third optical pattern OPc, which does not include the second interconnect M2 and via MC2.

[0077] Figure 12 This is a flowchart illustrating a semiconductor wafer fabrication method according to an embodiment of the present disclosure. Figure 13 This is a flowchart illustrating a method for determining the position of a tangent line according to an embodiment. Figure 14 This is a flowchart illustrating a method for determining the process conditions for scribing lines according to an embodiment. The processes in the flowchart can be performed in different sequences and may include ratios. Figures 12 to 14 The process described and shown in the document is less or more. Figure 15 This is a plan view illustrating the unit frame and cleaved lines on a semiconductor wafer according to an embodiment of the present disclosure. In the embodiment, Figures 12 to 15 The semiconductor wafer fabrication method shown can be implemented in the following ways: (refer to reference) Figures 1A to 1E and Figures 2A to 2E The SDBG process described is used during the wafer dicing process.

[0078] Reference Figure 12 S10 forms a semiconductor wafer having unit frames including frame identifiers. In this embodiment, the frame identifiers are used during stealth dicing. The frame identifiers can be identified as infrared patterns.

[0079] In the implementation method, forming Figure 3 Semiconductor wafer 10, which includes Figure 5 Unit frame UF1 or Figure 9 The unit frame UF2. For example, unit frames UF1 and UF2 include Figure 6 Frame identifier FA1, Figure 7 Frame identifier FB1, Figure 8A Frame identifier FC, Figure 8B Frame identifier FD or Figure 9 The frame identifiers are FA2 and FB2.

[0080] In the implementation, the optical patterns OP of the frame identifiers FA1, FB1, FA2, FB2, FC, and FD can be compared with reference to... Figures 10A to 10C The optical patterns described are essentially similar to one of OP1, OP2 and OP3.

[0081] Reference Figure 12 The frame identifier is used to determine the location of multiple scribing lines in S20. These multiple scribing lines can be scribing lines used during invisible scribing.

[0082] In this implementation, within the semiconductor wafer 10, frame identifiers FA1, FB1, FA2, FB2, FC, and FD are used to identify unit frames UF1 and UF2. Based on these frame identifiers, the relative positions of multiple scribe lines X1, X2, X3, X4, X5, Y1, Y2, and Y3 used for invisible dicing are identified and determined. The multiple scribe lines X1, X2, X3, X4, X5, Y1, Y2, and Y3 are spaced apart from the frame identifiers FA1, FB1, FA2, FB2, FC, and FD. Regarding... Figure 13 The flowchart details the process of determining the positions of multiple scribe lines. Infrared light is irradiated onto the lower surface of the substrate from below in step S201, and an image of the infrared light reflected from the substrate is acquired to identify the frame identifier of the unit frame. In the embodiment, as shown in reference... Figures 10A to 10C As described, the infrared inspection device 1010 illuminates the lower surface 12S2 of the substrate 12 with infrared light, and acquires an infrared image after the infrared light is reflected by the integrated circuit structure of the semiconductor wafer 10. The infrared image is used to identify the frame identifier FI.

[0083] Based on the identified frame identifier, the positions of multiple cleaving lines arranged along a first direction and multiple cleaving lines arranged along a second direction substantially perpendicular to the first direction within the unit frame are determined in S202. In an implementation, as referred to... Figure 5 As described, during stealth dicing, the positions of dicing lines X1, X2, X3, X4 and X5 arranged along a first direction and dicing lines Y1, Y2 and Y3 arranged along a second direction are determined individually based on frame identifiers FA1 and FB1 on the semiconductor wafer 10 and the size of the chip region CR.

[0084] Reference Figure 12 The process conditions for the S30 scribing process are determined for at least one location of multiple scribing lines. In the implementation method, refer to... Figure 14The flowchart shows that the process conditions for the scribing process include: determining the process conditions for S301 invisible scribing for multiple scribing lines arranged along the first direction; and determining the process conditions for S302 invisible scribing for multiple second scribing lines arranged along the second direction.

[0085] In implementation examples, the process conditions for stealth dicing may include laser power, laser frequency, laser scanning speed, the number of multiple modified layers formed in the substrate, the spacing between the modified layers formed in the substrate, and the position of the modified layers within the substrate.

[0086] Reference Figure 12 Based on the determined process conditions, the S40 semiconductor wafer is diced along multiple dicing lines. In this embodiment, refer to... Figure 15 When the process conditions for invisible dicing along scribe lines X1, X2, X3, X4, X5, Y1, Y2, and Y3 are determined within a pre-specified unit frame UFi, invisible dicing is performed on semiconductor wafer 10 along scribe lines X1, X2, X3, X4, X5, Y1, Y2, and Y3. For ease of illustration, Figure 15 Only the first tangent line X1 and the fifth tangent line X5, which are spaced apart along the first direction, and the sixth tangent line Y1 and the eighth tangent line Y3, which are spaced apart along the second direction, are shown.

[0087] Reference Figure 15 For multiple unit frames located in the same row H as the pre-specified unit frame UFi, invisible dicing of the semiconductor wafer 10 is performed in batches along the first dicing line X1, and invisible dicing of the semiconductor wafer 10 is performed sequentially along dicing lines X2, X3, X4 and X5. Invisible dicing of other rows is performed in the same manner.

[0088] For multiple unit frames located in the same column R as the pre-specified unit frame UFi, invisible dicing of semiconductor wafer 10 is performed in batches along the sixth dicing line Y1, and invisible dicing of semiconductor wafer 10 is performed sequentially along dicing lines Y2 and Y3. Invisible dicing of other rows is performed in the same manner.

[0089] although Figure 12Not shown in the flowchart, in some embodiments, the method for processing a semiconductor wafer may further include: comparing the positions of a plurality of scribe lines determined according to frame identifiers with the positions of a plurality of chip dicing lines formed as a result of performing a scribe process. According to embodiments of this disclosure, the frame identifiers are located in the scribe line or chip region and are spaced apart from the plurality of scribe lines. The frame identifiers may be retained after the scribe process without being destroyed by the scribe process. Therefore, the positions of the plurality of scribe lines set for the scribe process can be re-identified using the remaining frame identifiers. Additionally, the re-identified positions of the plurality of scribe lines can be compared with the positions of the plurality of chip dicing lines formed after the scribe process. According to embodiments, the method for processing a semiconductor wafer may further include: correcting the positions of scribe lines to be subjected to subsequent scribe processes based on the comparison results.

[0090] In this implementation, the position of the dicing line is corrected simultaneously with the dicing process for the semiconductor wafer 10. For example, refer to... Figure 15 The correction of the scribe line position can be performed in the following order. For multiple unit frames located in the same row H as the unit frame UFi, a stealth scribe is performed on the semiconductor wafer 10 along the first scribe line X1 identified by the frame identifier. As described, because the frame identifier is retained after the stealth scribe, the position of the first scribe line X1 determined by the frame identifier can be compared with the position of the chip dicing line formed as a result of the stealth scribe. Based on the comparison result, the position of the second scribe line X2, where the stealth scribe was performed, can then be corrected. Correcting the scribe line position can improve the process reliability of the stealth scribe.

[0091] As described, according to embodiments of this disclosure, invisible scribing can be performed under different process conditions on one or more of a plurality of distinct scribing lines within a unit frame. Figure 4 Compared to the example where stealth dicing was performed under the same process conditions for each of multiple dicing lines, in the embodiments of this disclosure, stealth dicing can be performed by selectively strengthening the process conditions for stealth dicing where undivided dicing occurs. When the process conditions for stealth dicing are uniformly strengthened to overcome the occurrence of undivided dicing, over-dicing in the semiconductor wafer can be prevented. As a result, undesirable bending in the semiconductor wafer due to thermal expansion accompanying over-dicing can be effectively prevented.

[0092] Figures 16 to 19 This is a flowchart illustrating a method for fabricating a semiconductor wafer according to embodiments of the present disclosure. The processes in the flowchart may be performed in different sequences and may include more than one step. Figures 16 to 19The process described and illustrated herein involves fewer or more processes. In this embodiment, the processing of the semiconductor wafer is performed in two stages: preliminary dicing and main dicing. Preliminary dicing is performed on dicing lines selected from a plurality of dicing lines. Main dicing can be performed on each of the plurality of invisible dicing lines using invisible dicing under the same process conditions.

[0093] Reference Figure 16 S11 forms a semiconductor wafer having unit frames including frame identifiers. In an embodiment, the frame identifiers may be used during blade sawing or laser grooving. The frame identifiers can be identified as visible light patterns, as shown in reference... Figure 11A , Figure 11B and Figure 11C As described.

[0094] In the implementation method, forming includes Figure 5 Unit frame UF1 or Figure 9 The semiconductor wafer 10 of unit frame UF2. Unit frame UF1 and unit frame UF2 include Figure 6 Frame identifier FA1, Figure 7 Frame identifier FB1, Figure 8A Frame identifier FC, Figure 8B Frame identifier FD or Figure 9 At least one of the frame identifiers FA2 and FB2.

[0095] The frame identifiers FA1, FB1, FA2, FB2, FC, and FD include multiple optical patterns OP that can be identified by brightness differences in response to visible light. Each of the multiple optical patterns OP can correspond to a reference. Figures 11A to 11C One of the optical patterns described, OPa, OPb, and OPc.

[0096] Reference Figure 16 The positions of the multiple scribing lines in S21 are determined using frame identifiers. These scribing lines can be used for blade sawing or laser grooving.

[0097] Determine the position reference of multiple scribing lines in S21 Figure 17 The flowchart is used to describe this. Figure 17 In step S211, visible light is irradiated onto the substrate from above, and an image of the visible light reflected from the substrate is obtained to identify the frame identifier of the unit frame. In an embodiment, when the visible light inspection device 1020 irradiates visible light from above the substrate 12, as shown in reference... Figures 11A to 11C As described, visible light reflected from the integrated circuit structure 11 of the semiconductor wafer 10 forms an image detected by a visible light inspection device 1020. The image, which responds to the visible light reflection, is used to identify the frame identifier FV.

[0098] Based on the identified frame identifier, the positions of a plurality of first tangent lines arranged along a first direction and a plurality of second tangent lines arranged along a second direction substantially perpendicular to the first direction within the unit frame of S212 are identified and determined. In the embodiment, reference is made to... Figure 5 During blade sawing or laser grooving, the positions of cleaving lines X1, X2, X3, X4 and X5 arranged along the first direction and cleaving lines Y1, Y2 and Y3 arranged along the second direction are determined individually based on the frame identifiers FA1 and FB1 on the semiconductor wafer 10 and the size of the chip region CR.

[0099] Reference Figure 16 The process conditions for preliminary scribing (S31) are determined for at least one location along multiple scribing lines. For example, preliminary scribing may include blade sawing or laser grooving. The process conditions for determining preliminary scribing (S31) are determined by referring to... Figure 18 The process is described using a flowchart. From multiple scribing lines arranged along the first and second directions, the scribing line for initial scribing in S311 is selected. The process conditions for initial scribing in S312 are determined for the selected scribing line. (Return to reference) Figure 5 Among the cleaving lines X1, X2, X3, X4 and X5 arranged along the first direction and the cleaving lines Y1, Y2 and Y3 arranged along the second direction, the cleaving line where the wafer is likely to be undivided is selected as the cleaving line for performing the initial cleaving.

[0100] Reference Figure 16 Based on the determined process conditions, preliminary dicing S41 is performed on the semiconductor wafer along multiple dicing lines. In this embodiment, the preliminary dicing can be performed according to a reference... Figure 15 The invisible cut described is performed in the same manner to intersect multiple unit frames along a first or second direction relative to the selected cut line.

[0101] Perform a main dicing S51 on the semiconductor wafer. For example, the main dicing can be a stealth dicing. Main dicing S51 refers to... Figure 19 The flowchart describes the process. The location of multiple hidden scribe lines in the S511 is determined using hidden scribe markers individually positioned on the semiconductor wafer. The location of the multiple hidden scribe lines in the S511 can be determined by referring to... Figure 4 The described example uses alignment marks CM to determine the positions of the first invisible scribe line X0 and the second invisible scribe line Y0 in a substantially similar manner. The invisible scribe identifier can be substantially similar to the alignment marks CM set within the chip region CR. In this implementation, determining the positions of the multiple invisible scribe lines in S511 is performed without performing a process for identifying unit frames within the semiconductor wafer 10.

[0102] Invisible scribing S512 is performed along multiple invisible scribing lines. Invisible scribing can be performed on each of the multiple invisible scribing lines under the same process conditions. In an embodiment, invisible scribing performed on a first invisible scribing line X0 arranged along a first direction can utilize the same process conditions. Similarly, invisible scribing performed on a second invisible scribing line Y0 arranged along a second direction can utilize the same process conditions.

[0103] As described, according to embodiments of this disclosure, preliminary dicing is performed on dicing lines where undivided areas may occur before performing primary dicing. During preliminary dicing, multiple dicing lines within a unit frame are identified using frame identifiers, thereby selecting the dicing lines for which preliminary dicing will be performed. After preliminary dicing, primary or secondary dicing is performed along individually determined secondary dicing lines. When dicing a semiconductor wafer according to this disclosure, defects due to undivided areas or undesirable bending due to over-divided areas in at least some regions of the wafer can be effectively prevented.

[0104] Figures 20A to 20D This is a diagram illustrating a semiconductor chip according to an embodiment of the present disclosure. Figure 20A , Figure 20B , Figure 20C and Figure 20D The first semiconductor chip SC1, the second semiconductor chip SC2, the third semiconductor chip SC3, and the fourth semiconductor chip SC4 are respectively referenced Figures 12 to 14 The described semiconductor wafer fabrication method or reference Figures 16 to 19 The described method for fabricating semiconductor wafers.

[0105] From settings Figure 5 The chip region CR and scribing SL in the unit frame UF1 are obtained Figure 20A The first semiconductor chip SC1 and Figure 20B The second semiconductor chip SC2. From the setting... Figure 9 The chip region CR and scribing SL in the unit frame UF2 are obtained Figure 20C The third semiconductor chip SC3 and Figure 20D The fourth semiconductor chip. (See reference...) Figure 5 and Figure 9 As described, because the frame identifiers FA1, FA2, FB1 and FB2 are separated from multiple cleaving lines X1, X2, X3, X4, X5, Y1, Y2 and Y3, the frame identifiers FA1, FA2, FB1 and FB2 can be retained in the semiconductor chips SC1, SC2, SC3 and SC4 respectively after cleaving the semiconductor wafer 10.

[0106] In this embodiment, semiconductor chips SC1, SC2, SC3, and SC4 have a substrate 12, which includes a chip region CR and residual scribe lines RSL located outside the chip region CR. The residual scribe lines RSL refer to the regions of semiconductor chips SC1, SC2, SC3, and SC4 remaining after the semiconductor wafers have been scribed along multiple scribe lines X1, X2, X3, X4, X5, Y1, Y2, and Y3 to manufacture semiconductor chips SC1, SC2, SC3, and SC4.

[0107] In one embodiment, at least one of the semiconductor chips SC1, SC2, SC3, and SC4 includes an infrared pattern recognizable by infrared light incident on the lower surface of the substrate 12, serving as frame identifiers FA1, FA2, FB1, and FB2 respectively disposed on the upper surface of the substrate 12. In this example, the frame identifiers FA1, FA2, FB1, and FB2 are infrared markers. In another embodiment, at least one of the semiconductor chips SC1, SC2, SC3, and SC4 includes a visible light pattern recognizable by visible light incident from above the substrate 12, serving as frame identifiers FA1, FA2, FB1, and FB2. In this example, the frame identifiers FA1, FA2, FB1, and FB2 are visible light markers.

[0108] Infrared and visible light markings comprise multiple optical patterns, which in turn comprise integrated circuit structures with different stacked configurations. The multiple optical patterns generate brightness differences through the varying light reflection and transmission characteristics resulting from the different stacked configurations of the integrated circuit structures. Infrared and / or visible light markings may include square or grid patterns formed by the multiple optical patterns.

[0109] In the implementation method, as referred to Figures 10A to 10C The described infrared marker includes multiple optical patterns OP1, OP2, and OP3, which generate brightness differences due to the material properties of the material layer and their arrangement at different distances from the upper surface of the substrate 12. In another embodiment, as shown in reference... Figures 11A to 11C The visible light markings described herein include multiple optical patterns OPa, OPb, and OPc, which generate brightness differences based on the structure of the interconnects and interlayer insulating layers of the substrate 12.

[0110] Multiple optical patterns OP1, OP2, OP3, OPa, OPb and OPc, such as Figure 20A As shown, it is arranged at the corner of the chip area CR adjacent to the scribing track SL, or as... Figure 20CThe arrangement shown is located at a corner within the chip region CR. Multiple optical patterns OP1, OP2, OP3, OPa, OPb, and OPc are arranged along the second direction (length) and the first direction (height) of the chip region CR. Detailed arrangement methods for the multiple optical patterns OP1, OP2, OP3, OPa, OPb, and OPc can be found in... Figure 6 The layouts are basically similar.

[0111] Multiple optical patterns OP1, OP2, OP3, OPa, OPb and OPc, such as Figure 20B The settings shown are in the lane SL, or as... Figure 20D The diagram shows the locations within the chip region CR. Multiple optical patterns OP1, OP2, OP3, OPa, OPb, and OPc are arranged in one direction along either the second direction (length) or the first direction (height) of the chip region CR. The detailed arrangement of the multiple optical patterns OP1, OP2, OP3, OPa, OPb, and OPc can be found in... Figure 7 The layouts are basically similar.

[0112] When multiple optical patterns OP1, OP2, OP3, OPa, OPb and OPc are arranged in the chip region CR, the multiple optical patterns OP1, OP2, OP3, OPa, OPb and OPc can be arranged in the peripheral circuit arrangement area of ​​the cell arrangement area and the peripheral circuit arrangement area of ​​the chip region CR.

[0113] Although detailed embodiments of the present disclosure have been described herein, those skilled in the art will understand that various modifications, additions, and substitutions may be made in relation to these embodiments without departing from the scope and technical concept of the present disclosure. Therefore, the scope of the present disclosure should not be limited to the embodiments described above. All changes within the meaning and equivalent scope of the claims are included within its scope.

[0114] Cross-references to related applications

[0115] This application claims priority to Korean Application No. 10-2024-0063487, filed on May 14, 2024, with the Korean Intellectual Property Office, the entirety of which is incorporated herein by reference.

Claims

1. A semiconductor chip, the semiconductor chip comprising: A substrate, the substrate including a chip region and residual scribe lines surrounding the chip region; as well as Infrared markers, which are disposed within the chip area or the residual scribe lines, comprise multiple optical patterns. The plurality of optical patterns include integrated circuit structures with different stacked structures above the substrate, and the plurality of optical patterns have different infrared reflection characteristics.

2. The semiconductor chip according to claim 1, wherein, The plurality of optical patterns are arranged along a first direction and a second direction in the residual scribe lines near the edge of the chip region.

3. The semiconductor chip according to claim 1, wherein, The plurality of optical patterns are arranged in the residual scribe line along one of the first and second directions of the chip region.

4. The semiconductor chip according to claim 1, in, The chip region includes a cell arrangement region and a peripheral circuit arrangement region, and The infrared marker is located in the peripheral circuit layout area.

5. The semiconductor chip according to claim 1, wherein, The plurality of optical patterns are arranged at the corners located within the chip area.

6. The semiconductor chip according to claim 1, wherein, The plurality of optical patterns are arranged in the chip region along one of a first direction and a second direction.

7. The semiconductor chip according to claim 1, wherein, The plurality of optical patterns of the infrared marker form a grid pattern that is correlated with the brightness differences between the plurality of optical patterns.

8. A semiconductor wafer comprising: A unit frame, repeatedly arranged on a substrate, wherein the unit frame comprises: Multiple chip areas; A scribing channel is disposed between the plurality of chip regions; and A frame identifier is provided in at least one of the plurality of chip regions or in the scribe line, and provides a reference for identifying the location of the plurality of scribe lines.

9. The semiconductor wafer according to claim 8, wherein, The frame identifier is a single identifier set within the unit frame.

10. The semiconductor wafer according to claim 8, in, At least one of the plurality of chip regions includes a cell arrangement region and a peripheral circuit arrangement region, and The frame identifier is located in the peripheral circuit layout area.

11. The semiconductor wafer according to claim 8, in, The frame identifier includes multiple optical patterns, which comprise integrated circuit structures with different stack-up structures, and The plurality of optical patterns are identified by the light reflection and light transmission characteristics of the integrated circuit structure.

12. The semiconductor wafer according to claim 11, wherein, Each of the plurality of optical patterns is associated with a different image among a plurality of images formed by infrared light irradiating a first surface of the substrate.

13. The semiconductor wafer according to claim 11, wherein, Each of the plurality of optical patterns is associated with a different image among a plurality of images formed by visible light irradiating the substrate.

14. A method for processing semiconductor wafers, the method comprising the following steps: Forming a semiconductor wafer comprising repeating unit frames arranged on a substrate, at least one of the unit frames comprising a frame identifier located in one or more chip regions or in a scribe line between the chip regions; The frame identifier is used to determine the positions of multiple scribing lines in the scribing channel, the multiple scribing lines separating the multiple chip regions; The process conditions for the scribing process are determined for at least one position of the plurality of scribing lines; as well as The semiconductor wafer is diced along the multiple dicing lines based on the process conditions.

15. The method according to claim 14, in, The frame identifier includes multiple optical patterns, which comprise integrated circuit structures with different stack-up structures, and Each of the plurality of optical patterns is distinguished by the light reflection and light transmission characteristics of the integrated circuit structure.

16. The method of claim 14, wherein, The steps for determining the positions of the multiple cleaving lines include the following: Infrared light is irradiated onto a first surface of the substrate, and an infrared image reflected from the substrate is obtained to identify the frame identifier of the unit frame; and The positions of the plurality of cleaving lines arranged along a first direction and along a second direction substantially perpendicular to the first direction within the unit frame are determined based on the identified frame identifier.

17. The method according to claim 16, wherein, The steps for determining the process conditions of the scribing process include the following: The process conditions for determining invisible dicing are defined for at least one of the plurality of dicing lines arranged along the first direction; and The process conditions for invisible slicing are determined for at least one of the plurality of slicing lines arranged along the second direction.

18. The method according to claim 14, wherein, The steps for determining the positions of the multiple cleaving lines include the following: Illuminating the substrate with visible light and obtaining an image of the visible light reflected from the substrate to identify the frame identifier of the unit frame; and The positions of the plurality of cleaving lines arranged along a first direction and along a second direction substantially perpendicular to the first direction within the unit frame are determined based on the identified frame identifier.

19. The method according to claim 18, wherein, The steps for determining the process conditions of the scribing process include the following: Selecting a first scribe line from among the plurality of scribe lines arranged along the first and second directions to perform the initial scribe; and The process conditions for preliminary dicing are determined for the first dicing line, and The initial cutting process includes blade sawing or laser grooving.

20. The method according to claim 19, wherein, The step of dicing the semiconductor wafer includes performing a preliminary dicing along the first dicing line.

21. The method of claim 20, further comprising performing a main cut after performing a preliminary cut. in, The main cut includes: The locations of multiple invisible scribe lines are determined using individually applied invisible scribe markers on the semiconductor wafer; and Perform invisible scribing along the multiple invisible scribing lines.

22. The method according to claim 21, wherein, The invisible scribing is performed using first scribing process conditions for a first invisible scribing line arranged along the first direction, and using second scribing process conditions for a second invisible scribing line arranged along the second direction.

23. The method of claim 14, further comprising the step of: The positions of the plurality of scribing lines determined from the frame identifier are compared with the positions of the plurality of chip cutting lines formed using the scribing process; as well as The position of the scribe line is then corrected for the subsequent scribe process.

24. The method according to claim 23, wherein, The step of correcting the position of the scribe line is performed during the scribe process for the semiconductor wafer.

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