Linear equalizer, electronic circuit, and electronic device

Abstract

The application provides a linear equalizer, an electronic circuit and an electronic device. In the linear equalizer, two ends of a first coupling capacitor are connected with a second differential input end and a first differential output end respectively, and two ends of a second coupling capacitor are connected with a first differential input end and a second differential output end respectively. Therefore, a first differential amplifier, the first coupling capacitor and the second coupling capacitor form an active inductor structure. On this basis, the active inductor module assists a T-shaped coil matching module, so that the equivalent input capacitance of the first differential amplifier decreases with the increase of the first differential input signal, thereby increasing the gain of a high frequency band in the T-shaped coil matching module and the working bandwidth of the T-shaped coil matching module. In addition, the matching type of the T-shaped coil matching module has high tolerance to loads and does not introduce additional nonlinearity, so that the process deviation of the T-shaped coil matching module is small, thereby improving the process stability of the linear equalizer.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more particularly to a linear equalizer, electronic circuit, and electronic device. Background Technology

[0002] Channels such as transmission lines and coaxial cables inherently have low-pass frequencies, and their conductor and dielectric losses cause signal attenuation. The attenuation increases with signal frequency. Furthermore, high-speed signals passing through these channels are prone to waveform distortion, affecting the behavior of subsequent circuits and causing bit errors. Since continuous-time linear equalizers compensate for channel losses and restore the original signal shape, reducing the bit error rate and improving the overall performance of communication systems, they have wide and important applications in both analog and digital circuits.

[0003] Traditional continuous-time linear equalizers are typically based on source degradation resistor-capacitor technology, inductor peaking technology, or transconductance-transimpedance amplifier architecture. However, continuous-time linear equalizers based on source degradation resistor-capacitor technology and those based on inductor peaking technology are difficult to achieve large operating bandwidths, while continuous-time linear equalizers based on transconductance-transimpedance amplifier architecture suffer from poor process stability. Summary of the Invention

[0004] This invention provides a linear equalizer, electronic circuit, and electronic device to improve the operating bandwidth of the linear equalizer while enhancing its process stability.

[0005] According to a first aspect of the present invention, a linear equalizer is provided, comprising:

[0006] A T-type coil matching module is used to perform impedance matching on a first differential input signal to form a first signal, and to perform impedance matching on a second differential input signal to form a second signal. The T-type coil matching module includes a first matching input terminal, a second matching input terminal, a first matching output terminal, and a second matching output terminal. The first matching input terminal and the second matching input terminal are respectively connected to the first differential input signal and the second differential input signal, and the first matching output terminal and the second matching output terminal respectively output the first signal and the second signal.

[0007] A first differential amplifier is used to amplify the first signal to form a first amplified signal and to amplify the second signal to form a second amplified signal. The first differential amplifier includes a first differential input terminal, a second differential input terminal, a first differential output terminal, and a second differential output terminal. The first differential input terminal is connected to the first matched output terminal to receive the first signal, and the second differential input terminal is connected to the second matched output terminal to receive the second signal. The first differential output terminal outputs the first amplified signal, and the second differential output terminal outputs the second amplified signal.

[0008] A first coupling capacitor, the two ends of which are respectively connected to the second differential input terminal and the first differential output terminal;

[0009] The second coupling capacitor is connected at both ends to the first differential input terminal and the second differential output terminal, respectively.

[0010] Optionally, the T-type coil matching module includes:

[0011] A first inductor, wherein a first end of the first inductor is connected to the first differential input signal as the first matched input terminal, and a second end of the first inductor is connected to the first differential input terminal as the first matched output terminal;

[0012] The second inductor has its first end connected to the second end of the first inductor.

[0013] The third inductor, wherein the second end of the third inductor is connected to the second differential input terminal as the second matched output terminal;

[0014] The fourth inductor has its first end connected to the second end of the third inductor, and the second end of the fourth inductor serves as the second matching input terminal for the second differential input signal.

[0015] A matching resistor is provided, the two ends of which are respectively connected to the second end of the second inductor and the first end of the third inductor, and the midpoint of the matching resistor is grounded.

[0016] A first matching capacitor, the two ends of which are respectively connected to the first end of the first inductor and the second end of the second inductor;

[0017] The second matching capacitor is connected at its two ends to the first end of the third inductor and the second end of the fourth inductor, respectively.

[0018] Optionally, the first differential amplifier includes:

[0019] The first push-pull amplification unit is used to amplify the first signal to output the amplified signal;

[0020] The second push-pull amplification unit is used to amplify the second signal to output the second amplified signal;

[0021] The first bias current unit is used to provide bias current for the first push-pull amplifier unit and the second push-pull amplifier unit.

[0022] The first common-mode feedback unit is used to adjust the bias current received by the first push-pull amplifier unit and the second push-pull amplifier unit according to the first amplified signal and the second amplified signal, so as to adjust the common-mode voltage of the first differential amplifier.

[0023] The first peaking unit includes a first peaking inductor, a first peaking resistor, and a second peaking resistor. The two ends of the first peaking resistor are respectively connected to the first differential output terminal and the first end of the first peaking inductor. The two ends of the second peaking resistor are respectively connected to the second differential output terminal and the second end of the first peaking inductor.

[0024] Optionally, the first bias current unit includes:

[0025] A first bias current source, the output terminal of which is connected to ground;

[0026] The first current mirror includes a first current input terminal, a first voltage input terminal, a first current output terminal, and a second current output terminal. The first current input terminal is connected to the input terminal of the first bias current source, the first voltage input terminal is connected to the first power supply voltage, the first current output terminal is connected to the first terminal of the first push-pull amplifier unit, and the second current output terminal is connected to the first terminal of the second push-pull amplifier unit.

[0027] Optionally, the first current mirror includes:

[0028] The first PMOS transistor has its gate connected to its drain terminal and used as the first current input terminal.

[0029] The drain terminal of the second PMOS transistor serves as the first current output terminal.

[0030] The third PMOS transistor has its drain terminal serving as the second current output terminal, its gate terminal connected to the gate terminals of the first PMOS transistor and the second PMOS transistor, and its source terminal connected to the source terminals of the first PMOS transistor and the second PMOS transistor, serving as the second current input terminal.

[0031] Optionally, the first push-pull amplification unit includes: a first push-pull PMOS transistor, the source terminal of which serves as the first terminal of the first push-pull amplification unit; a first push-pull NMOS transistor, the drain terminal of which is connected to the drain terminal of the first push-pull PMOS transistor and serves as the first differential output terminal; the gate terminal of which is connected to the gate terminal of the first push-pull PMOS transistor and serves as the first differential input terminal; and the source terminal of the first push-pull NMOS transistor is grounded.

[0032] The second push-pull amplification unit includes: a second push-pull PMOS transistor, the source terminal of which serves as the first terminal of the second push-pull amplification unit; a second push-pull NMOS transistor, the drain terminal of which is connected to the drain terminal of the second push-pull PMOS transistor and serves as the second differential output terminal; the gate terminal of which is connected to the gate terminal of the second push-pull PMOS transistor and serves as the second differential input terminal; and the source terminal of the second push-pull NMOS transistor is grounded.

[0033] Optionally, the first differential amplifier is a high-frequency gain differential amplifier, and the capacitance values ​​of the first coupling capacitor and the second coupling capacitor are the same. The capacitance value of the first coupling capacitor C1 is...

[0034] ,

[0035] in, The sum of the intrinsic gate-source capacitance of the first push-pull NMOS transistor and the intrinsic gate-source capacitance of the first push-pull PMOS transistor is used to characterize the capacitance of the first push-pull NMOS transistor. Used to characterize the transconductance of the first differential amplifier. The inductance value used to characterize the first peaked inductor Used to characterize the resistance value of the first peaking resistor. The parallel resistance value used to characterize the output resistance of the first push-pull NMOS transistor and the output resistance of the first push-pull PMOS transistor. The capacitance value used to characterize the load capacitance of the first differential amplifier.

[0036] Optionally, the first differential amplifier further includes:

[0037] The first degradation unit has two ends connected to the first end of the first push-pull amplification unit and the first end of the second push-pull amplification unit, respectively. The first degradation unit includes a first degradation capacitor and a first degradation resistor connected in parallel.

[0038] The first source degradation unit has two ends connected to the source terminal of the first push-pull NMOS transistor and ground, respectively. The first source degradation unit includes a first source degradation capacitor and a first source degradation resistor connected in parallel.

[0039] The second source degradation unit has two ends connected to the source terminal of the second push-pull NMOS transistor and ground, respectively. The second source degradation unit includes a second source degradation capacitor and a second source degradation resistor connected in parallel.

[0040] The first peaking unit includes a first peaking inductor, a first peaking resistor, and a second peaking resistor. The two ends of the first peaking resistor are respectively connected to the first differential output terminal and the first end of the first peaking inductor. The two ends of the second peaking resistor are respectively connected to the second differential output terminal and the second end of the first peaking inductor.

[0041] Optionally, the first common-mode feedback unit includes:

[0042] A first feedback amplifier, wherein the inverting input terminal of the first feedback amplifier is connected to a first reference voltage;

[0043] The first feedback resistor is connected at both ends to the first differential output terminal and the non-inverting input terminal of the first feedback amplifier, respectively.

[0044] The second feedback resistor is connected at both ends to the second differential output terminal and the non-inverting input terminal of the first feedback amplifier, respectively.

[0045] The first feedback PMOS transistor has its gate connected to the output of the first feedback amplifier, its drain connected to the first terminal of the first push-pull amplifier unit, and its source connected to the first power supply voltage.

[0046] The second feedback PMOS transistor has its gate connected to the output of the first feedback amplifier, its drain connected to the first terminal of the second push-pull amplifier unit, and its source connected to the first power supply voltage.

[0047] Optionally, it further includes a second differential amplifier for amplifying the first amplified signal to form a third amplified signal, and for amplifying the second amplified signal to form a fourth amplified signal. The second differential amplifier includes a third differential input terminal, a fourth differential input terminal, a third differential output terminal, and a fourth differential output terminal. The third differential input terminal is connected to the first differential output terminal to receive the first amplified signal, the fourth differential input terminal is connected to the second differential output terminal to receive the second amplified signal, the third differential output terminal outputs the third amplified signal, and the fourth differential output terminal outputs the fourth amplified signal.

[0048] Optionally, the first differential amplifier is a low-frequency gain differential amplifier, and the second differential amplifier is a high-frequency gain amplifier.

[0049] Optional, also includes:

[0050] The first neutralizing capacitor is connected at both ends to the fourth differential input terminal and the third differential output terminal, respectively.

[0051] The second neutralizing capacitor is connected at its two ends to the third differential input terminal and the fourth differential output terminal, respectively.

[0052] Optionally, the first neutralizing capacitor and the second neutralizing capacitor have the same capacitance value, and the capacitance value of the first neutralizing capacitor is less than the capacitance value of the first coupling capacitor.

[0053] Optionally, the second differential amplifier includes:

[0054] The third push-pull amplification unit is used to amplify the first amplified signal to output the third amplified signal;

[0055] A fourth push-pull amplification unit is used to amplify the second amplified signal to output the fourth amplified signal;

[0056] The second bias current unit is used to provide bias current for the third push-pull amplifier unit and the fourth push-pull amplifier unit;

[0057] The second common-mode feedback unit is used to adjust the bias current received by the third push-pull amplifier unit and the fourth push-pull amplifier unit according to the third amplified signal and the fourth amplified signal.

[0058] According to a second aspect of the present invention, an electronic circuit is provided, comprising the linear equalizer described above.

[0059] According to a third aspect of the present invention, an electronic device is provided, comprising the electronic circuit described above.

[0060] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0061] In the linear equalizer provided by this invention, since the two ends of the first coupling capacitor are respectively connected to the second differential input terminal and the first differential output terminal, and the two ends of the second coupling capacitor are respectively connected to the first differential input terminal and the second differential output terminal, the first differential amplifier, the first coupling capacitor, and the second coupling capacitor can form an active inductor structure. Furthermore, since the first differential input terminal is connected to the first matching output terminal, and the second differential input terminal is connected to the second matching output terminal, the active inductor module can assist the T-type coil matching module. This causes the equivalent input capacitance of the first differential amplifier to decrease as the first differential input signal increases, thereby increasing the high-frequency gain in the T-type coil matching module and improving its operating bandwidth, which in turn increases the operating bandwidth of the linear equalizer. In addition, since the matching type of the T-type coil matching module has a high tolerance to load and does not introduce additional nonlinearity, the manufacturing process deviation of the T-type coil matching module is small, thus improving the manufacturing stability of the linear equalizer.

[0062] Furthermore, since the linear equalizer also includes a second differential amplifier, which is used to amplify the first amplified signal to form a third amplified signal and to amplify the second amplified signal to form a fourth amplified signal, and the first differential amplifier is used to increase the low-frequency gain of the first and second signals, and the second differential amplifier is used to increase the high-frequency gain of the first and second amplified signals, the linear equalizer compensates for both the high-frequency and low-frequency bands of the first and second differential input signals, thereby enabling the linear equalizer to better recover the initial signal before transmission through the channel. Attached Figure Description

[0063] Figure 1 This is a schematic diagram of the circuit structure of a linear equalizer provided in an embodiment of the present invention;

[0064] Figure 2 This is a schematic diagram of the circuit structure of a T-type coil matching module provided in an embodiment of the present invention;

[0065] Figure 3 This is a schematic diagram of the circuit structure of the first differential amplifier provided in one embodiment of the present invention;

[0066] Figure 4 This is a circuit structure diagram of a linear equalizer provided in another embodiment of the present invention;

[0067] Figure 5This is a simulation diagram of the frequency response of a linear equalizer provided in another embodiment of the present invention.

[0068] Figure label:

[0069] Vin1 - First differential input signal;

[0070] Vin2 - Second differential input signal;

[0071] V1 - First signal;

[0072] V2 - Second signal;

[0073] V11 - First amplified signal;

[0074] V22 - Second amplified signal;

[0075] V3 - Third amplified signal;

[0076] V4 - Fourth amplified signal;

[0077] Vref1 - First reference voltage;

[0078] 1-First differential amplifier;

[0079] 2-Second differential amplifier;

[0080] 101 - First bias current unit;

[0081] 102 - First common-mode feedback unit;

[0082] 103 - First push-pull amplification unit;

[0083] 104 - Second push-pull amplifier unit;

[0084] 105 - Degenerate unit;

[0085] 106 - First source degradation unit;

[0086] 107 - Second source degradation unit;

[0087] 108-peak unit;

[0088] C1 - First coupling capacitor;

[0089] C2 - Second coupling capacitor;

[0090] C3 - First neutralizing capacitor;

[0091] C4 - Second neutralizing capacitor;

[0092] L1 - First inductor;

[0093] L2 - Second inductor;

[0094] L3 - Third inductor;

[0095] L4 - Fourth Inductor;

[0096] Cp1 - First matching capacitor;

[0097] Cp1 - Second matching capacitor;

[0098] RT - Matching resistor;

[0099] Ib1 - First bias current source;

[0100] Q1 - First PMOS transistor;

[0101] Q1 - Second PMOS transistor;

[0102] Q1 - Third PMOS transistor;

[0103] QP1 - First push-pull PMOS transistor;

[0104] QN1 - First push-pull NMOS transistor;

[0105] QP2 - Second push-pull PMOS transistor;

[0106] QN2 - Second push-pull NMOS transistor;

[0107] Cd - First degenerate capacitor;

[0108] Rd - First degraded resistor;

[0109] Cs1 is the first source degradation capacitor;

[0110] Rs1 - First source degradation resistor;

[0111] Cs2 - Second source degradation capacitor;

[0112] Rs2 - Second source degradation resistor;

[0113] Lo - First peaking inductor;

[0114] Ro1 - First peaking resistor;

[0115] Ro2 - Second peaking resistor;

[0116] D1 - First feedback amplifier;

[0117] Rr1 - First feedback resistor;

[0118] Rr2 - Second feedback resistor;

[0119] Qr1 - First feedback PMOS transistor;

[0120] Qr2 - Second feedback PMOS transistor. Detailed Implementation

[0121] As described in the background section, traditional continuous-time linear equalizers suffer from problems such as small operating bandwidth and poor process stability.

[0122] Specifically, source degradation resistor-capacitor (RCC) technology introduces a zero in the transfer function of a continuous-time linear equalizer by connecting a resistor and capacitor to the source of the common-source amplifier transistor. This boosts the amplifier's gain in the high-frequency range, compensating for the attenuation of high-frequency components during signal transmission. However, circuits commonly contain high-frequency poles introduced by parasitic resistance and capacitance. These poles negate the gain boost effect of the zero, severely limiting the zero-frequency setting in RCC technology. This makes it difficult to use RCC to compensate for the attenuation of high-frequency components during signal transmission and thus improve the operating bandwidth of the continuous-time linear equalizer.

[0123] Inductor peaking technology expands the amplifier's bandwidth by introducing an inductor at the amplifier's output to neutralize parasitic capacitance or load capacitance at the output node. However, this method is highly sensitive to the parasitic capacitance at the output node and the parasitic parameters of the inductor itself, which limits the bandwidth expansion effect and affects the controllability of the overall equalization performance.

[0124] Transconductance-transimpedance amplifier architectures use active inductors to replace passive inductors that are difficult to integrate on-chip, thereby improving circuit integration. However, active inductors are extremely sensitive to process variations and component mismatches, which can easily lead to changes in the equivalent inductance, affecting the center frequency and operating bandwidth of the continuous-time linear equalizer, as well as its process stability.

[0125] In view of this, the present invention creatively proposes a linear equalizer, comprising:

[0126] A T-type coil matching module is used to perform impedance matching on a first differential input signal to form a first signal, and to perform impedance matching on a second differential input signal to form a second signal. The T-type coil matching module includes a first matching input terminal, a second matching input terminal, a first matching output terminal, and a second matching output terminal. The first matching input terminal and the second matching input terminal are respectively connected to the first differential input signal and the second differential input signal, and the first matching output terminal and the second matching output terminal respectively output the first signal and the second signal.

[0127] A first differential amplifier is used to amplify the first signal to form a first amplified signal and to amplify the second signal to form a second amplified signal. The first differential amplifier includes a first differential input terminal, a second differential input terminal, a first differential output terminal, and a second differential output terminal. The first differential input terminal is connected to the first matched output terminal to receive the first signal, and the second differential input terminal is connected to the second matched output terminal to receive the second signal. The first differential output terminal outputs the first amplified signal, and the second differential output terminal outputs the second amplified signal.

[0128] A first coupling capacitor, the two ends of which are respectively connected to the second differential input terminal and the first differential output terminal;

[0129] The second coupling capacitor is connected at both ends to the first differential input terminal and the second differential output terminal, respectively.

[0130] Since the two ends of the first coupling capacitor are connected to the second differential input terminal and the first differential output terminal respectively, and the two ends of the second coupling capacitor are also connected to the first differential input terminal and the second differential output terminal respectively, the first differential amplifier, the first coupling capacitor, and the second coupling capacitor can form an active inductor structure. Furthermore, since the first differential input terminal is connected to the first matching output terminal, and the second differential input terminal is connected to the second matching output terminal, the active inductor module can assist the T-type coil matching module, thereby increasing the high-frequency gain in the T-type coil matching module and thus improving its operating bandwidth, which in turn increases the operating bandwidth of the linear equalizer. In addition, because the matching type of the T-type coil matching module has a high tolerance to load and does not introduce additional nonlinearity, the manufacturing process deviation of the T-type coil matching module is small, thereby improving the manufacturing stability of the linear equalizer.

[0131] To make the above-mentioned objects, features, and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. The terms "first," "second," "third," etc., in the specification, claims, and accompanying drawings of the present invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0132] Figure 1 This is a schematic diagram of the circuit structure of a linear equalizer provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the circuit structure of a T-type coil matching module provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of the circuit structure of the first differential amplifier provided in one embodiment of the present invention.

[0133] Please refer to Figure 1 This invention proposes a linear equalizer, comprising: a T-type coil matching module, a first differential amplifier 1, a first coupling capacitor C1, and a second coupling capacitor C2.

[0134] In this embodiment, the T-type coil matching module is used to perform impedance matching on the first differential input signal Vin1 to form a first signal V1, and to perform impedance matching on the second differential input signal Vin2 to form a second signal V2. The T-type coil matching module includes a first matching input terminal, a second matching input terminal, a first matching output terminal, and a second matching output terminal. The first matching input terminal and the second matching input terminal are respectively connected to the first differential input signal Vin1 and the second differential input signal Vin2, and the first matching output terminal and the second matching output terminal respectively output the first signal V1 and the second signal V2.

[0135] For details, please refer to Figure 2The T-type coil matching module includes: a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4, a matching resistor RT, a first matching capacitor Cp1, and a second matching capacitor Cp2. In this configuration, the first end of the first inductor L1 serves as the first matching input terminal and is connected to the first differential input signal Vin1. The second end of the first inductor L1 serves as the first matching output terminal and is connected to the first differential input terminal. The first end of the second inductor L2 is connected to the second end of the first inductor L1. The second end of the third inductor L3 serves as the second matching output terminal and is connected to the second differential input terminal. The first end of the fourth inductor L4 is connected to the second end of the third inductor L3. The second end of the fourth inductor L4 serves as the second matching input terminal and is connected to the second differential input signal Vin2. The two ends of the matching resistor RT are respectively connected to the second end of the second inductor L2 and the first end of the third inductor L3. Furthermore, the midpoint of the matching resistor RT is grounded. The two ends of the first matching capacitor Cp1 are respectively connected to the first end of the first inductor L1 and the second end of the second inductor L2. The two ends of the second matching capacitor Cp2 are respectively connected to the first end of the third inductor L3 and the second end of the fourth inductor L4.

[0136] The input impedance of the T-type coil matching module changes with the frequency of the input signal (i.e., the first differential input signal Vin1 and the second differential input signal Vin2). However, impedance matching can be achieved by adjusting the values ​​of the internal inductors and capacitors (i.e., the first inductor L1, the second inductor L2, the third inductor L3, the fourth inductor L4, the matching resistor RT, the first matching capacitor Cp1, and the second matching capacitor Cp2). This ensures that when the input signal is transmitted between circuit elements with different impedances, reflection and loss can be minimized, thereby improving the signal transmission efficiency.

[0137] In this embodiment, please refer to Figure 3 The first differential amplifier 1 amplifies the first signal V1 to form a first amplified signal V11, and amplifies the second signal V2 to form a second amplified signal V22. The first differential amplifier 1 includes a first differential input terminal, a second differential input terminal, a first differential output terminal, and a second differential output terminal. The first differential input terminal is connected to a first matched output terminal to receive the first signal V1, the second differential input terminal is connected to a second matched output terminal to receive the second signal V2, the first differential output terminal outputs the first amplified signal V11, and the second differential output terminal outputs the second amplified signal V22.

[0138] In this embodiment, the first differential amplifier 1 includes: a first bias current unit 101, a first push-pull amplification unit 103, a second push-pull amplification unit 104, and a first common-mode feedback unit 102. The first bias current unit 101 provides bias current to the first push-pull amplification unit 103 and the second push-pull amplification unit 104. The first push-pull amplification unit 103 amplifies a first signal V1 to output a first amplified signal V11. The second push-pull amplification unit 104 amplifies a second signal V2 to output a second amplified signal V22. The unit adjusts the bias current received by the first push-pull amplification unit 103 and the second push-pull amplification unit 104 according to the first amplified signal V11 and the second amplified signal V22 to adjust the common-mode voltage of the first differential amplifier 1.

[0139] The first bias current unit 101 includes a first bias current source Ib1 and a first current mirror. Specifically, the output terminal of the first bias current source Ib1 is connected to ground. The first current mirror includes a first current input terminal, a first voltage input terminal, a first current output terminal, and a second current output terminal. The first current input terminal is connected to the input terminal of the first bias current source Ib1, the first voltage input terminal is connected to a first power supply voltage, the first current output terminal is connected to the first terminal of the first push-pull amplifier unit 103, and the second current output terminal is connected to the first terminal of the second push-pull amplifier unit 104.

[0140] The magnitudes of the currents output from the first current output terminal and the second current output terminal are equal, which is equal to the current value output by the first bias current source Ib1.

[0141] Furthermore, the first current mirror includes a first PMOS transistor Q1, a second PMOS transistor Q2, and a third PMOS transistor Q3. Specifically, the gate of the first PMOS transistor Q1 is connected to its drain terminal as a first current input terminal, the drain terminal of the second PMOS transistor Q2 serves as a first current output terminal, the drain terminal of the third PMOS transistor Q3 serves as a second current output terminal, the gate terminal of the third PMOS transistor Q3 is connected to the gate terminals of the first PMOS transistor Q1 and the second PMOS transistor Q2, and the source terminal of the third PMOS transistor Q3 is connected to the source terminals of the first PMOS transistor Q1 and the second PMOS transistor Q2, serving as a second current input terminal.

[0142] In this embodiment, the first push-pull amplifier unit 103 includes a first push-pull PMOS transistor QP1 and a first push-pull NMOS transistor QN1. Specifically, the source terminal of the first push-pull PMOS transistor QP1 serves as the first terminal of the first push-pull amplifier unit 103, the drain terminal of the first push-pull NMOS transistor QN1 is connected to the drain terminal of the first push-pull PMOS transistor QP1 and serves as the first differential output terminal, the gate terminal of the first push-pull NMOS transistor QN1 is connected to the gate terminal of the first push-pull PMOS transistor QP1 and serves as the first differential input terminal, and the source terminal of the first push-pull NMOS transistor is grounded.

[0143] Correspondingly, the second push-pull amplifier unit 104 includes a second push-pull PMOS transistor QP2 and a second push-pull NMOS transistor QN2. Specifically, the source terminal of the second push-pull PMOS transistor QP2 serves as the first terminal of the second push-pull amplifier unit 104, the drain terminal of the second push-pull NMOS transistor QN2 is connected to the drain terminal of the second push-pull PMOS transistor QP2 and serves as the second differential output terminal, the gate terminal of the second push-pull NMOS transistor QN2 is connected to the gate terminal of the second push-pull PMOS transistor QP2 and serves as the second differential input terminal, and the source terminal of the second push-pull NMOS transistor is grounded.

[0144] The first differential amplifier 1 is used to increase the high-frequency gain of the first signal V1 and the second signal V2.

[0145] In addition, the first push-pull amplifier unit 103 and the second push-pull amplifier unit 104 can provide a relatively linear voltage transfer function and provide a certain load driving capability.

[0146] In this embodiment, the first differential amplifier 1 further includes: a first degradation unit 105, a first source degradation unit 106, a second source degradation unit 107, and a first peaking unit 108. Specifically, the two ends of the first degradation unit 105 are respectively connected to the first end of the first push-pull amplifier unit 103 and the first end of the second push-pull amplifier unit 104. The first degradation unit 105 includes a first degradation capacitor Cd and a first degradation resistor Rd connected in parallel. The two ends of the first source degradation unit 106 are respectively connected to the source terminal of the first push-pull NMOS transistor QN1 and ground. The first source degradation unit 106 includes a first source degradation capacitor Cs1 and a first source degradation resistor Rs1 connected in parallel. The two ends of the second source degradation unit 107 are respectively connected to the source terminal of the second push-pull NMOS transistor QN2 and ground. The second source degradation unit 107 includes a second source degradation capacitor Cs2 and a second source degradation resistor Rs2 connected in parallel. It includes a first peaking inductor Lo, a first peaking resistor Ro1, and a second peaking resistor Ro2. The two ends of the first peaking resistor Ro1 are respectively connected to the first differential output terminal and the first end of the first peaking inductor Lo. The two ends of the second peaking resistor Ro2 are respectively connected to the second differential output terminal and the second end of the first peaking inductor Lo. Among them, the capacitors and inductors in the first degradation unit 105, the first source degradation unit 106, and the second source degradation unit 107 are all adjustable. By adjusting the capacitors and inductors in the first degradation unit 105, the first source degradation unit 106, and the second source degradation unit 107, the core indicators such as the gain, bandwidth, linearity, input impedance matching, and stability of the first differential amplifier 1 can be improved.

[0147] Specifically, the first degradation unit 105, the first source degradation unit 106, and the second source degradation unit 107 can introduce the same zero point into the voltage transfer function of the first differential amplifier 1, thereby expanding the operating bandwidth of the first differential amplifier 1. The first peaking unit 108 can be used to neutralize the parasitic capacitance of the output node of the first differential amplifier 1, thereby further expanding the operating bandwidth of the first differential amplifier 1.

[0148] In this embodiment, the first common-mode feedback unit 102 includes: a first feedback amplifier D1, a first feedback resistor Rr1, a second feedback resistor Rr2, a first feedback PMOS transistor Qr1, and a second feedback PMOS transistor Qr2. Specifically, the inverting input terminal of the first feedback amplifier D1 is connected to a first reference voltage Vref1; the two ends of the first feedback resistor Rr1 are respectively connected to the first differential output terminal and the non-inverting input terminal of the first feedback amplifier D1; the two ends of the second feedback resistor Rr2 are respectively connected to the second differential output terminal and the non-inverting input terminal of the first feedback amplifier D1; the gate terminal of the first feedback PMOS transistor Qr1 is connected to the output terminal of the first feedback amplifier D1; the drain terminal of the first feedback PMOS transistor Qr1 is connected to the first terminal of the first push-pull amplifier unit 103; the source terminal of the first feedback PMOS transistor Qr1 is connected to a first power supply voltage; the gate terminal of the second feedback PMOS transistor Qr2 is connected to the output terminal of the first feedback amplifier D1; the drain terminal of the second feedback PMOS transistor Qr2 is connected to the first terminal of the second push-pull amplifier unit 104; and the source terminal of the second feedback PMOS transistor Qr2 is connected to the first power supply voltage.

[0149] In this circuit, the first feedback resistor Rr1 and the second feedback resistor Rr2 have the same resistance value. Therefore, the non-inverting input terminal of the first feedback amplifier D1 is connected to the common-mode voltage of the output terminal of the first differential amplifier 1. The first feedback amplifier D1 is used to compare the common-mode voltage with the first reference voltage Vref1 and output an error signal to the gate terminals of the first feedback PMOS transistor Qr1 and the second feedback PMOS transistor Qr2. This allows the first feedback PMOS transistor Qr1 and the second feedback PMOS transistor Qr2 to adjust the bias current received by the first push-pull amplifier unit 103 and the second push-pull amplifier unit 104, thereby maintaining the stability of the common-mode voltage at the output terminal of the first differential amplifier 1.

[0150] In this embodiment, please continue to refer to Figure 1 The two ends of the first coupling capacitor C1 are connected to the second differential input terminal and the first differential output terminal, respectively, and the two ends of the second coupling capacitor C2 are connected to the first differential input terminal and the second differential output terminal, respectively. Therefore, the first coupling capacitor C1, the second coupling capacitor C2, and the first differential amplifier 1 can form an active inductor structure. Since the first differential input terminal is connected to the first matching output terminal and the second differential input terminal is connected to the second matching output terminal, this active inductor structure can neutralize the load capacitance of the T-type coil matching module, thereby improving the quality factor of the T-type coil matching module. This allows the T-type coil matching module to obtain a larger peak gain without affecting the matching performance, and at the same time, expands its operating bandwidth.

[0151] In this embodiment, the first coupling capacitor C1 and the second coupling capacitor C2 have the same capacitance value, and the capacitance value of the first coupling capacitor C1 is within the range of...

[0152] ,

[0153] in, The sum of the intrinsic gate-source capacitance of the first push-pull NMOS transistor QN1 and the intrinsic gate-source capacitance of the first push-pull PMOS transistor QP1 is used to characterize the capacitance of the first push-pull NMOS transistor QN1. Used to characterize the transconductance of the first differential amplifier 1 The inductance value used to characterize the first peaked inductor Lo Used to characterize the resistance value of the first peaking resistor Ro1 The parallel resistance value used to characterize the output resistance of the first push-pull NMOS transistor QN1 and the output resistance of the first push-pull PMOS transistor QP1. The capacitance value used to characterize the load capacitance of the first differential amplifier 1.

[0154] Generally, the capacitance value of the first coupling capacitor C1 is twice the sum of the intrinsic gate-drain capacitance of the first push-pull NMOS transistor QN1 and the intrinsic gate-drain capacitance of the first push-pull PMOS transistor QP1, and this value falls within the range of the capacitance value of the first coupling capacitor C1.

[0155] In summary, in the linear equalizer provided by this invention, since the two ends of the first coupling capacitor C1 are respectively connected to the second differential input terminal and the first differential output terminal, and the two ends of the second coupling capacitor C2 are respectively connected to the first differential input terminal and the second differential output terminal, the first differential amplifier 1, the first coupling capacitor C1, and the second coupling capacitor C2 can form an active inductor structure. Furthermore, since the first differential input terminal is connected to the first matching output terminal, and the second differential input terminal is connected to the second matching output terminal, the active inductor module can assist the T-type coil matching module. This causes the equivalent input capacitance of the first differential amplifier to decrease as the first differential input signal increases, thereby increasing the high-frequency gain in the T-type coil matching module and improving its operating bandwidth, which in turn increases the operating bandwidth of the linear equalizer. In addition, because the matching type of the T-type coil matching module has a high tolerance to load and does not introduce additional nonlinearity, the manufacturing process deviation of the T-type coil matching module is small, thus improving the manufacturing stability of the linear equalizer.

[0156] Figure 4 This is a circuit structure diagram of a linear equalizer provided in another embodiment of the present invention. Figure 5 This is a simulation diagram of the frequency response of a linear equalizer provided in another embodiment of the present invention.

[0157] In another embodiment, please refer to Figure 4The linear equalizer also includes a second differential amplifier 2. The second differential amplifier 2 is used to amplify the first amplified signal V11 to form a third amplified signal V3, and to amplify the second amplified signal V22 to form a fourth amplified signal V4. The second differential amplifier 2 includes a third differential input terminal, a fourth differential input terminal, a third differential output terminal, and a fourth differential output terminal. The third differential input terminal is connected to the first differential output terminal to receive the first amplified signal V11, the fourth differential input terminal is connected to the second differential output terminal to receive the second amplified signal V22, the third differential output terminal outputs the third amplified signal V3, and the fourth differential output terminal outputs the fourth amplified signal V4.

[0158] Specifically, the second differential amplifier 2 includes: a second bias current unit, a third push-pull amplification unit, a fourth push-pull amplification unit, and a second common-mode feedback unit. The second bias current unit provides bias current to the third and fourth push-pull amplification units. The third push-pull amplification unit amplifies the first amplified signal V11 to output the third amplified signal V3. The fourth push-pull amplification unit amplifies the second amplified signal V22 to output the fourth amplified signal V4. The second bias current unit adjusts the bias current received by the third and fourth push-pull amplification units based on the third and fourth amplified signals V3 and V4.

[0159] Please continue to refer to the following: Figure 3 The structure of the second differential amplifier 2 is the same as that of the first differential amplifier 1, that is, the structure of the second bias current unit is the same as that of the first bias current unit 101, the structure of the third push-pull amplifier unit is the same as that of the first push-pull amplifier unit 103, the structure of the fourth push-pull amplifier unit is the same as that of the second push-pull amplifier unit 104, and the structure of the second common-mode feedback unit is the same as that of the first common-mode feedback unit 102, so they will not be described in detail here.

[0160] Correspondingly, the second differential amplifier 2 can also be equipped with a second degradation unit 105, a third source degradation unit 105, a fourth source degradation unit 105, and a second peaking unit 108. Furthermore, the positions of the second degradation unit 105, the third source degradation unit 105, and the fourth source degradation unit 105 in the second differential amplifier 2 are the same as those of the first degradation unit 105, the first source degradation unit 106, and the second source degradation unit 107 in the first differential amplifier 1, and their functions are also the same, so they will not be described again here. In addition, the position of the second peaking unit 108 in the second differential amplifier 2 is the same as that of the first peaking unit 108 in the first differential amplifier 1, but the function of the second peaking unit 108 is slightly different from that of the first peaking unit 108. The function of the second peaking unit 108 is that the peaking inductor in the second peaking unit 108 can resonate with the parasitic capacitance of the output node of the second differential amplifier 2, thereby providing extremely high high-frequency peaking gain and further compensating for the high-frequency components of the signal.

[0161] In another embodiment, please continue to refer to Figure 4 The linear equalizer also includes a first neutralizing capacitor C3 and a second neutralizing capacitor C4. Specifically, the two ends of the first neutralizing capacitor C3 are connected to the fourth differential input terminal and the third differential output terminal, respectively, and the two ends of the second neutralizing capacitor C4 are connected to the third differential input terminal and the fourth differential output terminal, respectively. The capacitance values ​​of the first neutralizing capacitor C3 and the second neutralizing capacitor C4 are the same, but the capacitance value of the first neutralizing capacitor C3 is less than the capacitance value of the first coupling capacitor C1. The capacitance value of the first neutralizing capacitor C3 is the sum of the gate-drain capacitances of the push-pull NMOS transistor and the push-pull PMOS transistor in the third push-pull amplifier unit. The first neutralizing capacitor C3 and the second neutralizing capacitor C4 can cancel the Miller effect, that is, they can cancel the influence of the gate-drain capacitances of the MOS transistors in the third and fourth push-pull amplifier units, thereby reducing the equivalent input capacitance of the second differential amplifier 2 and improving the operating bandwidth of the second differential amplifier 2. Furthermore, if the MOS transistors in the third and fourth push-pull amplification units are replaced with bipolar junction transistors, the first neutralizing capacitor C3 and the second neutralizing capacitor C4 can offset the effects of the parasitic capacitance between the base and collector.

[0162] In another embodiment, the first differential amplifier 1 is a low-frequency gain differential amplifier, and the second differential amplifier 2 is a high-frequency gain amplifier. Therefore, the MOSFETs of the first push-pull amplification unit 103 and the second push-pull amplification unit 104 in the first differential amplifier 1 should be MOSFETs with a larger channel width, and the MOSFETs of the third push-pull amplification unit and the fourth push-pull amplification unit in the second differential amplifier 2 should be MOSFETs with a smaller channel width. For example, the channel width of the MOSFETs of the first push-pull amplification unit 103 and the second push-pull amplification unit 104 is 2 to 3 times the channel width of the MOSFETs of the third push-pull amplification unit and the fourth push-pull amplification unit.

[0163] Therefore, the linear equalizer compensates for both the high-frequency and low-frequency bands of the first differential input signal Vin1 and the second differential input signal Vin2, thereby enabling the linear equalizer to better recover the initial signal before transmission through the channel.

[0164] In another embodiment, the linear equalizer is designed using a 28nm CMOS process. Please refer to [link / reference needed]. Figure 5 , Figure 5 This is a simulation graph of the frequency response curve of a linear equalizer. Figure 5 The three simulation curves in the image represent the frequency response of the linear equalizer under three different control words. Therefore, Figure 5 This demonstrates that the linear equalizer can achieve an extremely wide operating bandwidth exceeding 70 GHz. Furthermore, by controlling the source degradation unit, the low-frequency gain of the linear equalizer can be controlled under three different control words. In other words, by setting different control words, the linear equalizer can achieve controllable adjustment of the low-frequency gain, allowing it to better adapt to signals with varying attenuation. In addition, this linear equalizer can effectively perform ultra-wideband gain equalization on the input signal, restoring the original signal characteristics, reducing the bit error rate, and improving the overall performance of the communication system.

[0165] In summary, in another embodiment of the present invention, a linear equalizer further includes a second differential amplifier 2. The second differential amplifier 2 is used to amplify the first amplified signal V11 to form a third amplified signal V3, and to amplify the second amplified signal V22 to form a fourth amplified signal V4. At this time, the first differential amplifier 1 is used to improve the low-frequency gain of the first signal V1 and the second signal V2, and the second differential amplifier 2 is used to improve the high-frequency gain of the first amplified signal V11 and the second amplified signal V22. Therefore, the linear equalizer compensates for both the high-frequency and low-frequency bands of the first differential input signal Vin1 and the second differential input signal Vin2, thereby enabling the linear equalizer to better recover the initial signal before transmission through the channel.

[0166] This invention also provides an electronic circuit including the linear equalizer described above.

[0167] This invention also provides an electro-electronic device, including the electronic circuit described above.

[0168] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A linear equalizer characterized by, The T-shaped coil matching module is used for impedance matching of the first differential input signal to form a first signal and impedance matching of the second differential input signal to form a second signal, and comprises a first matching input end, a second matching input end, a first matching output end and a second matching output end. The first matching input end and the second matching input end are connected to the first differential input signal and the second differential input signal respectively, and the first matching output end and the second matching output end output the first signal and the second signal respectively. The first differential amplifier is used for amplifying the first signal to form a first amplified signal and amplifying the second signal to form a second amplified signal, and comprises a first differential input end, a second differential input end, a first differential output end and a second differential output end. The first differential input end is connected to the first matching output end to access the first signal, the second differential input end is connected to the second matching output end to access the second signal, the first differential output end outputs the first amplified signal, and the second differential output end outputs the second amplified signal. The first coupling capacitor has two ends connected to the second differential input end and the first differential output end respectively. The second coupling capacitor has two ends connected to the first differential input end and the second differential output end respectively. The first differential amplifier comprises a first push-pull amplification unit, a second push-pull amplification unit, a first bias current unit, a first common-mode feedback unit and a first peaking unit. The first push-pull amplification unit is used for amplifying the first signal to output the first amplified signal. The second push-pull amplification unit is used for amplifying the second signal to output the second amplified signal. The first bias current unit is used for providing bias current for the first push-pull amplification unit and the second push-pull amplification unit. The first common-mode feedback unit is used for adjusting the bias current received by the first push-pull amplification unit and the second push-pull amplification unit according to the first amplified signal and the second amplified signal, so as to adjust the common-mode voltage of the first differential amplifier. The first peaking unit comprises a first peaking inductor, a first peaking resistor and a second peaking resistor. The two ends of the first peaking resistor are connected to the first differential output end and the first end of the first peaking inductor respectively, and the two ends of the second peaking resistor are connected to the second differential output end and the second end of the first peaking inductor respectively. The T-shaped coil matching module comprises a first inductor, a second inductor and a third inductor.

2. The linear equalizer of claim 1, wherein, The first end of the first inductor is connected to the first differential input signal as the first matching input end, and the second end of the first inductor is connected to the first differential input end as the first matching output end. The first end of the second inductor is connected to the second end of the first inductor. The second end of the third inductor is connected to the second differential input end as the second matching output end. ​ a fourth inductor, a first end of the fourth inductor is connected with a second end of the third inductor, and a second end of the fourth inductor is connected with the second matching input end and inputs the second differential input signal; a matching resistor, two ends of the matching resistor are connected with a second end of the second inductor and a first end of the third inductor respectively, and a middle point of the matching resistor is grounded; a first matching capacitor, two ends of the first matching capacitor are connected with a first end of the first inductor and a second end of the second inductor respectively; a second matching capacitor, two ends of the second matching capacitor are connected with a first end of the third inductor and a second end of the fourth inductor respectively.

3. The linear equalizer of claim 1, wherein, The first bias current unit comprises: a first bias current source, an output end of the first bias current source is connected with the ground; a first current mirror, comprising a first current input end, a first voltage input end, a first current output end and a second current output end, the first current input end is connected with an input end of the first bias current source, the first voltage input end inputs a first power voltage, the first current output end is connected with a first end of the first push-pull amplification unit, and the second current output end is connected with a first end of the second push-pull amplification unit.

4. The linear equalizer of claim 3, wherein, The first current mirror comprises: a first PMOS tube, a gate of the first PMOS tube is connected with a drain end of the first PMOS tube and used as the first current input end; a second PMOS tube, a drain end of the second PMOS tube is used as the first current output end; a third PMOS tube, a drain end of the third PMOS tube is used as the second current output end, a gate end of the third PMOS tube is connected with a gate end of the first PMOS tube and a gate end of the second PMOS tube, and a source end of the third PMOS tube is connected with a source end of the first PMOS tube and a source end of the second PMOS tube and used as the second current input end.

5. The linear equalizer of claim 1, wherein, The first push-pull amplification unit comprises: a first push-pull PMOS tube, a source end of the first push-pull PMOS tube is used as the first end of the first push-pull amplification unit; a first push-pull NMOS tube, a drain end of the first push-pull NMOS tube is connected with a drain end of the first push-pull PMOS tube and used as the first differential output end, a gate end of the first push-pull NMOS tube is connected with a gate end of the first push-pull PMOS tube and used as the first differential input end, and a source end of the first push-pull NMOS is coupled with the ground; The second push-pull amplification unit comprises: a second push-pull PMOS tube, a source end of the second push-pull PMOS tube is used as the first end of the second push-pull amplification unit; a second push-pull NMOS tube, a drain end of the second push-pull NMOS tube is connected with a drain end of the second push-pull PMOS tube and used as the second differential output end, a gate end of the second push-pull NMOS tube is connected with a gate end of the second push-pull PMOS tube and used as the second differential input end, and a source end of the second push-pull NMOS is coupled with the ground.

6. The linear equalizer of claim 5, wherein, The first differential amplifier is a high-frequency gain differential amplifier, the first coupling capacitor and the second coupling capacitor have the same capacitance value, the capacitance value of the first coupling capacitor C1 is ， wherein, a sum of an intrinsic gate-source capacitance of the first push-pull NMOS transistor and an intrinsic gate-source capacitance of the first push-pull PMOS transistor, a transconductance of the first differential amplifier, an inductance value of the first peaking inductance, a resistance value of the first peaking resistance, a parallel resistance value of an output resistance of the first push-pull NMOS transistor and an output resistance of the first push-pull PMOS transistor, a capacitance value of a load capacitance of the first differential amplifier.

7. The linear equalizer of claim 6, wherein, The first differential amplifier further comprises: A first degeneration unit, two ends of the first degeneration unit are connected to the first end of the first push-pull amplification unit and the first end of the second push-pull amplification unit respectively, and the first degeneration unit comprises a first degeneration capacitor and a first degeneration resistor connected in parallel; A first source degeneration unit, two ends of the first source degeneration unit are connected to the source end of the first push-pull NMOS tube and the ground respectively, and the first source degeneration unit comprises a first source degeneration capacitor and a first source degeneration resistor connected in parallel; A second source degeneration unit, two ends of the second source degeneration unit are connected to the source end of the second push-pull NMOS tube and the ground respectively, and the second source degeneration unit comprises a second source degeneration capacitor and a second source degeneration resistor connected in parallel.

8. The linear equalizer of claim 1, wherein, The first common-mode feedback unit comprises: A first feedback amplifier, an inverting input end of the first feedback amplifier is connected to a first reference voltage; A first feedback resistor, two ends of the first feedback resistor are connected to the first differential output end and a non-inverting input end of the first feedback amplifier respectively; A second feedback resistor, two ends of the second feedback resistor are connected to the second differential output end and the non-inverting input end of the first feedback amplifier respectively; A first feedback PMOS tube, a gate end of the first feedback PMOS tube is connected to an output end of the first feedback amplifier, a drain end of the first feedback PMOS tube is connected to the first end of the first push-pull amplification unit, and a source end of the first feedback PMOS tube is connected to a first power supply voltage; A second feedback PMOS tube, a gate end of the second feedback PMOS tube is connected to the output end of the first feedback amplifier, a drain end of the second feedback PMOS tube is connected to the first end of the second push-pull amplification unit, and a source end of the second feedback PMOS tube is connected to the first power supply voltage.

9. The linear equalizer of claim 1, wherein, Further comprising a second differential amplifier, for amplifying the first amplified signal to form a third amplified signal, and for amplifying the second amplified signal to form a fourth amplified signal, the second differential amplifier comprises a third differential input end, a fourth differential input end, a third differential output end and a fourth differential output end, the third differential input end is connected to the first differential output end to access the first amplified signal, the fourth differential input end is connected to the second differential output end to access the second amplified signal, the third differential output end outputs the third amplified signal, and the fourth differential output end outputs the fourth amplified signal.

10. The linear equalizer of claim 9, wherein, The first differential amplifier is a low-frequency gain differential amplifier, and the second differential amplifier is a high-frequency gain amplifier.

11. The linear equalizer of claim 9, wherein, Further comprising: A first neutralizing capacitor, two ends of the first neutralizing capacitor are connected to the fourth differential input end and the third differential output end respectively; A second neutralizing capacitor, two ends of the second neutralizing capacitor are connected to the third differential input end and the fourth differential output end respectively.

12. The linear equalizer of claim 11, wherein, The first neutralizing capacitor and the second neutralizing capacitor have the same capacitance value, and the first neutralizing capacitor has a smaller capacitance value than the first coupling capacitor.

13. The linear equalizer of claim 9, wherein, The second differential amplifier comprises: a third push-pull amplification unit configured to amplify the first amplified signal to output a third amplified signal; a fourth push-pull amplification unit configured to amplify the second amplified signal to output a fourth amplified signal; a second bias current unit configured to provide bias currents for the third push-pull amplification unit and the fourth push-pull amplification unit; a second common-mode feedback unit configured to adjust the bias currents received by the third push-pull amplification unit and the fourth push-pull amplification unit according to the third amplified signal and the fourth amplified signal.

14. An electronic circuit, characterized by A linear equalizer comprising any one of the linear equalizers of claims 1 to 13.

15. An electronic device, comprising: An electronic circuit comprising the electronic circuit of claim 14.

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